1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <linux/log2.h> 21 #include <sound/dmaengine_pcm.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/tlv.h> 26 #include <sound/core.h> 27 28 #include "fsl_micfil.h" 29 #include "fsl_utils.h" 30 31 #define MICFIL_OSR_DEFAULT 16 32 33 #define MICFIL_NUM_RATES 7 34 #define MICFIL_CLK_SRC_NUM 3 35 /* clock source ids */ 36 #define MICFIL_AUDIO_PLL1 0 37 #define MICFIL_AUDIO_PLL2 1 38 #define MICFIL_CLK_EXT3 2 39 40 static const unsigned int fsl_micfil_rates[] = { 41 8000, 11025, 16000, 22050, 32000, 44100, 48000, 42 }; 43 44 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = { 45 .count = ARRAY_SIZE(fsl_micfil_rates), 46 .list = fsl_micfil_rates, 47 }; 48 49 enum quality { 50 QUALITY_HIGH, 51 QUALITY_MEDIUM, 52 QUALITY_LOW, 53 QUALITY_VLOW0, 54 QUALITY_VLOW1, 55 QUALITY_VLOW2, 56 }; 57 58 struct fsl_micfil { 59 struct platform_device *pdev; 60 struct regmap *regmap; 61 const struct fsl_micfil_soc_data *soc; 62 struct clk *busclk; 63 struct clk *mclk; 64 struct clk *pll8k_clk; 65 struct clk *pll11k_clk; 66 struct clk *clk_src[MICFIL_CLK_SRC_NUM]; 67 struct snd_dmaengine_dai_dma_data dma_params_rx; 68 struct sdma_peripheral_config sdmacfg; 69 struct snd_soc_card *card; 70 struct snd_pcm_hw_constraint_list constraint_rates; 71 unsigned int constraint_rates_list[MICFIL_NUM_RATES]; 72 unsigned int dataline; 73 char name[32]; 74 int irq[MICFIL_IRQ_LINES]; 75 enum quality quality; 76 int dc_remover; 77 int vad_init_mode; 78 int vad_enabled; 79 int vad_detected; 80 struct fsl_micfil_verid verid; 81 struct fsl_micfil_param param; 82 bool mclk_flag; /* mclk enable flag */ 83 bool dec_bypass; 84 }; 85 86 struct fsl_micfil_soc_data { 87 unsigned int fifos; 88 unsigned int fifo_depth; 89 unsigned int dataline; 90 bool imx; 91 bool use_edma; 92 bool use_verid; 93 bool volume_sx; 94 u64 formats; 95 int fifo_offset; 96 enum quality default_quality; 97 /* stores const value in formula to calculate range */ 98 int rangeadj_const[3][2]; 99 }; 100 101 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 102 .imx = true, 103 .fifos = 8, 104 .fifo_depth = 8, 105 .dataline = 0xf, 106 .formats = SNDRV_PCM_FMTBIT_S16_LE, 107 .volume_sx = true, 108 .fifo_offset = 0, 109 .default_quality = QUALITY_VLOW0, 110 }; 111 112 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 113 .imx = true, 114 .fifos = 8, 115 .fifo_depth = 32, 116 .dataline = 0xf, 117 .formats = SNDRV_PCM_FMTBIT_S32_LE, 118 .volume_sx = false, 119 .fifo_offset = 0, 120 .default_quality = QUALITY_MEDIUM, 121 .rangeadj_const = {{27, 7}, {27, 7}, {26, 7}}, 122 }; 123 124 static struct fsl_micfil_soc_data fsl_micfil_imx93 = { 125 .imx = true, 126 .fifos = 8, 127 .fifo_depth = 32, 128 .dataline = 0xf, 129 .formats = SNDRV_PCM_FMTBIT_S32_LE, 130 .use_edma = true, 131 .use_verid = true, 132 .volume_sx = false, 133 .fifo_offset = 0, 134 .default_quality = QUALITY_MEDIUM, 135 .rangeadj_const = {{30, 6}, {30, 6}, {29, 6}}, 136 }; 137 138 static struct fsl_micfil_soc_data fsl_micfil_imx943 = { 139 .imx = true, 140 .fifos = 8, 141 .fifo_depth = 32, 142 .dataline = 0xf, 143 .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U32_LE, 144 .use_edma = true, 145 .use_verid = true, 146 .volume_sx = false, 147 .fifo_offset = -4, 148 .default_quality = QUALITY_MEDIUM, 149 .rangeadj_const = {{34, 6}, {34, 6}, {33, 6}}, 150 }; 151 152 static const struct of_device_id fsl_micfil_dt_ids[] = { 153 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 154 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 155 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 }, 156 { .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 }, 157 {} 158 }; 159 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 160 161 static const char * const micfil_quality_select_texts[] = { 162 [QUALITY_HIGH] = "High", 163 [QUALITY_MEDIUM] = "Medium", 164 [QUALITY_LOW] = "Low", 165 [QUALITY_VLOW0] = "VLow0", 166 [QUALITY_VLOW1] = "Vlow1", 167 [QUALITY_VLOW2] = "Vlow2", 168 }; 169 170 static const struct soc_enum fsl_micfil_quality_enum = 171 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 172 micfil_quality_select_texts); 173 174 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 175 176 static int micfil_get_max_range(struct fsl_micfil *micfil) 177 { 178 int max_range; 179 180 switch (micfil->quality) { 181 case QUALITY_HIGH: 182 case QUALITY_VLOW0: 183 max_range = micfil->soc->rangeadj_const[0][0] - micfil->soc->rangeadj_const[0][1] * 184 ilog2(2 * MICFIL_OSR_DEFAULT); 185 break; 186 case QUALITY_MEDIUM: 187 case QUALITY_VLOW1: 188 max_range = micfil->soc->rangeadj_const[1][0] - micfil->soc->rangeadj_const[1][1] * 189 ilog2(MICFIL_OSR_DEFAULT); 190 break; 191 case QUALITY_LOW: 192 case QUALITY_VLOW2: 193 max_range = micfil->soc->rangeadj_const[2][0] - micfil->soc->rangeadj_const[2][1] * 194 ilog2(MICFIL_OSR_DEFAULT); 195 break; 196 default: 197 return 0; 198 } 199 max_range = max_range < 0 ? 0 : max_range; 200 201 return max_range; 202 } 203 204 static int micfil_range_set(struct snd_kcontrol *kcontrol, 205 struct snd_ctl_elem_value *ucontrol) 206 { 207 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol); 208 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 209 struct soc_mixer_control *mc = 210 (struct soc_mixer_control *)kcontrol->private_value; 211 unsigned int shift = mc->shift; 212 int max_range, new_range; 213 int ret; 214 215 new_range = ucontrol->value.integer.value[0]; 216 max_range = micfil_get_max_range(micfil); 217 if (new_range > max_range) 218 dev_warn(&micfil->pdev->dev, "range makes channel %d data unreliable\n", shift / 4); 219 220 ret = pm_runtime_resume_and_get(cmpnt->dev); 221 if (ret) 222 return ret; 223 224 ret = snd_soc_component_update_bits(cmpnt, REG_MICFIL_OUT_CTRL, 0xF << shift, 225 new_range << shift); 226 227 pm_runtime_put_autosuspend(cmpnt->dev); 228 229 return ret; 230 } 231 232 static int micfil_set_quality(struct fsl_micfil *micfil) 233 { 234 int range, max_range; 235 u32 qsel, val; 236 int i; 237 238 if (!micfil->soc->volume_sx) { 239 regmap_read(micfil->regmap, REG_MICFIL_OUT_CTRL, &val); 240 max_range = micfil_get_max_range(micfil); 241 for (i = 0; i < micfil->soc->fifos; i++) { 242 range = (val >> MICFIL_OUTGAIN_CHX_SHIFT(i)) & 0xF; 243 if (range > max_range) 244 dev_warn(&micfil->pdev->dev, "please reset channel %d range\n", i); 245 } 246 } 247 248 switch (micfil->quality) { 249 case QUALITY_HIGH: 250 qsel = MICFIL_QSEL_HIGH_QUALITY; 251 break; 252 case QUALITY_MEDIUM: 253 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 254 break; 255 case QUALITY_LOW: 256 qsel = MICFIL_QSEL_LOW_QUALITY; 257 break; 258 case QUALITY_VLOW0: 259 qsel = MICFIL_QSEL_VLOW0_QUALITY; 260 break; 261 case QUALITY_VLOW1: 262 qsel = MICFIL_QSEL_VLOW1_QUALITY; 263 break; 264 case QUALITY_VLOW2: 265 qsel = MICFIL_QSEL_VLOW2_QUALITY; 266 break; 267 default: 268 return -EINVAL; 269 } 270 271 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 272 MICFIL_CTRL2_QSEL, 273 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 274 } 275 276 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 277 struct snd_ctl_elem_value *ucontrol) 278 { 279 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol); 280 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 281 282 ucontrol->value.integer.value[0] = micfil->quality; 283 284 return 0; 285 } 286 287 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 288 struct snd_ctl_elem_value *ucontrol) 289 { 290 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol); 291 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 292 int val = ucontrol->value.integer.value[0]; 293 bool change = false; 294 int old_val; 295 int ret; 296 297 if (val < QUALITY_HIGH || val > QUALITY_VLOW2) 298 return -EINVAL; 299 300 if (micfil->quality != val) { 301 ret = pm_runtime_resume_and_get(cmpnt->dev); 302 if (ret) 303 return ret; 304 305 old_val = micfil->quality; 306 micfil->quality = val; 307 ret = micfil_set_quality(micfil); 308 309 pm_runtime_put_autosuspend(cmpnt->dev); 310 311 if (ret) { 312 micfil->quality = old_val; 313 return ret; 314 } 315 316 change = true; 317 } 318 319 return change; 320 } 321 322 static const char * const micfil_hwvad_enable[] = { 323 "Disable (Record only)", 324 "Enable (Record with Vad)", 325 }; 326 327 static const char * const micfil_hwvad_init_mode[] = { 328 "Envelope mode", "Energy mode", 329 }; 330 331 static const char * const micfil_hwvad_hpf_texts[] = { 332 "Filter bypass", 333 "Cut-off @1750Hz", 334 "Cut-off @215Hz", 335 "Cut-off @102Hz", 336 }; 337 338 /* 339 * DC Remover Control 340 * Filter Bypassed 1 1 341 * Cut-off @21Hz 0 0 342 * Cut-off @83Hz 0 1 343 * Cut-off @152HZ 1 0 344 */ 345 static const char * const micfil_dc_remover_texts[] = { 346 "Cut-off @21Hz", "Cut-off @83Hz", 347 "Cut-off @152Hz", "Bypass", 348 }; 349 350 static const struct soc_enum hwvad_enable_enum = 351 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 352 micfil_hwvad_enable); 353 static const struct soc_enum hwvad_init_mode_enum = 354 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 355 micfil_hwvad_init_mode); 356 static const struct soc_enum hwvad_hpf_enum = 357 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 358 ARRAY_SIZE(micfil_hwvad_hpf_texts), 359 micfil_hwvad_hpf_texts); 360 static const struct soc_enum fsl_micfil_dc_remover_enum = 361 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 362 micfil_dc_remover_texts); 363 364 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 365 struct snd_ctl_elem_value *ucontrol) 366 { 367 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 368 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 369 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 370 unsigned int *item = ucontrol->value.enumerated.item; 371 int val = snd_soc_enum_item_to_val(e, item[0]); 372 int i = 0, ret = 0; 373 u32 reg_val = 0; 374 375 if (val < 0 || val > 3) 376 return -EINVAL; 377 378 ret = pm_runtime_resume_and_get(comp->dev); 379 if (ret) 380 return ret; 381 382 micfil->dc_remover = val; 383 384 /* Calculate total value for all channels */ 385 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 386 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 387 388 /* Update DC Remover mode for all channels */ 389 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 390 MICFIL_DC_CTRL_CONFIG, reg_val); 391 392 pm_runtime_put_autosuspend(comp->dev); 393 394 return ret; 395 } 396 397 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 398 struct snd_ctl_elem_value *ucontrol) 399 { 400 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 401 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 402 403 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 404 405 return 0; 406 } 407 408 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 409 struct snd_ctl_elem_value *ucontrol) 410 { 411 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 412 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 413 unsigned int *item = ucontrol->value.enumerated.item; 414 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 415 int val = snd_soc_enum_item_to_val(e, item[0]); 416 bool change = false; 417 418 if (val < 0 || val > 1) 419 return -EINVAL; 420 421 change = (micfil->vad_enabled != val); 422 micfil->vad_enabled = val; 423 424 return change; 425 } 426 427 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 428 struct snd_ctl_elem_value *ucontrol) 429 { 430 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 431 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 432 433 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 434 435 return 0; 436 } 437 438 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 439 struct snd_ctl_elem_value *ucontrol) 440 { 441 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 442 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 443 unsigned int *item = ucontrol->value.enumerated.item; 444 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 445 int val = snd_soc_enum_item_to_val(e, item[0]); 446 bool change = false; 447 448 if (val < MICFIL_HWVAD_ENVELOPE_MODE || val > MICFIL_HWVAD_ENERGY_MODE) 449 return -EINVAL; 450 451 /* 0 - Envelope-based Mode 452 * 1 - Energy-based Mode 453 */ 454 change = (micfil->vad_init_mode != val); 455 micfil->vad_init_mode = val; 456 457 return change; 458 } 459 460 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 461 struct snd_ctl_elem_value *ucontrol) 462 { 463 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 464 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 465 466 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 467 468 return 0; 469 } 470 471 static int hwvad_detected(struct snd_kcontrol *kcontrol, 472 struct snd_ctl_elem_value *ucontrol) 473 { 474 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 475 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 476 477 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 478 479 return 0; 480 } 481 482 static const struct snd_kcontrol_new fsl_micfil_range_controls[] = { 483 SOC_SINGLE_EXT("CH0 Range", REG_MICFIL_OUT_CTRL, 484 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, 485 snd_soc_get_volsw, micfil_range_set), 486 SOC_SINGLE_EXT("CH1 Range", REG_MICFIL_OUT_CTRL, 487 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, 488 snd_soc_get_volsw, micfil_range_set), 489 SOC_SINGLE_EXT("CH2 Range", REG_MICFIL_OUT_CTRL, 490 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, 491 snd_soc_get_volsw, micfil_range_set), 492 SOC_SINGLE_EXT("CH3 Range", REG_MICFIL_OUT_CTRL, 493 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, 494 snd_soc_get_volsw, micfil_range_set), 495 SOC_SINGLE_EXT("CH4 Range", REG_MICFIL_OUT_CTRL, 496 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, 497 snd_soc_get_volsw, micfil_range_set), 498 SOC_SINGLE_EXT("CH5 Range", REG_MICFIL_OUT_CTRL, 499 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, 500 snd_soc_get_volsw, micfil_range_set), 501 SOC_SINGLE_EXT("CH6 Range", REG_MICFIL_OUT_CTRL, 502 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, 503 snd_soc_get_volsw, micfil_range_set), 504 SOC_SINGLE_EXT("CH7 Range", REG_MICFIL_OUT_CTRL, 505 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, 506 snd_soc_get_volsw, micfil_range_set), 507 }; 508 509 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = { 510 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 511 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv), 512 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 513 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv), 514 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 515 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv), 516 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 517 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv), 518 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 519 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv), 520 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 521 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv), 522 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 523 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv), 524 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 525 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv), 526 }; 527 528 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 529 SOC_ENUM_EXT("MICFIL Quality Select", 530 fsl_micfil_quality_enum, 531 micfil_quality_get, micfil_quality_set), 532 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 533 hwvad_get_enable, hwvad_put_enable), 534 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 535 hwvad_get_init_mode, hwvad_put_init_mode), 536 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 537 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 538 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 539 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 540 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 541 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 542 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 543 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 544 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 545 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 546 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 547 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 548 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 549 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 550 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 551 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 552 { 553 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 554 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 555 .name = "VAD Detected", 556 .info = snd_soc_info_bool_ext, 557 .get = hwvad_detected, 558 }, 559 }; 560 561 static int fsl_micfil_use_verid(struct device *dev) 562 { 563 struct fsl_micfil *micfil = dev_get_drvdata(dev); 564 unsigned int val; 565 int ret; 566 567 if (!micfil->soc->use_verid) 568 return 0; 569 570 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val); 571 if (ret < 0) 572 return ret; 573 574 dev_dbg(dev, "VERID: 0x%016X\n", val); 575 576 micfil->verid.version = val & 577 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK); 578 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT; 579 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK; 580 581 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val); 582 if (ret < 0) 583 return ret; 584 585 dev_dbg(dev, "PARAM: 0x%016X\n", val); 586 587 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >> 588 MICFIL_PARAM_NUM_HWVAD_SHIFT; 589 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD; 590 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE; 591 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD; 592 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS; 593 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS; 594 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER; 595 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH; 596 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >> 597 MICFIL_PARAM_FIFO_PTRWID_SHIFT; 598 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >> 599 MICFIL_PARAM_NPAIR_SHIFT; 600 601 return 0; 602 } 603 604 /* The SRES is a self-negated bit which provides the CPU with the 605 * capability to initialize the PDM Interface module through the 606 * slave-bus interface. This bit always reads as zero, and this 607 * bit is only effective when MDIS is cleared 608 */ 609 static int fsl_micfil_reset(struct device *dev) 610 { 611 struct fsl_micfil *micfil = dev_get_drvdata(dev); 612 int ret; 613 614 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 615 MICFIL_CTRL1_MDIS); 616 if (ret) 617 return ret; 618 619 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 620 MICFIL_CTRL1_SRES); 621 if (ret) 622 return ret; 623 624 /* 625 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 626 * as non-volatile register, so SRES still remain in regmap 627 * cache after set, that every update of REG_MICFIL_CTRL1, 628 * software reset happens. so clear it explicitly. 629 */ 630 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 631 MICFIL_CTRL1_SRES); 632 if (ret) 633 return ret; 634 635 /* 636 * Set SRES should clear CHnF flags, But even add delay here 637 * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 638 */ 639 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 640 if (ret) 641 return ret; 642 643 return 0; 644 } 645 646 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 647 struct snd_soc_dai *dai) 648 { 649 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 650 651 if (!micfil) { 652 dev_err(dai->dev, "micfil dai priv_data not set\n"); 653 return -EINVAL; 654 } 655 656 if (micfil->constraint_rates.count > 0) 657 snd_pcm_hw_constraint_list(substream->runtime, 0, 658 SNDRV_PCM_HW_PARAM_RATE, 659 &micfil->constraint_rates); 660 661 return 0; 662 } 663 664 /* Enable/disable hwvad interrupts */ 665 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 666 { 667 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 668 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 669 670 /* Voice Activity Detector Error Interruption */ 671 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 672 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 673 674 /* Voice Activity Detector Interruption */ 675 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 676 MICFIL_VAD0_CTRL1_IE, vadie_reg); 677 678 return 0; 679 } 680 681 /* Configuration done only in energy-based initialization mode */ 682 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 683 { 684 /* Keep the VADFRENDIS bitfield cleared. */ 685 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 686 MICFIL_VAD0_CTRL2_FRENDIS); 687 688 /* Keep the VADPREFEN bitfield cleared. */ 689 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 690 MICFIL_VAD0_CTRL2_PREFEN); 691 692 /* Keep the VADSFILEN bitfield cleared. */ 693 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 694 MICFIL_VAD0_SCONFIG_SFILEN); 695 696 /* Keep the VADSMAXEN bitfield cleared. */ 697 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 698 MICFIL_VAD0_SCONFIG_SMAXEN); 699 700 /* Keep the VADNFILAUTO bitfield asserted. */ 701 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 702 MICFIL_VAD0_NCONFIG_NFILAUT); 703 704 /* Keep the VADNMINEN bitfield cleared. */ 705 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 706 MICFIL_VAD0_NCONFIG_NMINEN); 707 708 /* Keep the VADNDECEN bitfield cleared. */ 709 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 710 MICFIL_VAD0_NCONFIG_NDECEN); 711 712 /* Keep the VADNOREN bitfield cleared. */ 713 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 714 MICFIL_VAD0_NCONFIG_NOREN); 715 716 return 0; 717 } 718 719 /* Configuration done only in envelope-based initialization mode */ 720 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 721 { 722 /* Assert the VADFRENDIS bitfield */ 723 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 724 MICFIL_VAD0_CTRL2_FRENDIS); 725 726 /* Assert the VADPREFEN bitfield. */ 727 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 728 MICFIL_VAD0_CTRL2_PREFEN); 729 730 /* Assert the VADSFILEN bitfield. */ 731 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 732 MICFIL_VAD0_SCONFIG_SFILEN); 733 734 /* Assert the VADSMAXEN bitfield. */ 735 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 736 MICFIL_VAD0_SCONFIG_SMAXEN); 737 738 /* Clear the VADNFILAUTO bitfield */ 739 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 740 MICFIL_VAD0_NCONFIG_NFILAUT); 741 742 /* Assert the VADNMINEN bitfield. */ 743 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 744 MICFIL_VAD0_NCONFIG_NMINEN); 745 746 /* Assert the VADNDECEN bitfield. */ 747 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 748 MICFIL_VAD0_NCONFIG_NDECEN); 749 750 /* Assert VADNOREN bitfield. */ 751 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 752 MICFIL_VAD0_NCONFIG_NOREN); 753 754 return 0; 755 } 756 757 /* 758 * Hardware Voice Active Detection: The HWVAD takes data from the input 759 * of a selected PDM microphone to detect if there is any 760 * voice activity. When a voice activity is detected, an interrupt could 761 * be delivered to the system. Initialization in section 8.4: 762 * Can work in two modes: 763 * -> Eneveope-based mode (section 8.4.1) 764 * -> Energy-based mode (section 8.4.2) 765 * 766 * It is important to remark that the HWVAD detector could be enabled 767 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 768 * bit in STAT register is cleared 769 */ 770 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 771 { 772 int ret; 773 774 micfil->vad_detected = 0; 775 776 /* envelope-based specific initialization */ 777 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 778 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 779 else 780 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 781 if (ret) 782 return ret; 783 784 /* Voice Activity Detector Internal Filters Initialization*/ 785 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 786 MICFIL_VAD0_CTRL1_ST10); 787 788 /* Voice Activity Detector Internal Filter */ 789 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 790 MICFIL_VAD0_CTRL1_ST10); 791 792 /* Enable Interrupts */ 793 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 794 if (ret) 795 return ret; 796 797 /* Voice Activity Detector Reset */ 798 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 799 MICFIL_VAD0_CTRL1_RST); 800 801 /* Voice Activity Detector Enabled */ 802 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 803 MICFIL_VAD0_CTRL1_EN); 804 805 return 0; 806 } 807 808 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 809 { 810 struct device *dev = &micfil->pdev->dev; 811 int ret = 0; 812 813 /* Disable HWVAD */ 814 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 815 MICFIL_VAD0_CTRL1_EN); 816 817 /* Disable hwvad interrupts */ 818 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 819 if (ret) 820 dev_err(dev, "Failed to disable interrupts\n"); 821 822 return ret; 823 } 824 825 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 826 struct snd_soc_dai *dai) 827 { 828 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 829 struct device *dev = &micfil->pdev->dev; 830 int ret; 831 832 switch (cmd) { 833 case SNDRV_PCM_TRIGGER_START: 834 case SNDRV_PCM_TRIGGER_RESUME: 835 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 836 ret = fsl_micfil_reset(dev); 837 if (ret) { 838 dev_err(dev, "failed to soft reset\n"); 839 return ret; 840 } 841 842 /* DMA Interrupt Selection - DISEL bits 843 * 00 - DMA and IRQ disabled 844 * 01 - DMA req enabled 845 * 10 - IRQ enabled 846 * 11 - reserved 847 */ 848 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 849 MICFIL_CTRL1_DISEL, 850 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 851 if (ret) 852 return ret; 853 854 /* Enable the module */ 855 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 856 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 857 if (ret) 858 return ret; 859 860 if (micfil->vad_enabled && !micfil->dec_bypass) 861 fsl_micfil_hwvad_enable(micfil); 862 863 break; 864 case SNDRV_PCM_TRIGGER_STOP: 865 case SNDRV_PCM_TRIGGER_SUSPEND: 866 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 867 if (micfil->vad_enabled && !micfil->dec_bypass) 868 fsl_micfil_hwvad_disable(micfil); 869 870 /* Disable the module */ 871 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 872 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 873 if (ret) 874 return ret; 875 876 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 877 MICFIL_CTRL1_DISEL, 878 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 879 if (ret) 880 return ret; 881 break; 882 default: 883 return -EINVAL; 884 } 885 return 0; 886 } 887 888 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 889 { 890 struct device *dev = &micfil->pdev->dev; 891 u64 ratio = sample_rate; 892 struct clk *clk; 893 int ret; 894 895 /* Get root clock */ 896 clk = micfil->mclk; 897 898 /* Disable clock first, for it was enabled by pm_runtime */ 899 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 900 micfil->pll11k_clk, ratio); 901 ret = clk_prepare_enable(clk); 902 if (ret) 903 return ret; 904 905 return 0; 906 } 907 908 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 909 struct snd_pcm_hw_params *params, 910 struct snd_soc_dai *dai) 911 { 912 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 913 unsigned int channels = params_channels(params); 914 snd_pcm_format_t format = params_format(params); 915 unsigned int rate = params_rate(params); 916 int clk_div = 8, mclk_rate, div_multiply_k; 917 int osr = MICFIL_OSR_DEFAULT; 918 int ret; 919 920 /* 1. Disable the module */ 921 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 922 MICFIL_CTRL1_PDMIEN); 923 if (ret) 924 return ret; 925 926 /* enable channels */ 927 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 928 0xFF, ((1 << channels) - 1)); 929 if (ret) 930 return ret; 931 932 ret = fsl_micfil_reparent_rootclk(micfil, rate); 933 if (ret) 934 return ret; 935 936 micfil->mclk_flag = true; 937 938 /* floor(K * CLKDIV) */ 939 switch (micfil->quality) { 940 case QUALITY_HIGH: 941 div_multiply_k = clk_div >> 1; 942 break; 943 case QUALITY_LOW: 944 case QUALITY_VLOW1: 945 div_multiply_k = clk_div << 1; 946 break; 947 case QUALITY_VLOW2: 948 div_multiply_k = clk_div << 2; 949 break; 950 case QUALITY_MEDIUM: 951 case QUALITY_VLOW0: 952 default: 953 div_multiply_k = clk_div; 954 break; 955 } 956 957 if (format == SNDRV_PCM_FORMAT_DSD_U32_LE) { 958 micfil->dec_bypass = true; 959 /* 960 * According to equation 29 in RM: 961 * MCLK_CLK_ROOT = PDM CLK rate * 2 * floor(K * CLKDIV) 962 * PDM CLK rate = rate * physical bit width (32) 963 */ 964 mclk_rate = rate * div_multiply_k * 32 * 2; 965 } else { 966 micfil->dec_bypass = false; 967 mclk_rate = rate * clk_div * osr * 8; 968 } 969 970 ret = clk_set_rate(micfil->mclk, mclk_rate); 971 if (ret) 972 return ret; 973 974 ret = micfil_set_quality(micfil); 975 if (ret) 976 return ret; 977 978 regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 979 MICFIL_CTRL2_DEC_BYPASS, 980 micfil->dec_bypass ? MICFIL_CTRL2_DEC_BYPASS : 0); 981 982 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 983 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 984 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 985 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr)); 986 987 /* Configure CIC OSR in VADCICOSR */ 988 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 989 MICFIL_VAD0_CTRL1_CICOSR, 990 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 991 992 /* Configure source channel in VADCHSEL */ 993 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 994 MICFIL_VAD0_CTRL1_CHSEL, 995 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 996 997 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 998 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 999 micfil->sdmacfg.n_fifos_src = channels; 1000 micfil->sdmacfg.sw_done = true; 1001 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 1002 if (micfil->soc->use_edma) 1003 micfil->dma_params_rx.maxburst = channels; 1004 1005 return 0; 1006 } 1007 1008 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream, 1009 struct snd_soc_dai *dai) 1010 { 1011 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 1012 1013 clk_disable_unprepare(micfil->mclk); 1014 micfil->mclk_flag = false; 1015 1016 return 0; 1017 } 1018 1019 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 1020 { 1021 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 1022 struct device *dev = cpu_dai->dev; 1023 unsigned int val = 0; 1024 int ret, i, max_range; 1025 1026 micfil->quality = micfil->soc->default_quality; 1027 micfil->card = cpu_dai->component->card; 1028 1029 /* set default gain to 2 */ 1030 if (micfil->soc->volume_sx) { 1031 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 1032 } else { 1033 max_range = micfil_get_max_range(micfil); 1034 for (i = 1; i < micfil->soc->fifos; i++) 1035 max_range |= max_range << 4; 1036 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, max_range); 1037 } 1038 1039 /* set DC Remover in bypass mode*/ 1040 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 1041 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 1042 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 1043 MICFIL_DC_CTRL_CONFIG, val); 1044 if (ret) { 1045 dev_err(dev, "failed to set DC Remover mode bits\n"); 1046 return ret; 1047 } 1048 micfil->dc_remover = MICFIL_DC_BYPASS; 1049 1050 snd_soc_dai_init_dma_data(cpu_dai, NULL, 1051 &micfil->dma_params_rx); 1052 1053 /* FIFO Watermark Control - FIFOWMK*/ 1054 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 1055 MICFIL_FIFO_CTRL_FIFOWMK, 1056 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 1057 if (ret) 1058 return ret; 1059 1060 return 0; 1061 } 1062 1063 static int fsl_micfil_component_probe(struct snd_soc_component *component) 1064 { 1065 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component); 1066 1067 if (micfil->soc->volume_sx) 1068 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls, 1069 ARRAY_SIZE(fsl_micfil_volume_sx_controls)); 1070 else 1071 snd_soc_add_component_controls(component, fsl_micfil_range_controls, 1072 ARRAY_SIZE(fsl_micfil_range_controls)); 1073 1074 return 0; 1075 } 1076 1077 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 1078 .probe = fsl_micfil_dai_probe, 1079 .startup = fsl_micfil_startup, 1080 .trigger = fsl_micfil_trigger, 1081 .hw_params = fsl_micfil_hw_params, 1082 .hw_free = fsl_micfil_hw_free, 1083 }; 1084 1085 static struct snd_soc_dai_driver fsl_micfil_dai = { 1086 .capture = { 1087 .stream_name = "CPU-Capture", 1088 .channels_min = 1, 1089 .channels_max = 8, 1090 .rates = SNDRV_PCM_RATE_8000_48000, 1091 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1092 }, 1093 .ops = &fsl_micfil_dai_ops, 1094 }; 1095 1096 static const struct snd_soc_component_driver fsl_micfil_component = { 1097 .name = "fsl-micfil-dai", 1098 .probe = fsl_micfil_component_probe, 1099 .controls = fsl_micfil_snd_controls, 1100 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 1101 .legacy_dai_naming = 1, 1102 }; 1103 1104 /* REGMAP */ 1105 static const struct reg_default fsl_micfil_reg_defaults[] = { 1106 {REG_MICFIL_CTRL1, 0x00000000}, 1107 {REG_MICFIL_CTRL2, 0x00000000}, 1108 {REG_MICFIL_STAT, 0x00000000}, 1109 {REG_MICFIL_FIFO_CTRL, 0x0000001F}, 1110 {REG_MICFIL_FIFO_STAT, 0x00000000}, 1111 {REG_MICFIL_DATACH0, 0x00000000}, 1112 {REG_MICFIL_DATACH1, 0x00000000}, 1113 {REG_MICFIL_DATACH2, 0x00000000}, 1114 {REG_MICFIL_DATACH3, 0x00000000}, 1115 {REG_MICFIL_DATACH4, 0x00000000}, 1116 {REG_MICFIL_DATACH5, 0x00000000}, 1117 {REG_MICFIL_DATACH6, 0x00000000}, 1118 {REG_MICFIL_DATACH7, 0x00000000}, 1119 {REG_MICFIL_DC_CTRL, 0x00000000}, 1120 {REG_MICFIL_OUT_CTRL, 0x00000000}, 1121 {REG_MICFIL_OUT_STAT, 0x00000000}, 1122 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 1123 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 1124 {REG_MICFIL_VAD0_STAT, 0x00000000}, 1125 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 1126 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 1127 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 1128 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 1129 }; 1130 1131 static const struct reg_default fsl_micfil_reg_defaults_v2[] = { 1132 {REG_MICFIL_CTRL1, 0x00000000}, 1133 {REG_MICFIL_CTRL2, 0x00000000}, 1134 {REG_MICFIL_STAT, 0x00000000}, 1135 {REG_MICFIL_FIFO_CTRL, 0x0000001F}, 1136 {REG_MICFIL_FIFO_STAT, 0x00000000}, 1137 {REG_MICFIL_DATACH0 - 0x4, 0x00000000}, 1138 {REG_MICFIL_DATACH1 - 0x4, 0x00000000}, 1139 {REG_MICFIL_DATACH2 - 0x4, 0x00000000}, 1140 {REG_MICFIL_DATACH3 - 0x4, 0x00000000}, 1141 {REG_MICFIL_DATACH4 - 0x4, 0x00000000}, 1142 {REG_MICFIL_DATACH5 - 0x4, 0x00000000}, 1143 {REG_MICFIL_DATACH6 - 0x4, 0x00000000}, 1144 {REG_MICFIL_DATACH7 - 0x4, 0x00000000}, 1145 {REG_MICFIL_DC_CTRL, 0x00000000}, 1146 {REG_MICFIL_OUT_CTRL, 0x00000000}, 1147 {REG_MICFIL_OUT_STAT, 0x00000000}, 1148 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 1149 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 1150 {REG_MICFIL_VAD0_STAT, 0x00000000}, 1151 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 1152 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 1153 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 1154 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 1155 }; 1156 1157 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 1158 { 1159 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1160 int ofs = micfil->soc->fifo_offset; 1161 1162 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs)) 1163 return true; 1164 1165 switch (reg) { 1166 case REG_MICFIL_CTRL1: 1167 case REG_MICFIL_CTRL2: 1168 case REG_MICFIL_STAT: 1169 case REG_MICFIL_FIFO_CTRL: 1170 case REG_MICFIL_FIFO_STAT: 1171 case REG_MICFIL_DC_CTRL: 1172 case REG_MICFIL_OUT_CTRL: 1173 case REG_MICFIL_OUT_STAT: 1174 case REG_MICFIL_VAD0_CTRL1: 1175 case REG_MICFIL_VAD0_CTRL2: 1176 case REG_MICFIL_VAD0_STAT: 1177 case REG_MICFIL_VAD0_SCONFIG: 1178 case REG_MICFIL_VAD0_NCONFIG: 1179 case REG_MICFIL_VAD0_NDATA: 1180 case REG_MICFIL_VAD0_ZCD: 1181 return true; 1182 case REG_MICFIL_FSYNC_CTRL: 1183 case REG_MICFIL_VERID: 1184 case REG_MICFIL_PARAM: 1185 if (micfil->soc->use_verid) 1186 return true; 1187 fallthrough; 1188 default: 1189 return false; 1190 } 1191 } 1192 1193 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 1194 { 1195 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1196 1197 switch (reg) { 1198 case REG_MICFIL_CTRL1: 1199 case REG_MICFIL_CTRL2: 1200 case REG_MICFIL_STAT: /* Write 1 to Clear */ 1201 case REG_MICFIL_FIFO_CTRL: 1202 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 1203 case REG_MICFIL_DC_CTRL: 1204 case REG_MICFIL_OUT_CTRL: 1205 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 1206 case REG_MICFIL_VAD0_CTRL1: 1207 case REG_MICFIL_VAD0_CTRL2: 1208 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 1209 case REG_MICFIL_VAD0_SCONFIG: 1210 case REG_MICFIL_VAD0_NCONFIG: 1211 case REG_MICFIL_VAD0_ZCD: 1212 return true; 1213 case REG_MICFIL_FSYNC_CTRL: 1214 if (micfil->soc->use_verid) 1215 return true; 1216 fallthrough; 1217 default: 1218 return false; 1219 } 1220 } 1221 1222 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 1223 { 1224 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1225 int ofs = micfil->soc->fifo_offset; 1226 1227 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs)) 1228 return true; 1229 1230 switch (reg) { 1231 case REG_MICFIL_STAT: 1232 case REG_MICFIL_FIFO_STAT: 1233 case REG_MICFIL_OUT_STAT: 1234 case REG_MICFIL_VERID: 1235 case REG_MICFIL_PARAM: 1236 case REG_MICFIL_VAD0_STAT: 1237 case REG_MICFIL_VAD0_NDATA: 1238 return true; 1239 default: 1240 return false; 1241 } 1242 } 1243 1244 static const struct regmap_config fsl_micfil_regmap_config = { 1245 .reg_bits = 32, 1246 .reg_stride = 4, 1247 .val_bits = 32, 1248 1249 .max_register = REG_MICFIL_VAD0_ZCD, 1250 .reg_defaults = fsl_micfil_reg_defaults, 1251 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 1252 .readable_reg = fsl_micfil_readable_reg, 1253 .volatile_reg = fsl_micfil_volatile_reg, 1254 .writeable_reg = fsl_micfil_writeable_reg, 1255 .cache_type = REGCACHE_MAPLE, 1256 }; 1257 1258 static const struct regmap_config fsl_micfil_regmap_config_v2 = { 1259 .reg_bits = 32, 1260 .reg_stride = 4, 1261 .val_bits = 32, 1262 1263 .max_register = REG_MICFIL_VAD0_ZCD, 1264 .reg_defaults = fsl_micfil_reg_defaults_v2, 1265 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2), 1266 .readable_reg = fsl_micfil_readable_reg, 1267 .volatile_reg = fsl_micfil_volatile_reg, 1268 .writeable_reg = fsl_micfil_writeable_reg, 1269 .cache_type = REGCACHE_MAPLE, 1270 }; 1271 1272 /* END OF REGMAP */ 1273 1274 static irqreturn_t micfil_isr(int irq, void *devid) 1275 { 1276 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1277 struct platform_device *pdev = micfil->pdev; 1278 u32 stat_reg; 1279 u32 fifo_stat_reg; 1280 u32 ctrl1_reg; 1281 bool dma_enabled; 1282 int i; 1283 1284 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1285 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 1286 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1287 1288 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 1289 1290 /* Channel 0-7 Output Data Flags */ 1291 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 1292 if (stat_reg & MICFIL_STAT_CHXF(i)) 1293 dev_dbg(&pdev->dev, 1294 "Data available in Data Channel %d\n", i); 1295 /* if DMA is not enabled, field must be written with 1 1296 * to clear 1297 */ 1298 if (!dma_enabled) 1299 regmap_write_bits(micfil->regmap, 1300 REG_MICFIL_STAT, 1301 MICFIL_STAT_CHXF(i), 1302 MICFIL_STAT_CHXF(i)); 1303 } 1304 1305 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 1306 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 1307 dev_dbg(&pdev->dev, 1308 "FIFO Overflow Exception flag for channel %d\n", 1309 i); 1310 1311 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 1312 dev_dbg(&pdev->dev, 1313 "FIFO Underflow Exception flag for channel %d\n", 1314 i); 1315 } 1316 1317 return IRQ_HANDLED; 1318 } 1319 1320 static irqreturn_t micfil_err_isr(int irq, void *devid) 1321 { 1322 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1323 struct platform_device *pdev = micfil->pdev; 1324 u32 fifo_stat_reg; 1325 u32 out_stat_reg; 1326 u32 stat_reg; 1327 1328 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1329 1330 if (stat_reg & MICFIL_STAT_BSY_FIL) 1331 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 1332 1333 if (stat_reg & MICFIL_STAT_FIR_RDY) 1334 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 1335 1336 if (stat_reg & MICFIL_STAT_LOWFREQF) { 1337 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 1338 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 1339 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF); 1340 } 1341 1342 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1343 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT, 1344 fifo_stat_reg, fifo_stat_reg); 1345 1346 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg); 1347 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT, 1348 out_stat_reg, out_stat_reg); 1349 1350 return IRQ_HANDLED; 1351 } 1352 1353 static irqreturn_t voice_detected_fn(int irq, void *devid) 1354 { 1355 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1356 struct snd_kcontrol *kctl; 1357 1358 if (!micfil->card) 1359 return IRQ_HANDLED; 1360 1361 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 1362 if (!kctl) 1363 return IRQ_HANDLED; 1364 1365 if (micfil->vad_detected) 1366 snd_ctl_notify(micfil->card->snd_card, 1367 SNDRV_CTL_EVENT_MASK_VALUE, 1368 &kctl->id); 1369 1370 return IRQ_HANDLED; 1371 } 1372 1373 static irqreturn_t hwvad_isr(int irq, void *devid) 1374 { 1375 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1376 struct device *dev = &micfil->pdev->dev; 1377 u32 vad0_reg; 1378 int ret; 1379 1380 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1381 1382 /* 1383 * The only difference between MICFIL_VAD0_STAT_EF and 1384 * MICFIL_VAD0_STAT_IF is that the former requires Write 1385 * 1 to Clear. Since both flags are set, it is enough 1386 * to only read one of them 1387 */ 1388 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 1389 /* Write 1 to clear */ 1390 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 1391 MICFIL_VAD0_STAT_IF, 1392 MICFIL_VAD0_STAT_IF); 1393 1394 micfil->vad_detected = 1; 1395 } 1396 1397 ret = fsl_micfil_hwvad_disable(micfil); 1398 if (ret) 1399 dev_err(dev, "Failed to disable hwvad\n"); 1400 1401 return IRQ_WAKE_THREAD; 1402 } 1403 1404 static irqreturn_t hwvad_err_isr(int irq, void *devid) 1405 { 1406 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1407 struct device *dev = &micfil->pdev->dev; 1408 u32 vad0_reg; 1409 1410 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1411 1412 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 1413 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 1414 1415 return IRQ_HANDLED; 1416 } 1417 1418 static int fsl_micfil_runtime_suspend(struct device *dev); 1419 static int fsl_micfil_runtime_resume(struct device *dev); 1420 1421 static int fsl_micfil_probe(struct platform_device *pdev) 1422 { 1423 struct device_node *np = pdev->dev.of_node; 1424 struct fsl_micfil *micfil; 1425 struct resource *res; 1426 void __iomem *regs; 1427 int ret, i; 1428 1429 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1430 if (!micfil) 1431 return -ENOMEM; 1432 1433 micfil->pdev = pdev; 1434 strscpy(micfil->name, np->name, sizeof(micfil->name)); 1435 1436 micfil->soc = of_device_get_match_data(&pdev->dev); 1437 1438 /* ipg_clk is used to control the registers 1439 * ipg_clk_app is used to operate the filter 1440 */ 1441 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1442 if (IS_ERR(micfil->mclk)) { 1443 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1444 PTR_ERR(micfil->mclk)); 1445 return PTR_ERR(micfil->mclk); 1446 } 1447 1448 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1449 if (IS_ERR(micfil->busclk)) { 1450 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1451 PTR_ERR(micfil->busclk)); 1452 return PTR_ERR(micfil->busclk); 1453 } 1454 1455 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1456 &micfil->pll11k_clk); 1457 1458 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk; 1459 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk; 1460 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3"); 1461 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3])) 1462 micfil->clk_src[MICFIL_CLK_EXT3] = NULL; 1463 1464 fsl_asoc_constrain_rates(&micfil->constraint_rates, 1465 &fsl_micfil_rate_constraints, 1466 micfil->clk_src[MICFIL_AUDIO_PLL1], 1467 micfil->clk_src[MICFIL_AUDIO_PLL2], 1468 micfil->clk_src[MICFIL_CLK_EXT3], 1469 micfil->constraint_rates_list); 1470 1471 /* init regmap */ 1472 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1473 if (IS_ERR(regs)) 1474 return PTR_ERR(regs); 1475 1476 if (of_device_is_compatible(np, "fsl,imx943-micfil")) 1477 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1478 regs, 1479 &fsl_micfil_regmap_config_v2); 1480 else 1481 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1482 regs, 1483 &fsl_micfil_regmap_config); 1484 if (IS_ERR(micfil->regmap)) { 1485 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1486 PTR_ERR(micfil->regmap)); 1487 return PTR_ERR(micfil->regmap); 1488 } 1489 1490 /* dataline mask for RX */ 1491 ret = of_property_read_u32_index(np, 1492 "fsl,dataline", 1493 0, 1494 &micfil->dataline); 1495 if (ret) 1496 micfil->dataline = 1; 1497 1498 if (micfil->dataline & ~micfil->soc->dataline) { 1499 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1500 micfil->soc->dataline); 1501 return -EINVAL; 1502 } 1503 1504 /* get IRQs */ 1505 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1506 micfil->irq[i] = platform_get_irq(pdev, i); 1507 if (micfil->irq[i] < 0) 1508 return micfil->irq[i]; 1509 } 1510 1511 /* Digital Microphone interface interrupt */ 1512 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1513 micfil_isr, IRQF_SHARED, 1514 micfil->name, micfil); 1515 if (ret) { 1516 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1517 micfil->irq[0]); 1518 return ret; 1519 } 1520 1521 /* Digital Microphone interface error interrupt */ 1522 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1523 micfil_err_isr, IRQF_SHARED, 1524 micfil->name, micfil); 1525 if (ret) { 1526 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1527 micfil->irq[1]); 1528 return ret; 1529 } 1530 1531 /* Digital Microphone interface voice activity detector event */ 1532 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1533 hwvad_isr, voice_detected_fn, 1534 IRQF_SHARED, micfil->name, micfil); 1535 if (ret) { 1536 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1537 micfil->irq[0]); 1538 return ret; 1539 } 1540 1541 /* Digital Microphone interface voice activity detector error */ 1542 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1543 hwvad_err_isr, IRQF_SHARED, 1544 micfil->name, micfil); 1545 if (ret) { 1546 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1547 micfil->irq[1]); 1548 return ret; 1549 } 1550 1551 micfil->dma_params_rx.chan_name = "rx"; 1552 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset; 1553 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1554 1555 platform_set_drvdata(pdev, micfil); 1556 1557 pm_runtime_enable(&pdev->dev); 1558 if (!pm_runtime_enabled(&pdev->dev)) { 1559 ret = fsl_micfil_runtime_resume(&pdev->dev); 1560 if (ret) 1561 goto err_pm_disable; 1562 } 1563 1564 ret = pm_runtime_resume_and_get(&pdev->dev); 1565 if (ret < 0) 1566 goto err_pm_get_sync; 1567 1568 /* Get micfil version */ 1569 ret = fsl_micfil_use_verid(&pdev->dev); 1570 if (ret < 0) 1571 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret); 1572 1573 ret = pm_runtime_put_sync(&pdev->dev); 1574 if (ret < 0 && ret != -ENOSYS) 1575 goto err_pm_get_sync; 1576 1577 regcache_cache_only(micfil->regmap, true); 1578 1579 /* 1580 * Register platform component before registering cpu dai for there 1581 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1582 */ 1583 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1584 if (ret) { 1585 dev_err(&pdev->dev, "failed to pcm register\n"); 1586 goto err_pm_disable; 1587 } 1588 1589 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1590 1591 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1592 &fsl_micfil_dai, 1); 1593 if (ret) { 1594 dev_err(&pdev->dev, "failed to register component %s\n", 1595 fsl_micfil_component.name); 1596 goto err_pm_disable; 1597 } 1598 1599 return ret; 1600 1601 err_pm_get_sync: 1602 if (!pm_runtime_status_suspended(&pdev->dev)) 1603 fsl_micfil_runtime_suspend(&pdev->dev); 1604 err_pm_disable: 1605 pm_runtime_disable(&pdev->dev); 1606 1607 return ret; 1608 } 1609 1610 static void fsl_micfil_remove(struct platform_device *pdev) 1611 { 1612 pm_runtime_disable(&pdev->dev); 1613 } 1614 1615 static int fsl_micfil_runtime_suspend(struct device *dev) 1616 { 1617 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1618 1619 regcache_cache_only(micfil->regmap, true); 1620 1621 if (micfil->mclk_flag) 1622 clk_disable_unprepare(micfil->mclk); 1623 clk_disable_unprepare(micfil->busclk); 1624 1625 return 0; 1626 } 1627 1628 static int fsl_micfil_runtime_resume(struct device *dev) 1629 { 1630 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1631 int ret; 1632 1633 ret = clk_prepare_enable(micfil->busclk); 1634 if (ret < 0) 1635 return ret; 1636 1637 if (micfil->mclk_flag) { 1638 ret = clk_prepare_enable(micfil->mclk); 1639 if (ret < 0) { 1640 clk_disable_unprepare(micfil->busclk); 1641 return ret; 1642 } 1643 } 1644 1645 regcache_cache_only(micfil->regmap, false); 1646 regcache_mark_dirty(micfil->regmap); 1647 regcache_sync(micfil->regmap); 1648 1649 return 0; 1650 } 1651 1652 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1653 RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, fsl_micfil_runtime_resume, NULL) 1654 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1655 }; 1656 1657 static struct platform_driver fsl_micfil_driver = { 1658 .probe = fsl_micfil_probe, 1659 .remove = fsl_micfil_remove, 1660 .driver = { 1661 .name = "fsl-micfil-dai", 1662 .pm = pm_ptr(&fsl_micfil_pm_ops), 1663 .of_match_table = fsl_micfil_dt_ids, 1664 }, 1665 }; 1666 module_platform_driver(fsl_micfil_driver); 1667 1668 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1669 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1670 MODULE_LICENSE("Dual BSD/GPL"); 1671