1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio codec driver for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <linux/dma-mapping.h> 22 #include <asm/io.h> 23 #include <sound/core.h> 24 #include <sound/hda_codec.h> 25 #include "hda_local.h" 26 #include "hda_auto_parser.h" 27 #include "hda_jack.h" 28 #include "generic.h" 29 30 #include "ca0132_regs.h" 31 32 /* Enable this to see controls for tuning purpose. */ 33 #define ENABLE_TUNING_CONTROLS 34 35 #ifdef ENABLE_TUNING_CONTROLS 36 #include <sound/tlv.h> 37 #endif 38 39 #define FLOAT_ZERO 0x00000000 40 #define FLOAT_ONE 0x3f800000 41 #define FLOAT_TWO 0x40000000 42 #define FLOAT_THREE 0x40400000 43 #define FLOAT_FIVE 0x40a00000 44 #define FLOAT_SIX 0x40c00000 45 #define FLOAT_EIGHT 0x41000000 46 #define FLOAT_MINUS_5 0xc0a00000 47 48 #define UNSOL_TAG_DSP 0x16 49 50 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 51 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 52 53 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 54 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 55 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 56 57 #define MASTERCONTROL 0x80 58 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 59 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 60 61 #define WIDGET_CHIP_CTRL 0x15 62 #define WIDGET_DSP_CTRL 0x16 63 64 #define MEM_CONNID_MICIN1 3 65 #define MEM_CONNID_MICIN2 5 66 #define MEM_CONNID_MICOUT1 12 67 #define MEM_CONNID_MICOUT2 14 68 #define MEM_CONNID_WUH 10 69 #define MEM_CONNID_DSP 16 70 #define MEM_CONNID_DMIC 100 71 72 #define SCP_SET 0 73 #define SCP_GET 1 74 75 #define EFX_FILE "ctefx.bin" 76 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 77 #define R3DI_EFX_FILE "ctefx-r3di.bin" 78 79 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 80 MODULE_FIRMWARE(EFX_FILE); 81 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 82 MODULE_FIRMWARE(R3DI_EFX_FILE); 83 #endif 84 85 static const char *const dirstr[2] = { "Playback", "Capture" }; 86 87 #define NUM_OF_OUTPUTS 2 88 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 89 enum { 90 SPEAKER_OUT, 91 HEADPHONE_OUT, 92 }; 93 94 enum { 95 DIGITAL_MIC, 96 LINE_MIC_IN 97 }; 98 99 /* Strings for Input Source Enum Control */ 100 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 101 #define IN_SRC_NUM_OF_INPUTS 3 102 enum { 103 REAR_MIC, 104 REAR_LINE_IN, 105 FRONT_MIC, 106 }; 107 108 enum { 109 #define VNODE_START_NID 0x80 110 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 111 VNID_MIC, 112 VNID_HP_SEL, 113 VNID_AMIC1_SEL, 114 VNID_HP_ASEL, 115 VNID_AMIC1_ASEL, 116 VNODE_END_NID, 117 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 118 119 #define EFFECT_START_NID 0x90 120 #define OUT_EFFECT_START_NID EFFECT_START_NID 121 SURROUND = OUT_EFFECT_START_NID, 122 CRYSTALIZER, 123 DIALOG_PLUS, 124 SMART_VOLUME, 125 X_BASS, 126 EQUALIZER, 127 OUT_EFFECT_END_NID, 128 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 129 130 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 131 ECHO_CANCELLATION = IN_EFFECT_START_NID, 132 VOICE_FOCUS, 133 MIC_SVM, 134 NOISE_REDUCTION, 135 IN_EFFECT_END_NID, 136 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 137 138 VOICEFX = IN_EFFECT_END_NID, 139 PLAY_ENHANCEMENT, 140 CRYSTAL_VOICE, 141 EFFECT_END_NID, 142 OUTPUT_SOURCE_ENUM, 143 INPUT_SOURCE_ENUM, 144 XBASS_XOVER, 145 EQ_PRESET_ENUM, 146 SMART_VOLUME_ENUM, 147 MIC_BOOST_ENUM, 148 AE5_HEADPHONE_GAIN_ENUM, 149 AE5_SOUND_FILTER_ENUM, 150 ZXR_HEADPHONE_GAIN, 151 SPEAKER_CHANNEL_CFG_ENUM, 152 SPEAKER_FULL_RANGE_FRONT, 153 SPEAKER_FULL_RANGE_REAR, 154 BASS_REDIRECTION, 155 BASS_REDIRECTION_XOVER, 156 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 157 }; 158 159 /* Effects values size*/ 160 #define EFFECT_VALS_MAX_COUNT 12 161 162 /* 163 * Default values for the effect slider controls, they are in order of their 164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 165 * X-bass. 166 */ 167 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 168 /* Amount of effect level sliders for ca0132_alt controls. */ 169 #define EFFECT_LEVEL_SLIDERS 5 170 171 /* Latency introduced by DSP blocks in milliseconds. */ 172 #define DSP_CAPTURE_INIT_LATENCY 0 173 #define DSP_CRYSTAL_VOICE_LATENCY 124 174 #define DSP_PLAYBACK_INIT_LATENCY 13 175 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 176 #define DSP_SPEAKER_OUT_LATENCY 7 177 178 struct ct_effect { 179 const char *name; 180 hda_nid_t nid; 181 int mid; /*effect module ID*/ 182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 183 int direct; /* 0:output; 1:input*/ 184 int params; /* number of default non-on/off params */ 185 /*effect default values, 1st is on/off. */ 186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 187 }; 188 189 #define EFX_DIR_OUT 0 190 #define EFX_DIR_IN 1 191 192 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 193 { .name = "Surround", 194 .nid = SURROUND, 195 .mid = 0x96, 196 .reqs = {0, 1}, 197 .direct = EFX_DIR_OUT, 198 .params = 1, 199 .def_vals = {0x3F800000, 0x3F2B851F} 200 }, 201 { .name = "Crystalizer", 202 .nid = CRYSTALIZER, 203 .mid = 0x96, 204 .reqs = {7, 8}, 205 .direct = EFX_DIR_OUT, 206 .params = 1, 207 .def_vals = {0x3F800000, 0x3F266666} 208 }, 209 { .name = "Dialog Plus", 210 .nid = DIALOG_PLUS, 211 .mid = 0x96, 212 .reqs = {2, 3}, 213 .direct = EFX_DIR_OUT, 214 .params = 1, 215 .def_vals = {0x00000000, 0x3F000000} 216 }, 217 { .name = "Smart Volume", 218 .nid = SMART_VOLUME, 219 .mid = 0x96, 220 .reqs = {4, 5, 6}, 221 .direct = EFX_DIR_OUT, 222 .params = 2, 223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 224 }, 225 { .name = "X-Bass", 226 .nid = X_BASS, 227 .mid = 0x96, 228 .reqs = {24, 23, 25}, 229 .direct = EFX_DIR_OUT, 230 .params = 2, 231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 232 }, 233 { .name = "Equalizer", 234 .nid = EQUALIZER, 235 .mid = 0x96, 236 .reqs = {9, 10, 11, 12, 13, 14, 237 15, 16, 17, 18, 19, 20}, 238 .direct = EFX_DIR_OUT, 239 .params = 11, 240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 241 0x00000000, 0x00000000, 0x00000000, 0x00000000, 242 0x00000000, 0x00000000, 0x00000000, 0x00000000} 243 }, 244 { .name = "Echo Cancellation", 245 .nid = ECHO_CANCELLATION, 246 .mid = 0x95, 247 .reqs = {0, 1, 2, 3}, 248 .direct = EFX_DIR_IN, 249 .params = 3, 250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 251 }, 252 { .name = "Voice Focus", 253 .nid = VOICE_FOCUS, 254 .mid = 0x95, 255 .reqs = {6, 7, 8, 9}, 256 .direct = EFX_DIR_IN, 257 .params = 3, 258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 259 }, 260 { .name = "Mic SVM", 261 .nid = MIC_SVM, 262 .mid = 0x95, 263 .reqs = {44, 45}, 264 .direct = EFX_DIR_IN, 265 .params = 1, 266 .def_vals = {0x00000000, 0x3F3D70A4} 267 }, 268 { .name = "Noise Reduction", 269 .nid = NOISE_REDUCTION, 270 .mid = 0x95, 271 .reqs = {4, 5}, 272 .direct = EFX_DIR_IN, 273 .params = 1, 274 .def_vals = {0x3F800000, 0x3F000000} 275 }, 276 { .name = "VoiceFX", 277 .nid = VOICEFX, 278 .mid = 0x95, 279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 280 .direct = EFX_DIR_IN, 281 .params = 8, 282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 284 0x00000000} 285 } 286 }; 287 288 /* Tuning controls */ 289 #ifdef ENABLE_TUNING_CONTROLS 290 291 enum { 292 #define TUNING_CTL_START_NID 0xC0 293 WEDGE_ANGLE = TUNING_CTL_START_NID, 294 SVM_LEVEL, 295 EQUALIZER_BAND_0, 296 EQUALIZER_BAND_1, 297 EQUALIZER_BAND_2, 298 EQUALIZER_BAND_3, 299 EQUALIZER_BAND_4, 300 EQUALIZER_BAND_5, 301 EQUALIZER_BAND_6, 302 EQUALIZER_BAND_7, 303 EQUALIZER_BAND_8, 304 EQUALIZER_BAND_9, 305 TUNING_CTL_END_NID 306 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 307 }; 308 309 struct ct_tuning_ctl { 310 const char *name; 311 hda_nid_t parent_nid; 312 hda_nid_t nid; 313 int mid; /*effect module ID*/ 314 int req; /*effect module request*/ 315 int direct; /* 0:output; 1:input*/ 316 unsigned int def_val;/*effect default values*/ 317 }; 318 319 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 320 { .name = "Wedge Angle", 321 .parent_nid = VOICE_FOCUS, 322 .nid = WEDGE_ANGLE, 323 .mid = 0x95, 324 .req = 8, 325 .direct = EFX_DIR_IN, 326 .def_val = 0x41F00000 327 }, 328 { .name = "SVM Level", 329 .parent_nid = MIC_SVM, 330 .nid = SVM_LEVEL, 331 .mid = 0x95, 332 .req = 45, 333 .direct = EFX_DIR_IN, 334 .def_val = 0x3F3D70A4 335 }, 336 { .name = "EQ Band0", 337 .parent_nid = EQUALIZER, 338 .nid = EQUALIZER_BAND_0, 339 .mid = 0x96, 340 .req = 11, 341 .direct = EFX_DIR_OUT, 342 .def_val = 0x00000000 343 }, 344 { .name = "EQ Band1", 345 .parent_nid = EQUALIZER, 346 .nid = EQUALIZER_BAND_1, 347 .mid = 0x96, 348 .req = 12, 349 .direct = EFX_DIR_OUT, 350 .def_val = 0x00000000 351 }, 352 { .name = "EQ Band2", 353 .parent_nid = EQUALIZER, 354 .nid = EQUALIZER_BAND_2, 355 .mid = 0x96, 356 .req = 13, 357 .direct = EFX_DIR_OUT, 358 .def_val = 0x00000000 359 }, 360 { .name = "EQ Band3", 361 .parent_nid = EQUALIZER, 362 .nid = EQUALIZER_BAND_3, 363 .mid = 0x96, 364 .req = 14, 365 .direct = EFX_DIR_OUT, 366 .def_val = 0x00000000 367 }, 368 { .name = "EQ Band4", 369 .parent_nid = EQUALIZER, 370 .nid = EQUALIZER_BAND_4, 371 .mid = 0x96, 372 .req = 15, 373 .direct = EFX_DIR_OUT, 374 .def_val = 0x00000000 375 }, 376 { .name = "EQ Band5", 377 .parent_nid = EQUALIZER, 378 .nid = EQUALIZER_BAND_5, 379 .mid = 0x96, 380 .req = 16, 381 .direct = EFX_DIR_OUT, 382 .def_val = 0x00000000 383 }, 384 { .name = "EQ Band6", 385 .parent_nid = EQUALIZER, 386 .nid = EQUALIZER_BAND_6, 387 .mid = 0x96, 388 .req = 17, 389 .direct = EFX_DIR_OUT, 390 .def_val = 0x00000000 391 }, 392 { .name = "EQ Band7", 393 .parent_nid = EQUALIZER, 394 .nid = EQUALIZER_BAND_7, 395 .mid = 0x96, 396 .req = 18, 397 .direct = EFX_DIR_OUT, 398 .def_val = 0x00000000 399 }, 400 { .name = "EQ Band8", 401 .parent_nid = EQUALIZER, 402 .nid = EQUALIZER_BAND_8, 403 .mid = 0x96, 404 .req = 19, 405 .direct = EFX_DIR_OUT, 406 .def_val = 0x00000000 407 }, 408 { .name = "EQ Band9", 409 .parent_nid = EQUALIZER, 410 .nid = EQUALIZER_BAND_9, 411 .mid = 0x96, 412 .req = 20, 413 .direct = EFX_DIR_OUT, 414 .def_val = 0x00000000 415 } 416 }; 417 #endif 418 419 /* Voice FX Presets */ 420 #define VOICEFX_MAX_PARAM_COUNT 9 421 422 struct ct_voicefx { 423 const char *name; 424 hda_nid_t nid; 425 int mid; 426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 427 }; 428 429 struct ct_voicefx_preset { 430 const char *name; /*preset name*/ 431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 432 }; 433 434 static const struct ct_voicefx ca0132_voicefx = { 435 .name = "VoiceFX Capture Switch", 436 .nid = VOICEFX, 437 .mid = 0x95, 438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 439 }; 440 441 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 442 { .name = "Neutral", 443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 444 0x44FA0000, 0x3F800000, 0x3F800000, 445 0x3F800000, 0x00000000, 0x00000000 } 446 }, 447 { .name = "Female2Male", 448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 449 0x44FA0000, 0x3F19999A, 0x3F866666, 450 0x3F800000, 0x00000000, 0x00000000 } 451 }, 452 { .name = "Male2Female", 453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 454 0x450AC000, 0x4017AE14, 0x3F6B851F, 455 0x3F800000, 0x00000000, 0x00000000 } 456 }, 457 { .name = "ScrappyKid", 458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 459 0x44FA0000, 0x40400000, 0x3F28F5C3, 460 0x3F800000, 0x00000000, 0x00000000 } 461 }, 462 { .name = "Elderly", 463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 464 0x44E10000, 0x3FB33333, 0x3FB9999A, 465 0x3F800000, 0x3E3A2E43, 0x00000000 } 466 }, 467 { .name = "Orc", 468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 469 0x45098000, 0x3F266666, 0x3FC00000, 470 0x3F800000, 0x00000000, 0x00000000 } 471 }, 472 { .name = "Elf", 473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 474 0x45193000, 0x3F8E147B, 0x3F75C28F, 475 0x3F800000, 0x00000000, 0x00000000 } 476 }, 477 { .name = "Dwarf", 478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 479 0x45007000, 0x3F451EB8, 0x3F7851EC, 480 0x3F800000, 0x00000000, 0x00000000 } 481 }, 482 { .name = "AlienBrute", 483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 484 0x451F6000, 0x3F266666, 0x3FA7D945, 485 0x3F800000, 0x3CF5C28F, 0x00000000 } 486 }, 487 { .name = "Robot", 488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 489 0x44FA0000, 0x3FB2718B, 0x3F800000, 490 0xBC07010E, 0x00000000, 0x00000000 } 491 }, 492 { .name = "Marine", 493 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 495 0x3F0A3D71, 0x00000000, 0x00000000 } 496 }, 497 { .name = "Emo", 498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 499 0x44FA0000, 0x3F800000, 0x3F800000, 500 0x3E4CCCCD, 0x00000000, 0x00000000 } 501 }, 502 { .name = "DeepVoice", 503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 505 0x3F800000, 0x00000000, 0x00000000 } 506 }, 507 { .name = "Munchkin", 508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 509 0x44FA0000, 0x3F800000, 0x3F1A043C, 510 0x3F800000, 0x00000000, 0x00000000 } 511 } 512 }; 513 514 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 515 516 #define EQ_PRESET_MAX_PARAM_COUNT 11 517 518 struct ct_eq { 519 const char *name; 520 hda_nid_t nid; 521 int mid; 522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 523 }; 524 525 struct ct_eq_preset { 526 const char *name; /*preset name*/ 527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 528 }; 529 530 static const struct ct_eq ca0132_alt_eq_enum = { 531 .name = "FX: Equalizer Preset Switch", 532 .nid = EQ_PRESET_ENUM, 533 .mid = 0x96, 534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 535 }; 536 537 538 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 539 { .name = "Flat", 540 .vals = { 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000, 0x00000000, 542 0x00000000, 0x00000000, 0x00000000, 543 0x00000000, 0x00000000 } 544 }, 545 { .name = "Acoustic", 546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 547 0x40000000, 0x00000000, 0x00000000, 548 0x00000000, 0x00000000, 0x40000000, 549 0x40000000, 0x40000000 } 550 }, 551 { .name = "Classical", 552 .vals = { 0x00000000, 0x00000000, 0x40C00000, 553 0x40C00000, 0x40466666, 0x00000000, 554 0x00000000, 0x00000000, 0x00000000, 555 0x40466666, 0x40466666 } 556 }, 557 { .name = "Country", 558 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 560 0x00000000, 0x00000000, 0x40000000, 561 0x40466666, 0x40800000 } 562 }, 563 { .name = "Dance", 564 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 565 0x40466666, 0x40866666, 0xBF99999A, 566 0xBF99999A, 0x00000000, 0x00000000, 567 0x40800000, 0x40800000 } 568 }, 569 { .name = "Jazz", 570 .vals = { 0x00000000, 0x00000000, 0x00000000, 571 0x3F8CCCCD, 0x40800000, 0x40800000, 572 0x40800000, 0x00000000, 0x3F8CCCCD, 573 0x40466666, 0x40466666 } 574 }, 575 { .name = "New Age", 576 .vals = { 0x00000000, 0x00000000, 0x40000000, 577 0x40000000, 0x00000000, 0x00000000, 578 0x00000000, 0x3F8CCCCD, 0x40000000, 579 0x40000000, 0x40000000 } 580 }, 581 { .name = "Pop", 582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 583 0x40000000, 0x40000000, 0x00000000, 584 0xBF99999A, 0xBF99999A, 0x00000000, 585 0x40466666, 0x40C00000 } 586 }, 587 { .name = "Rock", 588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 589 0x3F8CCCCD, 0x40000000, 0xBF99999A, 590 0xBF99999A, 0x00000000, 0x00000000, 591 0x40800000, 0x40800000 } 592 }, 593 { .name = "Vocal", 594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 595 0xBF99999A, 0x00000000, 0x40466666, 596 0x40800000, 0x40466666, 0x00000000, 597 0x00000000, 0x3F8CCCCD } 598 } 599 }; 600 601 /* 602 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 603 * set as not being full range, and bass redirection is enabled, all 604 * frequencies below the crossover frequency are redirected to the LFE 605 * channel. If the surround configuration has no LFE channel, this can't be 606 * enabled. X-Bass must be disabled when using these. 607 */ 608 enum speaker_range_reqs { 609 SPEAKER_BASS_REDIRECT = 0x15, 610 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 611 /* Between 0x16-0x1a are the X-Bass reqs. */ 612 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 613 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 614 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 615 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 616 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 617 }; 618 619 /* 620 * Definitions for the DSP req's to handle speaker tuning. These all belong to 621 * module ID 0x96, the output effects module. 622 */ 623 enum speaker_tuning_reqs { 624 /* 625 * Currently, this value is always set to 0.0f. However, on Windows, 626 * when selecting certain headphone profiles on the new Sound Blaster 627 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 628 * sent. This gets the speaker EQ address area, which is then used to 629 * send over (presumably) an equalizer profile for the specific 630 * headphone setup. It is sent using the same method the DSP 631 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 632 * file exists in linux firmware tree but goes unused. It would also 633 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 634 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 635 * set to 1.0f. 636 */ 637 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 638 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 639 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 640 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 641 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 642 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 643 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 644 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 645 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 646 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 647 /* 648 * Inversion is used when setting headphone virtualization to line 649 * out. Not sure why this is, but it's the only place it's ever used. 650 */ 651 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 652 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 653 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 654 SPEAKER_TUNING_LFE_INVERT = 0x2c, 655 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 656 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 657 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 658 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 659 /* Delay is used when setting surround speaker distance in Windows. */ 660 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 661 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 662 SPEAKER_TUNING_CENTER_DELAY = 0x33, 663 SPEAKER_TUNING_LFE_DELAY = 0x34, 664 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 665 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 666 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 667 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 668 /* Of these two, only mute seems to ever be used. */ 669 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 670 SPEAKER_TUNING_MUTE = 0x3a, 671 }; 672 673 /* Surround output channel count configuration structures. */ 674 #define SPEAKER_CHANNEL_CFG_COUNT 5 675 enum { 676 SPEAKER_CHANNELS_2_0, 677 SPEAKER_CHANNELS_2_1, 678 SPEAKER_CHANNELS_4_0, 679 SPEAKER_CHANNELS_4_1, 680 SPEAKER_CHANNELS_5_1, 681 }; 682 683 struct ca0132_alt_speaker_channel_cfg { 684 const char *name; 685 unsigned int val; 686 }; 687 688 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 689 { .name = "2.0", 690 .val = FLOAT_ONE 691 }, 692 { .name = "2.1", 693 .val = FLOAT_TWO 694 }, 695 { .name = "4.0", 696 .val = FLOAT_FIVE 697 }, 698 { .name = "4.1", 699 .val = FLOAT_SIX 700 }, 701 { .name = "5.1", 702 .val = FLOAT_EIGHT 703 } 704 }; 705 706 /* 707 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 708 * and I don't know what the third req is, but it's always zero. I assume it's 709 * some sort of update or set command to tell the DSP there's new volume info. 710 */ 711 #define DSP_VOL_OUT 0 712 #define DSP_VOL_IN 1 713 714 struct ct_dsp_volume_ctl { 715 hda_nid_t vnid; 716 int mid; /* module ID*/ 717 unsigned int reqs[3]; /* scp req ID */ 718 }; 719 720 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 721 { .vnid = VNID_SPK, 722 .mid = 0x32, 723 .reqs = {3, 4, 2} 724 }, 725 { .vnid = VNID_MIC, 726 .mid = 0x37, 727 .reqs = {2, 3, 1} 728 } 729 }; 730 731 /* Values for ca0113_mmio_command_set for selecting output. */ 732 #define AE_CA0113_OUT_SET_COMMANDS 6 733 struct ae_ca0113_output_set { 734 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 735 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 736 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 737 }; 738 739 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 740 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 741 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 742 /* Speakers. */ 743 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 744 /* Headphones. */ 745 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 746 }; 747 748 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 749 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 750 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 751 /* Speakers. */ 752 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 753 /* Headphones. */ 754 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 755 }; 756 757 /* ae5 ca0113 command sequences to set headphone gain levels. */ 758 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 759 struct ae5_headphone_gain_set { 760 const char *name; 761 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 762 }; 763 764 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 765 { .name = "Low (16-31", 766 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 767 }, 768 { .name = "Medium (32-149", 769 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 770 }, 771 { .name = "High (150-600", 772 .vals = { 0xff, 0xff, 0xff, 0x7f } 773 } 774 }; 775 776 struct ae5_filter_set { 777 const char *name; 778 unsigned int val; 779 }; 780 781 static const struct ae5_filter_set ae5_filter_presets[] = { 782 { .name = "Slow Roll Off", 783 .val = 0xa0 784 }, 785 { .name = "Minimum Phase", 786 .val = 0xc0 787 }, 788 { .name = "Fast Roll Off", 789 .val = 0x80 790 } 791 }; 792 793 /* 794 * Data structures for storing audio router remapping data. These are used to 795 * remap a currently active streams ports. 796 */ 797 struct chipio_stream_remap_data { 798 unsigned int stream_id; 799 unsigned int count; 800 801 unsigned int offset[16]; 802 unsigned int value[16]; 803 }; 804 805 static const struct chipio_stream_remap_data stream_remap_data[] = { 806 { .stream_id = 0x14, 807 .count = 0x04, 808 .offset = { 0x00, 0x04, 0x08, 0x0c }, 809 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 810 }, 811 { .stream_id = 0x0c, 812 .count = 0x0c, 813 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 814 0x20, 0x24, 0x28, 0x2c }, 815 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 816 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 817 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 818 }, 819 { .stream_id = 0x0c, 820 .count = 0x08, 821 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 822 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 823 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 824 } 825 }; 826 827 enum hda_cmd_vendor_io { 828 /* for DspIO node */ 829 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 830 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 831 832 VENDOR_DSPIO_STATUS = 0xF01, 833 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 834 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 835 VENDOR_DSPIO_DSP_INIT = 0x703, 836 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 837 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 838 839 /* for ChipIO node */ 840 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 841 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 842 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 843 VENDOR_CHIPIO_DATA_LOW = 0x300, 844 VENDOR_CHIPIO_DATA_HIGH = 0x400, 845 846 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 847 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 848 849 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 850 VENDOR_CHIPIO_STATUS = 0xF01, 851 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 852 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 853 854 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 855 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 856 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 857 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 858 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 859 860 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 861 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 862 863 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 864 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 865 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 866 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 867 VENDOR_CHIPIO_FLAG_SET = 0x70F, 868 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 869 VENDOR_CHIPIO_PARAM_SET = 0x710, 870 VENDOR_CHIPIO_PARAM_GET = 0xF10, 871 872 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 873 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 874 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 875 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 876 877 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 878 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 879 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 880 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 881 882 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 883 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 884 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 885 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 886 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 887 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 888 889 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 890 }; 891 892 /* 893 * Control flag IDs 894 */ 895 enum control_flag_id { 896 /* Connection manager stream setup is bypassed/enabled */ 897 CONTROL_FLAG_C_MGR = 0, 898 /* DSP DMA is bypassed/enabled */ 899 CONTROL_FLAG_DMA = 1, 900 /* 8051 'idle' mode is disabled/enabled */ 901 CONTROL_FLAG_IDLE_ENABLE = 2, 902 /* Tracker for the SPDIF-in path is bypassed/enabled */ 903 CONTROL_FLAG_TRACKER = 3, 904 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 905 CONTROL_FLAG_SPDIF2OUT = 4, 906 /* Digital Microphone is disabled/enabled */ 907 CONTROL_FLAG_DMIC = 5, 908 /* ADC_B rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_B_96KHZ = 6, 910 /* ADC_C rate is 48 kHz/96 kHz */ 911 CONTROL_FLAG_ADC_C_96KHZ = 7, 912 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 913 CONTROL_FLAG_DAC_96KHZ = 8, 914 /* DSP rate is 48 kHz/96 kHz */ 915 CONTROL_FLAG_DSP_96KHZ = 9, 916 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 917 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 918 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 919 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 920 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 921 CONTROL_FLAG_DECODE_LOOP = 12, 922 /* De-emphasis filter on DAC-1 disabled/enabled */ 923 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 924 /* De-emphasis filter on DAC-2 disabled/enabled */ 925 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 926 /* De-emphasis filter on DAC-3 disabled/enabled */ 927 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 928 /* High-pass filter on ADC_B disabled/enabled */ 929 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 930 /* High-pass filter on ADC_C disabled/enabled */ 931 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 932 /* Common mode on Port_A disabled/enabled */ 933 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 934 /* Common mode on Port_D disabled/enabled */ 935 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 936 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 938 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 939 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 940 /* ASI rate is 48kHz/96kHz */ 941 CONTROL_FLAG_ASI_96KHZ = 22, 942 /* DAC power settings able to control attached ports no/yes */ 943 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 944 /* Clock Stop OK reporting is disabled/enabled */ 945 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 946 /* Number of control flags */ 947 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 948 }; 949 950 /* 951 * Control parameter IDs 952 */ 953 enum control_param_id { 954 /* 0: None, 1: Mic1In*/ 955 CONTROL_PARAM_VIP_SOURCE = 1, 956 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 957 CONTROL_PARAM_SPDIF1_SOURCE = 2, 958 /* Port A output stage gain setting to use when 16 Ohm output 959 * impedance is selected*/ 960 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 961 /* Port D output stage gain setting to use when 16 Ohm output 962 * impedance is selected*/ 963 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 964 965 /* 966 * This control param name was found in the 8051 memory, and makes 967 * sense given the fact the AE-5 uses it and has the ASI flag set. 968 */ 969 CONTROL_PARAM_ASI = 23, 970 971 /* Stream Control */ 972 973 /* Select stream with the given ID */ 974 CONTROL_PARAM_STREAM_ID = 24, 975 /* Source connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 977 /* Destination connection point for the selected stream */ 978 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 979 /* Number of audio channels in the selected stream */ 980 CONTROL_PARAM_STREAMS_CHANNELS = 27, 981 /*Enable control for the selected stream */ 982 CONTROL_PARAM_STREAM_CONTROL = 28, 983 984 /* Connection Point Control */ 985 986 /* Select connection point with the given ID */ 987 CONTROL_PARAM_CONN_POINT_ID = 29, 988 /* Connection point sample rate */ 989 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 990 991 /* Node Control */ 992 993 /* Select HDA node with the given ID */ 994 CONTROL_PARAM_NODE_ID = 31 995 }; 996 997 /* 998 * Dsp Io Status codes 999 */ 1000 enum hda_vendor_status_dspio { 1001 /* Success */ 1002 VENDOR_STATUS_DSPIO_OK = 0x00, 1003 /* Busy, unable to accept new command, the host must retry */ 1004 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1005 /* SCP command queue is full */ 1006 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1007 /* SCP response queue is empty */ 1008 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1009 }; 1010 1011 /* 1012 * Chip Io Status codes 1013 */ 1014 enum hda_vendor_status_chipio { 1015 /* Success */ 1016 VENDOR_STATUS_CHIPIO_OK = 0x00, 1017 /* Busy, unable to accept new command, the host must retry */ 1018 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1019 }; 1020 1021 /* 1022 * CA0132 sample rate 1023 */ 1024 enum ca0132_sample_rate { 1025 SR_6_000 = 0x00, 1026 SR_8_000 = 0x01, 1027 SR_9_600 = 0x02, 1028 SR_11_025 = 0x03, 1029 SR_16_000 = 0x04, 1030 SR_22_050 = 0x05, 1031 SR_24_000 = 0x06, 1032 SR_32_000 = 0x07, 1033 SR_44_100 = 0x08, 1034 SR_48_000 = 0x09, 1035 SR_88_200 = 0x0A, 1036 SR_96_000 = 0x0B, 1037 SR_144_000 = 0x0C, 1038 SR_176_400 = 0x0D, 1039 SR_192_000 = 0x0E, 1040 SR_384_000 = 0x0F, 1041 1042 SR_COUNT = 0x10, 1043 1044 SR_RATE_UNKNOWN = 0x1F 1045 }; 1046 1047 enum dsp_download_state { 1048 DSP_DOWNLOAD_FAILED = -1, 1049 DSP_DOWNLOAD_INIT = 0, 1050 DSP_DOWNLOADING = 1, 1051 DSP_DOWNLOADED = 2 1052 }; 1053 1054 /* retrieve parameters from hda format */ 1055 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1056 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1057 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1058 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1059 1060 /* 1061 * CA0132 specific 1062 */ 1063 1064 #define AE5_STRIP_MAX_LEDS 100 1065 1066 struct ca0132_spec { 1067 struct hda_gen_spec gen; 1068 1069 const struct snd_kcontrol_new *mixers[5]; 1070 unsigned int num_mixers; 1071 const struct hda_verb *base_init_verbs; 1072 const struct hda_verb *base_exit_verbs; 1073 const struct hda_verb *chip_init_verbs; 1074 const struct hda_verb *desktop_init_verbs; 1075 struct hda_verb *spec_init_verbs; 1076 struct auto_pin_cfg autocfg; 1077 1078 /* Nodes configurations */ 1079 struct hda_multi_out multiout; 1080 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1081 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1082 unsigned int num_outputs; 1083 hda_nid_t input_pins[AUTO_PIN_LAST]; 1084 hda_nid_t adcs[AUTO_PIN_LAST]; 1085 hda_nid_t dig_out; 1086 hda_nid_t dig_in; 1087 unsigned int num_inputs; 1088 hda_nid_t shared_mic_nid; 1089 hda_nid_t shared_out_nid; 1090 hda_nid_t unsol_tag_hp; 1091 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1092 hda_nid_t unsol_tag_amic1; 1093 1094 /* chip access */ 1095 struct mutex chipio_mutex; /* chip access mutex */ 1096 u32 curr_chip_addx; 1097 1098 /* DSP download related */ 1099 enum dsp_download_state dsp_state; 1100 unsigned int dsp_stream_id; 1101 unsigned int wait_scp; 1102 unsigned int wait_scp_header; 1103 unsigned int wait_num_data; 1104 unsigned int scp_resp_header; 1105 unsigned int scp_resp_data[4]; 1106 unsigned int scp_resp_count; 1107 bool startup_check_entered; 1108 bool dsp_reload; 1109 1110 /* mixer and effects related */ 1111 unsigned char dmic_ctl; 1112 int cur_out_type; 1113 int cur_mic_type; 1114 long vnode_lvol[VNODES_COUNT]; 1115 long vnode_rvol[VNODES_COUNT]; 1116 long vnode_lswitch[VNODES_COUNT]; 1117 long vnode_rswitch[VNODES_COUNT]; 1118 long effects_switch[EFFECTS_COUNT]; 1119 long voicefx_val; 1120 long cur_mic_boost; 1121 /* ca0132_alt control related values */ 1122 unsigned char in_enum_val; 1123 unsigned char out_enum_val; 1124 unsigned char channel_cfg_val; 1125 unsigned char speaker_range_val[2]; 1126 unsigned char mic_boost_enum_val; 1127 unsigned char smart_volume_setting; 1128 unsigned char bass_redirection_val; 1129 long bass_redirect_xover_freq; 1130 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1131 long xbass_xover_freq; 1132 long eq_preset_val; 1133 unsigned int tlv[4]; 1134 struct hda_vmaster_mute_hook vmaster_mute; 1135 /* AE-5 Control values */ 1136 unsigned char ae5_headphone_gain_val; 1137 unsigned char ae5_filter_val; 1138 /* ZxR Control Values */ 1139 unsigned char zxr_gain_set; 1140 1141 struct hda_codec *codec; 1142 struct delayed_work unsol_hp_work; 1143 1144 #ifdef ENABLE_TUNING_CONTROLS 1145 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1146 #endif 1147 /* 1148 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1149 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1150 * things. 1151 */ 1152 bool use_pci_mmio; 1153 void __iomem *mem_base; 1154 1155 /* 1156 * Whether or not to use the alt functions like alt_select_out, 1157 * alt_select_in, etc. Only used on desktop codecs for now, because of 1158 * surround sound support. 1159 */ 1160 bool use_alt_functions; 1161 1162 /* 1163 * Whether or not to use alt controls: volume effect sliders, EQ 1164 * presets, smart volume presets, and new control names with FX prefix. 1165 * Renames PlayEnhancement and CrystalVoice too. 1166 */ 1167 bool use_alt_controls; 1168 1169 #if IS_ENABLED(CONFIG_SND_HDA_DSP_LOADER) 1170 /* AE-5 WS2812 strip control */ 1171 struct mutex ae5_strip_mutex; 1172 u32 ae5_strip_cur_colors[AE5_STRIP_MAX_LEDS]; 1173 int ae5_strip_cur_num_leds; 1174 #endif 1175 }; 1176 1177 /* 1178 * CA0132 quirks table 1179 */ 1180 enum { 1181 QUIRK_ALIENWARE, 1182 QUIRK_ALIENWARE_M17XR4, 1183 QUIRK_SBZ, 1184 QUIRK_ZXR, 1185 QUIRK_ZXR_DBPRO, 1186 QUIRK_R3DI, 1187 QUIRK_R3D, 1188 QUIRK_AE5, 1189 QUIRK_AE7, 1190 QUIRK_GENERIC, 1191 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET, 1192 }; 1193 1194 #ifdef CONFIG_PCI 1195 #define ca0132_quirk(spec) ((spec)->codec->fixup_id) 1196 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1197 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1198 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1199 #else 1200 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1201 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1202 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1203 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1204 #endif 1205 1206 static const struct hda_pintbl alienware_pincfgs[] = { 1207 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1208 { 0x0c, 0x411111f0 }, /* N/A */ 1209 { 0x0d, 0x411111f0 }, /* N/A */ 1210 { 0x0e, 0x411111f0 }, /* N/A */ 1211 { 0x0f, 0x0321101f }, /* HP */ 1212 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1213 { 0x11, 0x03a11021 }, /* Mic */ 1214 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1215 { 0x13, 0x411111f0 }, /* N/A */ 1216 { 0x18, 0x411111f0 }, /* N/A */ 1217 {} 1218 }; 1219 1220 /* Sound Blaster Z pin configs taken from Windows Driver */ 1221 static const struct hda_pintbl sbz_pincfgs[] = { 1222 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1223 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1224 { 0x0d, 0x014510f0 }, /* Digital Out */ 1225 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1226 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1227 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1228 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1229 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1230 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1231 { 0x18, 0x50d000f0 }, /* N/A */ 1232 {} 1233 }; 1234 1235 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1236 static const struct hda_pintbl zxr_pincfgs[] = { 1237 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1238 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1239 { 0x0d, 0x014510f0 }, /* Digital Out */ 1240 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1241 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1242 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1243 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1244 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1245 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1246 { 0x18, 0x50d000f0 }, /* N/A */ 1247 {} 1248 }; 1249 1250 /* Recon3D pin configs taken from Windows Driver */ 1251 static const struct hda_pintbl r3d_pincfgs[] = { 1252 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1253 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1254 { 0x0d, 0x014510f0 }, /* Digital Out */ 1255 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1256 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1257 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1258 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1259 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1260 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1261 { 0x18, 0x50d000f0 }, /* N/A */ 1262 {} 1263 }; 1264 1265 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1266 static const struct hda_pintbl ae5_pincfgs[] = { 1267 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1268 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1269 { 0x0d, 0x014510f0 }, /* Digital Out */ 1270 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1271 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1272 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1273 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1274 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1275 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1276 { 0x18, 0x50d000f0 }, /* N/A */ 1277 {} 1278 }; 1279 1280 /* Recon3D integrated pin configs taken from Windows Driver */ 1281 static const struct hda_pintbl r3di_pincfgs[] = { 1282 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1283 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1284 { 0x0d, 0x014510f0 }, /* Digital Out */ 1285 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1286 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1287 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1288 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1289 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1290 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1291 { 0x18, 0x500000f0 }, /* N/A */ 1292 {} 1293 }; 1294 1295 static const struct hda_pintbl ae7_pincfgs[] = { 1296 { 0x0b, 0x01017010 }, 1297 { 0x0c, 0x014510f0 }, 1298 { 0x0d, 0x414510f0 }, 1299 { 0x0e, 0x01c520f0 }, 1300 { 0x0f, 0x01017114 }, 1301 { 0x10, 0x01017011 }, 1302 { 0x11, 0x018170ff }, 1303 { 0x12, 0x01a170f0 }, 1304 { 0x13, 0x908700f0 }, 1305 { 0x18, 0x500000f0 }, 1306 {} 1307 }; 1308 1309 static const struct hda_pintbl ca0132_generic_pincfgs[] = { 1310 { 0x0b, 0x41014111 }, 1311 { 0x0c, 0x414520f0 }, /* SPDIF out */ 1312 { 0x0d, 0x01014010 }, /* lineout */ 1313 { 0x0e, 0x41c501f0 }, 1314 { 0x0f, 0x411111f0 }, /* disabled */ 1315 { 0x10, 0x411111f0 }, /* disabled */ 1316 { 0x11, 0x41012014 }, 1317 { 0x12, 0x37a790f0 }, /* mic */ 1318 { 0x13, 0x77a701f0 }, 1319 { 0x18, 0x500000f0 }, 1320 {} 1321 }; 1322 1323 static const struct hda_quirk ca0132_quirks[] = { 1324 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1325 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1326 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1327 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1328 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1329 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1330 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1331 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1332 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1333 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1334 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1335 SND_PCI_QUIRK(0x1458, 0xA046, "Gigabyte GA-Z170X-Gaming G1", QUIRK_GENERIC), 1336 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1337 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1338 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1339 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1340 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1341 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1342 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1343 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1344 {} 1345 }; 1346 1347 static const struct hda_model_fixup ca0132_quirk_models[] = { 1348 { .id = QUIRK_ALIENWARE, .name = "alienware" }, 1349 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" }, 1350 { .id = QUIRK_SBZ, .name = "sbz" }, 1351 { .id = QUIRK_ZXR, .name = "zxr" }, 1352 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" }, 1353 { .id = QUIRK_R3DI, .name = "r3di" }, 1354 { .id = QUIRK_R3D, .name = "r3d" }, 1355 { .id = QUIRK_AE5, .name = "ae5" }, 1356 { .id = QUIRK_AE7, .name = "ae7" }, 1357 { .id = QUIRK_GENERIC, .name = "generic" }, 1358 {} 1359 }; 1360 1361 /* Output selection quirk info structures. */ 1362 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1363 #define MAX_QUIRK_SCP_SET_VALS 2 1364 struct ca0132_alt_out_set_info { 1365 unsigned int dac2port; /* ParamID 0x0d value. */ 1366 1367 bool has_hda_gpio; 1368 char hda_gpio_pin; 1369 char hda_gpio_set; 1370 1371 unsigned int mmio_gpio_count; 1372 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1373 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1374 1375 unsigned int scp_cmds_count; 1376 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1377 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1378 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1379 1380 bool has_chipio_write; 1381 unsigned int chipio_write_addr; 1382 unsigned int chipio_write_data; 1383 }; 1384 1385 struct ca0132_alt_out_set_quirk_data { 1386 int quirk_id; 1387 1388 bool has_headphone_gain; 1389 bool is_ae_series; 1390 1391 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1392 }; 1393 1394 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1395 { .quirk_id = QUIRK_R3DI, 1396 .has_headphone_gain = false, 1397 .is_ae_series = false, 1398 .out_set_info = { 1399 /* Speakers. */ 1400 { .dac2port = 0x24, 1401 .has_hda_gpio = true, 1402 .hda_gpio_pin = 2, 1403 .hda_gpio_set = 1, 1404 .mmio_gpio_count = 0, 1405 .scp_cmds_count = 0, 1406 .has_chipio_write = false, 1407 }, 1408 /* Headphones. */ 1409 { .dac2port = 0x21, 1410 .has_hda_gpio = true, 1411 .hda_gpio_pin = 2, 1412 .hda_gpio_set = 0, 1413 .mmio_gpio_count = 0, 1414 .scp_cmds_count = 0, 1415 .has_chipio_write = false, 1416 } }, 1417 }, 1418 { .quirk_id = QUIRK_R3D, 1419 .has_headphone_gain = false, 1420 .is_ae_series = false, 1421 .out_set_info = { 1422 /* Speakers. */ 1423 { .dac2port = 0x24, 1424 .has_hda_gpio = false, 1425 .mmio_gpio_count = 1, 1426 .mmio_gpio_pin = { 1 }, 1427 .mmio_gpio_set = { 1 }, 1428 .scp_cmds_count = 0, 1429 .has_chipio_write = false, 1430 }, 1431 /* Headphones. */ 1432 { .dac2port = 0x21, 1433 .has_hda_gpio = false, 1434 .mmio_gpio_count = 1, 1435 .mmio_gpio_pin = { 1 }, 1436 .mmio_gpio_set = { 0 }, 1437 .scp_cmds_count = 0, 1438 .has_chipio_write = false, 1439 } }, 1440 }, 1441 { .quirk_id = QUIRK_SBZ, 1442 .has_headphone_gain = false, 1443 .is_ae_series = false, 1444 .out_set_info = { 1445 /* Speakers. */ 1446 { .dac2port = 0x18, 1447 .has_hda_gpio = false, 1448 .mmio_gpio_count = 3, 1449 .mmio_gpio_pin = { 7, 4, 1 }, 1450 .mmio_gpio_set = { 0, 1, 1 }, 1451 .scp_cmds_count = 0, 1452 .has_chipio_write = false, }, 1453 /* Headphones. */ 1454 { .dac2port = 0x12, 1455 .has_hda_gpio = false, 1456 .mmio_gpio_count = 3, 1457 .mmio_gpio_pin = { 7, 4, 1 }, 1458 .mmio_gpio_set = { 1, 1, 0 }, 1459 .scp_cmds_count = 0, 1460 .has_chipio_write = false, 1461 } }, 1462 }, 1463 { .quirk_id = QUIRK_ZXR, 1464 .has_headphone_gain = true, 1465 .is_ae_series = false, 1466 .out_set_info = { 1467 /* Speakers. */ 1468 { .dac2port = 0x24, 1469 .has_hda_gpio = false, 1470 .mmio_gpio_count = 3, 1471 .mmio_gpio_pin = { 2, 3, 5 }, 1472 .mmio_gpio_set = { 1, 1, 0 }, 1473 .scp_cmds_count = 0, 1474 .has_chipio_write = false, 1475 }, 1476 /* Headphones. */ 1477 { .dac2port = 0x21, 1478 .has_hda_gpio = false, 1479 .mmio_gpio_count = 3, 1480 .mmio_gpio_pin = { 2, 3, 5 }, 1481 .mmio_gpio_set = { 0, 1, 1 }, 1482 .scp_cmds_count = 0, 1483 .has_chipio_write = false, 1484 } }, 1485 }, 1486 { .quirk_id = QUIRK_AE5, 1487 .has_headphone_gain = true, 1488 .is_ae_series = true, 1489 .out_set_info = { 1490 /* Speakers. */ 1491 { .dac2port = 0xa4, 1492 .has_hda_gpio = false, 1493 .mmio_gpio_count = 0, 1494 .scp_cmds_count = 2, 1495 .scp_cmd_mid = { 0x96, 0x96 }, 1496 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1497 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1498 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1499 .has_chipio_write = true, 1500 .chipio_write_addr = 0x0018b03c, 1501 .chipio_write_data = 0x00000012 1502 }, 1503 /* Headphones. */ 1504 { .dac2port = 0xa1, 1505 .has_hda_gpio = false, 1506 .mmio_gpio_count = 0, 1507 .scp_cmds_count = 2, 1508 .scp_cmd_mid = { 0x96, 0x96 }, 1509 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1510 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1511 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1512 .has_chipio_write = true, 1513 .chipio_write_addr = 0x0018b03c, 1514 .chipio_write_data = 0x00000012 1515 } }, 1516 }, 1517 { .quirk_id = QUIRK_AE7, 1518 .has_headphone_gain = true, 1519 .is_ae_series = true, 1520 .out_set_info = { 1521 /* Speakers. */ 1522 { .dac2port = 0x58, 1523 .has_hda_gpio = false, 1524 .mmio_gpio_count = 1, 1525 .mmio_gpio_pin = { 0 }, 1526 .mmio_gpio_set = { 1 }, 1527 .scp_cmds_count = 2, 1528 .scp_cmd_mid = { 0x96, 0x96 }, 1529 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1530 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1531 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1532 .has_chipio_write = true, 1533 .chipio_write_addr = 0x0018b03c, 1534 .chipio_write_data = 0x00000000 1535 }, 1536 /* Headphones. */ 1537 { .dac2port = 0x58, 1538 .has_hda_gpio = false, 1539 .mmio_gpio_count = 1, 1540 .mmio_gpio_pin = { 0 }, 1541 .mmio_gpio_set = { 1 }, 1542 .scp_cmds_count = 2, 1543 .scp_cmd_mid = { 0x96, 0x96 }, 1544 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1545 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1546 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1547 .has_chipio_write = true, 1548 .chipio_write_addr = 0x0018b03c, 1549 .chipio_write_data = 0x00000010 1550 } }, 1551 } 1552 }; 1553 1554 /* 1555 * CA0132 codec access 1556 */ 1557 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1558 unsigned int verb, unsigned int parm, unsigned int *res) 1559 { 1560 unsigned int response; 1561 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1562 *res = response; 1563 1564 return ((response == -1) ? -1 : 0); 1565 } 1566 1567 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1568 unsigned short converter_format, unsigned int *res) 1569 { 1570 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1571 converter_format & 0xffff, res); 1572 } 1573 1574 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1575 hda_nid_t nid, unsigned char stream, 1576 unsigned char channel, unsigned int *res) 1577 { 1578 unsigned char converter_stream_channel = 0; 1579 1580 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1581 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1582 converter_stream_channel, res); 1583 } 1584 1585 /* Chip access helper function */ 1586 static int chipio_send(struct hda_codec *codec, 1587 unsigned int reg, 1588 unsigned int data) 1589 { 1590 unsigned int res; 1591 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1592 1593 /* send bits of data specified by reg */ 1594 do { 1595 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1596 reg, data); 1597 if (res == VENDOR_STATUS_CHIPIO_OK) 1598 return 0; 1599 msleep(20); 1600 } while (time_before(jiffies, timeout)); 1601 1602 return -EIO; 1603 } 1604 1605 /* 1606 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1607 */ 1608 static int chipio_write_address(struct hda_codec *codec, 1609 unsigned int chip_addx) 1610 { 1611 struct ca0132_spec *spec = codec->spec; 1612 int res; 1613 1614 if (spec->curr_chip_addx == chip_addx) 1615 return 0; 1616 1617 /* send low 16 bits of the address */ 1618 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1619 chip_addx & 0xffff); 1620 1621 if (res != -EIO) { 1622 /* send high 16 bits of the address */ 1623 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1624 chip_addx >> 16); 1625 } 1626 1627 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1628 1629 return res; 1630 } 1631 1632 /* 1633 * Write data through the vendor widget -- NOT protected by the Mutex! 1634 */ 1635 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1636 { 1637 struct ca0132_spec *spec = codec->spec; 1638 int res; 1639 1640 /* send low 16 bits of the data */ 1641 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1642 1643 if (res != -EIO) { 1644 /* send high 16 bits of the data */ 1645 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1646 data >> 16); 1647 } 1648 1649 /*If no error encountered, automatically increment the address 1650 as per chip behaviour*/ 1651 spec->curr_chip_addx = (res != -EIO) ? 1652 (spec->curr_chip_addx + 4) : ~0U; 1653 return res; 1654 } 1655 1656 /* 1657 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1658 */ 1659 static int chipio_write_data_multiple(struct hda_codec *codec, 1660 const u32 *data, 1661 unsigned int count) 1662 { 1663 int status = 0; 1664 1665 if (data == NULL) { 1666 codec_dbg(codec, "chipio_write_data null ptr\n"); 1667 return -EINVAL; 1668 } 1669 1670 while ((count-- != 0) && (status == 0)) 1671 status = chipio_write_data(codec, *data++); 1672 1673 return status; 1674 } 1675 1676 1677 /* 1678 * Read data through the vendor widget -- NOT protected by the Mutex! 1679 */ 1680 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1681 { 1682 struct ca0132_spec *spec = codec->spec; 1683 int res; 1684 1685 /* post read */ 1686 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1687 1688 if (res != -EIO) { 1689 /* read status */ 1690 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1691 } 1692 1693 if (res != -EIO) { 1694 /* read data */ 1695 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1696 VENDOR_CHIPIO_HIC_READ_DATA, 1697 0); 1698 } 1699 1700 /*If no error encountered, automatically increment the address 1701 as per chip behaviour*/ 1702 spec->curr_chip_addx = (res != -EIO) ? 1703 (spec->curr_chip_addx + 4) : ~0U; 1704 return res; 1705 } 1706 1707 /* 1708 * Write given value to the given address through the chip I/O widget. 1709 * protected by the Mutex 1710 */ 1711 static int chipio_write(struct hda_codec *codec, 1712 unsigned int chip_addx, const unsigned int data) 1713 { 1714 struct ca0132_spec *spec = codec->spec; 1715 int err; 1716 1717 guard(mutex)(&spec->chipio_mutex); 1718 1719 /* write the address, and if successful proceed to write data */ 1720 err = chipio_write_address(codec, chip_addx); 1721 if (err < 0) 1722 return err; 1723 1724 return chipio_write_data(codec, data); 1725 } 1726 1727 /* 1728 * Write given value to the given address through the chip I/O widget. 1729 * not protected by the Mutex 1730 */ 1731 static int chipio_write_no_mutex(struct hda_codec *codec, 1732 unsigned int chip_addx, const unsigned int data) 1733 { 1734 int err; 1735 1736 1737 /* write the address, and if successful proceed to write data */ 1738 err = chipio_write_address(codec, chip_addx); 1739 if (err < 0) 1740 goto exit; 1741 1742 err = chipio_write_data(codec, data); 1743 if (err < 0) 1744 goto exit; 1745 1746 exit: 1747 return err; 1748 } 1749 1750 /* 1751 * Write multiple values to the given address through the chip I/O widget. 1752 * protected by the Mutex 1753 */ 1754 static int chipio_write_multiple(struct hda_codec *codec, 1755 u32 chip_addx, 1756 const u32 *data, 1757 unsigned int count) 1758 { 1759 struct ca0132_spec *spec = codec->spec; 1760 int status; 1761 1762 guard(mutex)(&spec->chipio_mutex); 1763 status = chipio_write_address(codec, chip_addx); 1764 if (status < 0) 1765 return status; 1766 1767 return chipio_write_data_multiple(codec, data, count); 1768 } 1769 1770 /* 1771 * Read the given address through the chip I/O widget 1772 * protected by the Mutex 1773 */ 1774 static int chipio_read(struct hda_codec *codec, 1775 unsigned int chip_addx, unsigned int *data) 1776 { 1777 struct ca0132_spec *spec = codec->spec; 1778 int err; 1779 1780 guard(mutex)(&spec->chipio_mutex); 1781 1782 /* write the address, and if successful proceed to write data */ 1783 err = chipio_write_address(codec, chip_addx); 1784 if (err < 0) 1785 return err; 1786 1787 return chipio_read_data(codec, data); 1788 } 1789 1790 /* 1791 * Set chip control flags through the chip I/O widget. 1792 */ 1793 static void chipio_set_control_flag(struct hda_codec *codec, 1794 enum control_flag_id flag_id, 1795 bool flag_state) 1796 { 1797 unsigned int val; 1798 unsigned int flag_bit; 1799 1800 flag_bit = (flag_state ? 1 : 0); 1801 val = (flag_bit << 7) | (flag_id); 1802 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1803 VENDOR_CHIPIO_FLAG_SET, val); 1804 } 1805 1806 /* 1807 * Set chip parameters through the chip I/O widget. 1808 */ 1809 static void chipio_set_control_param(struct hda_codec *codec, 1810 enum control_param_id param_id, int param_val) 1811 { 1812 struct ca0132_spec *spec = codec->spec; 1813 int val; 1814 1815 if ((param_id < 32) && (param_val < 8)) { 1816 val = (param_val << 5) | (param_id); 1817 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1818 VENDOR_CHIPIO_PARAM_SET, val); 1819 } else { 1820 guard(mutex)(&spec->chipio_mutex); 1821 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1822 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1823 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1824 param_id); 1825 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1826 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1827 param_val); 1828 } 1829 } 1830 } 1831 1832 /* 1833 * Set chip parameters through the chip I/O widget. NO MUTEX. 1834 */ 1835 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1836 enum control_param_id param_id, int param_val) 1837 { 1838 int val; 1839 1840 if ((param_id < 32) && (param_val < 8)) { 1841 val = (param_val << 5) | (param_id); 1842 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1843 VENDOR_CHIPIO_PARAM_SET, val); 1844 } else { 1845 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1846 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1847 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1848 param_id); 1849 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1850 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1851 param_val); 1852 } 1853 } 1854 } 1855 /* 1856 * Connect stream to a source point, and then connect 1857 * that source point to a destination point. 1858 */ 1859 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1860 int streamid, int source_point, int dest_point) 1861 { 1862 chipio_set_control_param_no_mutex(codec, 1863 CONTROL_PARAM_STREAM_ID, streamid); 1864 chipio_set_control_param_no_mutex(codec, 1865 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1866 chipio_set_control_param_no_mutex(codec, 1867 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1868 } 1869 1870 /* 1871 * Set number of channels in the selected stream. 1872 */ 1873 static void chipio_set_stream_channels(struct hda_codec *codec, 1874 int streamid, unsigned int channels) 1875 { 1876 chipio_set_control_param_no_mutex(codec, 1877 CONTROL_PARAM_STREAM_ID, streamid); 1878 chipio_set_control_param_no_mutex(codec, 1879 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1880 } 1881 1882 /* 1883 * Enable/Disable audio stream. 1884 */ 1885 static void chipio_set_stream_control(struct hda_codec *codec, 1886 int streamid, int enable) 1887 { 1888 chipio_set_control_param_no_mutex(codec, 1889 CONTROL_PARAM_STREAM_ID, streamid); 1890 chipio_set_control_param_no_mutex(codec, 1891 CONTROL_PARAM_STREAM_CONTROL, enable); 1892 } 1893 1894 /* 1895 * Get ChipIO audio stream's status. 1896 */ 1897 static void chipio_get_stream_control(struct hda_codec *codec, 1898 int streamid, unsigned int *enable) 1899 { 1900 chipio_set_control_param_no_mutex(codec, 1901 CONTROL_PARAM_STREAM_ID, streamid); 1902 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1903 VENDOR_CHIPIO_PARAM_GET, 1904 CONTROL_PARAM_STREAM_CONTROL); 1905 } 1906 1907 /* 1908 * Set sampling rate of the connection point. NO MUTEX. 1909 */ 1910 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1911 int connid, enum ca0132_sample_rate rate) 1912 { 1913 chipio_set_control_param_no_mutex(codec, 1914 CONTROL_PARAM_CONN_POINT_ID, connid); 1915 chipio_set_control_param_no_mutex(codec, 1916 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1917 } 1918 1919 /* 1920 * Set sampling rate of the connection point. 1921 */ 1922 static void chipio_set_conn_rate(struct hda_codec *codec, 1923 int connid, enum ca0132_sample_rate rate) 1924 { 1925 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1926 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1927 rate); 1928 } 1929 1930 /* 1931 * Writes to the 8051's internal address space directly instead of indirectly, 1932 * giving access to the special function registers located at addresses 1933 * 0x80-0xFF. 1934 */ 1935 static void chipio_8051_write_direct(struct hda_codec *codec, 1936 unsigned int addr, unsigned int data) 1937 { 1938 unsigned int verb; 1939 1940 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1941 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1942 } 1943 1944 /* 1945 * Writes to the 8051's exram, which has 16-bits of address space. 1946 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1947 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1948 * setting the pmem bank selection SFR. 1949 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1950 * being writable. 1951 */ 1952 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1953 { 1954 unsigned int tmp; 1955 1956 /* Lower 8-bits. */ 1957 tmp = addr & 0xff; 1958 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1959 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1960 1961 /* Upper 8-bits. */ 1962 tmp = (addr >> 8) & 0xff; 1963 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1964 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1965 } 1966 1967 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1968 { 1969 /* 8-bits of data. */ 1970 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1971 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1972 } 1973 1974 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1975 { 1976 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1977 VENDOR_CHIPIO_8051_DATA_READ, 0); 1978 } 1979 1980 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1981 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1982 { 1983 /* 8-bits of data. */ 1984 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1985 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1986 } 1987 1988 static void chipio_8051_write_exram(struct hda_codec *codec, 1989 unsigned int addr, unsigned int data) 1990 { 1991 struct ca0132_spec *spec = codec->spec; 1992 1993 guard(mutex)(&spec->chipio_mutex); 1994 1995 chipio_8051_set_address(codec, addr); 1996 chipio_8051_set_data(codec, data); 1997 } 1998 1999 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 2000 unsigned int addr, unsigned int data) 2001 { 2002 chipio_8051_set_address(codec, addr); 2003 chipio_8051_set_data(codec, data); 2004 } 2005 2006 /* Readback data from the 8051's exram. No mutex. */ 2007 static void chipio_8051_read_exram(struct hda_codec *codec, 2008 unsigned int addr, unsigned int *data) 2009 { 2010 chipio_8051_set_address(codec, addr); 2011 *data = chipio_8051_get_data(codec); 2012 } 2013 2014 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 2015 unsigned int addr, unsigned int data) 2016 { 2017 struct ca0132_spec *spec = codec->spec; 2018 2019 guard(mutex)(&spec->chipio_mutex); 2020 2021 chipio_8051_set_address(codec, addr & 0xff); 2022 chipio_8051_set_data_pll(codec, data); 2023 } 2024 2025 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2026 unsigned int addr, unsigned int data) 2027 { 2028 chipio_8051_set_address(codec, addr & 0xff); 2029 chipio_8051_set_data_pll(codec, data); 2030 } 2031 2032 /* 2033 * Enable clocks. 2034 */ 2035 static void chipio_enable_clocks(struct hda_codec *codec) 2036 { 2037 struct ca0132_spec *spec = codec->spec; 2038 2039 guard(mutex)(&spec->chipio_mutex); 2040 2041 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2042 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2043 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2044 } 2045 2046 /* 2047 * CA0132 DSP IO stuffs 2048 */ 2049 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2050 unsigned int data) 2051 { 2052 int res; 2053 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2054 2055 /* send bits of data specified by reg to dsp */ 2056 do { 2057 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2058 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2059 return res; 2060 msleep(20); 2061 } while (time_before(jiffies, timeout)); 2062 2063 return -EIO; 2064 } 2065 2066 /* 2067 * Wait for DSP to be ready for commands 2068 */ 2069 static void dspio_write_wait(struct hda_codec *codec) 2070 { 2071 int status; 2072 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2073 2074 do { 2075 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2076 VENDOR_DSPIO_STATUS, 0); 2077 if ((status == VENDOR_STATUS_DSPIO_OK) || 2078 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2079 break; 2080 msleep(1); 2081 } while (time_before(jiffies, timeout)); 2082 } 2083 2084 /* 2085 * Write SCP data to DSP 2086 */ 2087 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2088 { 2089 struct ca0132_spec *spec = codec->spec; 2090 int status; 2091 2092 dspio_write_wait(codec); 2093 2094 guard(mutex)(&spec->chipio_mutex); 2095 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2096 scp_data & 0xffff); 2097 if (status < 0) 2098 return status; 2099 2100 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2101 scp_data >> 16); 2102 if (status < 0) 2103 return status; 2104 2105 /* OK, now check if the write itself has executed*/ 2106 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2107 VENDOR_DSPIO_STATUS, 0); 2108 2109 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2110 -EIO : 0; 2111 } 2112 2113 /* 2114 * Write multiple SCP data to DSP 2115 */ 2116 static int dspio_write_multiple(struct hda_codec *codec, 2117 unsigned int *buffer, unsigned int size) 2118 { 2119 int status = 0; 2120 unsigned int count; 2121 2122 if (buffer == NULL) 2123 return -EINVAL; 2124 2125 count = 0; 2126 while (count < size) { 2127 status = dspio_write(codec, *buffer++); 2128 if (status != 0) 2129 break; 2130 count++; 2131 } 2132 2133 return status; 2134 } 2135 2136 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2137 { 2138 int status; 2139 2140 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2141 if (status == -EIO) 2142 return status; 2143 2144 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2145 if (status == -EIO || 2146 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2147 return -EIO; 2148 2149 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2150 VENDOR_DSPIO_SCP_READ_DATA, 0); 2151 2152 return 0; 2153 } 2154 2155 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2156 unsigned int *buf_size, unsigned int size_count) 2157 { 2158 int status = 0; 2159 unsigned int size = *buf_size; 2160 unsigned int count; 2161 unsigned int skip_count; 2162 unsigned int dummy; 2163 2164 if (buffer == NULL) 2165 return -1; 2166 2167 count = 0; 2168 while (count < size && count < size_count) { 2169 status = dspio_read(codec, buffer++); 2170 if (status != 0) 2171 break; 2172 count++; 2173 } 2174 2175 skip_count = count; 2176 if (status == 0) { 2177 while (skip_count < size) { 2178 status = dspio_read(codec, &dummy); 2179 if (status != 0) 2180 break; 2181 skip_count++; 2182 } 2183 } 2184 *buf_size = count; 2185 2186 return status; 2187 } 2188 2189 /* 2190 * Construct the SCP header using corresponding fields 2191 */ 2192 static inline unsigned int 2193 make_scp_header(unsigned int target_id, unsigned int source_id, 2194 unsigned int get_flag, unsigned int req, 2195 unsigned int device_flag, unsigned int resp_flag, 2196 unsigned int error_flag, unsigned int data_size) 2197 { 2198 unsigned int header = 0; 2199 2200 header = (data_size & 0x1f) << 27; 2201 header |= (error_flag & 0x01) << 26; 2202 header |= (resp_flag & 0x01) << 25; 2203 header |= (device_flag & 0x01) << 24; 2204 header |= (req & 0x7f) << 17; 2205 header |= (get_flag & 0x01) << 16; 2206 header |= (source_id & 0xff) << 8; 2207 header |= target_id & 0xff; 2208 2209 return header; 2210 } 2211 2212 /* 2213 * Extract corresponding fields from SCP header 2214 */ 2215 static inline void 2216 extract_scp_header(unsigned int header, 2217 unsigned int *target_id, unsigned int *source_id, 2218 unsigned int *get_flag, unsigned int *req, 2219 unsigned int *device_flag, unsigned int *resp_flag, 2220 unsigned int *error_flag, unsigned int *data_size) 2221 { 2222 if (data_size) 2223 *data_size = (header >> 27) & 0x1f; 2224 if (error_flag) 2225 *error_flag = (header >> 26) & 0x01; 2226 if (resp_flag) 2227 *resp_flag = (header >> 25) & 0x01; 2228 if (device_flag) 2229 *device_flag = (header >> 24) & 0x01; 2230 if (req) 2231 *req = (header >> 17) & 0x7f; 2232 if (get_flag) 2233 *get_flag = (header >> 16) & 0x01; 2234 if (source_id) 2235 *source_id = (header >> 8) & 0xff; 2236 if (target_id) 2237 *target_id = header & 0xff; 2238 } 2239 2240 #define SCP_MAX_DATA_WORDS (16) 2241 2242 /* Structure to contain any SCP message */ 2243 struct scp_msg { 2244 unsigned int hdr; 2245 unsigned int data[SCP_MAX_DATA_WORDS]; 2246 }; 2247 2248 static void dspio_clear_response_queue(struct hda_codec *codec) 2249 { 2250 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2251 unsigned int dummy = 0; 2252 int status; 2253 2254 /* clear all from the response queue */ 2255 do { 2256 status = dspio_read(codec, &dummy); 2257 } while (status == 0 && time_before(jiffies, timeout)); 2258 } 2259 2260 static int dspio_get_response_data(struct hda_codec *codec) 2261 { 2262 struct ca0132_spec *spec = codec->spec; 2263 unsigned int data = 0; 2264 unsigned int count; 2265 2266 if (dspio_read(codec, &data) < 0) 2267 return -EIO; 2268 2269 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2270 spec->scp_resp_header = data; 2271 spec->scp_resp_count = data >> 27; 2272 count = spec->wait_num_data; 2273 dspio_read_multiple(codec, spec->scp_resp_data, 2274 &spec->scp_resp_count, count); 2275 return 0; 2276 } 2277 2278 return -EIO; 2279 } 2280 2281 /* 2282 * Send SCP message to DSP 2283 */ 2284 static int dspio_send_scp_message(struct hda_codec *codec, 2285 unsigned char *send_buf, 2286 unsigned int send_buf_size, 2287 unsigned char *return_buf, 2288 unsigned int return_buf_size, 2289 unsigned int *bytes_returned) 2290 { 2291 struct ca0132_spec *spec = codec->spec; 2292 int status; 2293 unsigned int scp_send_size = 0; 2294 unsigned int total_size; 2295 bool waiting_for_resp = false; 2296 unsigned int header; 2297 struct scp_msg *ret_msg; 2298 unsigned int resp_src_id, resp_target_id; 2299 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2300 2301 if (bytes_returned) 2302 *bytes_returned = 0; 2303 2304 /* get scp header from buffer */ 2305 header = *((unsigned int *)send_buf); 2306 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2307 &device_flag, NULL, NULL, &data_size); 2308 scp_send_size = data_size + 1; 2309 total_size = (scp_send_size * 4); 2310 2311 if (send_buf_size < total_size) 2312 return -EINVAL; 2313 2314 if (get_flag || device_flag) { 2315 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2316 return -EINVAL; 2317 2318 spec->wait_scp_header = *((unsigned int *)send_buf); 2319 2320 /* swap source id with target id */ 2321 resp_target_id = src_id; 2322 resp_src_id = target_id; 2323 spec->wait_scp_header &= 0xffff0000; 2324 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2325 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2326 spec->wait_scp = 1; 2327 waiting_for_resp = true; 2328 } 2329 2330 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2331 scp_send_size); 2332 if (status < 0) { 2333 spec->wait_scp = 0; 2334 return status; 2335 } 2336 2337 if (waiting_for_resp) { 2338 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2339 memset(return_buf, 0, return_buf_size); 2340 do { 2341 msleep(20); 2342 } while (spec->wait_scp && time_before(jiffies, timeout)); 2343 waiting_for_resp = false; 2344 if (!spec->wait_scp) { 2345 ret_msg = (struct scp_msg *)return_buf; 2346 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2347 memcpy(&ret_msg->data, spec->scp_resp_data, 2348 spec->wait_num_data); 2349 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2350 status = 0; 2351 } else { 2352 status = -EIO; 2353 } 2354 spec->wait_scp = 0; 2355 } 2356 2357 return status; 2358 } 2359 2360 /** 2361 * dspio_scp - Prepare and send the SCP message to DSP 2362 * @codec: the HDA codec 2363 * @mod_id: ID of the DSP module to send the command 2364 * @src_id: ID of the source 2365 * @req: ID of request to send to the DSP module 2366 * @dir: SET or GET 2367 * @data: pointer to the data to send with the request, request specific 2368 * @len: length of the data, in bytes 2369 * @reply: point to the buffer to hold data returned for a reply 2370 * @reply_len: length of the reply buffer returned from GET 2371 * 2372 * Returns zero or a negative error code. 2373 */ 2374 static int dspio_scp(struct hda_codec *codec, 2375 int mod_id, int src_id, int req, int dir, const void *data, 2376 unsigned int len, void *reply, unsigned int *reply_len) 2377 { 2378 int status = 0; 2379 struct scp_msg scp_send, scp_reply; 2380 unsigned int ret_bytes, send_size, ret_size; 2381 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2382 unsigned int reply_data_size; 2383 2384 memset(&scp_send, 0, sizeof(scp_send)); 2385 memset(&scp_reply, 0, sizeof(scp_reply)); 2386 2387 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2388 return -EINVAL; 2389 2390 if (dir == SCP_GET && reply == NULL) { 2391 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2392 return -EINVAL; 2393 } 2394 2395 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2396 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2397 return -EINVAL; 2398 } 2399 2400 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2401 0, 0, 0, len/sizeof(unsigned int)); 2402 if (data != NULL && len > 0) { 2403 len = min((unsigned int)(sizeof(scp_send.data)), len); 2404 memcpy(scp_send.data, data, len); 2405 } 2406 2407 ret_bytes = 0; 2408 send_size = sizeof(unsigned int) + len; 2409 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2410 send_size, (unsigned char *)&scp_reply, 2411 sizeof(scp_reply), &ret_bytes); 2412 2413 if (status < 0) { 2414 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2415 return status; 2416 } 2417 2418 /* extract send and reply headers members */ 2419 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2420 NULL, NULL, NULL, NULL, NULL); 2421 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2422 &reply_resp_flag, &reply_error_flag, 2423 &reply_data_size); 2424 2425 if (!send_get_flag) 2426 return 0; 2427 2428 if (reply_resp_flag && !reply_error_flag) { 2429 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2430 / sizeof(unsigned int); 2431 2432 if (*reply_len < ret_size*sizeof(unsigned int)) { 2433 codec_dbg(codec, "reply too long for buf\n"); 2434 return -EINVAL; 2435 } else if (ret_size != reply_data_size) { 2436 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2437 return -EINVAL; 2438 } else if (!reply) { 2439 codec_dbg(codec, "NULL reply\n"); 2440 return -EINVAL; 2441 } else { 2442 *reply_len = ret_size*sizeof(unsigned int); 2443 memcpy(reply, scp_reply.data, *reply_len); 2444 } 2445 } else { 2446 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2447 return -EIO; 2448 } 2449 2450 return status; 2451 } 2452 2453 /* 2454 * Set DSP parameters 2455 */ 2456 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2457 int src_id, int req, const void *data, unsigned int len) 2458 { 2459 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2460 NULL); 2461 } 2462 2463 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2464 int req, const unsigned int data) 2465 { 2466 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2467 sizeof(unsigned int)); 2468 } 2469 2470 /* 2471 * Allocate a DSP DMA channel via an SCP message 2472 */ 2473 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2474 { 2475 int status = 0; 2476 unsigned int size = sizeof(*dma_chan); 2477 2478 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2479 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2480 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2481 dma_chan, &size); 2482 2483 if (status < 0) { 2484 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2485 return status; 2486 } 2487 2488 if ((*dma_chan + 1) == 0) { 2489 codec_dbg(codec, "no free dma channels to allocate\n"); 2490 return -EBUSY; 2491 } 2492 2493 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2494 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2495 2496 return status; 2497 } 2498 2499 /* 2500 * Free a DSP DMA via an SCP message 2501 */ 2502 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2503 { 2504 int status = 0; 2505 unsigned int dummy = 0; 2506 2507 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2508 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2509 2510 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2511 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2512 sizeof(dma_chan), NULL, &dummy); 2513 2514 if (status < 0) { 2515 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2516 return status; 2517 } 2518 2519 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2520 2521 return status; 2522 } 2523 2524 /* 2525 * (Re)start the DSP 2526 */ 2527 static int dsp_set_run_state(struct hda_codec *codec) 2528 { 2529 unsigned int dbg_ctrl_reg; 2530 unsigned int halt_state; 2531 int err; 2532 2533 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2534 if (err < 0) 2535 return err; 2536 2537 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2538 DSP_DBGCNTL_STATE_LOBIT; 2539 2540 if (halt_state != 0) { 2541 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2542 DSP_DBGCNTL_SS_MASK); 2543 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2544 dbg_ctrl_reg); 2545 if (err < 0) 2546 return err; 2547 2548 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2549 DSP_DBGCNTL_EXEC_MASK; 2550 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2551 dbg_ctrl_reg); 2552 if (err < 0) 2553 return err; 2554 } 2555 2556 return 0; 2557 } 2558 2559 /* 2560 * Reset the DSP 2561 */ 2562 static int dsp_reset(struct hda_codec *codec) 2563 { 2564 unsigned int res; 2565 int retry = 20; 2566 2567 codec_dbg(codec, "dsp_reset\n"); 2568 do { 2569 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2570 retry--; 2571 } while (res == -EIO && retry); 2572 2573 if (!retry) { 2574 codec_dbg(codec, "dsp_reset timeout\n"); 2575 return -EIO; 2576 } 2577 2578 return 0; 2579 } 2580 2581 /* 2582 * Convert chip address to DSP address 2583 */ 2584 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2585 bool *code, bool *yram) 2586 { 2587 *code = *yram = false; 2588 2589 if (UC_RANGE(chip_addx, 1)) { 2590 *code = true; 2591 return UC_OFF(chip_addx); 2592 } else if (X_RANGE_ALL(chip_addx, 1)) { 2593 return X_OFF(chip_addx); 2594 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2595 *yram = true; 2596 return Y_OFF(chip_addx); 2597 } 2598 2599 return INVALID_CHIP_ADDRESS; 2600 } 2601 2602 /* 2603 * Check if the DSP DMA is active 2604 */ 2605 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2606 { 2607 unsigned int dma_chnlstart_reg; 2608 2609 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2610 2611 return ((dma_chnlstart_reg & (1 << 2612 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2613 } 2614 2615 static int dsp_dma_setup_common(struct hda_codec *codec, 2616 unsigned int chip_addx, 2617 unsigned int dma_chan, 2618 unsigned int port_map_mask, 2619 bool ovly) 2620 { 2621 int status = 0; 2622 unsigned int chnl_prop; 2623 unsigned int dsp_addx; 2624 unsigned int active; 2625 bool code, yram; 2626 2627 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2628 2629 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2630 codec_dbg(codec, "dma chan num invalid\n"); 2631 return -EINVAL; 2632 } 2633 2634 if (dsp_is_dma_active(codec, dma_chan)) { 2635 codec_dbg(codec, "dma already active\n"); 2636 return -EBUSY; 2637 } 2638 2639 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2640 2641 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2642 codec_dbg(codec, "invalid chip addr\n"); 2643 return -ENXIO; 2644 } 2645 2646 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2647 active = 0; 2648 2649 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2650 2651 if (ovly) { 2652 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2653 &chnl_prop); 2654 2655 if (status < 0) { 2656 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2657 return status; 2658 } 2659 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2660 } 2661 2662 if (!code) 2663 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2664 else 2665 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2666 2667 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2668 2669 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2670 if (status < 0) { 2671 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2672 return status; 2673 } 2674 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2675 2676 if (ovly) { 2677 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2678 &active); 2679 2680 if (status < 0) { 2681 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2682 return status; 2683 } 2684 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2685 } 2686 2687 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2688 DSPDMAC_ACTIVE_AAR_MASK; 2689 2690 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2691 if (status < 0) { 2692 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2693 return status; 2694 } 2695 2696 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2697 2698 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2699 port_map_mask); 2700 if (status < 0) { 2701 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2702 return status; 2703 } 2704 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2705 2706 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2707 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2708 if (status < 0) { 2709 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2710 return status; 2711 } 2712 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2713 2714 codec_dbg(codec, 2715 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2716 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2717 chip_addx, dsp_addx, dma_chan, 2718 port_map_mask, chnl_prop, active); 2719 2720 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2721 2722 return 0; 2723 } 2724 2725 /* 2726 * Setup the DSP DMA per-transfer-specific registers 2727 */ 2728 static int dsp_dma_setup(struct hda_codec *codec, 2729 unsigned int chip_addx, 2730 unsigned int count, 2731 unsigned int dma_chan) 2732 { 2733 int status = 0; 2734 bool code, yram; 2735 unsigned int dsp_addx; 2736 unsigned int addr_field; 2737 unsigned int incr_field; 2738 unsigned int base_cnt; 2739 unsigned int cur_cnt; 2740 unsigned int dma_cfg = 0; 2741 unsigned int adr_ofs = 0; 2742 unsigned int xfr_cnt = 0; 2743 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2744 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2745 2746 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2747 2748 if (count > max_dma_count) { 2749 codec_dbg(codec, "count too big\n"); 2750 return -EINVAL; 2751 } 2752 2753 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2754 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2755 codec_dbg(codec, "invalid chip addr\n"); 2756 return -ENXIO; 2757 } 2758 2759 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2760 2761 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2762 incr_field = 0; 2763 2764 if (!code) { 2765 addr_field <<= 1; 2766 if (yram) 2767 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2768 2769 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2770 } 2771 2772 dma_cfg = addr_field + incr_field; 2773 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2774 dma_cfg); 2775 if (status < 0) { 2776 codec_dbg(codec, "write DMACFG Reg fail\n"); 2777 return status; 2778 } 2779 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2780 2781 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2782 (code ? 0 : 1)); 2783 2784 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2785 adr_ofs); 2786 if (status < 0) { 2787 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2788 return status; 2789 } 2790 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2791 2792 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2793 2794 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2795 2796 xfr_cnt = base_cnt | cur_cnt; 2797 2798 status = chipio_write(codec, 2799 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2800 if (status < 0) { 2801 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2802 return status; 2803 } 2804 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2805 2806 codec_dbg(codec, 2807 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2808 "ADROFS=0x%x, XFRCNT=0x%x\n", 2809 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2810 2811 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2812 2813 return 0; 2814 } 2815 2816 /* 2817 * Start the DSP DMA 2818 */ 2819 static int dsp_dma_start(struct hda_codec *codec, 2820 unsigned int dma_chan, bool ovly) 2821 { 2822 unsigned int reg = 0; 2823 int status = 0; 2824 2825 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2826 2827 if (ovly) { 2828 status = chipio_read(codec, 2829 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2830 2831 if (status < 0) { 2832 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2833 return status; 2834 } 2835 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2836 2837 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2838 DSPDMAC_CHNLSTART_DIS_MASK); 2839 } 2840 2841 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2842 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2843 if (status < 0) { 2844 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2845 return status; 2846 } 2847 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2848 2849 return status; 2850 } 2851 2852 /* 2853 * Stop the DSP DMA 2854 */ 2855 static int dsp_dma_stop(struct hda_codec *codec, 2856 unsigned int dma_chan, bool ovly) 2857 { 2858 unsigned int reg = 0; 2859 int status = 0; 2860 2861 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2862 2863 if (ovly) { 2864 status = chipio_read(codec, 2865 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2866 2867 if (status < 0) { 2868 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2869 return status; 2870 } 2871 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2872 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2873 DSPDMAC_CHNLSTART_DIS_MASK); 2874 } 2875 2876 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2877 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2878 if (status < 0) { 2879 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2880 return status; 2881 } 2882 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2883 2884 return status; 2885 } 2886 2887 /** 2888 * dsp_allocate_router_ports - Allocate router ports 2889 * 2890 * @codec: the HDA codec 2891 * @num_chans: number of channels in the stream 2892 * @ports_per_channel: number of ports per channel 2893 * @start_device: start device 2894 * @port_map: pointer to the port list to hold the allocated ports 2895 * 2896 * Returns zero or a negative error code. 2897 */ 2898 static int dsp_allocate_router_ports(struct hda_codec *codec, 2899 unsigned int num_chans, 2900 unsigned int ports_per_channel, 2901 unsigned int start_device, 2902 unsigned int *port_map) 2903 { 2904 int status = 0; 2905 int res; 2906 u8 val; 2907 2908 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2909 if (status < 0) 2910 return status; 2911 2912 val = start_device << 6; 2913 val |= (ports_per_channel - 1) << 4; 2914 val |= num_chans - 1; 2915 2916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2917 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2918 val); 2919 2920 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2921 VENDOR_CHIPIO_PORT_ALLOC_SET, 2922 MEM_CONNID_DSP); 2923 2924 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2925 if (status < 0) 2926 return status; 2927 2928 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2929 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2930 2931 *port_map = res; 2932 2933 return (res < 0) ? res : 0; 2934 } 2935 2936 /* 2937 * Free router ports 2938 */ 2939 static int dsp_free_router_ports(struct hda_codec *codec) 2940 { 2941 int status = 0; 2942 2943 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2944 if (status < 0) 2945 return status; 2946 2947 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2948 VENDOR_CHIPIO_PORT_FREE_SET, 2949 MEM_CONNID_DSP); 2950 2951 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2952 2953 return status; 2954 } 2955 2956 /* 2957 * Allocate DSP ports for the download stream 2958 */ 2959 static int dsp_allocate_ports(struct hda_codec *codec, 2960 unsigned int num_chans, 2961 unsigned int rate_multi, unsigned int *port_map) 2962 { 2963 int status; 2964 2965 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2966 2967 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2968 codec_dbg(codec, "bad rate multiple\n"); 2969 return -EINVAL; 2970 } 2971 2972 status = dsp_allocate_router_ports(codec, num_chans, 2973 rate_multi, 0, port_map); 2974 2975 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2976 2977 return status; 2978 } 2979 2980 static int dsp_allocate_ports_format(struct hda_codec *codec, 2981 const unsigned short fmt, 2982 unsigned int *port_map) 2983 { 2984 unsigned int num_chans; 2985 2986 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2987 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2988 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2989 2990 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2991 codec_dbg(codec, "bad rate multiple\n"); 2992 return -EINVAL; 2993 } 2994 2995 num_chans = get_hdafmt_chs(fmt) + 1; 2996 2997 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2998 } 2999 3000 /* 3001 * free DSP ports 3002 */ 3003 static int dsp_free_ports(struct hda_codec *codec) 3004 { 3005 int status; 3006 3007 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 3008 3009 status = dsp_free_router_ports(codec); 3010 if (status < 0) { 3011 codec_dbg(codec, "free router ports fail\n"); 3012 return status; 3013 } 3014 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 3015 3016 return status; 3017 } 3018 3019 /* 3020 * HDA DMA engine stuffs for DSP code download 3021 */ 3022 struct dma_engine { 3023 struct hda_codec *codec; 3024 unsigned short m_converter_format; 3025 struct snd_dma_buffer *dmab; 3026 unsigned int buf_size; 3027 }; 3028 3029 3030 enum dma_state { 3031 DMA_STATE_STOP = 0, 3032 DMA_STATE_RUN = 1 3033 }; 3034 3035 static int dma_convert_to_hda_format(struct hda_codec *codec, 3036 unsigned int sample_rate, 3037 unsigned short channels, 3038 unsigned short *hda_format) 3039 { 3040 unsigned int format_val; 3041 3042 format_val = snd_hdac_stream_format(channels, 32, sample_rate); 3043 3044 if (hda_format) 3045 *hda_format = (unsigned short)format_val; 3046 3047 return 0; 3048 } 3049 3050 /* 3051 * Reset DMA for DSP download 3052 */ 3053 static int dma_reset(struct dma_engine *dma) 3054 { 3055 struct hda_codec *codec = dma->codec; 3056 struct ca0132_spec *spec = codec->spec; 3057 int status; 3058 3059 if (dma->dmab->area) 3060 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3061 3062 status = snd_hda_codec_load_dsp_prepare(codec, 3063 dma->m_converter_format, 3064 dma->buf_size, 3065 dma->dmab); 3066 if (status < 0) 3067 return status; 3068 spec->dsp_stream_id = status; 3069 return 0; 3070 } 3071 3072 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3073 { 3074 bool cmd; 3075 3076 switch (state) { 3077 case DMA_STATE_STOP: 3078 cmd = false; 3079 break; 3080 case DMA_STATE_RUN: 3081 cmd = true; 3082 break; 3083 default: 3084 return 0; 3085 } 3086 3087 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3088 return 0; 3089 } 3090 3091 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3092 { 3093 return dma->dmab->bytes; 3094 } 3095 3096 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3097 { 3098 return dma->dmab->area; 3099 } 3100 3101 static int dma_xfer(struct dma_engine *dma, 3102 const unsigned int *data, 3103 unsigned int count) 3104 { 3105 memcpy(dma->dmab->area, data, count); 3106 return 0; 3107 } 3108 3109 static void dma_get_converter_format( 3110 struct dma_engine *dma, 3111 unsigned short *format) 3112 { 3113 if (format) 3114 *format = dma->m_converter_format; 3115 } 3116 3117 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3118 { 3119 struct ca0132_spec *spec = dma->codec->spec; 3120 3121 return spec->dsp_stream_id; 3122 } 3123 3124 struct dsp_image_seg { 3125 u32 magic; 3126 u32 chip_addr; 3127 u32 count; 3128 u32 data[]; 3129 }; 3130 3131 static const u32 g_magic_value = 0x4c46584d; 3132 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3133 3134 static bool is_valid(const struct dsp_image_seg *p) 3135 { 3136 return p->magic == g_magic_value; 3137 } 3138 3139 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3140 { 3141 return g_chip_addr_magic_value == p->chip_addr; 3142 } 3143 3144 static bool is_last(const struct dsp_image_seg *p) 3145 { 3146 return p->count == 0; 3147 } 3148 3149 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3150 { 3151 return struct_size(p, data, p->count); 3152 } 3153 3154 static const struct dsp_image_seg *get_next_seg_ptr( 3155 const struct dsp_image_seg *p) 3156 { 3157 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3158 } 3159 3160 /* 3161 * CA0132 chip DSP transfer stuffs. For DSP download. 3162 */ 3163 #define INVALID_DMA_CHANNEL (~0U) 3164 3165 /* 3166 * Program a list of address/data pairs via the ChipIO widget. 3167 * The segment data is in the format of successive pairs of words. 3168 * These are repeated as indicated by the segment's count field. 3169 */ 3170 static int dspxfr_hci_write(struct hda_codec *codec, 3171 const struct dsp_image_seg *fls) 3172 { 3173 int status; 3174 const u32 *data; 3175 unsigned int count; 3176 3177 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3178 codec_dbg(codec, "hci_write invalid params\n"); 3179 return -EINVAL; 3180 } 3181 3182 count = fls->count; 3183 data = (u32 *)(fls->data); 3184 while (count >= 2) { 3185 status = chipio_write(codec, data[0], data[1]); 3186 if (status < 0) { 3187 codec_dbg(codec, "hci_write chipio failed\n"); 3188 return status; 3189 } 3190 count -= 2; 3191 data += 2; 3192 } 3193 return 0; 3194 } 3195 3196 /** 3197 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3198 * 3199 * @codec: the HDA codec 3200 * @fls: pointer to a fast load image 3201 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3202 * no relocation 3203 * @dma_engine: pointer to DMA engine to be used for DSP download 3204 * @dma_chan: The number of DMA channels used for DSP download 3205 * @port_map_mask: port mapping 3206 * @ovly: TRUE if overlay format is required 3207 * 3208 * Returns zero or a negative error code. 3209 */ 3210 static int dspxfr_one_seg(struct hda_codec *codec, 3211 const struct dsp_image_seg *fls, 3212 unsigned int reloc, 3213 struct dma_engine *dma_engine, 3214 unsigned int dma_chan, 3215 unsigned int port_map_mask, 3216 bool ovly) 3217 { 3218 int status = 0; 3219 bool comm_dma_setup_done = false; 3220 const unsigned int *data; 3221 unsigned int chip_addx; 3222 unsigned int words_to_write; 3223 unsigned int buffer_size_words; 3224 unsigned char *buffer_addx; 3225 unsigned short hda_format; 3226 unsigned int sample_rate_div; 3227 unsigned int sample_rate_mul; 3228 unsigned int num_chans; 3229 unsigned int hda_frame_size_words; 3230 unsigned int remainder_words; 3231 const u32 *data_remainder; 3232 u32 chip_addx_remainder; 3233 unsigned int run_size_words; 3234 const struct dsp_image_seg *hci_write = NULL; 3235 unsigned long timeout; 3236 bool dma_active; 3237 3238 if (fls == NULL) 3239 return -EINVAL; 3240 if (is_hci_prog_list_seg(fls)) { 3241 hci_write = fls; 3242 fls = get_next_seg_ptr(fls); 3243 } 3244 3245 if (hci_write && (!fls || is_last(fls))) { 3246 codec_dbg(codec, "hci_write\n"); 3247 return dspxfr_hci_write(codec, hci_write); 3248 } 3249 3250 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3251 codec_dbg(codec, "Invalid Params\n"); 3252 return -EINVAL; 3253 } 3254 3255 data = fls->data; 3256 chip_addx = fls->chip_addr; 3257 words_to_write = fls->count; 3258 3259 if (!words_to_write) 3260 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3261 if (reloc) 3262 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3263 3264 if (!UC_RANGE(chip_addx, words_to_write) && 3265 !X_RANGE_ALL(chip_addx, words_to_write) && 3266 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3267 codec_dbg(codec, "Invalid chip_addx Params\n"); 3268 return -EINVAL; 3269 } 3270 3271 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3272 sizeof(u32); 3273 3274 buffer_addx = dma_get_buffer_addr(dma_engine); 3275 3276 if (buffer_addx == NULL) { 3277 codec_dbg(codec, "dma_engine buffer NULL\n"); 3278 return -EINVAL; 3279 } 3280 3281 dma_get_converter_format(dma_engine, &hda_format); 3282 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3283 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3284 num_chans = get_hdafmt_chs(hda_format) + 1; 3285 3286 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3287 (num_chans * sample_rate_mul / sample_rate_div)); 3288 3289 if (hda_frame_size_words == 0) { 3290 codec_dbg(codec, "frmsz zero\n"); 3291 return -EINVAL; 3292 } 3293 3294 buffer_size_words = min(buffer_size_words, 3295 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3296 65536 : 32768)); 3297 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3298 codec_dbg(codec, 3299 "chpadr=0x%08x frmsz=%u nchan=%u " 3300 "rate_mul=%u div=%u bufsz=%u\n", 3301 chip_addx, hda_frame_size_words, num_chans, 3302 sample_rate_mul, sample_rate_div, buffer_size_words); 3303 3304 if (buffer_size_words < hda_frame_size_words) { 3305 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3306 return -EINVAL; 3307 } 3308 3309 remainder_words = words_to_write % hda_frame_size_words; 3310 data_remainder = data; 3311 chip_addx_remainder = chip_addx; 3312 3313 data += remainder_words; 3314 chip_addx += remainder_words*sizeof(u32); 3315 words_to_write -= remainder_words; 3316 3317 while (words_to_write != 0) { 3318 run_size_words = min(buffer_size_words, words_to_write); 3319 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3320 words_to_write, run_size_words, remainder_words); 3321 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3322 if (!comm_dma_setup_done) { 3323 status = dsp_dma_stop(codec, dma_chan, ovly); 3324 if (status < 0) 3325 return status; 3326 status = dsp_dma_setup_common(codec, chip_addx, 3327 dma_chan, port_map_mask, ovly); 3328 if (status < 0) 3329 return status; 3330 comm_dma_setup_done = true; 3331 } 3332 3333 status = dsp_dma_setup(codec, chip_addx, 3334 run_size_words, dma_chan); 3335 if (status < 0) 3336 return status; 3337 status = dsp_dma_start(codec, dma_chan, ovly); 3338 if (status < 0) 3339 return status; 3340 if (!dsp_is_dma_active(codec, dma_chan)) { 3341 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3342 return -EIO; 3343 } 3344 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3345 if (status < 0) 3346 return status; 3347 if (remainder_words != 0) { 3348 status = chipio_write_multiple(codec, 3349 chip_addx_remainder, 3350 data_remainder, 3351 remainder_words); 3352 if (status < 0) 3353 return status; 3354 remainder_words = 0; 3355 } 3356 if (hci_write) { 3357 status = dspxfr_hci_write(codec, hci_write); 3358 if (status < 0) 3359 return status; 3360 hci_write = NULL; 3361 } 3362 3363 timeout = jiffies + msecs_to_jiffies(2000); 3364 do { 3365 dma_active = dsp_is_dma_active(codec, dma_chan); 3366 if (!dma_active) 3367 break; 3368 msleep(20); 3369 } while (time_before(jiffies, timeout)); 3370 if (dma_active) 3371 break; 3372 3373 codec_dbg(codec, "+++++ DMA complete\n"); 3374 dma_set_state(dma_engine, DMA_STATE_STOP); 3375 status = dma_reset(dma_engine); 3376 3377 if (status < 0) 3378 return status; 3379 3380 data += run_size_words; 3381 chip_addx += run_size_words*sizeof(u32); 3382 words_to_write -= run_size_words; 3383 } 3384 3385 if (remainder_words != 0) { 3386 status = chipio_write_multiple(codec, chip_addx_remainder, 3387 data_remainder, remainder_words); 3388 } 3389 3390 return status; 3391 } 3392 3393 /** 3394 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3395 * 3396 * @codec: the HDA codec 3397 * @fls_data: pointer to a fast load image 3398 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3399 * no relocation 3400 * @sample_rate: sampling rate of the stream used for DSP download 3401 * @channels: channels of the stream used for DSP download 3402 * @ovly: TRUE if overlay format is required 3403 * 3404 * Returns zero or a negative error code. 3405 */ 3406 static int dspxfr_image(struct hda_codec *codec, 3407 const struct dsp_image_seg *fls_data, 3408 unsigned int reloc, 3409 unsigned int sample_rate, 3410 unsigned short channels, 3411 bool ovly) 3412 { 3413 struct ca0132_spec *spec = codec->spec; 3414 int status; 3415 unsigned short hda_format = 0; 3416 unsigned int response; 3417 unsigned char stream_id = 0; 3418 struct dma_engine *dma_engine; 3419 unsigned int dma_chan; 3420 unsigned int port_map_mask; 3421 3422 if (fls_data == NULL) 3423 return -EINVAL; 3424 3425 dma_engine = kzalloc_obj(*dma_engine); 3426 if (!dma_engine) 3427 return -ENOMEM; 3428 3429 dma_engine->dmab = kzalloc_obj(*dma_engine->dmab); 3430 if (!dma_engine->dmab) { 3431 kfree(dma_engine); 3432 return -ENOMEM; 3433 } 3434 3435 dma_engine->codec = codec; 3436 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3437 dma_engine->m_converter_format = hda_format; 3438 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3439 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3440 3441 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3442 3443 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3444 hda_format, &response); 3445 3446 if (status < 0) { 3447 codec_dbg(codec, "set converter format fail\n"); 3448 goto exit; 3449 } 3450 3451 status = snd_hda_codec_load_dsp_prepare(codec, 3452 dma_engine->m_converter_format, 3453 dma_engine->buf_size, 3454 dma_engine->dmab); 3455 if (status < 0) 3456 goto exit; 3457 spec->dsp_stream_id = status; 3458 3459 if (ovly) { 3460 status = dspio_alloc_dma_chan(codec, &dma_chan); 3461 if (status < 0) { 3462 codec_dbg(codec, "alloc dmachan fail\n"); 3463 dma_chan = INVALID_DMA_CHANNEL; 3464 goto exit; 3465 } 3466 } 3467 3468 port_map_mask = 0; 3469 status = dsp_allocate_ports_format(codec, hda_format, 3470 &port_map_mask); 3471 if (status < 0) { 3472 codec_dbg(codec, "alloc ports fail\n"); 3473 goto exit; 3474 } 3475 3476 stream_id = dma_get_stream_id(dma_engine); 3477 status = codec_set_converter_stream_channel(codec, 3478 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3479 if (status < 0) { 3480 codec_dbg(codec, "set stream chan fail\n"); 3481 goto exit; 3482 } 3483 3484 while ((fls_data != NULL) && !is_last(fls_data)) { 3485 if (!is_valid(fls_data)) { 3486 codec_dbg(codec, "FLS check fail\n"); 3487 status = -EINVAL; 3488 goto exit; 3489 } 3490 status = dspxfr_one_seg(codec, fls_data, reloc, 3491 dma_engine, dma_chan, 3492 port_map_mask, ovly); 3493 if (status < 0) 3494 break; 3495 3496 if (is_hci_prog_list_seg(fls_data)) 3497 fls_data = get_next_seg_ptr(fls_data); 3498 3499 if ((fls_data != NULL) && !is_last(fls_data)) 3500 fls_data = get_next_seg_ptr(fls_data); 3501 } 3502 3503 if (port_map_mask != 0) 3504 status = dsp_free_ports(codec); 3505 3506 if (status < 0) 3507 goto exit; 3508 3509 status = codec_set_converter_stream_channel(codec, 3510 WIDGET_CHIP_CTRL, 0, 0, &response); 3511 3512 exit: 3513 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3514 dspio_free_dma_chan(codec, dma_chan); 3515 3516 if (dma_engine->dmab->area) 3517 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3518 kfree(dma_engine->dmab); 3519 kfree(dma_engine); 3520 3521 return status; 3522 } 3523 3524 /* 3525 * CA0132 DSP download stuffs. 3526 */ 3527 static void dspload_post_setup(struct hda_codec *codec) 3528 { 3529 struct ca0132_spec *spec = codec->spec; 3530 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3531 if (!ca0132_use_alt_functions(spec)) { 3532 /*set DSP speaker to 2.0 configuration*/ 3533 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3534 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3535 3536 /*update write pointer*/ 3537 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3538 } 3539 } 3540 3541 /** 3542 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3543 * 3544 * @codec: the HDA codec 3545 * @fls: pointer to a fast load image 3546 * @ovly: TRUE if overlay format is required 3547 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3548 * no relocation 3549 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3550 * @router_chans: number of audio router channels to be allocated (0 means use 3551 * internal defaults; max is 32) 3552 * 3553 * Download DSP from a DSP Image Fast Load structure. This structure is a 3554 * linear, non-constant sized element array of structures, each of which 3555 * contain the count of the data to be loaded, the data itself, and the 3556 * corresponding starting chip address of the starting data location. 3557 * Returns zero or a negative error code. 3558 */ 3559 static int dspload_image(struct hda_codec *codec, 3560 const struct dsp_image_seg *fls, 3561 bool ovly, 3562 unsigned int reloc, 3563 bool autostart, 3564 int router_chans) 3565 { 3566 int status = 0; 3567 unsigned int sample_rate; 3568 unsigned short channels; 3569 3570 codec_dbg(codec, "---- dspload_image begin ------\n"); 3571 if (router_chans == 0) { 3572 if (!ovly) 3573 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3574 else 3575 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3576 } 3577 3578 sample_rate = 48000; 3579 channels = (unsigned short)router_chans; 3580 3581 while (channels > 16) { 3582 sample_rate *= 2; 3583 channels /= 2; 3584 } 3585 3586 do { 3587 codec_dbg(codec, "Ready to program DMA\n"); 3588 if (!ovly) 3589 status = dsp_reset(codec); 3590 3591 if (status < 0) 3592 break; 3593 3594 codec_dbg(codec, "dsp_reset() complete\n"); 3595 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3596 ovly); 3597 3598 if (status < 0) 3599 break; 3600 3601 codec_dbg(codec, "dspxfr_image() complete\n"); 3602 if (autostart && !ovly) { 3603 dspload_post_setup(codec); 3604 status = dsp_set_run_state(codec); 3605 } 3606 3607 codec_dbg(codec, "LOAD FINISHED\n"); 3608 } while (0); 3609 3610 return status; 3611 } 3612 3613 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3614 static bool dspload_is_loaded(struct hda_codec *codec) 3615 { 3616 unsigned int data = 0; 3617 int status = 0; 3618 3619 status = chipio_read(codec, 0x40004, &data); 3620 if ((status < 0) || (data != 1)) 3621 return false; 3622 3623 return true; 3624 } 3625 #else 3626 #define dspload_is_loaded(codec) false 3627 #endif 3628 3629 static bool dspload_wait_loaded(struct hda_codec *codec) 3630 { 3631 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3632 3633 do { 3634 if (dspload_is_loaded(codec)) { 3635 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3636 return true; 3637 } 3638 msleep(20); 3639 } while (time_before(jiffies, timeout)); 3640 3641 codec_err(codec, "ca0132 failed to download DSP\n"); 3642 return false; 3643 } 3644 3645 /* 3646 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3647 * based cards, and has a second mmio region, region2, that's used for special 3648 * commands. 3649 */ 3650 3651 /* 3652 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3653 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3654 * The first eight bits are just the number of the pin. So far, I've only seen 3655 * this number go to 7. 3656 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3657 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3658 * then off to send that bit. 3659 */ 3660 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3661 bool enable) 3662 { 3663 struct ca0132_spec *spec = codec->spec; 3664 unsigned short gpio_data; 3665 3666 gpio_data = gpio_pin & 0xF; 3667 gpio_data |= ((enable << 8) & 0x100); 3668 3669 writew(gpio_data, spec->mem_base + 0x320); 3670 } 3671 3672 /* 3673 * Special pci region2 commands that are only used by the AE-5. They follow 3674 * a set format, and require reads at certain points to seemingly 'clear' 3675 * the response data. My first tests didn't do these reads, and would cause 3676 * the card to get locked up until the memory was read. These commands 3677 * seem to work with three distinct values that I've taken to calling group, 3678 * target-id, and value. 3679 */ 3680 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3681 unsigned int target, unsigned int value) 3682 { 3683 struct ca0132_spec *spec = codec->spec; 3684 unsigned int write_val; 3685 3686 writel(0x0000007e, spec->mem_base + 0x210); 3687 readl(spec->mem_base + 0x210); 3688 writel(0x0000005a, spec->mem_base + 0x210); 3689 readl(spec->mem_base + 0x210); 3690 readl(spec->mem_base + 0x210); 3691 3692 writel(0x00800005, spec->mem_base + 0x20c); 3693 writel(group, spec->mem_base + 0x804); 3694 3695 writel(0x00800005, spec->mem_base + 0x20c); 3696 write_val = (target & 0xff); 3697 write_val |= (value << 8); 3698 3699 3700 writel(write_val, spec->mem_base + 0x204); 3701 /* 3702 * Need delay here or else it goes too fast and works inconsistently. 3703 */ 3704 msleep(20); 3705 3706 readl(spec->mem_base + 0x860); 3707 readl(spec->mem_base + 0x854); 3708 readl(spec->mem_base + 0x840); 3709 3710 writel(0x00800004, spec->mem_base + 0x20c); 3711 writel(0x00000000, spec->mem_base + 0x210); 3712 readl(spec->mem_base + 0x210); 3713 readl(spec->mem_base + 0x210); 3714 } 3715 3716 /* 3717 * This second type of command is used for setting the sound filter type. 3718 */ 3719 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3720 unsigned int group, unsigned int target, unsigned int value) 3721 { 3722 struct ca0132_spec *spec = codec->spec; 3723 unsigned int write_val; 3724 3725 writel(0x0000007e, spec->mem_base + 0x210); 3726 readl(spec->mem_base + 0x210); 3727 writel(0x0000005a, spec->mem_base + 0x210); 3728 readl(spec->mem_base + 0x210); 3729 readl(spec->mem_base + 0x210); 3730 3731 writel(0x00800003, spec->mem_base + 0x20c); 3732 writel(group, spec->mem_base + 0x804); 3733 3734 writel(0x00800005, spec->mem_base + 0x20c); 3735 write_val = (target & 0xff); 3736 write_val |= (value << 8); 3737 3738 3739 writel(write_val, spec->mem_base + 0x204); 3740 msleep(20); 3741 readl(spec->mem_base + 0x860); 3742 readl(spec->mem_base + 0x854); 3743 readl(spec->mem_base + 0x840); 3744 3745 writel(0x00800004, spec->mem_base + 0x20c); 3746 writel(0x00000000, spec->mem_base + 0x210); 3747 readl(spec->mem_base + 0x210); 3748 readl(spec->mem_base + 0x210); 3749 } 3750 3751 /* 3752 * Setup GPIO for the other variants of Core3D. 3753 */ 3754 3755 /* 3756 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3757 * the card shows as having no GPIO pins. 3758 */ 3759 static void ca0132_gpio_init(struct hda_codec *codec) 3760 { 3761 struct ca0132_spec *spec = codec->spec; 3762 3763 switch (ca0132_quirk(spec)) { 3764 case QUIRK_SBZ: 3765 case QUIRK_AE5: 3766 case QUIRK_AE7: 3767 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3768 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3769 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3770 break; 3771 case QUIRK_R3DI: 3772 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3773 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3774 break; 3775 default: 3776 break; 3777 } 3778 3779 } 3780 3781 /* Sets the GPIO for audio output. */ 3782 static void ca0132_gpio_setup(struct hda_codec *codec) 3783 { 3784 struct ca0132_spec *spec = codec->spec; 3785 3786 switch (ca0132_quirk(spec)) { 3787 case QUIRK_SBZ: 3788 snd_hda_codec_set_gpio(codec, 0x07, 0x07, 0x04, 0); 3789 snd_hda_codec_write(codec, 0x01, 0, 3790 AC_VERB_SET_GPIO_DATA, 0x06); 3791 break; 3792 case QUIRK_R3DI: 3793 snd_hda_codec_set_gpio(codec, 0x1F, 0x1E, 0x0C, 0); 3794 break; 3795 default: 3796 break; 3797 } 3798 } 3799 3800 /* 3801 * GPIO control functions for the Recon3D integrated. 3802 */ 3803 3804 enum r3di_gpio_bit { 3805 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3806 R3DI_MIC_SELECT_BIT = 1, 3807 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3808 R3DI_OUT_SELECT_BIT = 2, 3809 /* 3810 * I dunno what this actually does, but it stays on until the dsp 3811 * is downloaded. 3812 */ 3813 R3DI_GPIO_DSP_DOWNLOADING = 3, 3814 /* 3815 * Same as above, no clue what it does, but it comes on after the dsp 3816 * is downloaded. 3817 */ 3818 R3DI_GPIO_DSP_DOWNLOADED = 4 3819 }; 3820 3821 enum r3di_mic_select { 3822 /* Set GPIO bit 1 to 0 for rear mic */ 3823 R3DI_REAR_MIC = 0, 3824 /* Set GPIO bit 1 to 1 for front microphone*/ 3825 R3DI_FRONT_MIC = 1 3826 }; 3827 3828 enum r3di_out_select { 3829 /* Set GPIO bit 2 to 0 for headphone */ 3830 R3DI_HEADPHONE_OUT = 0, 3831 /* Set GPIO bit 2 to 1 for speaker */ 3832 R3DI_LINE_OUT = 1 3833 }; 3834 enum r3di_dsp_status { 3835 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3836 R3DI_DSP_DOWNLOADING = 0, 3837 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3838 R3DI_DSP_DOWNLOADED = 1 3839 }; 3840 3841 3842 static void r3di_gpio_mic_set(struct hda_codec *codec, 3843 enum r3di_mic_select cur_mic) 3844 { 3845 unsigned int cur_gpio; 3846 3847 /* Get the current GPIO Data setup */ 3848 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3849 3850 switch (cur_mic) { 3851 case R3DI_REAR_MIC: 3852 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3853 break; 3854 case R3DI_FRONT_MIC: 3855 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3856 break; 3857 } 3858 snd_hda_codec_write(codec, codec->core.afg, 0, 3859 AC_VERB_SET_GPIO_DATA, cur_gpio); 3860 } 3861 3862 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3863 enum r3di_dsp_status dsp_status) 3864 { 3865 unsigned int cur_gpio; 3866 3867 /* Get the current GPIO Data setup */ 3868 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3869 3870 switch (dsp_status) { 3871 case R3DI_DSP_DOWNLOADING: 3872 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3873 snd_hda_codec_write(codec, codec->core.afg, 0, 3874 AC_VERB_SET_GPIO_DATA, cur_gpio); 3875 break; 3876 case R3DI_DSP_DOWNLOADED: 3877 /* Set DOWNLOADING bit to 0. */ 3878 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3879 3880 snd_hda_codec_write(codec, codec->core.afg, 0, 3881 AC_VERB_SET_GPIO_DATA, cur_gpio); 3882 3883 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3884 break; 3885 } 3886 3887 snd_hda_codec_write(codec, codec->core.afg, 0, 3888 AC_VERB_SET_GPIO_DATA, cur_gpio); 3889 } 3890 3891 /* 3892 * PCM callbacks 3893 */ 3894 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3895 struct hda_codec *codec, 3896 unsigned int stream_tag, 3897 unsigned int format, 3898 struct snd_pcm_substream *substream) 3899 { 3900 struct ca0132_spec *spec = codec->spec; 3901 3902 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3903 3904 return 0; 3905 } 3906 3907 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3908 struct hda_codec *codec, 3909 struct snd_pcm_substream *substream) 3910 { 3911 struct ca0132_spec *spec = codec->spec; 3912 3913 if (spec->dsp_state == DSP_DOWNLOADING) 3914 return 0; 3915 3916 /*If Playback effects are on, allow stream some time to flush 3917 *effects tail*/ 3918 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3919 msleep(50); 3920 3921 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3922 3923 return 0; 3924 } 3925 3926 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3927 struct hda_codec *codec, 3928 struct snd_pcm_substream *substream) 3929 { 3930 struct ca0132_spec *spec = codec->spec; 3931 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3932 struct snd_pcm_runtime *runtime = substream->runtime; 3933 3934 if (spec->dsp_state != DSP_DOWNLOADED) 3935 return 0; 3936 3937 /* Add latency if playback enhancement and either effect is enabled. */ 3938 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3939 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3940 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3941 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3942 } 3943 3944 /* Applying Speaker EQ adds latency as well. */ 3945 if (spec->cur_out_type == SPEAKER_OUT) 3946 latency += DSP_SPEAKER_OUT_LATENCY; 3947 3948 return (latency * runtime->rate) / 1000; 3949 } 3950 3951 /* 3952 * Digital out 3953 */ 3954 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3955 struct hda_codec *codec, 3956 struct snd_pcm_substream *substream) 3957 { 3958 struct ca0132_spec *spec = codec->spec; 3959 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3960 } 3961 3962 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3963 struct hda_codec *codec, 3964 unsigned int stream_tag, 3965 unsigned int format, 3966 struct snd_pcm_substream *substream) 3967 { 3968 struct ca0132_spec *spec = codec->spec; 3969 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3970 stream_tag, format, substream); 3971 } 3972 3973 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3974 struct hda_codec *codec, 3975 struct snd_pcm_substream *substream) 3976 { 3977 struct ca0132_spec *spec = codec->spec; 3978 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3979 } 3980 3981 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3982 struct hda_codec *codec, 3983 struct snd_pcm_substream *substream) 3984 { 3985 struct ca0132_spec *spec = codec->spec; 3986 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3987 } 3988 3989 /* 3990 * Analog capture 3991 */ 3992 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3993 struct hda_codec *codec, 3994 unsigned int stream_tag, 3995 unsigned int format, 3996 struct snd_pcm_substream *substream) 3997 { 3998 snd_hda_codec_setup_stream(codec, hinfo->nid, 3999 stream_tag, 0, format); 4000 4001 return 0; 4002 } 4003 4004 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 4005 struct hda_codec *codec, 4006 struct snd_pcm_substream *substream) 4007 { 4008 struct ca0132_spec *spec = codec->spec; 4009 4010 if (spec->dsp_state == DSP_DOWNLOADING) 4011 return 0; 4012 4013 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4014 return 0; 4015 } 4016 4017 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4018 struct hda_codec *codec, 4019 struct snd_pcm_substream *substream) 4020 { 4021 struct ca0132_spec *spec = codec->spec; 4022 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4023 struct snd_pcm_runtime *runtime = substream->runtime; 4024 4025 if (spec->dsp_state != DSP_DOWNLOADED) 4026 return 0; 4027 4028 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4029 latency += DSP_CRYSTAL_VOICE_LATENCY; 4030 4031 return (latency * runtime->rate) / 1000; 4032 } 4033 4034 /* 4035 * Controls stuffs. 4036 */ 4037 4038 /* 4039 * Mixer controls helpers. 4040 */ 4041 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4042 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4043 .name = xname, \ 4044 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4045 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4046 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4047 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4048 .info = ca0132_volume_info, \ 4049 .get = ca0132_volume_get, \ 4050 .put = ca0132_volume_put, \ 4051 .tlv = { .c = ca0132_volume_tlv }, \ 4052 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4053 4054 /* 4055 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4056 * volume put, which is used for setting the DSP volume. This was done because 4057 * the ca0132 functions were taking too much time and causing lag. 4058 */ 4059 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4060 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4061 .name = xname, \ 4062 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4063 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4064 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4065 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4066 .info = snd_hda_mixer_amp_volume_info, \ 4067 .get = snd_hda_mixer_amp_volume_get, \ 4068 .put = ca0132_alt_volume_put, \ 4069 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4070 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4071 4072 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4073 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4074 .name = xname, \ 4075 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4076 .info = snd_hda_mixer_amp_switch_info, \ 4077 .get = ca0132_switch_get, \ 4078 .put = ca0132_switch_put, \ 4079 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4080 4081 /* stereo */ 4082 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4083 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4084 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4085 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4086 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4087 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4088 4089 /* lookup tables */ 4090 /* 4091 * Lookup table with decibel values for the DSP. When volume is changed in 4092 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4093 * these values have decimal points, probably because the Windows driver 4094 * actually uses floating point. We can't here, so I made a lookup table of 4095 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4096 * DAC's, and 9 is the maximum. 4097 */ 4098 static const unsigned int float_vol_db_lookup[] = { 4099 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4100 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4101 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4102 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4103 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4104 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4105 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4106 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4107 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4108 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4109 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4110 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4111 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4112 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4113 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4114 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4115 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4116 }; 4117 4118 /* 4119 * This table counts from float 0 to 1 in increments of .01, which is 4120 * useful for a few different sliders. 4121 */ 4122 static const unsigned int float_zero_to_one_lookup[] = { 4123 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4124 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4125 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4126 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4127 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4128 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4129 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4130 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4131 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4132 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4133 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4134 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4135 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4136 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4137 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4138 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4139 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4140 }; 4141 4142 /* 4143 * This table counts from float 10 to 1000, which is the range of the x-bass 4144 * crossover slider in Windows. 4145 */ 4146 static const unsigned int float_xbass_xover_lookup[] = { 4147 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4148 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4149 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4150 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4151 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4152 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4153 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4154 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4155 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4156 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4157 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4158 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4159 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4160 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4161 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4162 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4163 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4164 }; 4165 4166 /* The following are for tuning of products */ 4167 #ifdef ENABLE_TUNING_CONTROLS 4168 4169 static const unsigned int voice_focus_vals_lookup[] = { 4170 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4171 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4172 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4173 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4174 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4175 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4176 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4177 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4178 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4179 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4180 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4181 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4182 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4183 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4184 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4185 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4186 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4187 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4188 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4189 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4190 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4191 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4192 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4193 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4194 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4195 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4196 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4197 }; 4198 4199 static const unsigned int mic_svm_vals_lookup[] = { 4200 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4201 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4202 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4203 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4204 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4205 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4206 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4207 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4208 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4209 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4210 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4211 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4212 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4213 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4214 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4215 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4216 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4217 }; 4218 4219 static const unsigned int equalizer_vals_lookup[] = { 4220 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4221 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4222 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4223 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4224 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4225 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4226 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4227 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4228 0x41C00000 4229 }; 4230 4231 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4232 const unsigned int *lookup, int idx) 4233 { 4234 int i; 4235 4236 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4237 if (nid == ca0132_tuning_ctls[i].nid) { 4238 CLASS(snd_hda_power, pm)(codec); 4239 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4240 ca0132_tuning_ctls[i].req, 4241 &(lookup[idx]), sizeof(unsigned int)); 4242 return 1; 4243 } 4244 } 4245 4246 return -EINVAL; 4247 } 4248 4249 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4250 struct snd_ctl_elem_value *ucontrol) 4251 { 4252 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4253 struct ca0132_spec *spec = codec->spec; 4254 hda_nid_t nid = get_amp_nid(kcontrol); 4255 long *valp = ucontrol->value.integer.value; 4256 int idx = nid - TUNING_CTL_START_NID; 4257 4258 *valp = spec->cur_ctl_vals[idx]; 4259 return 0; 4260 } 4261 4262 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4263 struct snd_ctl_elem_info *uinfo) 4264 { 4265 int chs = get_amp_channels(kcontrol); 4266 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4267 uinfo->count = chs == 3 ? 2 : 1; 4268 uinfo->value.integer.min = 20; 4269 uinfo->value.integer.max = 180; 4270 uinfo->value.integer.step = 1; 4271 4272 return 0; 4273 } 4274 4275 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4276 struct snd_ctl_elem_value *ucontrol) 4277 { 4278 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4279 struct ca0132_spec *spec = codec->spec; 4280 hda_nid_t nid = get_amp_nid(kcontrol); 4281 long *valp = ucontrol->value.integer.value; 4282 int idx; 4283 4284 idx = nid - TUNING_CTL_START_NID; 4285 /* any change? */ 4286 if (spec->cur_ctl_vals[idx] == *valp) 4287 return 0; 4288 4289 spec->cur_ctl_vals[idx] = *valp; 4290 4291 idx = *valp - 20; 4292 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4293 4294 return 1; 4295 } 4296 4297 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4298 struct snd_ctl_elem_info *uinfo) 4299 { 4300 int chs = get_amp_channels(kcontrol); 4301 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4302 uinfo->count = chs == 3 ? 2 : 1; 4303 uinfo->value.integer.min = 0; 4304 uinfo->value.integer.max = 100; 4305 uinfo->value.integer.step = 1; 4306 4307 return 0; 4308 } 4309 4310 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4311 struct snd_ctl_elem_value *ucontrol) 4312 { 4313 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4314 struct ca0132_spec *spec = codec->spec; 4315 hda_nid_t nid = get_amp_nid(kcontrol); 4316 long *valp = ucontrol->value.integer.value; 4317 int idx; 4318 4319 idx = nid - TUNING_CTL_START_NID; 4320 /* any change? */ 4321 if (spec->cur_ctl_vals[idx] == *valp) 4322 return 0; 4323 4324 spec->cur_ctl_vals[idx] = *valp; 4325 4326 idx = *valp; 4327 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4328 4329 return 0; 4330 } 4331 4332 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4333 struct snd_ctl_elem_info *uinfo) 4334 { 4335 int chs = get_amp_channels(kcontrol); 4336 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4337 uinfo->count = chs == 3 ? 2 : 1; 4338 uinfo->value.integer.min = 0; 4339 uinfo->value.integer.max = 48; 4340 uinfo->value.integer.step = 1; 4341 4342 return 0; 4343 } 4344 4345 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4346 struct snd_ctl_elem_value *ucontrol) 4347 { 4348 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4349 struct ca0132_spec *spec = codec->spec; 4350 hda_nid_t nid = get_amp_nid(kcontrol); 4351 long *valp = ucontrol->value.integer.value; 4352 int idx; 4353 4354 idx = nid - TUNING_CTL_START_NID; 4355 /* any change? */ 4356 if (spec->cur_ctl_vals[idx] == *valp) 4357 return 0; 4358 4359 spec->cur_ctl_vals[idx] = *valp; 4360 4361 idx = *valp; 4362 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4363 4364 return 1; 4365 } 4366 4367 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4368 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4369 4370 static int add_tuning_control(struct hda_codec *codec, 4371 hda_nid_t pnid, hda_nid_t nid, 4372 const char *name, int dir) 4373 { 4374 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4375 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4376 struct snd_kcontrol_new knew = 4377 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4378 4379 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4380 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4381 knew.tlv.c = NULL; 4382 knew.tlv.p = NULL; 4383 switch (pnid) { 4384 case VOICE_FOCUS: 4385 knew.info = voice_focus_ctl_info; 4386 knew.get = tuning_ctl_get; 4387 knew.put = voice_focus_ctl_put; 4388 knew.tlv.p = voice_focus_db_scale; 4389 break; 4390 case MIC_SVM: 4391 knew.info = mic_svm_ctl_info; 4392 knew.get = tuning_ctl_get; 4393 knew.put = mic_svm_ctl_put; 4394 break; 4395 case EQUALIZER: 4396 knew.info = equalizer_ctl_info; 4397 knew.get = tuning_ctl_get; 4398 knew.put = equalizer_ctl_put; 4399 knew.tlv.p = eq_db_scale; 4400 break; 4401 default: 4402 return 0; 4403 } 4404 knew.private_value = 4405 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4406 snprintf(namestr, sizeof(namestr), "%s %s Volume", name, dirstr[dir]); 4407 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4408 } 4409 4410 static int add_tuning_ctls(struct hda_codec *codec) 4411 { 4412 int i; 4413 int err; 4414 4415 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4416 err = add_tuning_control(codec, 4417 ca0132_tuning_ctls[i].parent_nid, 4418 ca0132_tuning_ctls[i].nid, 4419 ca0132_tuning_ctls[i].name, 4420 ca0132_tuning_ctls[i].direct); 4421 if (err < 0) 4422 return err; 4423 } 4424 4425 return 0; 4426 } 4427 4428 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4429 { 4430 struct ca0132_spec *spec = codec->spec; 4431 int i; 4432 4433 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4434 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4435 /* SVM level defaults to 0.74. */ 4436 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4437 4438 /* EQ defaults to 0dB. */ 4439 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4440 spec->cur_ctl_vals[i] = 24; 4441 } 4442 #endif /*ENABLE_TUNING_CONTROLS*/ 4443 4444 /* 4445 * Select the active output. 4446 * If autodetect is enabled, output will be selected based on jack detection. 4447 * If jack inserted, headphone will be selected, else built-in speakers 4448 * If autodetect is disabled, output will be selected based on selection. 4449 */ 4450 static int ca0132_select_out(struct hda_codec *codec) 4451 { 4452 struct ca0132_spec *spec = codec->spec; 4453 unsigned int pin_ctl; 4454 int jack_present; 4455 int auto_jack; 4456 unsigned int tmp; 4457 int err; 4458 4459 codec_dbg(codec, "ca0132_select_out\n"); 4460 4461 CLASS(snd_hda_power_pm, pm)(codec); 4462 4463 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4464 4465 if (auto_jack) 4466 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4467 else 4468 jack_present = 4469 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4470 4471 if (jack_present) 4472 spec->cur_out_type = HEADPHONE_OUT; 4473 else 4474 spec->cur_out_type = SPEAKER_OUT; 4475 4476 if (spec->cur_out_type == SPEAKER_OUT) { 4477 codec_dbg(codec, "ca0132_select_out speaker\n"); 4478 /*speaker out config*/ 4479 tmp = FLOAT_ONE; 4480 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4481 if (err < 0) 4482 return err; 4483 /*enable speaker EQ*/ 4484 tmp = FLOAT_ONE; 4485 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4486 if (err < 0) 4487 return err; 4488 4489 /* Setup EAPD */ 4490 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4491 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4492 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4493 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4494 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4495 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4496 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4497 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4498 4499 /* disable headphone node */ 4500 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4501 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4502 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4503 pin_ctl & ~PIN_HP); 4504 /* enable speaker node */ 4505 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4506 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4507 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4508 pin_ctl | PIN_OUT); 4509 } else { 4510 codec_dbg(codec, "ca0132_select_out hp\n"); 4511 /*headphone out config*/ 4512 tmp = FLOAT_ZERO; 4513 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4514 if (err < 0) 4515 return err; 4516 /*disable speaker EQ*/ 4517 tmp = FLOAT_ZERO; 4518 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4519 if (err < 0) 4520 return err; 4521 4522 /* Setup EAPD */ 4523 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4524 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4525 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4526 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4527 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4528 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4529 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4530 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4531 4532 /* disable speaker*/ 4533 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4534 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4535 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4536 pin_ctl & ~PIN_HP); 4537 /* enable headphone*/ 4538 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4539 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4540 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4541 pin_ctl | PIN_HP); 4542 } 4543 4544 return 0; 4545 } 4546 4547 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4548 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4549 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4550 4551 static void ae5_mmio_select_out(struct hda_codec *codec) 4552 { 4553 struct ca0132_spec *spec = codec->spec; 4554 const struct ae_ca0113_output_set *out_cmds; 4555 unsigned int i; 4556 4557 if (ca0132_quirk(spec) == QUIRK_AE5) 4558 out_cmds = &ae5_ca0113_output_presets; 4559 else 4560 out_cmds = &ae7_ca0113_output_presets; 4561 4562 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4563 ca0113_mmio_command_set(codec, out_cmds->group[i], 4564 out_cmds->target[i], 4565 out_cmds->vals[spec->cur_out_type][i]); 4566 } 4567 4568 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4569 { 4570 struct ca0132_spec *spec = codec->spec; 4571 int quirk = ca0132_quirk(spec); 4572 unsigned int tmp; 4573 int err; 4574 4575 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4576 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4577 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4578 return 0; 4579 4580 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4581 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4582 err = dspio_set_uint_param(codec, 0x96, 4583 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4584 if (err < 0) 4585 return err; 4586 4587 /* When setting full-range rear, both rear and center/lfe are set. */ 4588 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4589 err = dspio_set_uint_param(codec, 0x96, 4590 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4591 if (err < 0) 4592 return err; 4593 4594 err = dspio_set_uint_param(codec, 0x96, 4595 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4596 if (err < 0) 4597 return err; 4598 4599 /* 4600 * Only the AE series cards set this value when setting full-range, 4601 * and it's always 1.0f. 4602 */ 4603 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4604 err = dspio_set_uint_param(codec, 0x96, 4605 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4606 if (err < 0) 4607 return err; 4608 } 4609 4610 return 0; 4611 } 4612 4613 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4614 bool val) 4615 { 4616 struct ca0132_spec *spec = codec->spec; 4617 unsigned int tmp; 4618 int err; 4619 4620 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4621 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4622 tmp = FLOAT_ONE; 4623 else 4624 tmp = FLOAT_ZERO; 4625 4626 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4627 if (err < 0) 4628 return err; 4629 4630 /* If it is enabled, make sure to set the crossover frequency. */ 4631 if (tmp) { 4632 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4633 err = dspio_set_uint_param(codec, 0x96, 4634 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4635 if (err < 0) 4636 return err; 4637 } 4638 4639 return 0; 4640 } 4641 4642 /* 4643 * These are the commands needed to setup output on each of the different card 4644 * types. 4645 */ 4646 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4647 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4648 { 4649 struct ca0132_spec *spec = codec->spec; 4650 int quirk = ca0132_quirk(spec); 4651 unsigned int i; 4652 4653 *quirk_data = NULL; 4654 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4655 if (quirk_out_set_data[i].quirk_id == quirk) { 4656 *quirk_data = &quirk_out_set_data[i]; 4657 return; 4658 } 4659 } 4660 } 4661 4662 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4663 { 4664 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4665 const struct ca0132_alt_out_set_info *out_info; 4666 struct ca0132_spec *spec = codec->spec; 4667 unsigned int i, gpio_data; 4668 int err; 4669 4670 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4671 if (!quirk_data) 4672 return 0; 4673 4674 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4675 if (quirk_data->is_ae_series) 4676 ae5_mmio_select_out(codec); 4677 4678 if (out_info->has_hda_gpio) { 4679 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4680 AC_VERB_GET_GPIO_DATA, 0); 4681 4682 if (out_info->hda_gpio_set) 4683 gpio_data |= (1 << out_info->hda_gpio_pin); 4684 else 4685 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4686 4687 snd_hda_codec_write(codec, codec->core.afg, 0, 4688 AC_VERB_SET_GPIO_DATA, gpio_data); 4689 } 4690 4691 if (out_info->mmio_gpio_count) { 4692 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4693 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4694 out_info->mmio_gpio_set[i]); 4695 } 4696 } 4697 4698 if (out_info->scp_cmds_count) { 4699 for (i = 0; i < out_info->scp_cmds_count; i++) { 4700 err = dspio_set_uint_param(codec, 4701 out_info->scp_cmd_mid[i], 4702 out_info->scp_cmd_req[i], 4703 out_info->scp_cmd_val[i]); 4704 if (err < 0) 4705 return err; 4706 } 4707 } 4708 4709 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4710 4711 if (out_info->has_chipio_write) { 4712 chipio_write(codec, out_info->chipio_write_addr, 4713 out_info->chipio_write_data); 4714 } 4715 4716 if (quirk_data->has_headphone_gain) { 4717 if (spec->cur_out_type != HEADPHONE_OUT) { 4718 if (quirk_data->is_ae_series) 4719 ae5_headphone_gain_set(codec, 2); 4720 else 4721 zxr_headphone_gain_set(codec, 0); 4722 } else { 4723 if (quirk_data->is_ae_series) 4724 ae5_headphone_gain_set(codec, 4725 spec->ae5_headphone_gain_val); 4726 else 4727 zxr_headphone_gain_set(codec, 4728 spec->zxr_gain_set); 4729 } 4730 } 4731 4732 return 0; 4733 } 4734 4735 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4736 bool out_enable, bool hp_enable) 4737 { 4738 unsigned int pin_ctl; 4739 4740 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4741 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4742 4743 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4744 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4745 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4746 } 4747 4748 /* 4749 * This function behaves similarly to the ca0132_select_out funciton above, 4750 * except with a few differences. It adds the ability to select the current 4751 * output with an enumerated control "output source" if the auto detect 4752 * mute switch is set to off. If the auto detect mute switch is enabled, it 4753 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4754 * It also adds the ability to auto-detect the front headphone port. 4755 */ 4756 static int ca0132_alt_select_out(struct hda_codec *codec) 4757 { 4758 struct ca0132_spec *spec = codec->spec; 4759 unsigned int tmp, outfx_set; 4760 int jack_present; 4761 int auto_jack; 4762 int err; 4763 /* Default Headphone is rear headphone */ 4764 hda_nid_t headphone_nid = spec->out_pins[1]; 4765 4766 codec_dbg(codec, "%s\n", __func__); 4767 4768 CLASS(snd_hda_power_pm, pm)(codec); 4769 4770 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4771 4772 /* 4773 * If headphone rear or front is plugged in, set to headphone. 4774 * If neither is plugged in, set to rear line out. Only if 4775 * hp/speaker auto detect is enabled. 4776 */ 4777 if (auto_jack) { 4778 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4779 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4780 4781 if (jack_present) 4782 spec->cur_out_type = HEADPHONE_OUT; 4783 else 4784 spec->cur_out_type = SPEAKER_OUT; 4785 } else 4786 spec->cur_out_type = spec->out_enum_val; 4787 4788 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4789 4790 /* Begin DSP output switch, mute DSP volume. */ 4791 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4792 if (err < 0) 4793 return err; 4794 4795 err = ca0132_alt_select_out_quirk_set(codec); 4796 if (err < 0) 4797 return err; 4798 4799 switch (spec->cur_out_type) { 4800 case SPEAKER_OUT: 4801 codec_dbg(codec, "%s speaker\n", __func__); 4802 4803 /* Enable EAPD */ 4804 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4805 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4806 4807 /* Disable headphone node. */ 4808 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4809 /* Set front L-R to output. */ 4810 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4811 /* Set Center/LFE to output. */ 4812 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4813 /* Set rear surround to output. */ 4814 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4815 4816 /* 4817 * Without PlayEnhancement being enabled, if we've got a 2.0 4818 * setup, set it to floating point eight to disable any DSP 4819 * processing effects. 4820 */ 4821 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4822 tmp = FLOAT_EIGHT; 4823 else 4824 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4825 4826 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4827 if (err < 0) 4828 return err; 4829 4830 break; 4831 case HEADPHONE_OUT: 4832 codec_dbg(codec, "%s hp\n", __func__); 4833 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4834 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4835 4836 /* Disable all speaker nodes. */ 4837 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4838 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4839 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4840 4841 /* enable headphone, either front or rear */ 4842 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4843 headphone_nid = spec->out_pins[2]; 4844 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4845 headphone_nid = spec->out_pins[1]; 4846 4847 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4848 4849 if (outfx_set) 4850 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4851 else 4852 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4853 4854 if (err < 0) 4855 return err; 4856 break; 4857 } 4858 /* 4859 * If output effects are enabled, set the X-Bass effect value again to 4860 * make sure that it's properly enabled/disabled for speaker 4861 * configurations with an LFE channel. 4862 */ 4863 if (outfx_set) 4864 ca0132_effects_set(codec, X_BASS, 4865 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4866 4867 /* Set speaker EQ bypass attenuation to 0. */ 4868 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4869 if (err < 0) 4870 return err; 4871 4872 /* 4873 * Although unused on all cards but the AE series, this is always set 4874 * to zero when setting the output. 4875 */ 4876 err = dspio_set_uint_param(codec, 0x96, 4877 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4878 if (err < 0) 4879 return err; 4880 4881 if (spec->cur_out_type == SPEAKER_OUT) 4882 err = ca0132_alt_surround_set_bass_redirection(codec, 4883 spec->bass_redirection_val); 4884 else 4885 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4886 if (err < 0) 4887 return err; 4888 4889 /* Unmute DSP now that we're done with output selection. */ 4890 err = dspio_set_uint_param(codec, 0x96, 4891 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4892 if (err < 0) 4893 return err; 4894 4895 if (spec->cur_out_type == SPEAKER_OUT) { 4896 err = ca0132_alt_set_full_range_speaker(codec); 4897 if (err < 0) 4898 return err; 4899 } 4900 4901 return 0; 4902 } 4903 4904 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4905 { 4906 struct ca0132_spec *spec = container_of( 4907 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4908 struct hda_jack_tbl *jack; 4909 4910 if (ca0132_use_alt_functions(spec)) 4911 ca0132_alt_select_out(spec->codec); 4912 else 4913 ca0132_select_out(spec->codec); 4914 4915 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4916 if (jack) { 4917 jack->block_report = 0; 4918 snd_hda_jack_report_sync(spec->codec); 4919 } 4920 } 4921 4922 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4923 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4924 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4925 static int stop_mic1(struct hda_codec *codec); 4926 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4927 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4928 4929 /* 4930 * Select the active VIP source 4931 */ 4932 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4933 { 4934 struct ca0132_spec *spec = codec->spec; 4935 unsigned int tmp; 4936 4937 if (spec->dsp_state != DSP_DOWNLOADED) 4938 return 0; 4939 4940 /* if CrystalVoice if off, vipsource should be 0 */ 4941 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4942 (val == 0)) { 4943 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4944 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4945 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4946 if (spec->cur_mic_type == DIGITAL_MIC) 4947 tmp = FLOAT_TWO; 4948 else 4949 tmp = FLOAT_ONE; 4950 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4951 tmp = FLOAT_ZERO; 4952 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4953 } else { 4954 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4955 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4956 if (spec->cur_mic_type == DIGITAL_MIC) 4957 tmp = FLOAT_TWO; 4958 else 4959 tmp = FLOAT_ONE; 4960 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4961 tmp = FLOAT_ONE; 4962 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4963 msleep(20); 4964 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4965 } 4966 4967 return 1; 4968 } 4969 4970 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4971 { 4972 struct ca0132_spec *spec = codec->spec; 4973 unsigned int tmp; 4974 4975 if (spec->dsp_state != DSP_DOWNLOADED) 4976 return 0; 4977 4978 codec_dbg(codec, "%s\n", __func__); 4979 4980 chipio_set_stream_control(codec, 0x03, 0); 4981 chipio_set_stream_control(codec, 0x04, 0); 4982 4983 /* if CrystalVoice is off, vipsource should be 0 */ 4984 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4985 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4986 codec_dbg(codec, "%s: off.", __func__); 4987 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4988 4989 tmp = FLOAT_ZERO; 4990 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4991 4992 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4993 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4994 if (ca0132_quirk(spec) == QUIRK_R3DI) 4995 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4996 4997 4998 if (spec->in_enum_val == REAR_LINE_IN) 4999 tmp = FLOAT_ZERO; 5000 else { 5001 if (ca0132_quirk(spec) == QUIRK_SBZ) 5002 tmp = FLOAT_THREE; 5003 else 5004 tmp = FLOAT_ONE; 5005 } 5006 5007 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5008 5009 } else { 5010 codec_dbg(codec, "%s: on.", __func__); 5011 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5012 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5013 if (ca0132_quirk(spec) == QUIRK_R3DI) 5014 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5015 5016 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5017 tmp = FLOAT_TWO; 5018 else 5019 tmp = FLOAT_ONE; 5020 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5021 5022 tmp = FLOAT_ONE; 5023 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5024 5025 msleep(20); 5026 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5027 } 5028 5029 chipio_set_stream_control(codec, 0x03, 1); 5030 chipio_set_stream_control(codec, 0x04, 1); 5031 5032 return 1; 5033 } 5034 5035 /* 5036 * Select the active microphone. 5037 * If autodetect is enabled, mic will be selected based on jack detection. 5038 * If jack inserted, ext.mic will be selected, else built-in mic 5039 * If autodetect is disabled, mic will be selected based on selection. 5040 */ 5041 static int ca0132_select_mic(struct hda_codec *codec) 5042 { 5043 struct ca0132_spec *spec = codec->spec; 5044 int jack_present; 5045 int auto_jack; 5046 5047 codec_dbg(codec, "ca0132_select_mic\n"); 5048 5049 CLASS(snd_hda_power_pm, pm)(codec); 5050 5051 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5052 5053 if (auto_jack) 5054 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5055 else 5056 jack_present = 5057 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5058 5059 if (jack_present) 5060 spec->cur_mic_type = LINE_MIC_IN; 5061 else 5062 spec->cur_mic_type = DIGITAL_MIC; 5063 5064 if (spec->cur_mic_type == DIGITAL_MIC) { 5065 /* enable digital Mic */ 5066 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5067 ca0132_set_dmic(codec, 1); 5068 ca0132_mic_boost_set(codec, 0); 5069 /* set voice focus */ 5070 ca0132_effects_set(codec, VOICE_FOCUS, 5071 spec->effects_switch 5072 [VOICE_FOCUS - EFFECT_START_NID]); 5073 } else { 5074 /* disable digital Mic */ 5075 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5076 ca0132_set_dmic(codec, 0); 5077 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5078 /* disable voice focus */ 5079 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5080 } 5081 5082 return 0; 5083 } 5084 5085 /* 5086 * Select the active input. 5087 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5088 * The front mic has no jack-detection, so the only way to switch to it 5089 * is to do it manually in alsamixer. 5090 */ 5091 static int ca0132_alt_select_in(struct hda_codec *codec) 5092 { 5093 struct ca0132_spec *spec = codec->spec; 5094 unsigned int tmp; 5095 5096 codec_dbg(codec, "%s\n", __func__); 5097 5098 CLASS(snd_hda_power_pm, pm)(codec); 5099 5100 chipio_set_stream_control(codec, 0x03, 0); 5101 chipio_set_stream_control(codec, 0x04, 0); 5102 5103 spec->cur_mic_type = spec->in_enum_val; 5104 5105 switch (spec->cur_mic_type) { 5106 case REAR_MIC: 5107 switch (ca0132_quirk(spec)) { 5108 case QUIRK_SBZ: 5109 case QUIRK_R3D: 5110 ca0113_mmio_gpio_set(codec, 0, false); 5111 tmp = FLOAT_THREE; 5112 break; 5113 case QUIRK_ZXR: 5114 tmp = FLOAT_THREE; 5115 break; 5116 case QUIRK_R3DI: 5117 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5118 tmp = FLOAT_ONE; 5119 break; 5120 case QUIRK_AE5: 5121 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5122 tmp = FLOAT_THREE; 5123 break; 5124 case QUIRK_AE7: 5125 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5126 tmp = FLOAT_THREE; 5127 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5128 SR_96_000); 5129 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5130 SR_96_000); 5131 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5132 break; 5133 default: 5134 tmp = FLOAT_ONE; 5135 break; 5136 } 5137 5138 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5139 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5140 if (ca0132_quirk(spec) == QUIRK_R3DI) 5141 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5142 5143 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5144 5145 chipio_set_stream_control(codec, 0x03, 1); 5146 chipio_set_stream_control(codec, 0x04, 1); 5147 switch (ca0132_quirk(spec)) { 5148 case QUIRK_SBZ: 5149 chipio_write(codec, 0x18B098, 0x0000000C); 5150 chipio_write(codec, 0x18B09C, 0x0000000C); 5151 break; 5152 case QUIRK_ZXR: 5153 chipio_write(codec, 0x18B098, 0x0000000C); 5154 chipio_write(codec, 0x18B09C, 0x000000CC); 5155 break; 5156 case QUIRK_AE5: 5157 chipio_write(codec, 0x18B098, 0x0000000C); 5158 chipio_write(codec, 0x18B09C, 0x0000004C); 5159 break; 5160 default: 5161 break; 5162 } 5163 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5164 break; 5165 case REAR_LINE_IN: 5166 ca0132_mic_boost_set(codec, 0); 5167 switch (ca0132_quirk(spec)) { 5168 case QUIRK_SBZ: 5169 case QUIRK_R3D: 5170 ca0113_mmio_gpio_set(codec, 0, false); 5171 break; 5172 case QUIRK_R3DI: 5173 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5174 break; 5175 case QUIRK_AE5: 5176 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5177 break; 5178 case QUIRK_AE7: 5179 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5180 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5181 SR_96_000); 5182 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5183 SR_96_000); 5184 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5185 break; 5186 default: 5187 break; 5188 } 5189 5190 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5191 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5192 if (ca0132_quirk(spec) == QUIRK_R3DI) 5193 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5194 5195 if (ca0132_quirk(spec) == QUIRK_AE7) 5196 tmp = FLOAT_THREE; 5197 else 5198 tmp = FLOAT_ZERO; 5199 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5200 5201 switch (ca0132_quirk(spec)) { 5202 case QUIRK_SBZ: 5203 case QUIRK_AE5: 5204 chipio_write(codec, 0x18B098, 0x00000000); 5205 chipio_write(codec, 0x18B09C, 0x00000000); 5206 break; 5207 default: 5208 break; 5209 } 5210 chipio_set_stream_control(codec, 0x03, 1); 5211 chipio_set_stream_control(codec, 0x04, 1); 5212 break; 5213 case FRONT_MIC: 5214 switch (ca0132_quirk(spec)) { 5215 case QUIRK_SBZ: 5216 case QUIRK_R3D: 5217 ca0113_mmio_gpio_set(codec, 0, true); 5218 ca0113_mmio_gpio_set(codec, 5, false); 5219 tmp = FLOAT_THREE; 5220 break; 5221 case QUIRK_R3DI: 5222 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5223 tmp = FLOAT_ONE; 5224 break; 5225 case QUIRK_AE5: 5226 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5227 tmp = FLOAT_THREE; 5228 break; 5229 default: 5230 tmp = FLOAT_ONE; 5231 break; 5232 } 5233 5234 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5235 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5236 if (ca0132_quirk(spec) == QUIRK_R3DI) 5237 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5238 5239 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5240 5241 chipio_set_stream_control(codec, 0x03, 1); 5242 chipio_set_stream_control(codec, 0x04, 1); 5243 5244 switch (ca0132_quirk(spec)) { 5245 case QUIRK_SBZ: 5246 chipio_write(codec, 0x18B098, 0x0000000C); 5247 chipio_write(codec, 0x18B09C, 0x000000CC); 5248 break; 5249 case QUIRK_AE5: 5250 chipio_write(codec, 0x18B098, 0x0000000C); 5251 chipio_write(codec, 0x18B09C, 0x0000004C); 5252 break; 5253 default: 5254 break; 5255 } 5256 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5257 break; 5258 } 5259 ca0132_cvoice_switch_set(codec); 5260 5261 return 0; 5262 } 5263 5264 /* 5265 * Check if VNODE settings take effect immediately. 5266 */ 5267 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5268 hda_nid_t vnid, 5269 hda_nid_t *shared_nid) 5270 { 5271 struct ca0132_spec *spec = codec->spec; 5272 hda_nid_t nid; 5273 5274 switch (vnid) { 5275 case VNID_SPK: 5276 nid = spec->shared_out_nid; 5277 break; 5278 case VNID_MIC: 5279 nid = spec->shared_mic_nid; 5280 break; 5281 default: 5282 return false; 5283 } 5284 5285 if (shared_nid) 5286 *shared_nid = nid; 5287 5288 return true; 5289 } 5290 5291 /* 5292 * The following functions are control change helpers. 5293 * They return 0 if no changed. Return 1 if changed. 5294 */ 5295 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5296 { 5297 struct ca0132_spec *spec = codec->spec; 5298 unsigned int tmp; 5299 5300 /* based on CrystalVoice state to enable VoiceFX. */ 5301 if (enable) { 5302 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5303 FLOAT_ONE : FLOAT_ZERO; 5304 } else { 5305 tmp = FLOAT_ZERO; 5306 } 5307 5308 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5309 ca0132_voicefx.reqs[0], tmp); 5310 5311 return 1; 5312 } 5313 5314 /* 5315 * Set the effects parameters 5316 */ 5317 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5318 { 5319 struct ca0132_spec *spec = codec->spec; 5320 unsigned int on, tmp, channel_cfg; 5321 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5322 int err = 0; 5323 int idx = nid - EFFECT_START_NID; 5324 5325 if ((idx < 0) || (idx >= num_fx)) 5326 return 0; /* no changed */ 5327 5328 /* for out effect, qualify with PE */ 5329 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5330 /* if PE if off, turn off out effects. */ 5331 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5332 val = 0; 5333 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5334 channel_cfg = spec->channel_cfg_val; 5335 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5336 channel_cfg != SPEAKER_CHANNELS_4_0) 5337 val = 0; 5338 } 5339 } 5340 5341 /* for in effect, qualify with CrystalVoice */ 5342 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5343 /* if CrystalVoice if off, turn off in effects. */ 5344 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5345 val = 0; 5346 5347 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5348 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5349 val = 0; 5350 5351 /* If Voice Focus on SBZ, set to two channel. */ 5352 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5353 && (spec->cur_mic_type != REAR_LINE_IN)) { 5354 if (spec->effects_switch[CRYSTAL_VOICE - 5355 EFFECT_START_NID]) { 5356 5357 if (spec->effects_switch[VOICE_FOCUS - 5358 EFFECT_START_NID]) { 5359 tmp = FLOAT_TWO; 5360 val = 1; 5361 } else 5362 tmp = FLOAT_ONE; 5363 5364 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5365 } 5366 } 5367 /* 5368 * For SBZ noise reduction, there's an extra command 5369 * to module ID 0x47. No clue why. 5370 */ 5371 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5372 && (spec->cur_mic_type != REAR_LINE_IN)) { 5373 if (spec->effects_switch[CRYSTAL_VOICE - 5374 EFFECT_START_NID]) { 5375 if (spec->effects_switch[NOISE_REDUCTION - 5376 EFFECT_START_NID]) 5377 tmp = FLOAT_ONE; 5378 else 5379 tmp = FLOAT_ZERO; 5380 } else 5381 tmp = FLOAT_ZERO; 5382 5383 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5384 } 5385 5386 /* If rear line in disable effects. */ 5387 if (ca0132_use_alt_functions(spec) && 5388 spec->in_enum_val == REAR_LINE_IN) 5389 val = 0; 5390 } 5391 5392 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5393 nid, val); 5394 5395 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5396 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5397 ca0132_effects[idx].reqs[0], on); 5398 5399 if (err < 0) 5400 return 0; /* no changed */ 5401 5402 return 1; 5403 } 5404 5405 /* 5406 * Turn on/off Playback Enhancements 5407 */ 5408 static int ca0132_pe_switch_set(struct hda_codec *codec) 5409 { 5410 struct ca0132_spec *spec = codec->spec; 5411 hda_nid_t nid; 5412 int i, ret = 0; 5413 5414 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5415 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5416 5417 if (ca0132_use_alt_functions(spec)) 5418 ca0132_alt_select_out(codec); 5419 5420 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5421 nid = OUT_EFFECT_START_NID; 5422 /* PE affects all out effects */ 5423 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5424 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5425 5426 return ret; 5427 } 5428 5429 /* Check if Mic1 is streaming, if so, stop streaming */ 5430 static int stop_mic1(struct hda_codec *codec) 5431 { 5432 struct ca0132_spec *spec = codec->spec; 5433 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5434 AC_VERB_GET_CONV, 0); 5435 if (oldval != 0) 5436 snd_hda_codec_write(codec, spec->adcs[0], 0, 5437 AC_VERB_SET_CHANNEL_STREAMID, 5438 0); 5439 return oldval; 5440 } 5441 5442 /* Resume Mic1 streaming if it was stopped. */ 5443 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5444 { 5445 struct ca0132_spec *spec = codec->spec; 5446 /* Restore the previous stream and channel */ 5447 if (oldval != 0) 5448 snd_hda_codec_write(codec, spec->adcs[0], 0, 5449 AC_VERB_SET_CHANNEL_STREAMID, 5450 oldval); 5451 } 5452 5453 /* 5454 * Turn on/off CrystalVoice 5455 */ 5456 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5457 { 5458 struct ca0132_spec *spec = codec->spec; 5459 hda_nid_t nid; 5460 int i, ret = 0; 5461 unsigned int oldval; 5462 5463 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5464 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5465 5466 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5467 nid = IN_EFFECT_START_NID; 5468 /* CrystalVoice affects all in effects */ 5469 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5470 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5471 5472 /* including VoiceFX */ 5473 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5474 5475 /* set correct vipsource */ 5476 oldval = stop_mic1(codec); 5477 if (ca0132_use_alt_functions(spec)) 5478 ret |= ca0132_alt_set_vipsource(codec, 1); 5479 else 5480 ret |= ca0132_set_vipsource(codec, 1); 5481 resume_mic1(codec, oldval); 5482 return ret; 5483 } 5484 5485 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5486 { 5487 struct ca0132_spec *spec = codec->spec; 5488 int ret = 0; 5489 5490 if (val) /* on */ 5491 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5492 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5493 else /* off */ 5494 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5495 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5496 5497 return ret; 5498 } 5499 5500 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5501 { 5502 struct ca0132_spec *spec = codec->spec; 5503 int ret = 0; 5504 5505 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5506 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5507 return ret; 5508 } 5509 5510 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5511 { 5512 unsigned int i; 5513 5514 for (i = 0; i < 4; i++) 5515 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5516 ae5_headphone_gain_presets[val].vals[i]); 5517 return 0; 5518 } 5519 5520 /* 5521 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5522 * amplifier to handle a 600 ohm load. 5523 */ 5524 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5525 { 5526 ca0113_mmio_gpio_set(codec, 1, val); 5527 5528 return 0; 5529 } 5530 5531 /* 5532 * Manual output selection (HP/Speaker Playback Switch or alt Output Select) 5533 * is meaningful only when HP/Speaker auto-detect is disabled, since the 5534 * select_out path always prefers jack presence when auto-detect is on. When 5535 * the user explicitly chooses an output, turn auto-detect off so the manual 5536 * choice actually takes effect, and notify userspace so the auto-detect 5537 * control reflects the new state. 5538 */ 5539 static void ca0132_disable_hp_auto_detect(struct hda_codec *codec) 5540 { 5541 struct ca0132_spec *spec = codec->spec; 5542 struct snd_kcontrol *kctl; 5543 5544 if (!spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]) 5545 return; 5546 5547 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 0; 5548 kctl = snd_hda_find_mixer_ctl(codec, 5549 "HP/Speaker Auto Detect Playback Switch"); 5550 if (kctl) 5551 snd_ctl_notify(codec->card, SNDRV_CTL_EVENT_MASK_VALUE, 5552 &kctl->id); 5553 } 5554 5555 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5556 struct snd_ctl_elem_value *ucontrol) 5557 { 5558 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5559 hda_nid_t nid = get_amp_nid(kcontrol); 5560 hda_nid_t shared_nid = 0; 5561 bool effective; 5562 int ret = 0; 5563 struct ca0132_spec *spec = codec->spec; 5564 int auto_jack; 5565 5566 if (nid == VNID_HP_SEL) { 5567 ca0132_disable_hp_auto_detect(codec); 5568 if (ca0132_use_alt_functions(spec)) 5569 ca0132_alt_select_out(codec); 5570 else 5571 ca0132_select_out(codec); 5572 return 1; 5573 } 5574 5575 if (nid == VNID_AMIC1_SEL) { 5576 auto_jack = 5577 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5578 if (!auto_jack) 5579 ca0132_select_mic(codec); 5580 return 1; 5581 } 5582 5583 if (nid == VNID_HP_ASEL) { 5584 if (ca0132_use_alt_functions(spec)) 5585 ca0132_alt_select_out(codec); 5586 else 5587 ca0132_select_out(codec); 5588 return 1; 5589 } 5590 5591 if (nid == VNID_AMIC1_ASEL) { 5592 ca0132_select_mic(codec); 5593 return 1; 5594 } 5595 5596 /* if effective conditions, then update hw immediately. */ 5597 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5598 if (effective) { 5599 int dir = get_amp_direction(kcontrol); 5600 int ch = get_amp_channels(kcontrol); 5601 unsigned long pval; 5602 5603 guard(mutex)(&codec->control_mutex); 5604 pval = kcontrol->private_value; 5605 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5606 0, dir); 5607 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5608 kcontrol->private_value = pval; 5609 } 5610 5611 return ret; 5612 } 5613 /* End of control change helpers. */ 5614 5615 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5616 long idx) 5617 { 5618 CLASS(snd_hda_power, pm)(codec); 5619 5620 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5621 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5622 } 5623 5624 /* 5625 * Below I've added controls to mess with the effect levels, I've only enabled 5626 * them on the Sound Blaster Z, but they would probably also work on the 5627 * Chromebook. I figured they were probably tuned specifically for it, and left 5628 * out for a reason. 5629 */ 5630 5631 /* Sets DSP effect level from the sliders above the controls */ 5632 5633 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5634 const unsigned int *lookup, int idx) 5635 { 5636 int i = 0; 5637 unsigned int y; 5638 /* 5639 * For X_BASS, req 2 is actually crossover freq instead of 5640 * effect level 5641 */ 5642 if (nid == X_BASS) 5643 y = 2; 5644 else 5645 y = 1; 5646 5647 CLASS(snd_hda_power, pm)(codec); 5648 if (nid == XBASS_XOVER) { 5649 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5650 if (ca0132_effects[i].nid == X_BASS) 5651 break; 5652 5653 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5654 ca0132_effects[i].reqs[1], 5655 &(lookup[idx - 1]), sizeof(unsigned int)); 5656 } else { 5657 /* Find the actual effect structure */ 5658 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5659 if (nid == ca0132_effects[i].nid) 5660 break; 5661 5662 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5663 ca0132_effects[i].reqs[y], 5664 &(lookup[idx]), sizeof(unsigned int)); 5665 } 5666 5667 return 0; 5668 } 5669 5670 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5671 struct snd_ctl_elem_value *ucontrol) 5672 { 5673 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5674 struct ca0132_spec *spec = codec->spec; 5675 long *valp = ucontrol->value.integer.value; 5676 hda_nid_t nid = get_amp_nid(kcontrol); 5677 5678 if (nid == BASS_REDIRECTION_XOVER) 5679 *valp = spec->bass_redirect_xover_freq; 5680 else 5681 *valp = spec->xbass_xover_freq; 5682 5683 return 0; 5684 } 5685 5686 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5687 struct snd_ctl_elem_value *ucontrol) 5688 { 5689 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5690 struct ca0132_spec *spec = codec->spec; 5691 hda_nid_t nid = get_amp_nid(kcontrol); 5692 long *valp = ucontrol->value.integer.value; 5693 int idx = nid - OUT_EFFECT_START_NID; 5694 5695 *valp = spec->fx_ctl_val[idx]; 5696 return 0; 5697 } 5698 5699 /* 5700 * The X-bass crossover starts at 10hz, so the min is 1. The 5701 * frequency is set in multiples of 10. 5702 */ 5703 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5704 struct snd_ctl_elem_info *uinfo) 5705 { 5706 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5707 uinfo->count = 1; 5708 uinfo->value.integer.min = 1; 5709 uinfo->value.integer.max = 100; 5710 uinfo->value.integer.step = 1; 5711 5712 return 0; 5713 } 5714 5715 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5716 struct snd_ctl_elem_info *uinfo) 5717 { 5718 int chs = get_amp_channels(kcontrol); 5719 5720 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5721 uinfo->count = chs == 3 ? 2 : 1; 5722 uinfo->value.integer.min = 0; 5723 uinfo->value.integer.max = 100; 5724 uinfo->value.integer.step = 1; 5725 5726 return 0; 5727 } 5728 5729 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5730 struct snd_ctl_elem_value *ucontrol) 5731 { 5732 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5733 struct ca0132_spec *spec = codec->spec; 5734 hda_nid_t nid = get_amp_nid(kcontrol); 5735 long *valp = ucontrol->value.integer.value; 5736 long *cur_val; 5737 int idx; 5738 5739 if (nid == BASS_REDIRECTION_XOVER) 5740 cur_val = &spec->bass_redirect_xover_freq; 5741 else 5742 cur_val = &spec->xbass_xover_freq; 5743 5744 /* any change? */ 5745 if (*cur_val == *valp) 5746 return 0; 5747 5748 *cur_val = *valp; 5749 5750 idx = *valp; 5751 if (nid == BASS_REDIRECTION_XOVER) 5752 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5753 else 5754 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5755 5756 return 0; 5757 } 5758 5759 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5760 struct snd_ctl_elem_value *ucontrol) 5761 { 5762 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5763 struct ca0132_spec *spec = codec->spec; 5764 hda_nid_t nid = get_amp_nid(kcontrol); 5765 long *valp = ucontrol->value.integer.value; 5766 int idx; 5767 5768 idx = nid - EFFECT_START_NID; 5769 /* any change? */ 5770 if (spec->fx_ctl_val[idx] == *valp) 5771 return 0; 5772 5773 spec->fx_ctl_val[idx] = *valp; 5774 5775 idx = *valp; 5776 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5777 5778 return 0; 5779 } 5780 5781 5782 /* 5783 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5784 * only has off or full 30 dB, and didn't like making a volume slider that has 5785 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5786 */ 5787 #define MIC_BOOST_NUM_OF_STEPS 4 5788 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5789 5790 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5791 struct snd_ctl_elem_info *uinfo) 5792 { 5793 const char *sfx = "dB"; 5794 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5795 5796 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5797 uinfo->count = 1; 5798 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5799 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5800 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5801 snprintf(namestr, sizeof(namestr), "%d %s", 5802 (uinfo->value.enumerated.item * 10), sfx); 5803 strscpy(uinfo->value.enumerated.name, namestr); 5804 return 0; 5805 } 5806 5807 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5808 struct snd_ctl_elem_value *ucontrol) 5809 { 5810 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5811 struct ca0132_spec *spec = codec->spec; 5812 5813 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5814 return 0; 5815 } 5816 5817 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5818 struct snd_ctl_elem_value *ucontrol) 5819 { 5820 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5821 struct ca0132_spec *spec = codec->spec; 5822 int sel = ucontrol->value.enumerated.item[0]; 5823 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5824 5825 if (sel >= items) 5826 return 0; 5827 5828 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5829 sel); 5830 5831 spec->mic_boost_enum_val = sel; 5832 5833 if (spec->in_enum_val != REAR_LINE_IN) 5834 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5835 5836 return 1; 5837 } 5838 5839 /* 5840 * Sound BlasterX AE-5 Headphone Gain Controls. 5841 */ 5842 #define AE5_HEADPHONE_GAIN_MAX 3 5843 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5844 struct snd_ctl_elem_info *uinfo) 5845 { 5846 const char *sfx = " Ohms)"; 5847 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5848 5849 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5850 uinfo->count = 1; 5851 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5852 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5853 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5854 snprintf(namestr, sizeof(namestr), "%s %s", 5855 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5856 sfx); 5857 strscpy(uinfo->value.enumerated.name, namestr); 5858 return 0; 5859 } 5860 5861 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5862 struct snd_ctl_elem_value *ucontrol) 5863 { 5864 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5865 struct ca0132_spec *spec = codec->spec; 5866 5867 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5868 return 0; 5869 } 5870 5871 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5872 struct snd_ctl_elem_value *ucontrol) 5873 { 5874 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5875 struct ca0132_spec *spec = codec->spec; 5876 int sel = ucontrol->value.enumerated.item[0]; 5877 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5878 5879 if (sel >= items) 5880 return 0; 5881 5882 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5883 sel); 5884 5885 spec->ae5_headphone_gain_val = sel; 5886 5887 if (spec->out_enum_val == HEADPHONE_OUT) 5888 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5889 5890 return 1; 5891 } 5892 5893 /* 5894 * Sound BlasterX AE-5 sound filter enumerated control. 5895 */ 5896 #define AE5_SOUND_FILTER_MAX 3 5897 5898 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5899 struct snd_ctl_elem_info *uinfo) 5900 { 5901 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5902 5903 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5904 uinfo->count = 1; 5905 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5906 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5907 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5908 snprintf(namestr, sizeof(namestr), "%s", 5909 ae5_filter_presets[uinfo->value.enumerated.item].name); 5910 strscpy(uinfo->value.enumerated.name, namestr); 5911 return 0; 5912 } 5913 5914 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5915 struct snd_ctl_elem_value *ucontrol) 5916 { 5917 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5918 struct ca0132_spec *spec = codec->spec; 5919 5920 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5921 return 0; 5922 } 5923 5924 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5925 struct snd_ctl_elem_value *ucontrol) 5926 { 5927 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5928 struct ca0132_spec *spec = codec->spec; 5929 int sel = ucontrol->value.enumerated.item[0]; 5930 unsigned int items = AE5_SOUND_FILTER_MAX; 5931 5932 if (sel >= items) 5933 return 0; 5934 5935 codec_dbg(codec, "ae5_sound_filter: %s\n", 5936 ae5_filter_presets[sel].name); 5937 5938 spec->ae5_filter_val = sel; 5939 5940 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5941 ae5_filter_presets[sel].val); 5942 5943 return 1; 5944 } 5945 5946 /* 5947 * Input Select Control for alternative ca0132 codecs. This exists because 5948 * front microphone has no auto-detect, and we need a way to set the rear 5949 * as line-in 5950 */ 5951 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5952 struct snd_ctl_elem_info *uinfo) 5953 { 5954 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5955 uinfo->count = 1; 5956 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5957 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5958 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5959 strscpy(uinfo->value.enumerated.name, 5960 in_src_str[uinfo->value.enumerated.item]); 5961 return 0; 5962 } 5963 5964 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5965 struct snd_ctl_elem_value *ucontrol) 5966 { 5967 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5968 struct ca0132_spec *spec = codec->spec; 5969 5970 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5971 return 0; 5972 } 5973 5974 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5975 struct snd_ctl_elem_value *ucontrol) 5976 { 5977 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5978 struct ca0132_spec *spec = codec->spec; 5979 int sel = ucontrol->value.enumerated.item[0]; 5980 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5981 5982 /* 5983 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5984 * line-in. 5985 */ 5986 if (ca0132_quirk(spec) == QUIRK_AE7) 5987 items = 2; 5988 5989 if (sel >= items) 5990 return 0; 5991 5992 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5993 sel, in_src_str[sel]); 5994 5995 spec->in_enum_val = sel; 5996 5997 ca0132_alt_select_in(codec); 5998 5999 return 1; 6000 } 6001 6002 /* Sound Blaster Z Output Select Control */ 6003 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 6004 struct snd_ctl_elem_info *uinfo) 6005 { 6006 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6007 uinfo->count = 1; 6008 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 6009 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 6010 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 6011 strscpy(uinfo->value.enumerated.name, 6012 out_type_str[uinfo->value.enumerated.item]); 6013 return 0; 6014 } 6015 6016 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6017 struct snd_ctl_elem_value *ucontrol) 6018 { 6019 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6020 struct ca0132_spec *spec = codec->spec; 6021 6022 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6023 return 0; 6024 } 6025 6026 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6027 struct snd_ctl_elem_value *ucontrol) 6028 { 6029 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6030 struct ca0132_spec *spec = codec->spec; 6031 int sel = ucontrol->value.enumerated.item[0]; 6032 unsigned int items = NUM_OF_OUTPUTS; 6033 6034 if (sel >= items) 6035 return 0; 6036 6037 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6038 sel, out_type_str[sel]); 6039 6040 spec->out_enum_val = sel; 6041 6042 ca0132_disable_hp_auto_detect(codec); 6043 ca0132_alt_select_out(codec); 6044 6045 return 1; 6046 } 6047 6048 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6049 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6050 struct snd_ctl_elem_info *uinfo) 6051 { 6052 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6053 6054 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6055 uinfo->count = 1; 6056 uinfo->value.enumerated.items = items; 6057 if (uinfo->value.enumerated.item >= items) 6058 uinfo->value.enumerated.item = items - 1; 6059 strscpy(uinfo->value.enumerated.name, 6060 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6061 return 0; 6062 } 6063 6064 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6065 struct snd_ctl_elem_value *ucontrol) 6066 { 6067 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6068 struct ca0132_spec *spec = codec->spec; 6069 6070 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6071 return 0; 6072 } 6073 6074 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6075 struct snd_ctl_elem_value *ucontrol) 6076 { 6077 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6078 struct ca0132_spec *spec = codec->spec; 6079 int sel = ucontrol->value.enumerated.item[0]; 6080 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6081 6082 if (sel >= items) 6083 return 0; 6084 6085 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6086 sel, speaker_channel_cfgs[sel].name); 6087 6088 spec->channel_cfg_val = sel; 6089 6090 if (spec->out_enum_val == SPEAKER_OUT) 6091 ca0132_alt_select_out(codec); 6092 6093 return 1; 6094 } 6095 6096 /* 6097 * Smart Volume output setting control. Three different settings, Normal, 6098 * which takes the value from the smart volume slider. The two others, loud 6099 * and night, disregard the slider value and have uneditable values. 6100 */ 6101 #define NUM_OF_SVM_SETTINGS 3 6102 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6103 6104 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6105 struct snd_ctl_elem_info *uinfo) 6106 { 6107 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6108 uinfo->count = 1; 6109 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6110 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6111 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6112 strscpy(uinfo->value.enumerated.name, 6113 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6114 return 0; 6115 } 6116 6117 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6118 struct snd_ctl_elem_value *ucontrol) 6119 { 6120 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6121 struct ca0132_spec *spec = codec->spec; 6122 6123 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6124 return 0; 6125 } 6126 6127 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6128 struct snd_ctl_elem_value *ucontrol) 6129 { 6130 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6131 struct ca0132_spec *spec = codec->spec; 6132 int sel = ucontrol->value.enumerated.item[0]; 6133 unsigned int items = NUM_OF_SVM_SETTINGS; 6134 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6135 unsigned int tmp; 6136 6137 if (sel >= items) 6138 return 0; 6139 6140 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6141 sel, out_svm_set_enum_str[sel]); 6142 6143 spec->smart_volume_setting = sel; 6144 6145 switch (sel) { 6146 case 0: 6147 tmp = FLOAT_ZERO; 6148 break; 6149 case 1: 6150 tmp = FLOAT_ONE; 6151 break; 6152 case 2: 6153 tmp = FLOAT_TWO; 6154 break; 6155 default: 6156 tmp = FLOAT_ZERO; 6157 break; 6158 } 6159 /* Req 2 is the Smart Volume Setting req. */ 6160 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6161 ca0132_effects[idx].reqs[2], tmp); 6162 return 1; 6163 } 6164 6165 /* Sound Blaster Z EQ preset controls */ 6166 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6167 struct snd_ctl_elem_info *uinfo) 6168 { 6169 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6170 6171 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6172 uinfo->count = 1; 6173 uinfo->value.enumerated.items = items; 6174 if (uinfo->value.enumerated.item >= items) 6175 uinfo->value.enumerated.item = items - 1; 6176 strscpy(uinfo->value.enumerated.name, 6177 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6178 return 0; 6179 } 6180 6181 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6182 struct snd_ctl_elem_value *ucontrol) 6183 { 6184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6185 struct ca0132_spec *spec = codec->spec; 6186 6187 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6188 return 0; 6189 } 6190 6191 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6192 struct snd_ctl_elem_value *ucontrol) 6193 { 6194 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6195 struct ca0132_spec *spec = codec->spec; 6196 int i, err = 0; 6197 int sel = ucontrol->value.enumerated.item[0]; 6198 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6199 6200 if (sel >= items) 6201 return 0; 6202 6203 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6204 ca0132_alt_eq_presets[sel].name); 6205 /* 6206 * Idx 0 is default. 6207 * Default needs to qualify with CrystalVoice state. 6208 */ 6209 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6210 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6211 ca0132_alt_eq_enum.reqs[i], 6212 ca0132_alt_eq_presets[sel].vals[i]); 6213 if (err < 0) 6214 break; 6215 } 6216 6217 if (err >= 0) 6218 spec->eq_preset_val = sel; 6219 6220 return 1; 6221 } 6222 6223 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6224 struct snd_ctl_elem_info *uinfo) 6225 { 6226 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6227 6228 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6229 uinfo->count = 1; 6230 uinfo->value.enumerated.items = items; 6231 if (uinfo->value.enumerated.item >= items) 6232 uinfo->value.enumerated.item = items - 1; 6233 strscpy(uinfo->value.enumerated.name, 6234 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6235 return 0; 6236 } 6237 6238 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6239 struct snd_ctl_elem_value *ucontrol) 6240 { 6241 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6242 struct ca0132_spec *spec = codec->spec; 6243 6244 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6245 return 0; 6246 } 6247 6248 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6249 struct snd_ctl_elem_value *ucontrol) 6250 { 6251 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6252 struct ca0132_spec *spec = codec->spec; 6253 int i, err = 0; 6254 int sel = ucontrol->value.enumerated.item[0]; 6255 6256 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6257 return 0; 6258 6259 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6260 sel, ca0132_voicefx_presets[sel].name); 6261 6262 /* 6263 * Idx 0 is default. 6264 * Default needs to qualify with CrystalVoice state. 6265 */ 6266 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6267 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6268 ca0132_voicefx.reqs[i], 6269 ca0132_voicefx_presets[sel].vals[i]); 6270 if (err < 0) 6271 break; 6272 } 6273 6274 if (err >= 0) { 6275 spec->voicefx_val = sel; 6276 /* enable voice fx */ 6277 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6278 } 6279 6280 return 1; 6281 } 6282 6283 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6284 struct snd_ctl_elem_value *ucontrol) 6285 { 6286 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6287 struct ca0132_spec *spec = codec->spec; 6288 hda_nid_t nid = get_amp_nid(kcontrol); 6289 int ch = get_amp_channels(kcontrol); 6290 long *valp = ucontrol->value.integer.value; 6291 6292 /* vnode */ 6293 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6294 if (ch & 1) { 6295 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6296 valp++; 6297 } 6298 if (ch & 2) { 6299 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6300 valp++; 6301 } 6302 return 0; 6303 } 6304 6305 /* effects, include PE and CrystalVoice */ 6306 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6307 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6308 return 0; 6309 } 6310 6311 /* mic boost */ 6312 if (nid == spec->input_pins[0]) { 6313 *valp = spec->cur_mic_boost; 6314 return 0; 6315 } 6316 6317 if (nid == ZXR_HEADPHONE_GAIN) { 6318 *valp = spec->zxr_gain_set; 6319 return 0; 6320 } 6321 6322 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6323 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6324 return 0; 6325 } 6326 6327 if (nid == BASS_REDIRECTION) { 6328 *valp = spec->bass_redirection_val; 6329 return 0; 6330 } 6331 6332 return 0; 6333 } 6334 6335 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6336 struct snd_ctl_elem_value *ucontrol) 6337 { 6338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6339 struct ca0132_spec *spec = codec->spec; 6340 hda_nid_t nid = get_amp_nid(kcontrol); 6341 int ch = get_amp_channels(kcontrol); 6342 long *valp = ucontrol->value.integer.value; 6343 6344 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6345 nid, *valp); 6346 6347 CLASS(snd_hda_power, pm)(codec); 6348 /* vnode */ 6349 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6350 if (ch & 1) { 6351 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6352 valp++; 6353 } 6354 if (ch & 2) { 6355 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6356 valp++; 6357 } 6358 return ca0132_vnode_switch_set(kcontrol, ucontrol); 6359 } 6360 6361 /* PE */ 6362 if (nid == PLAY_ENHANCEMENT) { 6363 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6364 return ca0132_pe_switch_set(codec); 6365 } 6366 6367 /* CrystalVoice */ 6368 if (nid == CRYSTAL_VOICE) { 6369 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6370 return ca0132_cvoice_switch_set(codec); 6371 } 6372 6373 /* out and in effects */ 6374 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6375 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6376 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6377 return ca0132_effects_set(codec, nid, *valp); 6378 } 6379 6380 /* mic boost */ 6381 if (nid == spec->input_pins[0]) { 6382 spec->cur_mic_boost = *valp; 6383 if (ca0132_use_alt_functions(spec)) { 6384 if (spec->in_enum_val != REAR_LINE_IN) 6385 return ca0132_mic_boost_set(codec, *valp); 6386 } else { 6387 /* Mic boost does not apply to Digital Mic */ 6388 if (spec->cur_mic_type != DIGITAL_MIC) 6389 return ca0132_mic_boost_set(codec, *valp); 6390 } 6391 6392 return 1; 6393 } 6394 6395 if (nid == ZXR_HEADPHONE_GAIN) { 6396 spec->zxr_gain_set = *valp; 6397 if (spec->cur_out_type == HEADPHONE_OUT) 6398 return zxr_headphone_gain_set(codec, *valp); 6399 else 6400 return 0; 6401 } 6402 6403 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6404 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6405 if (spec->cur_out_type == SPEAKER_OUT) 6406 ca0132_alt_set_full_range_speaker(codec); 6407 6408 return 0; 6409 } 6410 6411 if (nid == BASS_REDIRECTION) { 6412 spec->bass_redirection_val = *valp; 6413 if (spec->cur_out_type == SPEAKER_OUT) 6414 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6415 6416 return 0; 6417 } 6418 6419 return 1; 6420 } 6421 6422 /* 6423 * Volume related 6424 */ 6425 /* 6426 * Sets the internal DSP decibel level to match the DAC for output, and the 6427 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6428 * all alternative codecs set DSP playback volume. 6429 */ 6430 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6431 { 6432 struct ca0132_spec *spec = codec->spec; 6433 unsigned int dsp_dir; 6434 unsigned int lookup_val; 6435 6436 if (nid == VNID_SPK) 6437 dsp_dir = DSP_VOL_OUT; 6438 else 6439 dsp_dir = DSP_VOL_IN; 6440 6441 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6442 6443 dspio_set_uint_param(codec, 6444 ca0132_alt_vol_ctls[dsp_dir].mid, 6445 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6446 float_vol_db_lookup[lookup_val]); 6447 6448 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6449 6450 dspio_set_uint_param(codec, 6451 ca0132_alt_vol_ctls[dsp_dir].mid, 6452 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6453 float_vol_db_lookup[lookup_val]); 6454 6455 dspio_set_uint_param(codec, 6456 ca0132_alt_vol_ctls[dsp_dir].mid, 6457 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6458 } 6459 6460 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6461 struct snd_ctl_elem_info *uinfo) 6462 { 6463 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6464 struct ca0132_spec *spec = codec->spec; 6465 hda_nid_t nid = get_amp_nid(kcontrol); 6466 int ch = get_amp_channels(kcontrol); 6467 int dir = get_amp_direction(kcontrol); 6468 unsigned long pval; 6469 int err; 6470 6471 switch (nid) { 6472 case VNID_SPK: 6473 /* follow shared_out info */ 6474 nid = spec->shared_out_nid; 6475 scoped_guard(mutex, &codec->control_mutex) { 6476 pval = kcontrol->private_value; 6477 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6478 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6479 kcontrol->private_value = pval; 6480 } 6481 break; 6482 case VNID_MIC: 6483 /* follow shared_mic info */ 6484 nid = spec->shared_mic_nid; 6485 scoped_guard(mutex, &codec->control_mutex) { 6486 pval = kcontrol->private_value; 6487 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6488 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6489 kcontrol->private_value = pval; 6490 } 6491 break; 6492 default: 6493 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6494 } 6495 return err; 6496 } 6497 6498 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6499 struct snd_ctl_elem_value *ucontrol) 6500 { 6501 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6502 struct ca0132_spec *spec = codec->spec; 6503 hda_nid_t nid = get_amp_nid(kcontrol); 6504 int ch = get_amp_channels(kcontrol); 6505 long *valp = ucontrol->value.integer.value; 6506 6507 /* store the left and right volume */ 6508 if (ch & 1) { 6509 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6510 valp++; 6511 } 6512 if (ch & 2) { 6513 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6514 valp++; 6515 } 6516 return 0; 6517 } 6518 6519 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6520 struct snd_ctl_elem_value *ucontrol) 6521 { 6522 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6523 struct ca0132_spec *spec = codec->spec; 6524 hda_nid_t nid = get_amp_nid(kcontrol); 6525 int ch = get_amp_channels(kcontrol); 6526 long *valp = ucontrol->value.integer.value; 6527 hda_nid_t shared_nid = 0; 6528 bool effective; 6529 int changed = 1; 6530 6531 /* store the left and right volume */ 6532 if (ch & 1) { 6533 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6534 valp++; 6535 } 6536 if (ch & 2) { 6537 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6538 valp++; 6539 } 6540 6541 /* if effective conditions, then update hw immediately. */ 6542 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6543 if (effective) { 6544 int dir = get_amp_direction(kcontrol); 6545 unsigned long pval; 6546 6547 CLASS(snd_hda_power, pm)(codec); 6548 guard(mutex)(&codec->control_mutex); 6549 pval = kcontrol->private_value; 6550 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6551 0, dir); 6552 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6553 kcontrol->private_value = pval; 6554 } 6555 6556 return changed; 6557 } 6558 6559 /* 6560 * This function is the same as the one above, because using an if statement 6561 * inside of the above volume control for the DSP volume would cause too much 6562 * lag. This is a lot more smooth. 6563 */ 6564 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6565 struct snd_ctl_elem_value *ucontrol) 6566 { 6567 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6568 struct ca0132_spec *spec = codec->spec; 6569 hda_nid_t nid = get_amp_nid(kcontrol); 6570 int ch = get_amp_channels(kcontrol); 6571 long *valp = ucontrol->value.integer.value; 6572 hda_nid_t vnid = 0; 6573 6574 switch (nid) { 6575 case 0x02: 6576 vnid = VNID_SPK; 6577 break; 6578 case 0x07: 6579 vnid = VNID_MIC; 6580 break; 6581 } 6582 6583 /* store the left and right volume */ 6584 if (ch & 1) { 6585 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6586 valp++; 6587 } 6588 if (ch & 2) { 6589 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6590 valp++; 6591 } 6592 6593 CLASS(snd_hda_power, pm)(codec); 6594 ca0132_alt_dsp_volume_put(codec, vnid); 6595 guard(mutex)(&codec->control_mutex); 6596 return snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6597 } 6598 6599 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6600 unsigned int size, unsigned int __user *tlv) 6601 { 6602 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6603 struct ca0132_spec *spec = codec->spec; 6604 hda_nid_t nid = get_amp_nid(kcontrol); 6605 int ch = get_amp_channels(kcontrol); 6606 int dir = get_amp_direction(kcontrol); 6607 unsigned long pval; 6608 int err; 6609 6610 switch (nid) { 6611 case VNID_SPK: 6612 /* follow shared_out tlv */ 6613 nid = spec->shared_out_nid; 6614 scoped_guard(mutex, &codec->control_mutex) { 6615 pval = kcontrol->private_value; 6616 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6617 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6618 kcontrol->private_value = pval; 6619 } 6620 break; 6621 case VNID_MIC: 6622 /* follow shared_mic tlv */ 6623 nid = spec->shared_mic_nid; 6624 scoped_guard(mutex, &codec->control_mutex) { 6625 pval = kcontrol->private_value; 6626 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6627 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6628 kcontrol->private_value = pval; 6629 } 6630 break; 6631 default: 6632 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6633 } 6634 return err; 6635 } 6636 6637 /* Add volume slider control for effect level */ 6638 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6639 const char *pfx, int dir) 6640 { 6641 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6642 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6643 struct snd_kcontrol_new knew = 6644 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6645 6646 snprintf(namestr, sizeof(namestr), "FX: %s %s Volume", pfx, dirstr[dir]); 6647 6648 knew.tlv.c = NULL; 6649 6650 switch (nid) { 6651 case XBASS_XOVER: 6652 knew.info = ca0132_alt_xbass_xover_slider_info; 6653 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6654 knew.put = ca0132_alt_xbass_xover_slider_put; 6655 break; 6656 default: 6657 knew.info = ca0132_alt_effect_slider_info; 6658 knew.get = ca0132_alt_slider_ctl_get; 6659 knew.put = ca0132_alt_effect_slider_put; 6660 knew.private_value = 6661 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6662 break; 6663 } 6664 6665 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6666 } 6667 6668 /* 6669 * Added FX: prefix for the alternative codecs, because otherwise the surround 6670 * effect would conflict with the Surround sound volume control. Also seems more 6671 * clear as to what the switches do. Left alone for others. 6672 */ 6673 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6674 const char *pfx, int dir) 6675 { 6676 struct ca0132_spec *spec = codec->spec; 6677 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6678 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6679 struct snd_kcontrol_new knew = 6680 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6681 /* If using alt_controls, add FX: prefix. But, don't add FX: 6682 * prefix to OutFX or InFX enable controls. 6683 */ 6684 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6685 snprintf(namestr, sizeof(namestr), "FX: %s %s Switch", pfx, dirstr[dir]); 6686 else 6687 snprintf(namestr, sizeof(namestr), "%s %s Switch", pfx, dirstr[dir]); 6688 6689 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6690 } 6691 6692 static int add_voicefx(struct hda_codec *codec) 6693 { 6694 struct snd_kcontrol_new knew = 6695 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6696 VOICEFX, 1, 0, HDA_INPUT); 6697 knew.info = ca0132_voicefx_info; 6698 knew.get = ca0132_voicefx_get; 6699 knew.put = ca0132_voicefx_put; 6700 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6701 } 6702 6703 /* Create the EQ Preset control */ 6704 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6705 { 6706 struct snd_kcontrol_new knew = 6707 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6708 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6709 knew.info = ca0132_alt_eq_preset_info; 6710 knew.get = ca0132_alt_eq_preset_get; 6711 knew.put = ca0132_alt_eq_preset_put; 6712 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6713 snd_ctl_new1(&knew, codec)); 6714 } 6715 6716 /* 6717 * Add enumerated control for the three different settings of the smart volume 6718 * output effect. Normal just uses the slider value, and loud and night are 6719 * their own things that ignore that value. 6720 */ 6721 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6722 { 6723 struct snd_kcontrol_new knew = 6724 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6725 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6726 knew.info = ca0132_alt_svm_setting_info; 6727 knew.get = ca0132_alt_svm_setting_get; 6728 knew.put = ca0132_alt_svm_setting_put; 6729 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6730 snd_ctl_new1(&knew, codec)); 6731 6732 } 6733 6734 /* 6735 * Create an Output Select enumerated control for codecs with surround 6736 * out capabilities. 6737 */ 6738 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6739 { 6740 struct snd_kcontrol_new knew = 6741 HDA_CODEC_MUTE_MONO("Output Select", 6742 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6743 knew.info = ca0132_alt_output_select_get_info; 6744 knew.get = ca0132_alt_output_select_get; 6745 knew.put = ca0132_alt_output_select_put; 6746 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6747 snd_ctl_new1(&knew, codec)); 6748 } 6749 6750 /* 6751 * Add a control for selecting channel count on speaker output. Setting this 6752 * allows the DSP to do bass redirection and channel upmixing on surround 6753 * configurations. 6754 */ 6755 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6756 { 6757 struct snd_kcontrol_new knew = 6758 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6759 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6760 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6761 knew.get = ca0132_alt_speaker_channel_cfg_get; 6762 knew.put = ca0132_alt_speaker_channel_cfg_put; 6763 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6764 snd_ctl_new1(&knew, codec)); 6765 } 6766 6767 /* 6768 * Full range front stereo and rear surround switches. When these are set to 6769 * full range, the lower frequencies from these channels are no longer 6770 * redirected to the LFE channel. 6771 */ 6772 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6773 { 6774 struct snd_kcontrol_new knew = 6775 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6776 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6777 6778 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6779 snd_ctl_new1(&knew, codec)); 6780 } 6781 6782 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6783 { 6784 struct snd_kcontrol_new knew = 6785 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6786 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6787 6788 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6789 snd_ctl_new1(&knew, codec)); 6790 } 6791 6792 /* 6793 * Bass redirection redirects audio below the crossover frequency to the LFE 6794 * channel on speakers that are set as not being full-range. On configurations 6795 * without an LFE channel, it does nothing. Bass redirection seems to be the 6796 * replacement for X-Bass on configurations with an LFE channel. 6797 */ 6798 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6799 { 6800 const char *namestr = "Bass Redirection Crossover"; 6801 struct snd_kcontrol_new knew = 6802 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6803 HDA_OUTPUT); 6804 6805 knew.tlv.c = NULL; 6806 knew.info = ca0132_alt_xbass_xover_slider_info; 6807 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6808 knew.put = ca0132_alt_xbass_xover_slider_put; 6809 6810 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6811 snd_ctl_new1(&knew, codec)); 6812 } 6813 6814 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6815 { 6816 const char *namestr = "Bass Redirection"; 6817 struct snd_kcontrol_new knew = 6818 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6819 HDA_OUTPUT); 6820 6821 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6822 snd_ctl_new1(&knew, codec)); 6823 } 6824 6825 /* 6826 * Create an Input Source enumerated control for the alternate ca0132 codecs 6827 * because the front microphone has no auto-detect, and Line-in has to be set 6828 * somehow. 6829 */ 6830 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6831 { 6832 struct snd_kcontrol_new knew = 6833 HDA_CODEC_MUTE_MONO("Input Source", 6834 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6835 knew.info = ca0132_alt_input_source_info; 6836 knew.get = ca0132_alt_input_source_get; 6837 knew.put = ca0132_alt_input_source_put; 6838 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6839 snd_ctl_new1(&knew, codec)); 6840 } 6841 6842 /* 6843 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6844 * more control than the original mic boost, which is either full 30dB or off. 6845 */ 6846 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6847 { 6848 struct snd_kcontrol_new knew = 6849 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6850 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6851 knew.info = ca0132_alt_mic_boost_info; 6852 knew.get = ca0132_alt_mic_boost_get; 6853 knew.put = ca0132_alt_mic_boost_put; 6854 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6855 snd_ctl_new1(&knew, codec)); 6856 6857 } 6858 6859 #if IS_ENABLED(CONFIG_SND_HDA_DSP_LOADER) 6860 static int ae5_add_strip_controls(struct hda_codec *codec); 6861 #else 6862 static inline int ae5_add_strip_controls(struct hda_codec *codec) 6863 { 6864 return 0; 6865 } 6866 #endif 6867 6868 /* 6869 * Add headphone gain enumerated control for the AE-5. This switches between 6870 * three modes, low, medium, and high. When non-headphone outputs are selected, 6871 * it is automatically set to high. This is the same behavior as Windows. 6872 */ 6873 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6874 { 6875 struct snd_kcontrol_new knew = 6876 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6877 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6878 knew.info = ae5_headphone_gain_info; 6879 knew.get = ae5_headphone_gain_get; 6880 knew.put = ae5_headphone_gain_put; 6881 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6882 snd_ctl_new1(&knew, codec)); 6883 } 6884 6885 /* 6886 * Add sound filter enumerated control for the AE-5. This adds three different 6887 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6888 * read into it, it changes the DAC's interpolation filter. 6889 */ 6890 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6891 { 6892 struct snd_kcontrol_new knew = 6893 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6894 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6895 knew.info = ae5_sound_filter_info; 6896 knew.get = ae5_sound_filter_get; 6897 knew.put = ae5_sound_filter_put; 6898 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6899 snd_ctl_new1(&knew, codec)); 6900 } 6901 6902 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6903 { 6904 struct snd_kcontrol_new knew = 6905 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6906 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6907 6908 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6909 snd_ctl_new1(&knew, codec)); 6910 } 6911 6912 /* 6913 * Need to create follower controls for the alternate codecs that have surround 6914 * capabilities. 6915 */ 6916 static const char * const ca0132_alt_follower_pfxs[] = { 6917 "Front", "Surround", "Center", "LFE", NULL, 6918 }; 6919 6920 /* 6921 * Also need special channel map, because the default one is incorrect. 6922 * I think this has to do with the pin for rear surround being 0x11, 6923 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6924 */ 6925 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6926 { .channels = 2, 6927 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6928 { .channels = 4, 6929 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6930 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6931 { .channels = 6, 6932 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6933 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6934 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6935 { } 6936 }; 6937 6938 /* Add the correct chmap for streams with 6 channels. */ 6939 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6940 { 6941 int err = 0; 6942 struct hda_pcm *pcm; 6943 6944 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6945 struct hda_pcm_stream *hinfo = 6946 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6947 struct snd_pcm_chmap *chmap; 6948 const struct snd_pcm_chmap_elem *elem; 6949 6950 elem = ca0132_alt_chmaps; 6951 if (hinfo->channels_max == 6) { 6952 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6953 SNDRV_PCM_STREAM_PLAYBACK, 6954 elem, hinfo->channels_max, 0, &chmap); 6955 if (err < 0) 6956 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6957 } 6958 } 6959 } 6960 6961 /* 6962 * When changing Node IDs for Mixer Controls below, make sure to update 6963 * Node IDs in ca0132_config() as well. 6964 */ 6965 static const struct snd_kcontrol_new ca0132_mixer[] = { 6966 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6967 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6968 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6969 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6970 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6971 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6972 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6973 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6974 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6975 0x12, 1, HDA_INPUT), 6976 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6977 VNID_HP_SEL, 1, HDA_OUTPUT), 6978 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6979 VNID_AMIC1_SEL, 1, HDA_INPUT), 6980 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6981 VNID_HP_ASEL, 1, HDA_OUTPUT), 6982 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6983 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6984 { } /* end */ 6985 }; 6986 6987 /* 6988 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6989 * surround controls. Also sets both the Front Playback and Capture Volume 6990 * controls to alt so they set the DSP's decibel level. 6991 */ 6992 static const struct snd_kcontrol_new desktop_mixer[] = { 6993 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6994 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6995 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6996 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6997 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6998 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6999 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7000 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7001 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 7002 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7003 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7004 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7005 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7006 VNID_HP_ASEL, 1, HDA_OUTPUT), 7007 { } /* end */ 7008 }; 7009 7010 /* 7011 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 7012 * because it doesn't set decibel levels for the DSP for capture. 7013 */ 7014 static const struct snd_kcontrol_new r3di_mixer[] = { 7015 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 7016 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 7017 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 7018 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 7019 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7020 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7021 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7022 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7023 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7024 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7025 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7026 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7027 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7028 VNID_HP_ASEL, 1, HDA_OUTPUT), 7029 { } /* end */ 7030 }; 7031 7032 static int ca0132_build_controls(struct hda_codec *codec) 7033 { 7034 struct ca0132_spec *spec = codec->spec; 7035 int i, num_fx, num_sliders; 7036 int err = 0; 7037 7038 /* Add Mixer controls */ 7039 for (i = 0; i < spec->num_mixers; i++) { 7040 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7041 if (err < 0) 7042 return err; 7043 } 7044 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7045 if (ca0132_use_alt_functions(spec)) { 7046 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7047 spec->tlv); 7048 snd_hda_add_vmaster(codec, "Master Playback Volume", 7049 spec->tlv, ca0132_alt_follower_pfxs, 7050 "Playback Volume", 0); 7051 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7052 NULL, ca0132_alt_follower_pfxs, 7053 "Playback Switch", 7054 true, 0, &spec->vmaster_mute.sw_kctl); 7055 if (err < 0) 7056 return err; 7057 } 7058 7059 /* Add in and out effects controls. 7060 * VoiceFX, PE and CrystalVoice are added separately. 7061 */ 7062 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7063 for (i = 0; i < num_fx; i++) { 7064 /* Desktop cards break if Echo Cancellation is used. */ 7065 if (ca0132_use_pci_mmio(spec)) { 7066 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7067 OUT_EFFECTS_COUNT)) 7068 continue; 7069 } 7070 7071 err = add_fx_switch(codec, ca0132_effects[i].nid, 7072 ca0132_effects[i].name, 7073 ca0132_effects[i].direct); 7074 if (err < 0) 7075 return err; 7076 } 7077 /* 7078 * If codec has use_alt_controls set to true, add effect level sliders, 7079 * EQ presets, and Smart Volume presets. Also, change names to add FX 7080 * prefix, and change PlayEnhancement and CrystalVoice to match. 7081 */ 7082 if (ca0132_use_alt_controls(spec)) { 7083 err = ca0132_alt_add_svm_enum(codec); 7084 if (err < 0) 7085 return err; 7086 7087 err = add_ca0132_alt_eq_presets(codec); 7088 if (err < 0) 7089 return err; 7090 7091 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7092 "Enable OutFX", 0); 7093 if (err < 0) 7094 return err; 7095 7096 err = add_fx_switch(codec, CRYSTAL_VOICE, 7097 "Enable InFX", 1); 7098 if (err < 0) 7099 return err; 7100 7101 num_sliders = OUT_EFFECTS_COUNT - 1; 7102 for (i = 0; i < num_sliders; i++) { 7103 err = ca0132_alt_add_effect_slider(codec, 7104 ca0132_effects[i].nid, 7105 ca0132_effects[i].name, 7106 ca0132_effects[i].direct); 7107 if (err < 0) 7108 return err; 7109 } 7110 7111 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7112 "X-Bass Crossover", EFX_DIR_OUT); 7113 7114 if (err < 0) 7115 return err; 7116 } else { 7117 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7118 "PlayEnhancement", 0); 7119 if (err < 0) 7120 return err; 7121 7122 err = add_fx_switch(codec, CRYSTAL_VOICE, 7123 "CrystalVoice", 1); 7124 if (err < 0) 7125 return err; 7126 } 7127 err = add_voicefx(codec); 7128 if (err < 0) 7129 return err; 7130 7131 /* 7132 * If the codec uses alt_functions, you need the enumerated controls 7133 * to select the new outputs and inputs, plus add the new mic boost 7134 * setting control. 7135 */ 7136 if (ca0132_use_alt_functions(spec)) { 7137 err = ca0132_alt_add_output_enum(codec); 7138 if (err < 0) 7139 return err; 7140 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7141 if (err < 0) 7142 return err; 7143 err = ca0132_alt_add_front_full_range_switch(codec); 7144 if (err < 0) 7145 return err; 7146 err = ca0132_alt_add_rear_full_range_switch(codec); 7147 if (err < 0) 7148 return err; 7149 err = ca0132_alt_add_bass_redirection_crossover(codec); 7150 if (err < 0) 7151 return err; 7152 err = ca0132_alt_add_bass_redirection_switch(codec); 7153 if (err < 0) 7154 return err; 7155 err = ca0132_alt_add_mic_boost_enum(codec); 7156 if (err < 0) 7157 return err; 7158 /* 7159 * ZxR only has microphone input, there is no front panel 7160 * header on the card, and aux-in is handled by the DBPro board. 7161 */ 7162 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7163 err = ca0132_alt_add_input_enum(codec); 7164 if (err < 0) 7165 return err; 7166 } 7167 } 7168 7169 switch (ca0132_quirk(spec)) { 7170 case QUIRK_AE5: 7171 err = ae5_add_strip_controls(codec); 7172 if (err < 0) 7173 return err; 7174 fallthrough; 7175 case QUIRK_AE7: 7176 err = ae5_add_headphone_gain_enum(codec); 7177 if (err < 0) 7178 return err; 7179 err = ae5_add_sound_filter_enum(codec); 7180 if (err < 0) 7181 return err; 7182 break; 7183 case QUIRK_ZXR: 7184 err = zxr_add_headphone_gain_switch(codec); 7185 if (err < 0) 7186 return err; 7187 break; 7188 default: 7189 break; 7190 } 7191 7192 #ifdef ENABLE_TUNING_CONTROLS 7193 add_tuning_ctls(codec); 7194 #endif 7195 7196 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7197 if (err < 0) 7198 return err; 7199 7200 if (spec->dig_out) { 7201 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7202 spec->dig_out); 7203 if (err < 0) 7204 return err; 7205 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7206 if (err < 0) 7207 return err; 7208 /* spec->multiout.share_spdif = 1; */ 7209 } 7210 7211 if (spec->dig_in) { 7212 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7213 if (err < 0) 7214 return err; 7215 } 7216 7217 if (ca0132_use_alt_functions(spec)) 7218 ca0132_alt_add_chmap_ctls(codec); 7219 7220 return 0; 7221 } 7222 7223 static int dbpro_build_controls(struct hda_codec *codec) 7224 { 7225 struct ca0132_spec *spec = codec->spec; 7226 int err = 0; 7227 7228 if (spec->dig_out) { 7229 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7230 spec->dig_out); 7231 if (err < 0) 7232 return err; 7233 } 7234 7235 if (spec->dig_in) { 7236 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7237 if (err < 0) 7238 return err; 7239 } 7240 7241 return 0; 7242 } 7243 7244 /* 7245 * PCM 7246 */ 7247 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7248 .substreams = 1, 7249 .channels_min = 2, 7250 .channels_max = 6, 7251 .ops = { 7252 .prepare = ca0132_playback_pcm_prepare, 7253 .cleanup = ca0132_playback_pcm_cleanup, 7254 .get_delay = ca0132_playback_pcm_delay, 7255 }, 7256 }; 7257 7258 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7259 .substreams = 1, 7260 .channels_min = 2, 7261 .channels_max = 2, 7262 .ops = { 7263 .prepare = ca0132_capture_pcm_prepare, 7264 .cleanup = ca0132_capture_pcm_cleanup, 7265 .get_delay = ca0132_capture_pcm_delay, 7266 }, 7267 }; 7268 7269 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7270 .substreams = 1, 7271 .channels_min = 2, 7272 .channels_max = 2, 7273 .ops = { 7274 .open = ca0132_dig_playback_pcm_open, 7275 .close = ca0132_dig_playback_pcm_close, 7276 .prepare = ca0132_dig_playback_pcm_prepare, 7277 .cleanup = ca0132_dig_playback_pcm_cleanup 7278 }, 7279 }; 7280 7281 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7282 .substreams = 1, 7283 .channels_min = 2, 7284 .channels_max = 2, 7285 }; 7286 7287 static int ca0132_build_pcms(struct hda_codec *codec) 7288 { 7289 struct ca0132_spec *spec = codec->spec; 7290 struct hda_pcm *info; 7291 7292 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7293 if (!info) 7294 return -ENOMEM; 7295 if (ca0132_use_alt_functions(spec)) { 7296 info->own_chmap = true; 7297 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7298 = ca0132_alt_chmaps; 7299 } 7300 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7301 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7302 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7303 spec->multiout.max_channels; 7304 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7305 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7306 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7307 7308 /* With the DSP enabled, desktops don't use this ADC. */ 7309 if (!ca0132_use_alt_functions(spec)) { 7310 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7311 if (!info) 7312 return -ENOMEM; 7313 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7314 ca0132_pcm_analog_capture; 7315 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7316 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7317 } 7318 7319 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7320 if (!info) 7321 return -ENOMEM; 7322 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7323 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7324 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7325 7326 if (!spec->dig_out && !spec->dig_in) 7327 return 0; 7328 7329 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7330 if (!info) 7331 return -ENOMEM; 7332 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7333 if (spec->dig_out) { 7334 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7335 ca0132_pcm_digital_playback; 7336 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7337 } 7338 if (spec->dig_in) { 7339 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7340 ca0132_pcm_digital_capture; 7341 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7342 } 7343 7344 return 0; 7345 } 7346 7347 static int dbpro_build_pcms(struct hda_codec *codec) 7348 { 7349 struct ca0132_spec *spec = codec->spec; 7350 struct hda_pcm *info; 7351 7352 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7353 if (!info) 7354 return -ENOMEM; 7355 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7356 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7357 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7358 7359 7360 if (!spec->dig_out && !spec->dig_in) 7361 return 0; 7362 7363 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7364 if (!info) 7365 return -ENOMEM; 7366 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7367 if (spec->dig_out) { 7368 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7369 ca0132_pcm_digital_playback; 7370 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7371 } 7372 if (spec->dig_in) { 7373 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7374 ca0132_pcm_digital_capture; 7375 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7376 } 7377 7378 return 0; 7379 } 7380 7381 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7382 { 7383 if (pin) { 7384 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7385 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7386 snd_hda_codec_write(codec, pin, 0, 7387 AC_VERB_SET_AMP_GAIN_MUTE, 7388 AMP_OUT_UNMUTE); 7389 } 7390 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7391 snd_hda_codec_write(codec, dac, 0, 7392 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7393 } 7394 7395 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7396 { 7397 if (pin) { 7398 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7399 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7400 snd_hda_codec_write(codec, pin, 0, 7401 AC_VERB_SET_AMP_GAIN_MUTE, 7402 AMP_IN_UNMUTE(0)); 7403 } 7404 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7405 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7406 AMP_IN_UNMUTE(0)); 7407 7408 /* init to 0 dB and unmute. */ 7409 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7410 HDA_AMP_VOLMASK, 0x5a); 7411 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7412 HDA_AMP_MUTE, 0); 7413 } 7414 } 7415 7416 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7417 { 7418 unsigned int caps; 7419 7420 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7421 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7422 snd_hda_override_amp_caps(codec, nid, dir, caps); 7423 } 7424 7425 /* 7426 * Switch between Digital built-in mic and analog mic. 7427 */ 7428 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7429 { 7430 struct ca0132_spec *spec = codec->spec; 7431 unsigned int tmp; 7432 u8 val; 7433 unsigned int oldval; 7434 7435 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7436 7437 oldval = stop_mic1(codec); 7438 ca0132_set_vipsource(codec, 0); 7439 if (enable) { 7440 /* set DMic input as 2-ch */ 7441 tmp = FLOAT_TWO; 7442 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7443 7444 val = spec->dmic_ctl; 7445 val |= 0x80; 7446 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7447 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7448 7449 if (!(spec->dmic_ctl & 0x20)) 7450 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7451 } else { 7452 /* set AMic input as mono */ 7453 tmp = FLOAT_ONE; 7454 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7455 7456 val = spec->dmic_ctl; 7457 /* clear bit7 and bit5 to disable dmic */ 7458 val &= 0x5f; 7459 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7460 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7461 7462 if (!(spec->dmic_ctl & 0x20)) 7463 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7464 } 7465 ca0132_set_vipsource(codec, 1); 7466 resume_mic1(codec, oldval); 7467 } 7468 7469 /* 7470 * Initialization for Digital Mic. 7471 */ 7472 static void ca0132_init_dmic(struct hda_codec *codec) 7473 { 7474 struct ca0132_spec *spec = codec->spec; 7475 u8 val; 7476 7477 /* Setup Digital Mic here, but don't enable. 7478 * Enable based on jack detect. 7479 */ 7480 7481 /* MCLK uses MPIO1, set to enable. 7482 * Bit 2-0: MPIO select 7483 * Bit 3: set to disable 7484 * Bit 7-4: reserved 7485 */ 7486 val = 0x01; 7487 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7488 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7489 7490 /* Data1 uses MPIO3. Data2 not use 7491 * Bit 2-0: Data1 MPIO select 7492 * Bit 3: set disable Data1 7493 * Bit 6-4: Data2 MPIO select 7494 * Bit 7: set disable Data2 7495 */ 7496 val = 0x83; 7497 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7498 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7499 7500 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7501 * Bit 3-0: Channel mask 7502 * Bit 4: set for 48KHz, clear for 32KHz 7503 * Bit 5: mode 7504 * Bit 6: set to select Data2, clear for Data1 7505 * Bit 7: set to enable DMic, clear for AMic 7506 */ 7507 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7508 val = 0x33; 7509 else 7510 val = 0x23; 7511 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7512 spec->dmic_ctl = val; 7513 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7514 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7515 } 7516 7517 /* 7518 * Initialization for Analog Mic 2 7519 */ 7520 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7521 { 7522 struct ca0132_spec *spec = codec->spec; 7523 7524 guard(mutex)(&spec->chipio_mutex); 7525 7526 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7527 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7528 } 7529 7530 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7531 { 7532 struct ca0132_spec *spec = codec->spec; 7533 int i; 7534 7535 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7536 snd_hda_codec_update_widgets(codec); 7537 7538 for (i = 0; i < spec->multiout.num_dacs; i++) 7539 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7540 7541 for (i = 0; i < spec->num_outputs; i++) 7542 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7543 7544 for (i = 0; i < spec->num_inputs; i++) { 7545 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7546 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7547 } 7548 } 7549 7550 7551 /* If there is an active channel for some reason, find it and free it. */ 7552 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7553 { 7554 unsigned int i, tmp; 7555 int status; 7556 7557 /* Read active DSPDMAC channel register. */ 7558 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7559 if (status >= 0) { 7560 /* AND against 0xfff to get the active channel bits. */ 7561 tmp = tmp & 0xfff; 7562 7563 /* If there are no active channels, nothing to free. */ 7564 if (!tmp) 7565 return; 7566 } else { 7567 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7568 __func__); 7569 return; 7570 } 7571 7572 /* 7573 * Check each DSP DMA channel for activity, and if the channel is 7574 * active, free it. 7575 */ 7576 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7577 if (dsp_is_dma_active(codec, i)) { 7578 status = dspio_free_dma_chan(codec, i); 7579 if (status < 0) 7580 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7581 __func__, i); 7582 } 7583 } 7584 } 7585 7586 /* 7587 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7588 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7589 * Instead, audio is now routed through the DSP's DMA controllers, which 7590 * the DSP is tasked with setting up itself. Through debugging, it seems the 7591 * cause of most of the no-audio on startup issues were due to improperly 7592 * configured DSP DMA channels. 7593 * 7594 * Normally, the DSP configures these the first time an HDA audio stream is 7595 * started post DSP firmware download. That is why creating a 'dummy' stream 7596 * worked in fixing the audio in some cases. This works most of the time, but 7597 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7598 * configuration registers, it ends up in a broken state. Issues can also 7599 * arise if streams are started in an unusual order, i.e the audio output dma 7600 * channel being sandwiched between the mic1 and mic2 dma channels. 7601 * 7602 * The solution to this is to make sure that the DSP has no DMA channels 7603 * in use post DSP firmware download, and then to manually start each default 7604 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7605 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7606 */ 7607 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7608 { 7609 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7610 struct ca0132_spec *spec = codec->spec; 7611 unsigned int i, tmp; 7612 7613 /* 7614 * Check if any of the default streams are active, and if they are, 7615 * stop them. 7616 */ 7617 scoped_guard(mutex, &spec->chipio_mutex) { 7618 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7619 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7620 7621 if (tmp) { 7622 chipio_set_stream_control(codec, 7623 dsp_dma_stream_ids[i], 0); 7624 } 7625 } 7626 } 7627 7628 /* 7629 * If all DSP streams are inactive, there should be no active DSP DMA 7630 * channels. Check and make sure this is the case, and if it isn't, 7631 * free any active channels. 7632 */ 7633 ca0132_alt_free_active_dma_channels(codec); 7634 7635 guard(mutex)(&spec->chipio_mutex); 7636 7637 /* Make sure stream 0x0c is six channels. */ 7638 chipio_set_stream_channels(codec, 0x0c, 6); 7639 7640 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7641 chipio_set_stream_control(codec, 7642 dsp_dma_stream_ids[i], 1); 7643 7644 /* Give the DSP some time to setup the DMA channel. */ 7645 msleep(75); 7646 } 7647 } 7648 7649 /* 7650 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7651 * router', where each entry represents a 48khz audio channel, with a format 7652 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7653 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7654 * and 3 if it's using Sample Rate Converter ports. 7655 * An example is: 7656 * 0x0001f8c0 7657 * In this case, f8 is the destination, and c0 is the source. The number value 7658 * is 1. 7659 * This region of memory is normally managed internally by the 8051, where 7660 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7661 * entry within the 0x190000 range, and when a range of entries is in use, the 7662 * ending value is overwritten with 0xff. 7663 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7664 * streamID's, where each entry is a starting 0x190000 port offset. 7665 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7666 * offset for the corresponding streamID. 7667 * 7668 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7669 * the 8051, then manually overwritten to remap the ports to work with the 7670 * new DACs. 7671 * 7672 * Currently known portID's: 7673 * 0x00-0x1f: HDA audio stream input/output ports. 7674 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7675 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7676 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7677 * 0xe0-0xff: DAC/ADC audio input/output ports. 7678 * 7679 * Currently known streamID's: 7680 * 0x03: Mic1 ADC to DSP. 7681 * 0x04: Mic2 ADC to DSP. 7682 * 0x05: HDA node 0x02 audio stream to DSP. 7683 * 0x0f: DSP Mic exit to HDA node 0x07. 7684 * 0x0c: DSP processed audio to DACs. 7685 * 0x14: DAC0, front L/R. 7686 * 7687 * It is possible to route the HDA audio streams directly to the DAC and 7688 * bypass the DSP entirely, with the only downside being that since the DSP 7689 * does volume control, the only volume control you'll get is through PCM on 7690 * the PC side, in the same way volume is handled for optical out. This may be 7691 * useful for debugging. 7692 */ 7693 static void chipio_remap_stream(struct hda_codec *codec, 7694 const struct chipio_stream_remap_data *remap_data) 7695 { 7696 unsigned int i, stream_offset; 7697 7698 /* Get the starting port for the stream to be remapped. */ 7699 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7700 &stream_offset); 7701 7702 /* 7703 * Check if the stream's port value is 0xff, because the 8051 may not 7704 * have gotten around to setting up the stream yet. Wait until it's 7705 * setup to remap it's ports. 7706 */ 7707 if (stream_offset == 0xff) { 7708 for (i = 0; i < 5; i++) { 7709 msleep(25); 7710 7711 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7712 &stream_offset); 7713 7714 if (stream_offset != 0xff) 7715 break; 7716 } 7717 } 7718 7719 if (stream_offset == 0xff) { 7720 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7721 __func__, remap_data->stream_id); 7722 return; 7723 } 7724 7725 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7726 stream_offset *= 0x04; 7727 stream_offset += 0x190000; 7728 7729 for (i = 0; i < remap_data->count; i++) { 7730 chipio_write_no_mutex(codec, 7731 stream_offset + remap_data->offset[i], 7732 remap_data->value[i]); 7733 } 7734 7735 /* Update stream map configuration. */ 7736 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7737 } 7738 7739 /* 7740 * Default speaker tuning values setup for alternative codecs. 7741 */ 7742 static const unsigned int sbz_default_delay_values[] = { 7743 /* Non-zero values are floating point 0.000198. */ 7744 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7745 }; 7746 7747 static const unsigned int zxr_default_delay_values[] = { 7748 /* Non-zero values are floating point 0.000220. */ 7749 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7750 }; 7751 7752 static const unsigned int ae5_default_delay_values[] = { 7753 /* Non-zero values are floating point 0.000100. */ 7754 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7755 }; 7756 7757 /* 7758 * If we never change these, probably only need them on initialization. 7759 */ 7760 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7761 { 7762 struct ca0132_spec *spec = codec->spec; 7763 unsigned int i, tmp, start_req, end_req; 7764 const unsigned int *values; 7765 7766 switch (ca0132_quirk(spec)) { 7767 case QUIRK_SBZ: 7768 values = sbz_default_delay_values; 7769 break; 7770 case QUIRK_ZXR: 7771 values = zxr_default_delay_values; 7772 break; 7773 case QUIRK_AE5: 7774 case QUIRK_AE7: 7775 values = ae5_default_delay_values; 7776 break; 7777 default: 7778 values = sbz_default_delay_values; 7779 break; 7780 } 7781 7782 tmp = FLOAT_ZERO; 7783 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7784 7785 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7786 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7787 for (i = start_req; i < end_req + 1; i++) 7788 dspio_set_uint_param(codec, 0x96, i, tmp); 7789 7790 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7791 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7792 for (i = start_req; i < end_req + 1; i++) 7793 dspio_set_uint_param(codec, 0x96, i, tmp); 7794 7795 7796 for (i = 0; i < 6; i++) 7797 dspio_set_uint_param(codec, 0x96, 7798 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7799 } 7800 7801 /* 7802 * Initialize mic for non-chromebook ca0132 implementations. 7803 */ 7804 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7805 { 7806 struct ca0132_spec *spec = codec->spec; 7807 unsigned int tmp; 7808 7809 /* Mic 1 Setup */ 7810 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7811 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7812 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7813 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7814 tmp = FLOAT_ONE; 7815 } else 7816 tmp = FLOAT_THREE; 7817 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7818 7819 /* Mic 2 setup (not present on desktop cards) */ 7820 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7821 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7822 if (ca0132_quirk(spec) == QUIRK_R3DI) 7823 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7824 tmp = FLOAT_ZERO; 7825 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7826 } 7827 7828 /* 7829 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7830 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7831 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7832 * having an updated DAC, which changes the destination to that DAC. 7833 */ 7834 static void sbz_connect_streams(struct hda_codec *codec) 7835 { 7836 struct ca0132_spec *spec = codec->spec; 7837 7838 guard(mutex)(&spec->chipio_mutex); 7839 7840 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7841 7842 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7843 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7844 7845 /* Setup stream 0x14 with it's source and destination points */ 7846 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7847 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7848 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7849 chipio_set_stream_channels(codec, 0x14, 2); 7850 chipio_set_stream_control(codec, 0x14, 1); 7851 7852 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7853 } 7854 7855 /* 7856 * Write data through ChipIO to setup proper stream destinations. 7857 * Not sure how it exactly works, but it seems to direct data 7858 * to different destinations. Example is f8 to c0, e0 to c0. 7859 * All I know is, if you don't set these, you get no sound. 7860 */ 7861 static void sbz_chipio_startup_data(struct hda_codec *codec) 7862 { 7863 const struct chipio_stream_remap_data *dsp_out_remap_data; 7864 struct ca0132_spec *spec = codec->spec; 7865 7866 guard(mutex)(&spec->chipio_mutex); 7867 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7868 7869 /* Remap DAC0's output ports. */ 7870 chipio_remap_stream(codec, &stream_remap_data[0]); 7871 7872 /* Remap DSP audio output stream ports. */ 7873 switch (ca0132_quirk(spec)) { 7874 case QUIRK_SBZ: 7875 dsp_out_remap_data = &stream_remap_data[1]; 7876 break; 7877 7878 case QUIRK_ZXR: 7879 dsp_out_remap_data = &stream_remap_data[2]; 7880 break; 7881 7882 default: 7883 dsp_out_remap_data = NULL; 7884 break; 7885 } 7886 7887 if (dsp_out_remap_data) 7888 chipio_remap_stream(codec, dsp_out_remap_data); 7889 7890 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7891 } 7892 7893 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7894 { 7895 struct ca0132_spec *spec = codec->spec; 7896 unsigned int tmp; 7897 7898 chipio_set_stream_control(codec, 0x03, 0); 7899 chipio_set_stream_control(codec, 0x04, 0); 7900 7901 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7902 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7903 7904 tmp = FLOAT_THREE; 7905 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7906 7907 chipio_set_stream_control(codec, 0x03, 1); 7908 chipio_set_stream_control(codec, 0x04, 1); 7909 7910 switch (ca0132_quirk(spec)) { 7911 case QUIRK_SBZ: 7912 chipio_write(codec, 0x18b098, 0x0000000c); 7913 chipio_write(codec, 0x18b09C, 0x0000000c); 7914 break; 7915 case QUIRK_AE5: 7916 chipio_write(codec, 0x18b098, 0x0000000c); 7917 chipio_write(codec, 0x18b09c, 0x0000004c); 7918 break; 7919 default: 7920 break; 7921 } 7922 } 7923 7924 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7925 { 7926 struct ca0132_spec *spec = codec->spec; 7927 7928 chipio_8051_write_direct(codec, 0x93, 0x10); 7929 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7930 7931 writeb(0xff, spec->mem_base + 0x304); 7932 writeb(0xff, spec->mem_base + 0x304); 7933 writeb(0xff, spec->mem_base + 0x304); 7934 writeb(0xff, spec->mem_base + 0x304); 7935 writeb(0x00, spec->mem_base + 0x100); 7936 writeb(0xff, spec->mem_base + 0x304); 7937 writeb(0x00, spec->mem_base + 0x100); 7938 writeb(0xff, spec->mem_base + 0x304); 7939 writeb(0x00, spec->mem_base + 0x100); 7940 writeb(0xff, spec->mem_base + 0x304); 7941 writeb(0x00, spec->mem_base + 0x100); 7942 writeb(0xff, spec->mem_base + 0x304); 7943 7944 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7945 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7946 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7947 } 7948 7949 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7950 { 7951 /* 7952 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7953 * which seems to be 'multichannel'. This is also mentioned in the 7954 * AE-5's registry values in Windows. 7955 */ 7956 chipio_set_control_param(codec, 3, 0); 7957 /* 7958 * I believe ASI is 'audio serial interface' and that it's used to 7959 * change colors on the external LED strip connected to the AE-5. 7960 */ 7961 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7962 7963 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7964 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7965 7966 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7967 } 7968 7969 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7970 { 7971 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7972 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7973 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7974 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7975 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7976 } 7977 7978 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7979 { 7980 struct ca0132_spec *spec = codec->spec; 7981 7982 guard(mutex)(&spec->chipio_mutex); 7983 7984 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7985 7986 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7987 7988 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7989 7990 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7991 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7992 chipio_set_stream_channels(codec, 0x18, 6); 7993 chipio_set_stream_control(codec, 0x18, 1); 7994 7995 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7996 7997 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7998 7999 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 8000 } 8001 8002 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 8003 { 8004 struct ca0132_spec *spec = codec->spec; 8005 8006 guard(mutex)(&spec->chipio_mutex); 8007 8008 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8009 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8010 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8011 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8012 8013 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8014 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8015 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 8016 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 8017 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 8018 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 8019 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8020 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8021 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8022 ca0113_mmio_gpio_set(codec, 0, true); 8023 ca0113_mmio_gpio_set(codec, 1, true); 8024 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8025 8026 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8027 8028 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8029 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8030 } 8031 8032 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8033 { 8034 struct ca0132_spec *spec = codec->spec; 8035 8036 guard(mutex)(&spec->chipio_mutex); 8037 8038 /* Seems to share the same port remapping as the SBZ. */ 8039 chipio_remap_stream(codec, &stream_remap_data[1]); 8040 8041 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8042 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8043 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8044 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8045 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8046 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8047 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8048 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8049 } 8050 8051 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8052 { 8053 struct ca0132_spec *spec = codec->spec; 8054 8055 guard(mutex)(&spec->chipio_mutex); 8056 8057 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8058 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8059 8060 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8061 8062 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8063 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8064 8065 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8066 chipio_set_stream_channels(codec, 0x18, 6); 8067 chipio_set_stream_control(codec, 0x18, 1); 8068 8069 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8070 } 8071 8072 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8073 { 8074 static const unsigned int addr[] = { 8075 0x41, 0x45, 0x40, 0x43, 0x51 8076 }; 8077 static const unsigned int data[] = { 8078 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8079 }; 8080 unsigned int i; 8081 8082 for (i = 0; i < ARRAY_SIZE(addr); i++) 8083 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8084 } 8085 8086 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8087 { 8088 struct ca0132_spec *spec = codec->spec; 8089 static const unsigned int target[] = { 8090 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8091 }; 8092 static const unsigned int data[] = { 8093 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8094 }; 8095 unsigned int i; 8096 8097 guard(mutex)(&spec->chipio_mutex); 8098 8099 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8100 8101 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8102 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8103 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8104 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8105 8106 ae7_post_dsp_pll_setup(codec); 8107 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8108 8109 for (i = 0; i < ARRAY_SIZE(target); i++) 8110 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8111 8112 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8113 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8114 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8115 8116 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8117 chipio_set_stream_channels(codec, 0x21, 2); 8118 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8119 8120 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8121 /* 8122 * In the 8051's memory, this param is referred to as 'n2sid', which I 8123 * believe is 'node to streamID'. It seems to be a way to assign a 8124 * stream to a given HDA node. 8125 */ 8126 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8127 8128 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8129 8130 /* 8131 * Now, at this point on Windows, an actual stream is setup and 8132 * seemingly sends data to the HDA node 0x09, which is the digital 8133 * audio input node. This is left out here, because obviously I don't 8134 * know what data is being sent. Interestingly, the AE-5 seems to go 8135 * through the motions of getting here and never actually takes this 8136 * step, but the AE-7 does. 8137 */ 8138 8139 ca0113_mmio_gpio_set(codec, 0, 1); 8140 ca0113_mmio_gpio_set(codec, 1, 1); 8141 8142 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8143 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8144 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8145 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8146 8147 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8148 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8149 8150 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8151 chipio_set_stream_channels(codec, 0x18, 6); 8152 8153 /* 8154 * Runs again, this has been repeated a few times, but I'm just 8155 * following what the Windows driver does. 8156 */ 8157 ae7_post_dsp_pll_setup(codec); 8158 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8159 } 8160 8161 /* 8162 * The Windows driver has commands that seem to setup ASI, which I believe to 8163 * be some sort of audio serial interface. My current speculation is that it's 8164 * related to communicating with the new DAC. 8165 */ 8166 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8167 { 8168 chipio_8051_write_direct(codec, 0x93, 0x10); 8169 8170 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8171 8172 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8173 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8174 8175 chipio_set_control_param(codec, 3, 3); 8176 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8177 8178 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8179 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8180 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8181 8182 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8183 8184 ae7_post_dsp_pll_setup(codec); 8185 ae7_post_dsp_asi_stream_setup(codec); 8186 8187 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8188 8189 ae7_post_dsp_asi_setup_ports(codec); 8190 } 8191 8192 /* 8193 * Setup default parameters for DSP 8194 */ 8195 static void ca0132_setup_defaults(struct hda_codec *codec) 8196 { 8197 struct ca0132_spec *spec = codec->spec; 8198 unsigned int tmp; 8199 int num_fx; 8200 int idx, i; 8201 8202 if (spec->dsp_state != DSP_DOWNLOADED) 8203 return; 8204 8205 /* out, in effects + voicefx */ 8206 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8207 for (idx = 0; idx < num_fx; idx++) { 8208 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8209 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8210 ca0132_effects[idx].reqs[i], 8211 ca0132_effects[idx].def_vals[i]); 8212 } 8213 } 8214 8215 /*remove DSP headroom*/ 8216 tmp = FLOAT_ZERO; 8217 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8218 8219 /*set speaker EQ bypass attenuation*/ 8220 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8221 8222 /* set AMic1 and AMic2 as mono mic */ 8223 tmp = FLOAT_ONE; 8224 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8225 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8226 8227 /* set AMic1 as CrystalVoice input */ 8228 tmp = FLOAT_ONE; 8229 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8230 8231 /* set WUH source */ 8232 tmp = FLOAT_TWO; 8233 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8234 } 8235 8236 /* 8237 * Setup default parameters for Recon3D/Recon3Di DSP. 8238 */ 8239 8240 static void r3d_setup_defaults(struct hda_codec *codec) 8241 { 8242 struct ca0132_spec *spec = codec->spec; 8243 unsigned int tmp; 8244 int num_fx; 8245 int idx, i; 8246 8247 if (spec->dsp_state != DSP_DOWNLOADED) 8248 return; 8249 8250 ca0132_alt_init_analog_mics(codec); 8251 ca0132_alt_start_dsp_audio_streams(codec); 8252 8253 /*remove DSP headroom*/ 8254 tmp = FLOAT_ZERO; 8255 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8256 8257 /* set WUH source */ 8258 tmp = FLOAT_TWO; 8259 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8260 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8261 8262 /* Set speaker source? */ 8263 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8264 8265 if (ca0132_quirk(spec) == QUIRK_R3DI) 8266 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8267 8268 /* Disable mute on Center/LFE. */ 8269 if (ca0132_quirk(spec) == QUIRK_R3D) { 8270 ca0113_mmio_gpio_set(codec, 2, false); 8271 ca0113_mmio_gpio_set(codec, 4, true); 8272 } 8273 8274 /* Setup effect defaults */ 8275 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8276 for (idx = 0; idx < num_fx; idx++) { 8277 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8278 dspio_set_uint_param(codec, 8279 ca0132_effects[idx].mid, 8280 ca0132_effects[idx].reqs[i], 8281 ca0132_effects[idx].def_vals[i]); 8282 } 8283 } 8284 } 8285 8286 /* 8287 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8288 * than the Chromebook setup. 8289 */ 8290 static void sbz_setup_defaults(struct hda_codec *codec) 8291 { 8292 struct ca0132_spec *spec = codec->spec; 8293 unsigned int tmp; 8294 int num_fx; 8295 int idx, i; 8296 8297 if (spec->dsp_state != DSP_DOWNLOADED) 8298 return; 8299 8300 ca0132_alt_init_analog_mics(codec); 8301 ca0132_alt_start_dsp_audio_streams(codec); 8302 sbz_connect_streams(codec); 8303 sbz_chipio_startup_data(codec); 8304 8305 /* 8306 * Sets internal input loopback to off, used to have a switch to 8307 * enable input loopback, but turned out to be way too buggy. 8308 */ 8309 tmp = FLOAT_ONE; 8310 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8311 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8312 8313 /*remove DSP headroom*/ 8314 tmp = FLOAT_ZERO; 8315 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8316 8317 /* set WUH source */ 8318 tmp = FLOAT_TWO; 8319 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8320 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8321 8322 /* Set speaker source? */ 8323 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8324 8325 ca0132_alt_dsp_initial_mic_setup(codec); 8326 8327 /* out, in effects + voicefx */ 8328 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8329 for (idx = 0; idx < num_fx; idx++) { 8330 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8331 dspio_set_uint_param(codec, 8332 ca0132_effects[idx].mid, 8333 ca0132_effects[idx].reqs[i], 8334 ca0132_effects[idx].def_vals[i]); 8335 } 8336 } 8337 8338 ca0132_alt_init_speaker_tuning(codec); 8339 } 8340 8341 /* 8342 * Sound BlasterX AE-5 External WS2812B RGB LED Strip Transport 8343 */ 8344 #if IS_ENABLED(CONFIG_SND_HDA_DSP_LOADER) 8345 #define AE5_STRIP_DMA_SIZE 0x8000 8346 #define AE5_STRIP_TOTAL_WORDS (AE5_STRIP_DMA_SIZE / sizeof(u32)) 8347 #define AE5_STRIP_PREAMBLE_WORDS 5 8348 #define AE5_STRIP_WORDS_PER_LED 4 8349 #define AE5_STRIP_RESET_GAP_WORDS 83 8350 8351 #define CA0113_SERIALIZER_BASE(spec, ch) ((spec)->mem_base + 0x42c + (ch) * 0x40) 8352 #define CA0113_SERIALIZER_CLK(spec, ch) ((spec)->mem_base + 0x43c + (ch) * 0x40) 8353 #define CA0113_SERIALIZER_OUT(spec, ch) ((spec)->mem_base + 0x454 + (ch) * 0x40) 8354 8355 static void ae5_strip_encode_24(u32 u, u32 *words) 8356 { 8357 /* 8358 * 24-bit pixel -> 4 x 32-bit audio words (6 bits per word). 8359 * Hardware audio serializer transmits MSB first (bits 31 down to 0). 8360 * For word i (i8 = 23, 17, 11, 5), bit_idx 0..5 (MSB to LSB within the word) 8361 * is placed at n = 29 - bit_idx * 4: 8362 * Bit 0 -> 0b100 << n (375ns high, 1042ns low): BIT(n + 2) 8363 * Bit 1 -> 0b111 << n (1083ns high, 333ns low): BIT(n + 2) | BIT(n + 1) | BIT(n) 8364 */ 8365 int i8 = 23; 8366 int i, bit_idx; 8367 8368 for (i = 0; i < 4; i++) { 8369 u32 out = 0; 8370 8371 for (bit_idx = 0; bit_idx < 6; bit_idx++) { 8372 int bit = (u >> (i8 - bit_idx)) & 1; 8373 int n = 29 - bit_idx * 4; 8374 8375 out |= (bit ? (BIT(2) | BIT(1) | BIT(0)) : BIT(2)) << n; 8376 } 8377 words[i] = out; 8378 i8 -= 6; 8379 } 8380 } 8381 8382 static struct hdac_stream *ae5_strip_find_stream(struct hda_codec *codec) 8383 { 8384 struct ca0132_spec *spec = codec->spec; 8385 struct hdac_bus *bus = &codec->bus->core; 8386 struct hdac_stream *s, *dsp = NULL, *first = NULL; 8387 8388 guard(spinlock_irqsave)(&bus->reg_lock); 8389 list_for_each_entry(s, &bus->stream_list, list) { 8390 if (s->direction != SNDRV_PCM_STREAM_PLAYBACK) 8391 continue; 8392 if (s->opened || s->running || s->locked) 8393 continue; 8394 if (!first) 8395 first = s; 8396 /* The DSP DMA consumes the DSP-loader stream (tag in dsp_stream_id). */ 8397 if (spec->dsp_stream_id && s->stream_tag == spec->dsp_stream_id) 8398 dsp = s; 8399 } 8400 8401 s = dsp ? dsp : first; 8402 if (s) 8403 s->opened = 1; 8404 8405 return s; 8406 } 8407 8408 /* 8409 * Caller must hold spec->ae5_strip_mutex. 8410 */ 8411 static int ae5_strip_send_frame(struct hda_codec *codec, const u32 *grb_colors, int num_leds) 8412 { 8413 struct ca0132_spec *spec = codec->spec; 8414 struct hdac_bus *bus = &codec->bus->core; 8415 struct snd_dma_buffer dmab; 8416 struct hdac_stream *hstr = NULL; 8417 unsigned int format, stream_tag; 8418 u32 enc_words[4]; 8419 __le32 *dst; 8420 int word_idx = 0; 8421 int frame_words; 8422 int led, w, i; 8423 int retries = 20; /* ~100ms max */ 8424 8425 if (!spec || !spec->mem_base) 8426 return -ENODEV; 8427 if (num_leds <= 0 || num_leds > AE5_STRIP_MAX_LEDS) 8428 return -EINVAL; 8429 8430 lockdep_assert_held(&spec->ae5_strip_mutex); 8431 8432 CLASS(snd_hda_power_pm, pm)(codec); 8433 if (pm.err < 0) 8434 return pm.err; 8435 8436 /* 8437 * 44.1kHz, 24-bit, 2-channel format (0x4031) matches Windows CtxHda 8438 * HDAUDIO_STREAM_FORMAT. 8439 */ 8440 format = snd_hdac_stream_format(2, 24, 44100); 8441 8442 for (;;) { 8443 hstr = ae5_strip_find_stream(codec); 8444 if (!hstr) { 8445 if (--retries <= 0) { 8446 codec_warn(codec, "AE5 strip: no free azx stream after retries\n"); 8447 return -EBUSY; 8448 } 8449 usleep_range(5000, 10000); 8450 continue; 8451 } 8452 8453 stream_tag = snd_hdac_dsp_prepare(hstr, format, AE5_STRIP_DMA_SIZE, &dmab); 8454 if ((int)stream_tag > 0) 8455 break; 8456 8457 /* Prepare failed (e.g. -EBUSY due to race with playback starting); retry */ 8458 scoped_guard(spinlock_irq, &bus->reg_lock) 8459 hstr->opened = 0; 8460 8461 if (--retries <= 0) { 8462 codec_warn(codec, "AE5 strip: snd_hdac_dsp_prepare failed %d\n", 8463 (int)stream_tag); 8464 return (int)stream_tag; 8465 } 8466 usleep_range(5000, 10000); 8467 } 8468 8469 /* 1. Populate the 32KB DMA buffer with repeating WS2812 frames + reset gaps */ 8470 memset(dmab.area, 0, AE5_STRIP_DMA_SIZE); 8471 dst = (__le32 *)dmab.area; 8472 8473 /* Words per frame: preamble + (num_leds * words_per_led) + reset gap */ 8474 frame_words = AE5_STRIP_PREAMBLE_WORDS + (num_leds * AE5_STRIP_WORDS_PER_LED) + 8475 AE5_STRIP_RESET_GAP_WORDS; 8476 8477 while (word_idx + frame_words <= AE5_STRIP_TOTAL_WORDS) { 8478 /* Preamble per Windows CtxHda FUN_00042944 */ 8479 for (w = 0; w < AE5_STRIP_PREAMBLE_WORDS; w++) { 8480 *dst++ = 0; 8481 word_idx++; 8482 } 8483 /* LEDs */ 8484 for (led = 0; led < num_leds; led++) { 8485 ae5_strip_encode_24(grb_colors[led], enc_words); 8486 for (w = 0; w < AE5_STRIP_WORDS_PER_LED; w++) { 8487 *dst++ = cpu_to_le32(enc_words[w]); 8488 word_idx++; 8489 } 8490 } 8491 /* Zero reset gap (> 1.8 ms; WS2812 requires > 50 us low) */ 8492 for (w = 0; w < AE5_STRIP_RESET_GAP_WORDS; w++) { 8493 *dst++ = 0; 8494 word_idx++; 8495 } 8496 } 8497 while (word_idx < AE5_STRIP_TOTAL_WORDS) { 8498 *dst++ = 0; 8499 word_idx++; 8500 } 8501 /* Ensure DMA buffer writes are committed before triggering the HDA stream */ 8502 wmb(); 8503 8504 /* 2. Configure CA0113 BAR2 hardware registers */ 8505 /* Power up clocks (CtxHdb 0x141b7 / 0x14210) */ 8506 writel(readl(spec->mem_base + 0xc04) | 0x7, spec->mem_base + 0xc04); 8507 8508 /* Base serializer initialization (CtxHdb 0x14ba4) */ 8509 writel(readl(spec->mem_base + 0x400) | 1, spec->mem_base + 0x400); 8510 for (i = 0; i < 4; i++) { 8511 writel(readl(CA0113_SERIALIZER_BASE(spec, i)) & ~1, 8512 CA0113_SERIALIZER_BASE(spec, i)); 8513 writel(0, CA0113_SERIALIZER_CLK(spec, i)); 8514 } 8515 writel(readl(spec->mem_base + 0x408) | 1, spec->mem_base + 0x408); 8516 writel(readl(spec->mem_base + 0x40c) | 1, spec->mem_base + 0x40c); 8517 writel((readl(spec->mem_base + 0x410) & ~0xb) | 0x14, spec->mem_base + 0x410); 8518 8519 /* Configure serializers 0..3 clocking (CtxHdb 0x14a6c) */ 8520 for (i = 0; i < 4; i++) 8521 writel(readl(CA0113_SERIALIZER_CLK(spec, i)) | 0x33, 8522 CA0113_SERIALIZER_CLK(spec, i)); 8523 8524 /* BAR2 + 0x100 format & channel enables: 8525 * - base 0x70f 8526 * - bit 28 = 1 (24-bit audio format via CtxHdb 0x14f58) 8527 * - bits 29..31 = 1 (44.1 kHz sample rate via CtxHdb 0x14fa4) 8528 * - bits 4..7 = 0xf (stage 1 enables) 8529 * - bits 12..15 = 0xf (stage 2 enables) 8530 * => 0x3000ff8f 8531 */ 8532 writel((readl(spec->mem_base + 0x100) & ~0xe000ffff) | 0x3000ff8f, spec->mem_base + 0x100); 8533 8534 /* Enable serializer output drivers for pins 0..3 (CtxHdb 0x14e94) */ 8535 for (i = 0; i < 4; i++) 8536 writel(readl(CA0113_SERIALIZER_OUT(spec, i)) | 1, 8537 CA0113_SERIALIZER_OUT(spec, i)); 8538 8539 /* Route all channels 0..3 to stream_tag (CtxHdb 0x1502c) */ 8540 writel((stream_tag << 28) | (stream_tag << 20) | (stream_tag << 12) | (stream_tag << 4), 8541 spec->mem_base + 0x104); 8542 8543 /* Enable CA0113 MMIO GPIO 0 & 1 */ 8544 ca0113_mmio_gpio_set(codec, 0, true); 8545 ca0113_mmio_gpio_set(codec, 1, true); 8546 8547 codec_dbg(codec, "AE5 strip: send_frame: num_leds=%d stream_tag=%u (0x%08x)\n", 8548 num_leds, stream_tag, readl(spec->mem_base + 0x104)); 8549 8550 /* 3. Trigger stream transmission on HDA link */ 8551 snd_hdac_dsp_trigger(hstr, true); 8552 /* 8553 * WS2812 latches on the >50us reset gap after one frame. The 32KB buffer holds ~64 8554 * repeating frame+reset cycles; at ~1.4ms/frame a 15ms run transmits ~10 complete 8555 * cycles - more than enough to latch reliably. Keep it short so rapid sysfs writes 8556 * (OpenRGB effects/theme changes) are not serialized behind a 1s blocking sleep. 8557 */ 8558 usleep_range(15000, 20000); 8559 snd_hdac_dsp_trigger(hstr, false); 8560 codec_dbg(codec, "AE5 strip: trigger complete\n"); 8561 8562 /* Teardown: clear 0x104 pin mux back to 0 */ 8563 writel(0x00000000, spec->mem_base + 0x104); 8564 8565 snd_hdac_dsp_cleanup(hstr, &dmab); 8566 scoped_guard(spinlock_irq, &bus->reg_lock) 8567 hstr->opened = 0; 8568 8569 return 0; 8570 } 8571 8572 static int ae5_strip_ctl_info(struct snd_kcontrol *kcontrol, 8573 struct snd_ctl_elem_info *uinfo) 8574 { 8575 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 8576 uinfo->count = AE5_STRIP_MAX_LEDS * 3; 8577 return 0; 8578 } 8579 8580 static int ae5_strip_ctl_get(struct snd_kcontrol *kcontrol, 8581 struct snd_ctl_elem_value *ucontrol) 8582 { 8583 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 8584 struct ca0132_spec *spec = codec->spec; 8585 int i; 8586 8587 guard(mutex)(&spec->ae5_strip_mutex); 8588 for (i = 0; i < AE5_STRIP_MAX_LEDS; i++) { 8589 u32 grb = spec->ae5_strip_cur_colors[i]; 8590 8591 ucontrol->value.bytes.data[i * 3 + 0] = (grb >> 8) & 0xff; 8592 ucontrol->value.bytes.data[i * 3 + 1] = (grb >> 16) & 0xff; 8593 ucontrol->value.bytes.data[i * 3 + 2] = grb & 0xff; 8594 } 8595 return 0; 8596 } 8597 8598 static int ae5_strip_ctl_put(struct snd_kcontrol *kcontrol, 8599 struct snd_ctl_elem_value *ucontrol) 8600 { 8601 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 8602 struct ca0132_spec *spec = codec->spec; 8603 u32 colors[AE5_STRIP_MAX_LEDS]; 8604 int i, num_leds, change, ret; 8605 8606 guard(mutex)(&spec->ae5_strip_mutex); 8607 for (i = 0; i < AE5_STRIP_MAX_LEDS; i++) { 8608 u8 r = ucontrol->value.bytes.data[i * 3 + 0]; 8609 u8 g = ucontrol->value.bytes.data[i * 3 + 1]; 8610 u8 b = ucontrol->value.bytes.data[i * 3 + 2]; 8611 8612 colors[i] = ((u32)g << 16) | ((u32)r << 8) | (u32)b; 8613 } 8614 change = memcmp(spec->ae5_strip_cur_colors, colors, 8615 sizeof(spec->ae5_strip_cur_colors)) != 0; 8616 num_leds = spec->ae5_strip_cur_num_leds; 8617 ret = ae5_strip_send_frame(codec, colors, num_leds); 8618 if (ret < 0) 8619 return ret; 8620 if (change) 8621 memcpy(spec->ae5_strip_cur_colors, colors, 8622 sizeof(spec->ae5_strip_cur_colors)); 8623 return change; 8624 } 8625 8626 static int ae5_strip_num_leds_info(struct snd_kcontrol *kcontrol, 8627 struct snd_ctl_elem_info *uinfo) 8628 { 8629 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 8630 uinfo->count = 1; 8631 uinfo->value.integer.min = 1; 8632 uinfo->value.integer.max = AE5_STRIP_MAX_LEDS; 8633 return 0; 8634 } 8635 8636 static int ae5_strip_num_leds_get(struct snd_kcontrol *kcontrol, 8637 struct snd_ctl_elem_value *ucontrol) 8638 { 8639 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 8640 struct ca0132_spec *spec = codec->spec; 8641 8642 guard(mutex)(&spec->ae5_strip_mutex); 8643 ucontrol->value.integer.value[0] = spec->ae5_strip_cur_num_leds; 8644 return 0; 8645 } 8646 8647 static int ae5_strip_num_leds_put(struct snd_kcontrol *kcontrol, 8648 struct snd_ctl_elem_value *ucontrol) 8649 { 8650 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 8651 struct ca0132_spec *spec = codec->spec; 8652 int val = ucontrol->value.integer.value[0]; 8653 int ret; 8654 8655 if (val < 1 || val > AE5_STRIP_MAX_LEDS) 8656 return -EINVAL; 8657 8658 guard(mutex)(&spec->ae5_strip_mutex); 8659 if (spec->ae5_strip_cur_num_leds == val) 8660 return 0; 8661 ret = ae5_strip_send_frame(codec, spec->ae5_strip_cur_colors, val); 8662 if (ret < 0) 8663 return ret; 8664 spec->ae5_strip_cur_num_leds = val; 8665 return 1; 8666 } 8667 8668 static const struct snd_kcontrol_new ae5_strip_ctls[] = { 8669 { 8670 .iface = SNDRV_CTL_ELEM_IFACE_CARD, 8671 .name = "AE-5 LED Strip", 8672 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 8673 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 8674 .info = ae5_strip_ctl_info, 8675 .get = ae5_strip_ctl_get, 8676 .put = ae5_strip_ctl_put, 8677 }, 8678 { 8679 .iface = SNDRV_CTL_ELEM_IFACE_CARD, 8680 .name = "AE-5 LED Strip Count", 8681 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 8682 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 8683 .info = ae5_strip_num_leds_info, 8684 .get = ae5_strip_num_leds_get, 8685 .put = ae5_strip_num_leds_put, 8686 }, 8687 }; 8688 8689 static int ae5_add_strip_controls(struct hda_codec *codec) 8690 { 8691 int i, err; 8692 8693 for (i = 0; i < ARRAY_SIZE(ae5_strip_ctls); i++) { 8694 err = snd_hda_ctl_add(codec, 0, 8695 snd_ctl_new1(&ae5_strip_ctls[i], codec)); 8696 if (err < 0) 8697 return err; 8698 } 8699 return 0; 8700 } 8701 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 8702 8703 static void ae5_setup_defaults(struct hda_codec *codec) 8704 { 8705 struct ca0132_spec *spec = codec->spec; 8706 unsigned int tmp; 8707 int num_fx; 8708 int idx, i; 8709 8710 if (spec->dsp_state != DSP_DOWNLOADED) 8711 return; 8712 8713 ca0132_alt_init_analog_mics(codec); 8714 ca0132_alt_start_dsp_audio_streams(codec); 8715 8716 /* New, unknown SCP req's */ 8717 tmp = FLOAT_ZERO; 8718 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8719 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8720 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8721 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8722 8723 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8724 ca0113_mmio_gpio_set(codec, 0, false); 8725 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8726 8727 /* Internal loopback off */ 8728 tmp = FLOAT_ONE; 8729 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8730 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8731 8732 /*remove DSP headroom*/ 8733 tmp = FLOAT_ZERO; 8734 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8735 8736 /* set WUH source */ 8737 tmp = FLOAT_TWO; 8738 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8739 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8740 8741 /* Set speaker source? */ 8742 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8743 8744 ca0132_alt_dsp_initial_mic_setup(codec); 8745 ae5_post_dsp_register_set(codec); 8746 ae5_post_dsp_param_setup(codec); 8747 ae5_post_dsp_pll_setup(codec); 8748 ae5_post_dsp_stream_setup(codec); 8749 ae5_post_dsp_startup_data(codec); 8750 8751 /* out, in effects + voicefx */ 8752 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8753 for (idx = 0; idx < num_fx; idx++) { 8754 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8755 dspio_set_uint_param(codec, 8756 ca0132_effects[idx].mid, 8757 ca0132_effects[idx].reqs[i], 8758 ca0132_effects[idx].def_vals[i]); 8759 } 8760 } 8761 8762 ca0132_alt_init_speaker_tuning(codec); 8763 } 8764 8765 /* 8766 * Setup default parameters for the Sound Blaster AE-7 DSP. 8767 */ 8768 static void ae7_setup_defaults(struct hda_codec *codec) 8769 { 8770 struct ca0132_spec *spec = codec->spec; 8771 unsigned int tmp; 8772 int num_fx; 8773 int idx, i; 8774 8775 if (spec->dsp_state != DSP_DOWNLOADED) 8776 return; 8777 8778 ca0132_alt_init_analog_mics(codec); 8779 ca0132_alt_start_dsp_audio_streams(codec); 8780 ae7_post_dsp_setup_ports(codec); 8781 8782 tmp = FLOAT_ZERO; 8783 dspio_set_uint_param(codec, 0x96, 8784 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8785 dspio_set_uint_param(codec, 0x96, 8786 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8787 8788 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8789 8790 /* New, unknown SCP req's */ 8791 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8792 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8793 8794 ca0113_mmio_gpio_set(codec, 0, false); 8795 8796 /* Internal loopback off */ 8797 tmp = FLOAT_ONE; 8798 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8799 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8800 8801 /*remove DSP headroom*/ 8802 tmp = FLOAT_ZERO; 8803 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8804 8805 /* set WUH source */ 8806 tmp = FLOAT_TWO; 8807 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8808 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8809 8810 /* Set speaker source? */ 8811 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8812 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8813 8814 /* 8815 * This is the second time we've called this, but this is seemingly 8816 * what Windows does. 8817 */ 8818 ca0132_alt_init_analog_mics(codec); 8819 8820 ae7_post_dsp_asi_setup(codec); 8821 8822 /* 8823 * Not sure why, but these are both set to 1. They're only set to 0 8824 * upon shutdown. 8825 */ 8826 ca0113_mmio_gpio_set(codec, 0, true); 8827 ca0113_mmio_gpio_set(codec, 1, true); 8828 8829 /* Volume control related. */ 8830 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8831 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8832 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8833 8834 /* out, in effects + voicefx */ 8835 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8836 for (idx = 0; idx < num_fx; idx++) { 8837 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8838 dspio_set_uint_param(codec, 8839 ca0132_effects[idx].mid, 8840 ca0132_effects[idx].reqs[i], 8841 ca0132_effects[idx].def_vals[i]); 8842 } 8843 } 8844 8845 ca0132_alt_init_speaker_tuning(codec); 8846 } 8847 8848 /* 8849 * Initialization of flags in chip 8850 */ 8851 static void ca0132_init_flags(struct hda_codec *codec) 8852 { 8853 struct ca0132_spec *spec = codec->spec; 8854 8855 if (ca0132_use_alt_functions(spec)) { 8856 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8857 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8858 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8859 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8860 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8861 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8862 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8863 chipio_set_control_flag(codec, 8864 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8865 chipio_set_control_flag(codec, 8866 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8867 } else { 8868 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8869 chipio_set_control_flag(codec, 8870 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8871 chipio_set_control_flag(codec, 8872 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8873 chipio_set_control_flag(codec, 8874 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8875 chipio_set_control_flag(codec, 8876 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8877 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8878 } 8879 } 8880 8881 /* 8882 * Initialization of parameters in chip 8883 */ 8884 static void ca0132_init_params(struct hda_codec *codec) 8885 { 8886 struct ca0132_spec *spec = codec->spec; 8887 8888 if (ca0132_use_alt_functions(spec)) { 8889 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8890 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8891 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8892 chipio_set_control_param(codec, 0, 0); 8893 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8894 } 8895 8896 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8897 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8898 } 8899 8900 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8901 { 8902 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8903 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8904 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8905 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8906 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8907 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8908 8909 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8910 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8911 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8912 } 8913 8914 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8915 { 8916 struct ca0132_spec *spec = codec->spec; 8917 const struct dsp_image_seg *dsp_os_image; 8918 const struct firmware *fw_entry __free(firmware) = NULL; 8919 /* 8920 * Alternate firmwares for different variants. The Recon3Di apparently 8921 * can use the default firmware, but I'll leave the option in case 8922 * it needs it again. 8923 */ 8924 switch (ca0132_quirk(spec)) { 8925 case QUIRK_SBZ: 8926 case QUIRK_R3D: 8927 case QUIRK_AE5: 8928 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8929 codec->card->dev) != 0) 8930 codec_dbg(codec, "Desktop firmware not found."); 8931 else 8932 codec_dbg(codec, "Desktop firmware selected."); 8933 break; 8934 case QUIRK_R3DI: 8935 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8936 codec->card->dev) != 0) 8937 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8938 else 8939 codec_dbg(codec, "Recon3Di firmware selected."); 8940 break; 8941 default: 8942 break; 8943 } 8944 /* 8945 * Use default ctefx.bin if no alt firmware is detected, or if none 8946 * exists for your particular codec. 8947 */ 8948 if (!fw_entry) { 8949 codec_dbg(codec, "Default firmware selected."); 8950 if (request_firmware(&fw_entry, EFX_FILE, 8951 codec->card->dev) != 0) 8952 return false; 8953 } 8954 8955 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8956 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8957 codec_err(codec, "ca0132 DSP load image failed\n"); 8958 return false; 8959 } 8960 8961 return dspload_wait_loaded(codec); 8962 } 8963 8964 static void ca0132_download_dsp(struct hda_codec *codec) 8965 { 8966 struct ca0132_spec *spec = codec->spec; 8967 8968 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8969 return; /* NOP */ 8970 #endif 8971 8972 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8973 return; /* don't retry failures */ 8974 8975 chipio_enable_clocks(codec); 8976 if (spec->dsp_state != DSP_DOWNLOADED) { 8977 spec->dsp_state = DSP_DOWNLOADING; 8978 8979 if (!ca0132_download_dsp_images(codec)) 8980 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8981 else 8982 spec->dsp_state = DSP_DOWNLOADED; 8983 } 8984 8985 /* For codecs using alt functions, this is already done earlier */ 8986 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8987 ca0132_set_dsp_msr(codec, true); 8988 } 8989 8990 static void ca0132_process_dsp_response(struct hda_codec *codec, 8991 struct hda_jack_callback *callback) 8992 { 8993 struct ca0132_spec *spec = codec->spec; 8994 8995 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8996 CLASS(snd_hda_power_pm, pm)(codec); 8997 if (spec->wait_scp) { 8998 if (dspio_get_response_data(codec) >= 0) 8999 spec->wait_scp = 0; 9000 } 9001 9002 dspio_clear_response_queue(codec); 9003 } 9004 9005 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 9006 { 9007 struct ca0132_spec *spec = codec->spec; 9008 struct hda_jack_tbl *tbl; 9009 9010 /* Delay enabling the HP amp, to let the mic-detection 9011 * state machine run. 9012 */ 9013 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 9014 if (tbl) 9015 tbl->block_report = 1; 9016 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 9017 } 9018 9019 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 9020 { 9021 struct ca0132_spec *spec = codec->spec; 9022 9023 if (ca0132_use_alt_functions(spec)) 9024 ca0132_alt_select_in(codec); 9025 else 9026 ca0132_select_mic(codec); 9027 } 9028 9029 static void ca0132_setup_unsol(struct hda_codec *codec) 9030 { 9031 struct ca0132_spec *spec = codec->spec; 9032 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 9033 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 9034 amic_callback); 9035 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 9036 ca0132_process_dsp_response); 9037 /* Front headphone jack detection */ 9038 if (ca0132_use_alt_functions(spec)) 9039 snd_hda_jack_detect_enable_callback(codec, 9040 spec->unsol_tag_front_hp, hp_callback); 9041 } 9042 9043 /* 9044 * Verbs tables. 9045 */ 9046 9047 /* Sends before DSP download. */ 9048 static const struct hda_verb ca0132_base_init_verbs[] = { 9049 /*enable ct extension*/ 9050 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 9051 {} 9052 }; 9053 9054 /* Send at exit. */ 9055 static const struct hda_verb ca0132_base_exit_verbs[] = { 9056 /*set afg to D3*/ 9057 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 9058 /*disable ct extension*/ 9059 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 9060 {} 9061 }; 9062 9063 /* Other verbs tables. Sends after DSP download. */ 9064 9065 static const struct hda_verb ca0132_init_verbs0[] = { 9066 /* chip init verbs */ 9067 {0x15, 0x70D, 0xF0}, 9068 {0x15, 0x70E, 0xFE}, 9069 {0x15, 0x707, 0x75}, 9070 {0x15, 0x707, 0xD3}, 9071 {0x15, 0x707, 0x09}, 9072 {0x15, 0x707, 0x53}, 9073 {0x15, 0x707, 0xD4}, 9074 {0x15, 0x707, 0xEF}, 9075 {0x15, 0x707, 0x75}, 9076 {0x15, 0x707, 0xD3}, 9077 {0x15, 0x707, 0x09}, 9078 {0x15, 0x707, 0x02}, 9079 {0x15, 0x707, 0x37}, 9080 {0x15, 0x707, 0x78}, 9081 {0x15, 0x53C, 0xCE}, 9082 {0x15, 0x575, 0xC9}, 9083 {0x15, 0x53D, 0xCE}, 9084 {0x15, 0x5B7, 0xC9}, 9085 {0x15, 0x70D, 0xE8}, 9086 {0x15, 0x70E, 0xFE}, 9087 {0x15, 0x707, 0x02}, 9088 {0x15, 0x707, 0x68}, 9089 {0x15, 0x707, 0x62}, 9090 {0x15, 0x53A, 0xCE}, 9091 {0x15, 0x546, 0xC9}, 9092 {0x15, 0x53B, 0xCE}, 9093 {0x15, 0x5E8, 0xC9}, 9094 {} 9095 }; 9096 9097 /* Extra init verbs for desktop cards. */ 9098 static const struct hda_verb ca0132_init_verbs1[] = { 9099 {0x15, 0x70D, 0x20}, 9100 {0x15, 0x70E, 0x19}, 9101 {0x15, 0x707, 0x00}, 9102 {0x15, 0x539, 0xCE}, 9103 {0x15, 0x546, 0xC9}, 9104 {0x15, 0x70D, 0xB7}, 9105 {0x15, 0x70E, 0x09}, 9106 {0x15, 0x707, 0x10}, 9107 {0x15, 0x70D, 0xAF}, 9108 {0x15, 0x70E, 0x09}, 9109 {0x15, 0x707, 0x01}, 9110 {0x15, 0x707, 0x05}, 9111 {0x15, 0x70D, 0x73}, 9112 {0x15, 0x70E, 0x09}, 9113 {0x15, 0x707, 0x14}, 9114 {0x15, 0x6FF, 0xC4}, 9115 {} 9116 }; 9117 9118 static void ca0132_init_chip(struct hda_codec *codec) 9119 { 9120 struct ca0132_spec *spec = codec->spec; 9121 int num_fx; 9122 int i; 9123 unsigned int on; 9124 9125 mutex_init(&spec->chipio_mutex); 9126 #if IS_ENABLED(CONFIG_SND_HDA_DSP_LOADER) 9127 mutex_init(&spec->ae5_strip_mutex); 9128 spec->ae5_strip_cur_num_leds = 10; 9129 #endif 9130 9131 /* 9132 * The Windows driver always does this upon startup, which seems to 9133 * clear out any previous configuration. This should help issues where 9134 * a boot into Windows prior to a boot into Linux breaks things. Also, 9135 * Windows always sends the reset twice. 9136 */ 9137 if (ca0132_use_alt_functions(spec)) { 9138 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 9139 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 9140 9141 snd_hda_codec_write(codec, codec->core.afg, 0, 9142 AC_VERB_SET_CODEC_RESET, 0); 9143 snd_hda_codec_write(codec, codec->core.afg, 0, 9144 AC_VERB_SET_CODEC_RESET, 0); 9145 } 9146 9147 spec->cur_out_type = SPEAKER_OUT; 9148 if (!ca0132_use_alt_functions(spec)) 9149 spec->cur_mic_type = DIGITAL_MIC; 9150 else 9151 spec->cur_mic_type = REAR_MIC; 9152 9153 spec->cur_mic_boost = 0; 9154 9155 for (i = 0; i < VNODES_COUNT; i++) { 9156 spec->vnode_lvol[i] = 0x5a; 9157 spec->vnode_rvol[i] = 0x5a; 9158 spec->vnode_lswitch[i] = 0; 9159 spec->vnode_rswitch[i] = 0; 9160 } 9161 9162 /* 9163 * Default states for effects are in ca0132_effects[]. 9164 */ 9165 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 9166 for (i = 0; i < num_fx; i++) { 9167 on = (unsigned int)ca0132_effects[i].reqs[0]; 9168 spec->effects_switch[i] = on ? 1 : 0; 9169 } 9170 /* 9171 * Sets defaults for the effect slider controls, only for alternative 9172 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 9173 */ 9174 if (ca0132_use_alt_controls(spec)) { 9175 /* Set speakers to default to full range. */ 9176 spec->speaker_range_val[0] = 1; 9177 spec->speaker_range_val[1] = 1; 9178 9179 spec->xbass_xover_freq = 8; 9180 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 9181 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 9182 9183 spec->bass_redirect_xover_freq = 8; 9184 } 9185 9186 spec->voicefx_val = 0; 9187 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 9188 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 9189 9190 /* 9191 * The ZxR doesn't have a front panel header, and it's line-in is on 9192 * the daughter board. So, there is no input enum control, and we need 9193 * to make sure that spec->in_enum_val is set properly. 9194 */ 9195 if (ca0132_quirk(spec) == QUIRK_ZXR) 9196 spec->in_enum_val = REAR_MIC; 9197 9198 #ifdef ENABLE_TUNING_CONTROLS 9199 ca0132_init_tuning_defaults(codec); 9200 #endif 9201 } 9202 9203 /* 9204 * Recon3Di exit specific commands. 9205 */ 9206 /* prevents popping noise on shutdown */ 9207 static void r3di_gpio_shutdown(struct hda_codec *codec) 9208 { 9209 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 9210 } 9211 9212 /* 9213 * Sound Blaster Z exit specific commands. 9214 */ 9215 static void sbz_region2_exit(struct hda_codec *codec) 9216 { 9217 struct ca0132_spec *spec = codec->spec; 9218 unsigned int i; 9219 9220 for (i = 0; i < 4; i++) 9221 writeb(0x0, spec->mem_base + 0x100); 9222 for (i = 0; i < 8; i++) 9223 writeb(0xb3, spec->mem_base + 0x304); 9224 9225 ca0113_mmio_gpio_set(codec, 0, false); 9226 ca0113_mmio_gpio_set(codec, 1, false); 9227 ca0113_mmio_gpio_set(codec, 4, true); 9228 ca0113_mmio_gpio_set(codec, 5, false); 9229 ca0113_mmio_gpio_set(codec, 7, false); 9230 } 9231 9232 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 9233 { 9234 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 9235 unsigned int i; 9236 9237 snd_hda_codec_write(codec, 0x11, 0, 9238 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 9239 9240 for (i = 0; i < ARRAY_SIZE(pins); i++) 9241 snd_hda_codec_write(codec, pins[i], 0, 9242 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 9243 } 9244 9245 static void ca0132_clear_unsolicited(struct hda_codec *codec) 9246 { 9247 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 9248 unsigned int i; 9249 9250 for (i = 0; i < ARRAY_SIZE(pins); i++) { 9251 snd_hda_codec_write(codec, pins[i], 0, 9252 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 9253 } 9254 } 9255 9256 /* On shutdown, sends commands in sets of three */ 9257 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 9258 int mask, int data) 9259 { 9260 if (dir >= 0) 9261 snd_hda_codec_write(codec, 0x01, 0, 9262 AC_VERB_SET_GPIO_DIRECTION, dir); 9263 if (mask >= 0) 9264 snd_hda_codec_write(codec, 0x01, 0, 9265 AC_VERB_SET_GPIO_MASK, mask); 9266 9267 if (data >= 0) 9268 snd_hda_codec_write(codec, 0x01, 0, 9269 AC_VERB_SET_GPIO_DATA, data); 9270 } 9271 9272 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 9273 { 9274 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 9275 unsigned int i; 9276 9277 for (i = 0; i < ARRAY_SIZE(pins); i++) 9278 snd_hda_codec_write(codec, pins[i], 0, 9279 AC_VERB_SET_POWER_STATE, 0x03); 9280 } 9281 9282 static void sbz_exit_chip(struct hda_codec *codec) 9283 { 9284 chipio_set_stream_control(codec, 0x03, 0); 9285 chipio_set_stream_control(codec, 0x04, 0); 9286 9287 /* Mess with GPIO */ 9288 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 9289 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 9290 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 9291 9292 chipio_set_stream_control(codec, 0x14, 0); 9293 chipio_set_stream_control(codec, 0x0C, 0); 9294 9295 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9296 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9297 9298 chipio_write(codec, 0x18a020, 0x00000083); 9299 9300 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 9301 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 9302 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 9303 9304 chipio_set_stream_control(codec, 0x0C, 0); 9305 9306 chipio_set_control_param(codec, 0x0D, 0x24); 9307 9308 ca0132_clear_unsolicited(codec); 9309 sbz_set_pin_ctl_default(codec); 9310 9311 snd_hda_codec_write(codec, 0x0B, 0, 9312 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9313 9314 sbz_region2_exit(codec); 9315 } 9316 9317 static void r3d_exit_chip(struct hda_codec *codec) 9318 { 9319 ca0132_clear_unsolicited(codec); 9320 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9321 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 9322 } 9323 9324 static void ae5_exit_chip(struct hda_codec *codec) 9325 { 9326 chipio_set_stream_control(codec, 0x03, 0); 9327 chipio_set_stream_control(codec, 0x04, 0); 9328 9329 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9330 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9331 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9332 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9333 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9334 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 9335 ca0113_mmio_gpio_set(codec, 0, false); 9336 ca0113_mmio_gpio_set(codec, 1, false); 9337 9338 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9339 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9340 9341 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9342 9343 chipio_set_stream_control(codec, 0x18, 0); 9344 chipio_set_stream_control(codec, 0x0c, 0); 9345 9346 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 9347 } 9348 9349 static void ae7_exit_chip(struct hda_codec *codec) 9350 { 9351 chipio_set_stream_control(codec, 0x18, 0); 9352 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 9353 chipio_set_stream_channels(codec, 0x21, 0); 9354 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 9355 chipio_set_control_param(codec, 0x20, 0x01); 9356 9357 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 9358 9359 chipio_set_stream_control(codec, 0x18, 0); 9360 chipio_set_stream_control(codec, 0x0c, 0); 9361 9362 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 9363 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 9364 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9365 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 9366 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 9367 ca0113_mmio_gpio_set(codec, 0, false); 9368 ca0113_mmio_gpio_set(codec, 1, false); 9369 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9370 9371 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9372 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9373 } 9374 9375 static void zxr_exit_chip(struct hda_codec *codec) 9376 { 9377 chipio_set_stream_control(codec, 0x03, 0); 9378 chipio_set_stream_control(codec, 0x04, 0); 9379 chipio_set_stream_control(codec, 0x14, 0); 9380 chipio_set_stream_control(codec, 0x0C, 0); 9381 9382 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9383 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9384 9385 chipio_write(codec, 0x18a020, 0x00000083); 9386 9387 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9388 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9389 9390 ca0132_clear_unsolicited(codec); 9391 sbz_set_pin_ctl_default(codec); 9392 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9393 9394 ca0113_mmio_gpio_set(codec, 5, false); 9395 ca0113_mmio_gpio_set(codec, 2, false); 9396 ca0113_mmio_gpio_set(codec, 3, false); 9397 ca0113_mmio_gpio_set(codec, 0, false); 9398 ca0113_mmio_gpio_set(codec, 4, true); 9399 ca0113_mmio_gpio_set(codec, 0, true); 9400 ca0113_mmio_gpio_set(codec, 5, true); 9401 ca0113_mmio_gpio_set(codec, 2, false); 9402 ca0113_mmio_gpio_set(codec, 3, false); 9403 } 9404 9405 static void ca0132_exit_chip(struct hda_codec *codec) 9406 { 9407 /* put any chip cleanup stuffs here. */ 9408 9409 if (dspload_is_loaded(codec)) 9410 dsp_reset(codec); 9411 } 9412 9413 /* 9414 * This fixes a problem that was hard to reproduce. Very rarely, I would 9415 * boot up, and there would be no sound, but the DSP indicated it had loaded 9416 * properly. I did a few memory dumps to see if anything was different, and 9417 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9418 * checks if those areas are uninitialized, and if they are, it'll attempt to 9419 * reload the card 3 times. Usually it fixes by the second. 9420 */ 9421 static void sbz_dsp_startup_check(struct hda_codec *codec) 9422 { 9423 struct ca0132_spec *spec = codec->spec; 9424 unsigned int dsp_data_check[4]; 9425 unsigned int cur_address = 0x390; 9426 unsigned int i; 9427 unsigned int failure = 0; 9428 unsigned int reload = 3; 9429 9430 if (spec->startup_check_entered) 9431 return; 9432 9433 spec->startup_check_entered = true; 9434 9435 for (i = 0; i < 4; i++) { 9436 chipio_read(codec, cur_address, &dsp_data_check[i]); 9437 cur_address += 0x4; 9438 } 9439 for (i = 0; i < 4; i++) { 9440 if (dsp_data_check[i] == 0xa1a2a3a4) 9441 failure = 1; 9442 } 9443 9444 codec_dbg(codec, "Startup Check: %d ", failure); 9445 if (failure) 9446 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9447 /* 9448 * While the failure condition is true, and we haven't reached our 9449 * three reload limit, continue trying to reload the driver and 9450 * fix the issue. 9451 */ 9452 while (failure && (reload != 0)) { 9453 codec_info(codec, "Reloading... Tries left: %d", reload); 9454 sbz_exit_chip(codec); 9455 spec->dsp_state = DSP_DOWNLOAD_INIT; 9456 snd_hda_codec_init(codec); 9457 failure = 0; 9458 for (i = 0; i < 4; i++) { 9459 chipio_read(codec, cur_address, &dsp_data_check[i]); 9460 cur_address += 0x4; 9461 } 9462 for (i = 0; i < 4; i++) { 9463 if (dsp_data_check[i] == 0xa1a2a3a4) 9464 failure = 1; 9465 } 9466 reload--; 9467 } 9468 9469 if (!failure && reload < 3) 9470 codec_info(codec, "DSP fixed."); 9471 9472 if (!failure) 9473 return; 9474 9475 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9476 } 9477 9478 /* 9479 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9480 * extra precision for decibel values. If you had the dB value in floating point 9481 * you would take the value after the decimal point, multiply by 64, and divide 9482 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9483 * implement fixed point or floating point dB volumes. For now, I'll set them 9484 * to 0 just incase a value has lingered from a boot into Windows. 9485 */ 9486 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9487 { 9488 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9489 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9490 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9491 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9492 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9493 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9494 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9495 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9496 } 9497 9498 /* 9499 * Extra commands that don't really fit anywhere else. 9500 */ 9501 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9502 { 9503 struct ca0132_spec *spec = codec->spec; 9504 9505 writel(0x00820680, spec->mem_base + 0x01C); 9506 writel(0x00820680, spec->mem_base + 0x01C); 9507 9508 chipio_write(codec, 0x18b0a4, 0x000000c2); 9509 9510 snd_hda_codec_write(codec, 0x11, 0, 9511 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9512 } 9513 9514 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9515 { 9516 chipio_write(codec, 0x18b0a4, 0x000000c2); 9517 9518 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9519 9520 snd_hda_codec_write(codec, 0x11, 0, 9521 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9522 } 9523 9524 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9525 { 9526 chipio_write(codec, 0x18b0a4, 0x000000c2); 9527 9528 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9529 chipio_8051_write_exram(codec, 0x1920, 0x00); 9530 chipio_8051_write_exram(codec, 0x1921, 0x40); 9531 9532 snd_hda_codec_write(codec, 0x11, 0, 9533 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9534 } 9535 9536 /* 9537 * The ZxR seems to use alternative DAC's for the surround channels, which 9538 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9539 * this up, we get no audio out of the surround jacks. 9540 */ 9541 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9542 { 9543 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9544 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9545 unsigned int i; 9546 9547 chipio_write(codec, 0x189000, 0x0001f100); 9548 msleep(50); 9549 chipio_write(codec, 0x18900c, 0x0001f100); 9550 msleep(50); 9551 9552 /* 9553 * This writes a RET instruction at the entry point of the function at 9554 * 0xfa92 in exram. This function seems to have something to do with 9555 * ASI. Might be some way to prevent the card from reconfiguring the 9556 * ASI stuff itself. 9557 */ 9558 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9559 9560 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9561 9562 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9563 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9564 9565 chipio_write(codec, 0x18902c, 0x00000000); 9566 msleep(50); 9567 chipio_write(codec, 0x18902c, 0x00000003); 9568 msleep(50); 9569 9570 for (i = 0; i < ARRAY_SIZE(addr); i++) 9571 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9572 } 9573 9574 /* 9575 * These are sent before the DSP is downloaded. Not sure 9576 * what they do, or if they're necessary. Could possibly 9577 * be removed. Figure they're better to leave in. 9578 */ 9579 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9580 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9581 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9582 }; 9583 9584 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9585 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9586 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9587 0x000000c1, 0x00000080 9588 }; 9589 9590 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9591 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9592 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9593 0x000000c1, 0x00000080 9594 }; 9595 9596 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9597 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9598 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9599 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9600 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9601 }; 9602 9603 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9604 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9605 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9606 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9607 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9608 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9609 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9610 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9611 0x00000080, 0x00880680 9612 }; 9613 9614 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9615 { 9616 struct ca0132_spec *spec = codec->spec; 9617 unsigned int tmp[2], i, count, cur_addr; 9618 const unsigned int *addr, *data; 9619 9620 addr = ca0113_mmio_init_address_sbz; 9621 for (i = 0; i < 3; i++) 9622 writel(0x00000000, spec->mem_base + addr[i]); 9623 9624 cur_addr = i; 9625 switch (ca0132_quirk(spec)) { 9626 case QUIRK_ZXR: 9627 tmp[0] = 0x00880480; 9628 tmp[1] = 0x00000080; 9629 break; 9630 case QUIRK_SBZ: 9631 tmp[0] = 0x00820680; 9632 tmp[1] = 0x00000083; 9633 break; 9634 case QUIRK_R3D: 9635 tmp[0] = 0x00880680; 9636 tmp[1] = 0x00000083; 9637 break; 9638 default: 9639 tmp[0] = 0x00000000; 9640 tmp[1] = 0x00000000; 9641 break; 9642 } 9643 9644 for (i = 0; i < 2; i++) 9645 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9646 9647 cur_addr += i; 9648 9649 switch (ca0132_quirk(spec)) { 9650 case QUIRK_ZXR: 9651 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9652 data = ca0113_mmio_init_data_zxr; 9653 break; 9654 default: 9655 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9656 data = ca0113_mmio_init_data_sbz; 9657 break; 9658 } 9659 9660 for (i = 0; i < count; i++) 9661 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9662 } 9663 9664 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9665 { 9666 struct ca0132_spec *spec = codec->spec; 9667 const unsigned int *addr, *data; 9668 unsigned int i, count; 9669 9670 addr = ca0113_mmio_init_address_ae5; 9671 data = ca0113_mmio_init_data_ae5; 9672 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9673 9674 if (ca0132_quirk(spec) == QUIRK_AE7) { 9675 writel(0x00000680, spec->mem_base + 0x1c); 9676 writel(0x00880680, spec->mem_base + 0x1c); 9677 } 9678 9679 for (i = 0; i < count; i++) { 9680 /* 9681 * AE-7 shares all writes with the AE-5, except that it writes 9682 * a different value to 0x20c. 9683 */ 9684 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9685 writel(0x00800001, spec->mem_base + addr[i]); 9686 continue; 9687 } 9688 9689 writel(data[i], spec->mem_base + addr[i]); 9690 } 9691 9692 if (ca0132_quirk(spec) == QUIRK_AE5) 9693 writel(0x00880680, spec->mem_base + 0x1c); 9694 } 9695 9696 static void ca0132_mmio_init(struct hda_codec *codec) 9697 { 9698 struct ca0132_spec *spec = codec->spec; 9699 9700 switch (ca0132_quirk(spec)) { 9701 case QUIRK_R3D: 9702 case QUIRK_SBZ: 9703 case QUIRK_ZXR: 9704 ca0132_mmio_init_sbz(codec); 9705 break; 9706 case QUIRK_AE5: 9707 ca0132_mmio_init_ae5(codec); 9708 break; 9709 default: 9710 break; 9711 } 9712 } 9713 9714 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9715 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9716 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9717 }; 9718 9719 static const unsigned char ca0132_ae5_register_set_data[] = { 9720 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9721 0x01, 0x6b, 0x57 9722 }; 9723 9724 /* 9725 * This function writes to some SFR's, does some region2 writes, and then 9726 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9727 * what it does. 9728 */ 9729 static void ae5_register_set(struct hda_codec *codec) 9730 { 9731 struct ca0132_spec *spec = codec->spec; 9732 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9733 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9734 const unsigned char *data = ca0132_ae5_register_set_data; 9735 unsigned int i, cur_addr; 9736 unsigned char tmp[3]; 9737 9738 if (ca0132_quirk(spec) == QUIRK_AE7) 9739 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9740 9741 chipio_8051_write_direct(codec, 0x93, 0x10); 9742 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9743 9744 if (ca0132_quirk(spec) == QUIRK_AE7) { 9745 tmp[0] = 0x03; 9746 tmp[1] = 0x03; 9747 tmp[2] = 0x07; 9748 } else { 9749 tmp[0] = 0x0f; 9750 tmp[1] = 0x0f; 9751 tmp[2] = 0x0f; 9752 } 9753 9754 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9755 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9756 9757 /* 9758 * First writes are in single bytes, final are in 4 bytes. So, we use 9759 * writeb, then writel. 9760 */ 9761 for (i = 0; cur_addr < 12; i++, cur_addr++) 9762 writeb(data[i], spec->mem_base + addr[cur_addr]); 9763 9764 for (; cur_addr < count; i++, cur_addr++) 9765 writel(data[i], spec->mem_base + addr[cur_addr]); 9766 9767 writel(0x00800001, spec->mem_base + 0x20c); 9768 9769 if (ca0132_quirk(spec) == QUIRK_AE7) { 9770 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9771 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9772 } else { 9773 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9774 } 9775 9776 chipio_8051_write_direct(codec, 0x90, 0x00); 9777 chipio_8051_write_direct(codec, 0x90, 0x10); 9778 9779 if (ca0132_quirk(spec) == QUIRK_AE5) 9780 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9781 } 9782 9783 /* 9784 * Extra init functions for alternative ca0132 codecs. Done 9785 * here so they don't clutter up the main ca0132_init function 9786 * anymore than they have to. 9787 */ 9788 static void ca0132_alt_init(struct hda_codec *codec) 9789 { 9790 struct ca0132_spec *spec = codec->spec; 9791 9792 ca0132_alt_vol_setup(codec); 9793 9794 switch (ca0132_quirk(spec)) { 9795 case QUIRK_SBZ: 9796 codec_dbg(codec, "SBZ alt_init"); 9797 ca0132_gpio_init(codec); 9798 sbz_pre_dsp_setup(codec); 9799 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9800 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9801 break; 9802 case QUIRK_R3DI: 9803 codec_dbg(codec, "R3DI alt_init"); 9804 ca0132_gpio_init(codec); 9805 ca0132_gpio_setup(codec); 9806 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9807 r3di_pre_dsp_setup(codec); 9808 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9809 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9810 break; 9811 case QUIRK_R3D: 9812 r3d_pre_dsp_setup(codec); 9813 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9814 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9815 break; 9816 case QUIRK_AE5: 9817 ca0132_gpio_init(codec); 9818 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9819 chipio_write(codec, 0x18b030, 0x00000020); 9820 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9821 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9822 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9823 break; 9824 case QUIRK_AE7: 9825 ca0132_gpio_init(codec); 9826 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9827 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9828 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9829 chipio_write(codec, 0x18b008, 0x000000f8); 9830 chipio_write(codec, 0x18b008, 0x000000f0); 9831 chipio_write(codec, 0x18b030, 0x00000020); 9832 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9833 break; 9834 case QUIRK_ZXR: 9835 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9836 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9837 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9838 zxr_pre_dsp_setup(codec); 9839 break; 9840 default: 9841 break; 9842 } 9843 } 9844 9845 static int ca0132_init(struct hda_codec *codec) 9846 { 9847 struct ca0132_spec *spec = codec->spec; 9848 struct auto_pin_cfg *cfg = &spec->autocfg; 9849 int i; 9850 bool dsp_loaded; 9851 9852 /* 9853 * If the DSP is already downloaded, and init has been entered again, 9854 * there's only two reasons for it. One, the codec has awaken from a 9855 * suspended state, and in that case dspload_is_loaded will return 9856 * false, and the init will be ran again. The other reason it gets 9857 * re entered is on startup for some reason it triggers a suspend and 9858 * resume state. In this case, it will check if the DSP is downloaded, 9859 * and not run the init function again. For codecs using alt_functions, 9860 * it will check if the DSP is loaded properly. 9861 */ 9862 if (spec->dsp_state == DSP_DOWNLOADED) { 9863 dsp_loaded = dspload_is_loaded(codec); 9864 if (!dsp_loaded) { 9865 spec->dsp_reload = true; 9866 spec->dsp_state = DSP_DOWNLOAD_INIT; 9867 } else { 9868 if (ca0132_quirk(spec) == QUIRK_SBZ) 9869 sbz_dsp_startup_check(codec); 9870 return 0; 9871 } 9872 } 9873 9874 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9875 spec->dsp_state = DSP_DOWNLOAD_INIT; 9876 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9877 9878 if (ca0132_use_pci_mmio(spec)) 9879 ca0132_mmio_init(codec); 9880 9881 CLASS(snd_hda_power_pm, pm)(codec); 9882 9883 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9884 ae5_register_set(codec); 9885 9886 ca0132_init_params(codec); 9887 ca0132_init_flags(codec); 9888 9889 snd_hda_sequence_write(codec, spec->base_init_verbs); 9890 9891 if (ca0132_use_alt_functions(spec)) 9892 ca0132_alt_init(codec); 9893 9894 ca0132_download_dsp(codec); 9895 9896 ca0132_refresh_widget_caps(codec); 9897 9898 switch (ca0132_quirk(spec)) { 9899 case QUIRK_R3DI: 9900 case QUIRK_R3D: 9901 r3d_setup_defaults(codec); 9902 break; 9903 case QUIRK_SBZ: 9904 case QUIRK_ZXR: 9905 sbz_setup_defaults(codec); 9906 break; 9907 case QUIRK_AE5: 9908 ae5_setup_defaults(codec); 9909 break; 9910 case QUIRK_AE7: 9911 ae7_setup_defaults(codec); 9912 break; 9913 default: 9914 ca0132_setup_defaults(codec); 9915 ca0132_init_analog_mic2(codec); 9916 ca0132_init_dmic(codec); 9917 break; 9918 } 9919 9920 for (i = 0; i < spec->num_outputs; i++) 9921 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9922 9923 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9924 9925 for (i = 0; i < spec->num_inputs; i++) 9926 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9927 9928 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9929 9930 if (!ca0132_use_alt_functions(spec)) { 9931 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9933 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9934 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9935 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9936 } 9937 9938 if (ca0132_quirk(spec) == QUIRK_SBZ) 9939 ca0132_gpio_setup(codec); 9940 9941 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9942 if (ca0132_use_alt_functions(spec)) { 9943 ca0132_alt_select_out(codec); 9944 ca0132_alt_select_in(codec); 9945 } else { 9946 ca0132_select_out(codec); 9947 ca0132_select_mic(codec); 9948 } 9949 9950 snd_hda_jack_report_sync(codec); 9951 9952 /* 9953 * Re set the PlayEnhancement switch on a resume event, because the 9954 * controls will not be reloaded. 9955 */ 9956 if (spec->dsp_reload) { 9957 spec->dsp_reload = false; 9958 ca0132_pe_switch_set(codec); 9959 } 9960 9961 return 0; 9962 } 9963 9964 static int dbpro_init(struct hda_codec *codec) 9965 { 9966 struct ca0132_spec *spec = codec->spec; 9967 struct auto_pin_cfg *cfg = &spec->autocfg; 9968 unsigned int i; 9969 9970 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9971 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9972 9973 for (i = 0; i < spec->num_inputs; i++) 9974 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9975 9976 return 0; 9977 } 9978 9979 static void ca0132_free(struct hda_codec *codec) 9980 { 9981 struct ca0132_spec *spec = codec->spec; 9982 9983 cancel_delayed_work_sync(&spec->unsol_hp_work); 9984 snd_hda_power_up(codec); 9985 switch (ca0132_quirk(spec)) { 9986 case QUIRK_SBZ: 9987 sbz_exit_chip(codec); 9988 break; 9989 case QUIRK_ZXR: 9990 zxr_exit_chip(codec); 9991 break; 9992 case QUIRK_R3D: 9993 r3d_exit_chip(codec); 9994 break; 9995 case QUIRK_AE5: 9996 ae5_exit_chip(codec); 9997 break; 9998 case QUIRK_AE7: 9999 ae7_exit_chip(codec); 10000 break; 10001 case QUIRK_R3DI: 10002 r3di_gpio_shutdown(codec); 10003 break; 10004 default: 10005 break; 10006 } 10007 10008 snd_hda_sequence_write(codec, spec->base_exit_verbs); 10009 ca0132_exit_chip(codec); 10010 10011 snd_hda_power_down(codec); 10012 #ifdef CONFIG_PCI 10013 if (spec->mem_base) 10014 pci_iounmap(codec->bus->pci, spec->mem_base); 10015 #endif 10016 #if IS_ENABLED(CONFIG_SND_HDA_DSP_LOADER) 10017 mutex_destroy(&spec->ae5_strip_mutex); 10018 #endif 10019 kfree(spec->spec_init_verbs); 10020 kfree(codec->spec); 10021 codec->spec = NULL; 10022 } 10023 10024 static void dbpro_free(struct hda_codec *codec) 10025 { 10026 struct ca0132_spec *spec = codec->spec; 10027 10028 zxr_dbpro_power_state_shutdown(codec); 10029 10030 kfree(spec->spec_init_verbs); 10031 kfree(codec->spec); 10032 codec->spec = NULL; 10033 } 10034 10035 static void ca0132_config(struct hda_codec *codec) 10036 { 10037 struct ca0132_spec *spec = codec->spec; 10038 10039 spec->dacs[0] = 0x2; 10040 spec->dacs[1] = 0x3; 10041 spec->dacs[2] = 0x4; 10042 10043 spec->multiout.dac_nids = spec->dacs; 10044 spec->multiout.num_dacs = 3; 10045 10046 if (!ca0132_use_alt_functions(spec)) 10047 spec->multiout.max_channels = 2; 10048 else 10049 spec->multiout.max_channels = 6; 10050 10051 switch (ca0132_quirk(spec)) { 10052 case QUIRK_ALIENWARE: 10053 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 10054 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 10055 break; 10056 case QUIRK_SBZ: 10057 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 10058 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 10059 break; 10060 case QUIRK_ZXR: 10061 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 10062 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 10063 break; 10064 case QUIRK_R3D: 10065 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 10066 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 10067 break; 10068 case QUIRK_R3DI: 10069 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 10070 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 10071 break; 10072 case QUIRK_AE5: 10073 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 10074 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 10075 break; 10076 case QUIRK_AE7: 10077 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 10078 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 10079 break; 10080 default: 10081 break; 10082 } 10083 10084 switch (ca0132_quirk(spec)) { 10085 case QUIRK_ALIENWARE: 10086 spec->num_outputs = 2; 10087 spec->out_pins[0] = 0x0b; /* speaker out */ 10088 spec->out_pins[1] = 0x0f; 10089 spec->shared_out_nid = 0x2; 10090 spec->unsol_tag_hp = 0x0f; 10091 10092 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 10093 spec->adcs[1] = 0x8; /* analog mic2 */ 10094 spec->adcs[2] = 0xa; /* what u hear */ 10095 10096 spec->num_inputs = 3; 10097 spec->input_pins[0] = 0x12; 10098 spec->input_pins[1] = 0x11; 10099 spec->input_pins[2] = 0x13; 10100 spec->shared_mic_nid = 0x7; 10101 spec->unsol_tag_amic1 = 0x11; 10102 break; 10103 case QUIRK_SBZ: 10104 case QUIRK_R3D: 10105 spec->num_outputs = 2; 10106 spec->out_pins[0] = 0x0B; /* Line out */ 10107 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 10108 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 10109 spec->out_pins[3] = 0x11; /* Rear surround */ 10110 spec->shared_out_nid = 0x2; 10111 spec->unsol_tag_hp = spec->out_pins[1]; 10112 spec->unsol_tag_front_hp = spec->out_pins[2]; 10113 10114 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 10115 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 10116 spec->adcs[2] = 0xa; /* what u hear */ 10117 10118 spec->num_inputs = 2; 10119 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 10120 spec->input_pins[1] = 0x13; /* What U Hear */ 10121 spec->shared_mic_nid = 0x7; 10122 spec->unsol_tag_amic1 = spec->input_pins[0]; 10123 10124 /* SPDIF I/O */ 10125 spec->dig_out = 0x05; 10126 spec->multiout.dig_out_nid = spec->dig_out; 10127 spec->dig_in = 0x09; 10128 break; 10129 case QUIRK_ZXR: 10130 spec->num_outputs = 2; 10131 spec->out_pins[0] = 0x0B; /* Line out */ 10132 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 10133 spec->out_pins[2] = 0x10; /* Center/LFE */ 10134 spec->out_pins[3] = 0x11; /* Rear surround */ 10135 spec->shared_out_nid = 0x2; 10136 spec->unsol_tag_hp = spec->out_pins[1]; 10137 spec->unsol_tag_front_hp = spec->out_pins[2]; 10138 10139 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 10140 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 10141 spec->adcs[2] = 0xa; /* what u hear */ 10142 10143 spec->num_inputs = 2; 10144 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 10145 spec->input_pins[1] = 0x13; /* What U Hear */ 10146 spec->shared_mic_nid = 0x7; 10147 spec->unsol_tag_amic1 = spec->input_pins[0]; 10148 break; 10149 case QUIRK_ZXR_DBPRO: 10150 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 10151 10152 spec->num_inputs = 1; 10153 spec->input_pins[0] = 0x11; /* RCA Line-in */ 10154 10155 spec->dig_out = 0x05; 10156 spec->multiout.dig_out_nid = spec->dig_out; 10157 10158 spec->dig_in = 0x09; 10159 break; 10160 case QUIRK_AE5: 10161 case QUIRK_AE7: 10162 spec->num_outputs = 2; 10163 spec->out_pins[0] = 0x0B; /* Line out */ 10164 spec->out_pins[1] = 0x11; /* Rear headphone out */ 10165 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 10166 spec->out_pins[3] = 0x0F; /* Rear surround */ 10167 spec->shared_out_nid = 0x2; 10168 spec->unsol_tag_hp = spec->out_pins[1]; 10169 spec->unsol_tag_front_hp = spec->out_pins[2]; 10170 10171 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 10172 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 10173 spec->adcs[2] = 0xa; /* what u hear */ 10174 10175 spec->num_inputs = 2; 10176 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 10177 spec->input_pins[1] = 0x13; /* What U Hear */ 10178 spec->shared_mic_nid = 0x7; 10179 spec->unsol_tag_amic1 = spec->input_pins[0]; 10180 10181 /* SPDIF I/O */ 10182 spec->dig_out = 0x05; 10183 spec->multiout.dig_out_nid = spec->dig_out; 10184 break; 10185 case QUIRK_R3DI: 10186 spec->num_outputs = 2; 10187 spec->out_pins[0] = 0x0B; /* Line out */ 10188 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 10189 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 10190 spec->out_pins[3] = 0x11; /* Rear surround */ 10191 spec->shared_out_nid = 0x2; 10192 spec->unsol_tag_hp = spec->out_pins[1]; 10193 spec->unsol_tag_front_hp = spec->out_pins[2]; 10194 10195 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 10196 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 10197 spec->adcs[2] = 0x0a; /* what u hear */ 10198 10199 spec->num_inputs = 2; 10200 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 10201 spec->input_pins[1] = 0x13; /* What U Hear */ 10202 spec->shared_mic_nid = 0x7; 10203 spec->unsol_tag_amic1 = spec->input_pins[0]; 10204 10205 /* SPDIF I/O */ 10206 spec->dig_out = 0x05; 10207 spec->multiout.dig_out_nid = spec->dig_out; 10208 break; 10209 default: 10210 spec->num_outputs = 2; 10211 spec->out_pins[0] = 0x0b; /* speaker out */ 10212 spec->out_pins[1] = 0x10; /* headphone out */ 10213 spec->shared_out_nid = 0x2; 10214 spec->unsol_tag_hp = spec->out_pins[1]; 10215 10216 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 10217 spec->adcs[1] = 0x8; /* analog mic2 */ 10218 spec->adcs[2] = 0xa; /* what u hear */ 10219 10220 spec->num_inputs = 3; 10221 spec->input_pins[0] = 0x12; 10222 spec->input_pins[1] = 0x11; 10223 spec->input_pins[2] = 0x13; 10224 spec->shared_mic_nid = 0x7; 10225 spec->unsol_tag_amic1 = spec->input_pins[0]; 10226 10227 /* SPDIF I/O */ 10228 spec->dig_out = 0x05; 10229 spec->multiout.dig_out_nid = spec->dig_out; 10230 spec->dig_in = 0x09; 10231 break; 10232 } 10233 10234 /* Default HP/Speaker auto-detect from headphone pin verb: enable if the 10235 * pin config indicates presence detect (not AC_DEFCFG_MISC_NO_PRESENCE). 10236 */ 10237 if (spec->unsol_tag_hp && 10238 (snd_hda_query_pin_caps(codec, spec->unsol_tag_hp) & AC_PINCAP_PRES_DETECT) && 10239 !(get_defcfg_misc(snd_hda_codec_get_pincfg(codec, spec->unsol_tag_hp)) & 10240 AC_DEFCFG_MISC_NO_PRESENCE)) 10241 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 1; 10242 } 10243 10244 static int ca0132_prepare_verbs(struct hda_codec *codec) 10245 { 10246 /* Verbs + terminator (an empty element) */ 10247 #define NUM_SPEC_VERBS 2 10248 struct ca0132_spec *spec = codec->spec; 10249 10250 spec->chip_init_verbs = ca0132_init_verbs0; 10251 /* 10252 * Since desktop cards use pci_mmio, this can be used to determine 10253 * whether or not to use these verbs instead of a separate bool. 10254 */ 10255 if (ca0132_use_pci_mmio(spec)) 10256 spec->desktop_init_verbs = ca0132_init_verbs1; 10257 spec->spec_init_verbs = kzalloc_objs(struct hda_verb, NUM_SPEC_VERBS); 10258 if (!spec->spec_init_verbs) 10259 return -ENOMEM; 10260 10261 /* config EAPD */ 10262 spec->spec_init_verbs[0].nid = 0x0b; 10263 spec->spec_init_verbs[0].param = 0x78D; 10264 spec->spec_init_verbs[0].verb = 0x00; 10265 10266 /* Previously commented configuration */ 10267 /* 10268 spec->spec_init_verbs[2].nid = 0x0b; 10269 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 10270 spec->spec_init_verbs[2].verb = 0x02; 10271 10272 spec->spec_init_verbs[3].nid = 0x10; 10273 spec->spec_init_verbs[3].param = 0x78D; 10274 spec->spec_init_verbs[3].verb = 0x02; 10275 10276 spec->spec_init_verbs[4].nid = 0x10; 10277 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 10278 spec->spec_init_verbs[4].verb = 0x02; 10279 */ 10280 10281 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 10282 return 0; 10283 } 10284 10285 /* 10286 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 10287 * Sound Blaster Z cards. However, they have different HDA codec subsystem 10288 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 10289 * daughter boards ID. 10290 */ 10291 static void sbz_detect_quirk(struct hda_codec *codec) 10292 { 10293 switch (codec->core.subsystem_id) { 10294 case 0x11020033: 10295 codec->fixup_id = QUIRK_ZXR; 10296 break; 10297 case 0x1102003f: 10298 codec->fixup_id = QUIRK_ZXR_DBPRO; 10299 break; 10300 default: 10301 codec->fixup_id = QUIRK_SBZ; 10302 break; 10303 } 10304 } 10305 10306 static void ca0132_generic_init_hook(struct hda_codec *codec) 10307 { 10308 struct ca0132_spec *spec = codec->spec; 10309 10310 snd_hda_sequence_write(codec, spec->spec_init_verbs); 10311 } 10312 10313 static int ca0132_generic_probe(struct hda_codec *codec) 10314 { 10315 struct ca0132_spec *spec = codec->spec; 10316 struct auto_pin_cfg *cfg = &spec->gen.autocfg; 10317 int err; 10318 10319 snd_hda_gen_spec_init(&spec->gen); 10320 10321 snd_hda_apply_pincfgs(codec, ca0132_generic_pincfgs); 10322 10323 ca0132_init_chip(codec); 10324 10325 err = ca0132_prepare_verbs(codec); 10326 if (err < 0) 10327 return err; 10328 10329 err = snd_hda_parse_pin_def_config(codec, cfg, NULL); 10330 if (err < 0) 10331 return err; 10332 err = snd_hda_gen_parse_auto_config(codec, cfg); 10333 if (err < 0) 10334 return err; 10335 10336 spec->gen.init_hook = ca0132_generic_init_hook; 10337 spec->gen.automute_speaker = 0; 10338 spec->gen.automute_lo = 0; 10339 10340 snd_hda_sequence_write(codec, spec->spec_init_verbs); 10341 return 0; 10342 } 10343 10344 static void ca0132_codec_remove(struct hda_codec *codec) 10345 { 10346 struct ca0132_spec *spec = codec->spec; 10347 10348 switch (ca0132_quirk(spec)) { 10349 case QUIRK_GENERIC: 10350 snd_hda_gen_remove(codec); 10351 return; 10352 case QUIRK_ZXR_DBPRO: 10353 return dbpro_free(codec); 10354 default: 10355 return ca0132_free(codec); 10356 } 10357 } 10358 10359 static int ca0132_codec_probe(struct hda_codec *codec, 10360 const struct hda_device_id *id) 10361 { 10362 struct ca0132_spec *spec; 10363 int err; 10364 10365 codec_dbg(codec, "%s\n", __func__); 10366 10367 spec = kzalloc_obj(*spec); 10368 if (!spec) 10369 return -ENOMEM; 10370 codec->spec = spec; 10371 spec->codec = codec; 10372 10373 /* These must be set before any path is taken */ 10374 codec->pcm_format_first = 1; 10375 codec->no_sticky_stream = 1; 10376 10377 /* Detect codec quirk */ 10378 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL); 10379 switch (ca0132_quirk(spec)) { 10380 case QUIRK_SBZ: 10381 sbz_detect_quirk(codec); 10382 break; 10383 case QUIRK_GENERIC: 10384 return ca0132_generic_probe(codec); 10385 default: 10386 break; 10387 } 10388 10389 spec->dsp_state = DSP_DOWNLOAD_INIT; 10390 spec->num_mixers = 1; 10391 10392 /* Set which mixers each quirk uses. */ 10393 switch (ca0132_quirk(spec)) { 10394 case QUIRK_SBZ: 10395 spec->mixers[0] = desktop_mixer; 10396 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10397 break; 10398 case QUIRK_ZXR: 10399 spec->mixers[0] = desktop_mixer; 10400 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10401 break; 10402 case QUIRK_ZXR_DBPRO: 10403 break; 10404 case QUIRK_R3D: 10405 spec->mixers[0] = desktop_mixer; 10406 snd_hda_codec_set_name(codec, "Recon3D"); 10407 break; 10408 case QUIRK_R3DI: 10409 spec->mixers[0] = r3di_mixer; 10410 snd_hda_codec_set_name(codec, "Recon3Di"); 10411 break; 10412 case QUIRK_AE5: 10413 spec->mixers[0] = desktop_mixer; 10414 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10415 break; 10416 case QUIRK_AE7: 10417 spec->mixers[0] = desktop_mixer; 10418 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10419 break; 10420 default: 10421 spec->mixers[0] = ca0132_mixer; 10422 break; 10423 } 10424 10425 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10426 switch (ca0132_quirk(spec)) { 10427 case QUIRK_SBZ: 10428 case QUIRK_R3D: 10429 case QUIRK_AE5: 10430 case QUIRK_AE7: 10431 case QUIRK_ZXR: 10432 spec->use_alt_controls = true; 10433 spec->use_alt_functions = true; 10434 spec->use_pci_mmio = true; 10435 break; 10436 case QUIRK_R3DI: 10437 spec->use_alt_controls = true; 10438 spec->use_alt_functions = true; 10439 spec->use_pci_mmio = false; 10440 break; 10441 default: 10442 spec->use_alt_controls = false; 10443 spec->use_alt_functions = false; 10444 spec->use_pci_mmio = false; 10445 break; 10446 } 10447 10448 #ifdef CONFIG_PCI 10449 if (spec->use_pci_mmio) { 10450 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10451 if (spec->mem_base == NULL) { 10452 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10453 codec->fixup_id = QUIRK_NONE; 10454 } 10455 } 10456 #endif 10457 10458 spec->base_init_verbs = ca0132_base_init_verbs; 10459 spec->base_exit_verbs = ca0132_base_exit_verbs; 10460 10461 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10462 10463 ca0132_init_chip(codec); 10464 10465 ca0132_config(codec); 10466 10467 err = ca0132_prepare_verbs(codec); 10468 if (err < 0) 10469 goto error; 10470 10471 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10472 if (err < 0) 10473 goto error; 10474 10475 ca0132_setup_unsol(codec); 10476 10477 return 0; 10478 10479 error: 10480 ca0132_codec_remove(codec); 10481 return err; 10482 } 10483 10484 static int ca0132_codec_build_controls(struct hda_codec *codec) 10485 { 10486 struct ca0132_spec *spec = codec->spec; 10487 10488 switch (ca0132_quirk(spec)) { 10489 case QUIRK_GENERIC: 10490 return snd_hda_gen_build_controls(codec); 10491 case QUIRK_ZXR_DBPRO: 10492 return dbpro_build_controls(codec); 10493 default: 10494 return ca0132_build_controls(codec); 10495 } 10496 } 10497 10498 static int ca0132_codec_build_pcms(struct hda_codec *codec) 10499 { 10500 struct ca0132_spec *spec = codec->spec; 10501 10502 switch (ca0132_quirk(spec)) { 10503 case QUIRK_GENERIC: 10504 return snd_hda_gen_build_pcms(codec); 10505 case QUIRK_ZXR_DBPRO: 10506 return dbpro_build_pcms(codec); 10507 default: 10508 return ca0132_build_pcms(codec); 10509 } 10510 } 10511 10512 static int ca0132_codec_init(struct hda_codec *codec) 10513 { 10514 struct ca0132_spec *spec = codec->spec; 10515 10516 switch (ca0132_quirk(spec)) { 10517 case QUIRK_GENERIC: 10518 return snd_hda_gen_init(codec); 10519 case QUIRK_ZXR_DBPRO: 10520 return dbpro_init(codec); 10521 default: 10522 return ca0132_init(codec); 10523 } 10524 } 10525 10526 static int ca0132_codec_suspend(struct hda_codec *codec) 10527 { 10528 struct ca0132_spec *spec = codec->spec; 10529 10530 if (ca0132_quirk(spec) == QUIRK_GENERIC) 10531 return 0; 10532 10533 cancel_delayed_work_sync(&spec->unsol_hp_work); 10534 return 0; 10535 } 10536 10537 static const struct hda_codec_ops ca0132_codec_ops = { 10538 .probe = ca0132_codec_probe, 10539 .remove = ca0132_codec_remove, 10540 .build_controls = ca0132_codec_build_controls, 10541 .build_pcms = ca0132_codec_build_pcms, 10542 .init = ca0132_codec_init, 10543 .unsol_event = snd_hda_jack_unsol_event, 10544 .suspend = ca0132_codec_suspend, 10545 }; 10546 10547 /* 10548 * driver entries 10549 */ 10550 static const struct hda_device_id snd_hda_id_ca0132[] = { 10551 HDA_CODEC_ID(0x11020011, "CA0132"), 10552 {} /* terminator */ 10553 }; 10554 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10555 10556 MODULE_LICENSE("GPL"); 10557 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10558 10559 static struct hda_codec_driver ca0132_driver = { 10560 .id = snd_hda_id_ca0132, 10561 .ops = &ca0132_codec_ops, 10562 }; 10563 10564 module_hda_codec_driver(ca0132_driver); 10565