1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SWSMU_CODE_LAYER_L3
29
30 #include "amdgpu.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v14_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "amdgpu_ras.h"
39 #include "smu_cmn.h"
40
41 #include "asic_reg/thm/thm_14_0_2_offset.h"
42 #include "asic_reg/thm/thm_14_0_2_sh_mask.h"
43 #include "asic_reg/mp/mp_14_0_2_offset.h"
44 #include "asic_reg/mp/mp_14_0_2_sh_mask.h"
45
46 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0 0x0341
47 #define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX 0
48 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 0x0342
49 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0
50
51 const int decoded_link_speed[5] = {1, 2, 3, 4, 5};
52 const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32};
53 /*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58 #undef pr_err
59 #undef pr_warn
60 #undef pr_info
61 #undef pr_debug
62
63 MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin");
64 MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin");
65 MODULE_FIRMWARE("amdgpu/smu_14_0_3_kicker.bin");
66
67 #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1
68
smu_v14_0_init_microcode(struct smu_context * smu)69 int smu_v14_0_init_microcode(struct smu_context *smu)
70 {
71 struct amdgpu_device *adev = smu->adev;
72 char ucode_prefix[30];
73 int err = 0;
74 const struct smc_firmware_header_v1_0 *hdr;
75 const struct common_firmware_header *header;
76 struct amdgpu_firmware_info *ucode = NULL;
77
78 /* doesn't need to load smu firmware in IOV mode */
79 if (amdgpu_sriov_vf(adev))
80 return 0;
81
82 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
83 if (amdgpu_is_kicker_fw(adev))
84 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
85 "amdgpu/%s_kicker.bin", ucode_prefix);
86 else
87 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
88 "amdgpu/%s.bin", ucode_prefix);
89 if (err)
90 goto out;
91
92 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
93 amdgpu_ucode_print_smc_hdr(&hdr->header);
94 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
95
96 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
97 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
98 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
99 ucode->fw = adev->pm.fw;
100 header = (const struct common_firmware_header *)ucode->fw->data;
101 adev->firmware.fw_size +=
102 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
103 }
104
105 out:
106 if (err)
107 amdgpu_ucode_release(&adev->pm.fw);
108 return err;
109 }
110
smu_v14_0_fini_microcode(struct smu_context * smu)111 void smu_v14_0_fini_microcode(struct smu_context *smu)
112 {
113 struct amdgpu_device *adev = smu->adev;
114
115 amdgpu_ucode_release(&adev->pm.fw);
116 adev->pm.fw_version = 0;
117 }
118
smu_v14_0_load_microcode(struct smu_context * smu)119 int smu_v14_0_load_microcode(struct smu_context *smu)
120 {
121 struct amdgpu_device *adev = smu->adev;
122 const uint32_t *src;
123 const struct smc_firmware_header_v1_0 *hdr;
124 uint32_t addr_start = MP1_SRAM;
125 uint32_t i;
126 uint32_t smc_fw_size;
127 uint32_t mp1_fw_flags;
128
129 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
130 src = (const uint32_t *)(adev->pm.fw->data +
131 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
132 smc_fw_size = hdr->header.ucode_size_bytes;
133
134 for (i = 1; i < smc_fw_size/4 - 1; i++) {
135 WREG32_PCIE(addr_start, src[i]);
136 addr_start += 4;
137 }
138
139 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
140 1 & MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
141 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
142 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
143
144 for (i = 0; i < adev->usec_timeout; i++) {
145 if (smu->is_apu)
146 mp1_fw_flags = RREG32_PCIE(MP1_Public |
147 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
148 else
149 mp1_fw_flags = RREG32_PCIE(MP1_Public |
150 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
151 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
152 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
153 break;
154 udelay(1);
155 }
156
157 if (i == adev->usec_timeout)
158 return -ETIME;
159
160 return 0;
161 }
162
smu_v14_0_init_pptable_microcode(struct smu_context * smu)163 int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
164 {
165 struct amdgpu_device *adev = smu->adev;
166 struct amdgpu_firmware_info *ucode = NULL;
167 uint32_t size = 0, pptable_id = 0;
168 int ret = 0;
169 void *table;
170
171 /* doesn't need to load smu firmware in IOV mode */
172 if (amdgpu_sriov_vf(adev))
173 return 0;
174
175 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
176 return 0;
177
178 if (!adev->scpm_enabled)
179 return 0;
180
181 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) ||
182 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3)))
183 return 0;
184
185 /* override pptable_id from driver parameter */
186 if (amdgpu_smu_pptable_id >= 0) {
187 pptable_id = amdgpu_smu_pptable_id;
188 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
189 } else {
190 pptable_id = smu->smu_table.boot_values.pp_table_id;
191 }
192
193 /* "pptable_id == 0" means vbios carries the pptable. */
194 if (!pptable_id)
195 return 0;
196
197 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
198 if (ret)
199 return ret;
200
201 smu->pptable_firmware.data = table;
202 smu->pptable_firmware.size = size;
203
204 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
205 ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
206 ucode->fw = &smu->pptable_firmware;
207 adev->firmware.fw_size +=
208 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
209
210 return 0;
211 }
212
smu_v14_0_check_fw_status(struct smu_context * smu)213 int smu_v14_0_check_fw_status(struct smu_context *smu)
214 {
215 struct amdgpu_device *adev = smu->adev;
216 uint32_t mp1_fw_flags;
217
218 if (smu->is_apu)
219 mp1_fw_flags = RREG32_PCIE(MP1_Public |
220 (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
221 else
222 mp1_fw_flags = RREG32_PCIE(MP1_Public |
223 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
224
225 if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
226 MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
227 return 0;
228
229 return -EIO;
230 }
231
smu_v14_0_check_fw_version(struct smu_context * smu)232 int smu_v14_0_check_fw_version(struct smu_context *smu)
233 {
234 struct amdgpu_device *adev = smu->adev;
235 uint32_t if_version = 0xff, smu_version = 0xff;
236 uint8_t smu_program, smu_major, smu_minor, smu_debug;
237 int ret = 0;
238
239 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
240 if (ret)
241 return ret;
242
243 smu_program = (smu_version >> 24) & 0xff;
244 smu_major = (smu_version >> 16) & 0xff;
245 smu_minor = (smu_version >> 8) & 0xff;
246 smu_debug = (smu_version >> 0) & 0xff;
247 if (smu->is_apu)
248 adev->pm.fw_version = smu_version;
249
250 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
251 case IP_VERSION(14, 0, 0):
252 case IP_VERSION(14, 0, 4):
253 case IP_VERSION(14, 0, 5):
254 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;
255 break;
256 case IP_VERSION(14, 0, 1):
257 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;
258 break;
259 case IP_VERSION(14, 0, 2):
260 case IP_VERSION(14, 0, 3):
261 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_2;
262 break;
263 default:
264 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
265 amdgpu_ip_version(adev, MP1_HWIP, 0));
266 smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_INV;
267 break;
268 }
269
270 if (adev->pm.fw)
271 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
272 smu_program, smu_version, smu_major, smu_minor, smu_debug);
273
274 /*
275 * 1. if_version mismatch is not critical as our fw is designed
276 * to be backward compatible.
277 * 2. New fw usually brings some optimizations. But that's visible
278 * only on the paired driver.
279 * Considering above, we just leave user a verbal message instead
280 * of halt driver loading.
281 */
282 if (if_version != smu->smc_driver_if_version) {
283 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
284 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
285 smu->smc_driver_if_version, if_version,
286 smu_program, smu_version, smu_major, smu_minor, smu_debug);
287 dev_info(adev->dev, "SMU driver if version not matched\n");
288 }
289
290 return ret;
291 }
292
smu_v14_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)293 static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
294 {
295 struct amdgpu_device *adev = smu->adev;
296 uint32_t ppt_offset_bytes;
297 const struct smc_firmware_header_v2_0 *v2;
298
299 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
300
301 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
302 *size = le32_to_cpu(v2->ppt_size_bytes);
303 *table = (uint8_t *)v2 + ppt_offset_bytes;
304
305 return 0;
306 }
307
smu_v14_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)308 static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
309 uint32_t *size, uint32_t pptable_id)
310 {
311 struct amdgpu_device *adev = smu->adev;
312 const struct smc_firmware_header_v2_1 *v2_1;
313 struct smc_soft_pptable_entry *entries;
314 uint32_t pptable_count = 0;
315 int i = 0;
316
317 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
318 entries = (struct smc_soft_pptable_entry *)
319 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
320 pptable_count = le32_to_cpu(v2_1->pptable_count);
321 for (i = 0; i < pptable_count; i++) {
322 if (le32_to_cpu(entries[i].id) == pptable_id) {
323 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
324 *size = le32_to_cpu(entries[i].ppt_size_bytes);
325 break;
326 }
327 }
328
329 if (i == pptable_count)
330 return -EINVAL;
331
332 return 0;
333 }
334
smu_v14_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)335 static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
336 {
337 struct amdgpu_device *adev = smu->adev;
338 uint16_t atom_table_size;
339 uint8_t frev, crev;
340 int ret, index;
341
342 dev_info(adev->dev, "use vbios provided pptable\n");
343 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
344 powerplayinfo);
345
346 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
347 (uint8_t **)table);
348 if (ret)
349 return ret;
350
351 if (size)
352 *size = atom_table_size;
353
354 return 0;
355 }
356
smu_v14_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)357 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
358 void **table,
359 uint32_t *size,
360 uint32_t pptable_id)
361 {
362 const struct smc_firmware_header_v1_0 *hdr;
363 struct amdgpu_device *adev = smu->adev;
364 uint16_t version_major, version_minor;
365 int ret;
366
367 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
368 if (!hdr)
369 return -EINVAL;
370
371 dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
372
373 version_major = le16_to_cpu(hdr->header.header_version_major);
374 version_minor = le16_to_cpu(hdr->header.header_version_minor);
375 if (version_major != 2) {
376 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
377 version_major, version_minor);
378 return -EINVAL;
379 }
380
381 switch (version_minor) {
382 case 0:
383 ret = smu_v14_0_set_pptable_v2_0(smu, table, size);
384 break;
385 case 1:
386 ret = smu_v14_0_set_pptable_v2_1(smu, table, size, pptable_id);
387 break;
388 default:
389 ret = -EINVAL;
390 break;
391 }
392
393 return ret;
394 }
395
smu_v14_0_setup_pptable(struct smu_context * smu)396 int smu_v14_0_setup_pptable(struct smu_context *smu)
397 {
398 struct amdgpu_device *adev = smu->adev;
399 uint32_t size = 0, pptable_id = 0;
400 void *table;
401 int ret = 0;
402
403 /* override pptable_id from driver parameter */
404 if (amdgpu_smu_pptable_id >= 0) {
405 pptable_id = amdgpu_smu_pptable_id;
406 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
407 } else {
408 pptable_id = smu->smu_table.boot_values.pp_table_id;
409 }
410
411 /* force using vbios pptable in sriov mode */
412 if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
413 ret = smu_v14_0_get_pptable_from_vbios(smu, &table, &size);
414 else
415 ret = smu_v14_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
416
417 if (ret)
418 return ret;
419
420 if (!smu->smu_table.power_play_table)
421 smu->smu_table.power_play_table = table;
422 if (!smu->smu_table.power_play_table_size)
423 smu->smu_table.power_play_table_size = size;
424
425 return 0;
426 }
427
smu_v14_0_init_smc_tables(struct smu_context * smu)428 int smu_v14_0_init_smc_tables(struct smu_context *smu)
429 {
430 struct smu_table_context *smu_table = &smu->smu_table;
431 struct smu_table *tables = smu_table->tables;
432 int ret = 0;
433
434 smu_table->driver_pptable =
435 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
436 if (!smu_table->driver_pptable) {
437 ret = -ENOMEM;
438 goto err0_out;
439 }
440
441 smu_table->max_sustainable_clocks =
442 kzalloc_obj(struct smu_14_0_max_sustainable_clocks);
443 if (!smu_table->max_sustainable_clocks) {
444 ret = -ENOMEM;
445 goto err1_out;
446 }
447
448 if (tables[SMU_TABLE_OVERDRIVE].size) {
449 smu_table->overdrive_table =
450 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
451 if (!smu_table->overdrive_table) {
452 ret = -ENOMEM;
453 goto err2_out;
454 }
455
456 smu_table->boot_overdrive_table =
457 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
458 if (!smu_table->boot_overdrive_table) {
459 ret = -ENOMEM;
460 goto err3_out;
461 }
462
463 smu_table->user_overdrive_table =
464 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
465 if (!smu_table->user_overdrive_table) {
466 ret = -ENOMEM;
467 goto err4_out;
468 }
469 }
470
471 smu_table->combo_pptable =
472 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
473 if (!smu_table->combo_pptable) {
474 ret = -ENOMEM;
475 goto err5_out;
476 }
477
478 return 0;
479
480 err5_out:
481 kfree(smu_table->user_overdrive_table);
482 err4_out:
483 kfree(smu_table->boot_overdrive_table);
484 err3_out:
485 kfree(smu_table->overdrive_table);
486 err2_out:
487 kfree(smu_table->max_sustainable_clocks);
488 err1_out:
489 kfree(smu_table->driver_pptable);
490 err0_out:
491 return ret;
492 }
493
smu_v14_0_fini_smc_tables(struct smu_context * smu)494 int smu_v14_0_fini_smc_tables(struct smu_context *smu)
495 {
496 struct smu_table_context *smu_table = &smu->smu_table;
497 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
498
499 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
500 kfree(smu_table->combo_pptable);
501 kfree(smu_table->boot_overdrive_table);
502 kfree(smu_table->overdrive_table);
503 kfree(smu_table->max_sustainable_clocks);
504 kfree(smu_table->driver_pptable);
505 smu_table->combo_pptable = NULL;
506 smu_table->boot_overdrive_table = NULL;
507 smu_table->overdrive_table = NULL;
508 smu_table->max_sustainable_clocks = NULL;
509 smu_table->driver_pptable = NULL;
510 kfree(smu_table->hardcode_pptable);
511 smu_table->hardcode_pptable = NULL;
512
513 kfree(smu_table->ecc_table);
514 kfree(smu_table->metrics_table);
515 kfree(smu_table->watermarks_table);
516 smu_table->ecc_table = NULL;
517 smu_table->metrics_table = NULL;
518 smu_table->watermarks_table = NULL;
519 smu_table->metrics_time = 0;
520
521 kfree(smu_dpm->dpm_context);
522 kfree(smu_dpm->golden_dpm_context);
523 kfree(smu_dpm->dpm_current_power_state);
524 kfree(smu_dpm->dpm_request_power_state);
525 smu_dpm->dpm_context = NULL;
526 smu_dpm->golden_dpm_context = NULL;
527 smu_dpm->dpm_context_size = 0;
528 smu_dpm->dpm_current_power_state = NULL;
529 smu_dpm->dpm_request_power_state = NULL;
530
531 return 0;
532 }
533
smu_v14_0_init_power(struct smu_context * smu)534 int smu_v14_0_init_power(struct smu_context *smu)
535 {
536 struct smu_power_context *smu_power = &smu->smu_power;
537
538 if (smu_power->power_context || smu_power->power_context_size != 0)
539 return -EINVAL;
540
541 smu_power->power_context = kzalloc_obj(struct smu_14_0_dpm_context);
542 if (!smu_power->power_context)
543 return -ENOMEM;
544 smu_power->power_context_size = sizeof(struct smu_14_0_dpm_context);
545
546 return 0;
547 }
548
smu_v14_0_fini_power(struct smu_context * smu)549 int smu_v14_0_fini_power(struct smu_context *smu)
550 {
551 struct smu_power_context *smu_power = &smu->smu_power;
552
553 if (!smu_power->power_context || smu_power->power_context_size == 0)
554 return -EINVAL;
555
556 kfree(smu_power->power_context);
557 smu_power->power_context = NULL;
558 smu_power->power_context_size = 0;
559
560 return 0;
561 }
562
smu_v14_0_get_vbios_bootup_values(struct smu_context * smu)563 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
564 {
565 int ret, index;
566 uint16_t size;
567 uint8_t frev, crev;
568 struct atom_common_table_header *header;
569 struct atom_firmware_info_v3_4 *v_3_4;
570 struct atom_firmware_info_v3_3 *v_3_3;
571 struct atom_firmware_info_v3_1 *v_3_1;
572 struct atom_smu_info_v3_6 *smu_info_v3_6;
573 struct atom_smu_info_v4_0 *smu_info_v4_0;
574
575 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
576 firmwareinfo);
577
578 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
579 (uint8_t **)&header);
580 if (ret)
581 return ret;
582
583 if (header->format_revision != 3) {
584 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu14\n");
585 return -EINVAL;
586 }
587
588 switch (header->content_revision) {
589 case 0:
590 case 1:
591 case 2:
592 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
593 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
594 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
595 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
596 smu->smu_table.boot_values.socclk = 0;
597 smu->smu_table.boot_values.dcefclk = 0;
598 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
599 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
600 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
601 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
602 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
603 smu->smu_table.boot_values.pp_table_id = 0;
604 break;
605 case 3:
606 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
607 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
608 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
609 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
610 smu->smu_table.boot_values.socclk = 0;
611 smu->smu_table.boot_values.dcefclk = 0;
612 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
613 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
614 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
615 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
616 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
617 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
618 break;
619 case 4:
620 default:
621 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
622 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
623 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
624 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
625 smu->smu_table.boot_values.socclk = 0;
626 smu->smu_table.boot_values.dcefclk = 0;
627 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
628 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
629 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
630 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
631 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
632 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
633 break;
634 }
635
636 smu->smu_table.boot_values.format_revision = header->format_revision;
637 smu->smu_table.boot_values.content_revision = header->content_revision;
638
639 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
640 smu_info);
641 if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
642 (uint8_t **)&header)) {
643
644 if ((frev == 3) && (crev == 6)) {
645 smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
646
647 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
648 smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
649 smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
650 smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
651 } else if ((frev == 3) && (crev == 1)) {
652 return 0;
653 } else if ((frev == 4) && (crev == 0)) {
654 smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
655
656 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
657 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
658 smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
659 smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
660 smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
661 } else {
662 dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
663 (uint32_t)frev, (uint32_t)crev);
664 }
665 }
666
667 return 0;
668 }
669
670
smu_v14_0_notify_memory_pool_location(struct smu_context * smu)671 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
672 {
673 struct smu_table_context *smu_table = &smu->smu_table;
674 struct smu_table *memory_pool = &smu_table->memory_pool;
675 int ret = 0;
676 uint64_t address;
677 uint32_t address_low, address_high;
678
679 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
680 return ret;
681
682 address = memory_pool->mc_address;
683 address_high = (uint32_t)upper_32_bits(address);
684 address_low = (uint32_t)lower_32_bits(address);
685
686 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
687 address_high, NULL);
688 if (ret)
689 return ret;
690 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
691 address_low, NULL);
692 if (ret)
693 return ret;
694 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
695 (uint32_t)memory_pool->size, NULL);
696 if (ret)
697 return ret;
698
699 return ret;
700 }
701
smu_v14_0_set_driver_table_location(struct smu_context * smu)702 int smu_v14_0_set_driver_table_location(struct smu_context *smu)
703 {
704 struct smu_table *driver_table = &smu->smu_table.driver_table;
705 int ret = 0;
706
707 if (driver_table->mc_address) {
708 ret = smu_cmn_send_smc_msg_with_param(smu,
709 SMU_MSG_SetDriverDramAddrHigh,
710 upper_32_bits(driver_table->mc_address),
711 NULL);
712 if (!ret)
713 ret = smu_cmn_send_smc_msg_with_param(smu,
714 SMU_MSG_SetDriverDramAddrLow,
715 lower_32_bits(driver_table->mc_address),
716 NULL);
717 }
718
719 return ret;
720 }
721
smu_v14_0_set_tool_table_location(struct smu_context * smu)722 int smu_v14_0_set_tool_table_location(struct smu_context *smu)
723 {
724 int ret = 0;
725 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
726
727 if (tool_table->mc_address) {
728 ret = smu_cmn_send_smc_msg_with_param(smu,
729 SMU_MSG_SetToolsDramAddrHigh,
730 upper_32_bits(tool_table->mc_address),
731 NULL);
732 if (!ret)
733 ret = smu_cmn_send_smc_msg_with_param(smu,
734 SMU_MSG_SetToolsDramAddrLow,
735 lower_32_bits(tool_table->mc_address),
736 NULL);
737 }
738
739 return ret;
740 }
741
smu_v14_0_set_allowed_mask(struct smu_context * smu)742 int smu_v14_0_set_allowed_mask(struct smu_context *smu)
743 {
744 struct smu_feature *feature = &smu->smu_feature;
745 int ret = 0;
746 uint32_t feature_mask[2];
747
748 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
749 feature->feature_num < SMU_FEATURE_NUM_DEFAULT)
750 return -EINVAL;
751
752 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
753
754 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
755 feature_mask[1], NULL);
756 if (ret)
757 return ret;
758
759 return smu_cmn_send_smc_msg_with_param(smu,
760 SMU_MSG_SetAllowedFeaturesMaskLow,
761 feature_mask[0],
762 NULL);
763 }
764
smu_v14_0_gfx_off_control(struct smu_context * smu,bool enable)765 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
766 {
767 int ret = 0;
768 struct amdgpu_device *adev = smu->adev;
769
770 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
771 case IP_VERSION(14, 0, 0):
772 case IP_VERSION(14, 0, 1):
773 case IP_VERSION(14, 0, 2):
774 case IP_VERSION(14, 0, 3):
775 case IP_VERSION(14, 0, 4):
776 case IP_VERSION(14, 0, 5):
777 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
778 return 0;
779 if (enable)
780 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
781 else
782 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
783 break;
784 default:
785 break;
786 }
787
788 return ret;
789 }
790
smu_v14_0_system_features_control(struct smu_context * smu,bool en)791 int smu_v14_0_system_features_control(struct smu_context *smu,
792 bool en)
793 {
794 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
795 SMU_MSG_DisableAllSmuFeatures), NULL);
796 }
797
smu_v14_0_notify_display_change(struct smu_context * smu)798 int smu_v14_0_notify_display_change(struct smu_context *smu)
799 {
800 int ret = 0;
801
802 if (!smu->pm_enabled)
803 return ret;
804
805 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
806 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
807 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
808
809 return ret;
810 }
811
smu_v14_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)812 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
813 uint32_t *power_limit)
814 {
815 int power_src;
816 int ret = 0;
817
818 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
819 return -EINVAL;
820
821 power_src = smu_cmn_to_asic_specific_index(smu,
822 CMN2ASIC_MAPPING_PWR,
823 smu->adev->pm.ac_power ?
824 SMU_POWER_SOURCE_AC :
825 SMU_POWER_SOURCE_DC);
826 if (power_src < 0)
827 return -EINVAL;
828
829 ret = smu_cmn_send_smc_msg_with_param(smu,
830 SMU_MSG_GetPptLimit,
831 power_src << 16,
832 power_limit);
833 if (ret)
834 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
835
836 return ret;
837 }
838
smu_v14_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)839 int smu_v14_0_set_power_limit(struct smu_context *smu,
840 enum smu_ppt_limit_type limit_type,
841 uint32_t limit)
842 {
843 int ret = 0;
844
845 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
846 return -EINVAL;
847
848 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
849 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
850 return -EOPNOTSUPP;
851 }
852
853 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
854 if (ret) {
855 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
856 return ret;
857 }
858
859 smu->current_power_limit = limit;
860
861 return 0;
862 }
863
smu_v14_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)864 static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
865 struct amdgpu_irq_src *source,
866 unsigned tyep,
867 enum amdgpu_interrupt_state state)
868 {
869 struct smu_context *smu = adev->powerplay.pp_handle;
870 uint32_t low, high;
871 uint32_t val = 0;
872
873 switch (state) {
874 case AMDGPU_IRQ_STATE_DISABLE:
875 /* For THM irqs */
876 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
877 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
878 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
879 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
880
881 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
882
883 /* For MP1 SW irqs */
884 if (smu->is_apu) {
885 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
886 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
887 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
888 } else {
889 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
890 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
891 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
892 }
893
894 break;
895 case AMDGPU_IRQ_STATE_ENABLE:
896 /* For THM irqs */
897 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
898 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
899 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
900 smu->thermal_range.software_shutdown_temp);
901 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
902 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
903 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
904 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
905 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
906 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
907 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
908 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
909 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
910
911 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
912 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
913 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
914 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
915
916 /* For MP1 SW irqs */
917 if (smu->is_apu) {
918 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
919 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
920 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
921 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0, val);
922
923 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
924 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
925 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
926 } else {
927 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
928 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
929 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
930 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
931
932 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
933 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
934 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
935 }
936
937 break;
938 default:
939 break;
940 }
941
942 return 0;
943 }
944
945 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
946 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
947
smu_v14_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)948 static int smu_v14_0_irq_process(struct amdgpu_device *adev,
949 struct amdgpu_irq_src *source,
950 struct amdgpu_iv_entry *entry)
951 {
952 struct smu_context *smu = adev->powerplay.pp_handle;
953 uint32_t client_id = entry->client_id;
954 uint32_t src_id = entry->src_id;
955
956 /*
957 * ctxid is used to distinguish different
958 * events for SMCToHost interrupt.
959 */
960 uint32_t ctxid = entry->src_data[0];
961 uint32_t data;
962 uint32_t high;
963
964 if (client_id == SOC15_IH_CLIENTID_THM) {
965 switch (src_id) {
966 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
967 schedule_delayed_work(&smu->swctf_delayed_work,
968 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
969 break;
970 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
971 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
972 break;
973 default:
974 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
975 src_id);
976 break;
977 }
978 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
979 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
980 /* ACK SMUToHost interrupt */
981 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
982 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
983 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
984
985 switch (ctxid) {
986 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL:
987 high = smu->thermal_range.software_shutdown_temp +
988 smu->thermal_range.software_shutdown_temp_offset;
989 high = min_t(typeof(high),
990 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
991 high);
992 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
993 high,
994 smu->thermal_range.software_shutdown_temp_offset);
995
996 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
997 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
998 DIG_THERM_INTH,
999 (high & 0xff));
1000 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1001 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1002 break;
1003 case SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY:
1004 high = min_t(typeof(high),
1005 SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1006 smu->thermal_range.software_shutdown_temp);
1007 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1008
1009 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1010 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1011 DIG_THERM_INTH,
1012 (high & 0xff));
1013 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1014 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1015 break;
1016 default:
1017 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1018 ctxid, client_id);
1019 break;
1020 }
1021 }
1022 }
1023
1024 return 0;
1025 }
1026
1027 static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = {
1028 .set = smu_v14_0_set_irq_state,
1029 .process = smu_v14_0_irq_process,
1030 };
1031
smu_v14_0_register_irq_handler(struct smu_context * smu)1032 int smu_v14_0_register_irq_handler(struct smu_context *smu)
1033 {
1034 struct amdgpu_device *adev = smu->adev;
1035 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1036 int ret = 0;
1037
1038 if (amdgpu_sriov_vf(adev))
1039 return 0;
1040
1041 irq_src->num_types = 1;
1042 irq_src->funcs = &smu_v14_0_irq_funcs;
1043
1044 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1045 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1046 irq_src);
1047 if (ret)
1048 return ret;
1049
1050 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1051 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1052 irq_src);
1053 if (ret)
1054 return ret;
1055
1056 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1057 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1058 irq_src);
1059 if (ret)
1060 return ret;
1061
1062 return ret;
1063 }
1064
smu_v14_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1065 static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
1066 uint64_t event_arg)
1067 {
1068 int ret = 0;
1069
1070 dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1071 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1072
1073 return ret;
1074 }
1075
smu_v14_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1076 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1077 uint64_t event_arg)
1078 {
1079 int ret = -EINVAL;
1080
1081 switch (event) {
1082 case SMU_EVENT_RESET_COMPLETE:
1083 ret = smu_v14_0_wait_for_reset_complete(smu, event_arg);
1084 break;
1085 default:
1086 break;
1087 }
1088
1089 return ret;
1090 }
1091
smu_v14_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1092 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1093 uint32_t *min, uint32_t *max)
1094 {
1095 int ret = 0, clk_id = 0;
1096 uint32_t param = 0;
1097 uint32_t clock_limit;
1098
1099 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1100 switch (clk_type) {
1101 case SMU_MCLK:
1102 case SMU_UCLK:
1103 clock_limit = smu->smu_table.boot_values.uclk;
1104 break;
1105 case SMU_GFXCLK:
1106 case SMU_SCLK:
1107 clock_limit = smu->smu_table.boot_values.gfxclk;
1108 break;
1109 case SMU_SOCCLK:
1110 clock_limit = smu->smu_table.boot_values.socclk;
1111 break;
1112 default:
1113 clock_limit = 0;
1114 break;
1115 }
1116
1117 /* clock in Mhz unit */
1118 if (min)
1119 *min = clock_limit / 100;
1120 if (max)
1121 *max = clock_limit / 100;
1122
1123 return 0;
1124 }
1125
1126 clk_id = smu_cmn_to_asic_specific_index(smu,
1127 CMN2ASIC_MAPPING_CLK,
1128 clk_type);
1129 if (clk_id < 0) {
1130 ret = -EINVAL;
1131 goto failed;
1132 }
1133 param = (clk_id & 0xffff) << 16;
1134
1135 if (max) {
1136 if (smu->adev->pm.ac_power)
1137 ret = smu_cmn_send_smc_msg_with_param(smu,
1138 SMU_MSG_GetMaxDpmFreq,
1139 param,
1140 max);
1141 else
1142 ret = smu_cmn_send_smc_msg_with_param(smu,
1143 SMU_MSG_GetDcModeMaxDpmFreq,
1144 param,
1145 max);
1146 if (ret)
1147 goto failed;
1148 }
1149
1150 if (min) {
1151 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1152 if (ret)
1153 goto failed;
1154 }
1155
1156 failed:
1157 return ret;
1158 }
1159
smu_v14_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1160 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
1161 enum smu_clk_type clk_type,
1162 uint32_t min,
1163 uint32_t max,
1164 bool automatic)
1165 {
1166 int ret = 0, clk_id = 0;
1167 uint32_t param;
1168
1169 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1170 return 0;
1171
1172 clk_id = smu_cmn_to_asic_specific_index(smu,
1173 CMN2ASIC_MAPPING_CLK,
1174 clk_type);
1175 if (clk_id < 0)
1176 return clk_id;
1177
1178 if (max > 0) {
1179 max = SMU_V14_SOFT_FREQ_ROUND(max);
1180 if (automatic)
1181 param = (uint32_t)((clk_id << 16) | 0xffff);
1182 else
1183 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1184 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1185 param, NULL);
1186 if (ret)
1187 goto out;
1188 }
1189
1190 if (min > 0) {
1191 if (automatic)
1192 param = (uint32_t)((clk_id << 16) | 0);
1193 else
1194 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1195 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1196 param, NULL);
1197 if (ret)
1198 goto out;
1199 }
1200
1201 out:
1202 return ret;
1203 }
1204
smu_v14_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1205 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
1206 enum smu_clk_type clk_type,
1207 uint32_t min,
1208 uint32_t max)
1209 {
1210 int ret = 0, clk_id = 0;
1211 uint32_t param;
1212
1213 if (min <= 0 && max <= 0)
1214 return -EINVAL;
1215
1216 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1217 return 0;
1218
1219 clk_id = smu_cmn_to_asic_specific_index(smu,
1220 CMN2ASIC_MAPPING_CLK,
1221 clk_type);
1222 if (clk_id < 0)
1223 return clk_id;
1224
1225 if (max > 0) {
1226 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1227 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1228 param, NULL);
1229 if (ret)
1230 return ret;
1231 }
1232
1233 if (min > 0) {
1234 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1235 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1236 param, NULL);
1237 if (ret)
1238 return ret;
1239 }
1240
1241 return ret;
1242 }
1243
smu_v14_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1244 int smu_v14_0_set_performance_level(struct smu_context *smu,
1245 enum amd_dpm_forced_level level)
1246 {
1247 struct smu_14_0_dpm_context *dpm_context =
1248 smu->smu_dpm.dpm_context;
1249 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1250 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1251 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1252 struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
1253 struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
1254 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
1255 struct smu_umd_pstate_table *pstate_table =
1256 &smu->pstate_table;
1257 struct amdgpu_device *adev = smu->adev;
1258 uint32_t sclk_min = 0, sclk_max = 0;
1259 uint32_t mclk_min = 0, mclk_max = 0;
1260 uint32_t socclk_min = 0, socclk_max = 0;
1261 uint32_t vclk_min = 0, vclk_max = 0;
1262 uint32_t dclk_min = 0, dclk_max = 0;
1263 uint32_t fclk_min = 0, fclk_max = 0;
1264 int ret = 0, i;
1265 bool auto_level = false;
1266
1267 switch (level) {
1268 case AMD_DPM_FORCED_LEVEL_HIGH:
1269 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1270 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1271 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1272 vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
1273 dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
1274 fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
1275 break;
1276 case AMD_DPM_FORCED_LEVEL_LOW:
1277 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
1278 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
1279 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
1280 vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table);
1281 dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table);
1282 fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table);
1283 break;
1284 case AMD_DPM_FORCED_LEVEL_AUTO:
1285 sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
1286 sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1287 mclk_min = SMU_DPM_TABLE_MIN(mem_table);
1288 mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1289 socclk_min = SMU_DPM_TABLE_MIN(soc_table);
1290 socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1291 vclk_min = SMU_DPM_TABLE_MIN(vclk_table);
1292 vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
1293 dclk_min = SMU_DPM_TABLE_MIN(dclk_table);
1294 dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
1295 fclk_min = SMU_DPM_TABLE_MIN(fclk_table);
1296 fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
1297 auto_level = true;
1298 break;
1299 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1300 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1301 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1302 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1303 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1304 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1305 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1306 break;
1307 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1308 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1309 break;
1310 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1311 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1312 break;
1313 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1314 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1315 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1316 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1317 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1318 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1319 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1320 break;
1321 case AMD_DPM_FORCED_LEVEL_MANUAL:
1322 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1323 return 0;
1324 default:
1325 dev_err(adev->dev, "Invalid performance level %d\n", level);
1326 return -EINVAL;
1327 }
1328
1329 if (sclk_min && sclk_max) {
1330 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1331 SMU_GFXCLK,
1332 sclk_min,
1333 sclk_max,
1334 auto_level);
1335 if (ret)
1336 return ret;
1337
1338 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1339 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1340 }
1341
1342 if (mclk_min && mclk_max) {
1343 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1344 SMU_MCLK,
1345 mclk_min,
1346 mclk_max,
1347 auto_level);
1348 if (ret)
1349 return ret;
1350
1351 pstate_table->uclk_pstate.curr.min = mclk_min;
1352 pstate_table->uclk_pstate.curr.max = mclk_max;
1353 }
1354
1355 if (socclk_min && socclk_max) {
1356 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1357 SMU_SOCCLK,
1358 socclk_min,
1359 socclk_max,
1360 auto_level);
1361 if (ret)
1362 return ret;
1363
1364 pstate_table->socclk_pstate.curr.min = socclk_min;
1365 pstate_table->socclk_pstate.curr.max = socclk_max;
1366 }
1367
1368 if (vclk_min && vclk_max) {
1369 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1370 if (adev->vcn.harvest_config & (1 << i))
1371 continue;
1372 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1373 i ? SMU_VCLK1 : SMU_VCLK,
1374 vclk_min,
1375 vclk_max,
1376 auto_level);
1377 if (ret)
1378 return ret;
1379 }
1380 pstate_table->vclk_pstate.curr.min = vclk_min;
1381 pstate_table->vclk_pstate.curr.max = vclk_max;
1382 }
1383
1384 if (dclk_min && dclk_max) {
1385 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1386 if (adev->vcn.harvest_config & (1 << i))
1387 continue;
1388 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1389 i ? SMU_DCLK1 : SMU_DCLK,
1390 dclk_min,
1391 dclk_max,
1392 auto_level);
1393 if (ret)
1394 return ret;
1395 }
1396 pstate_table->dclk_pstate.curr.min = dclk_min;
1397 pstate_table->dclk_pstate.curr.max = dclk_max;
1398 }
1399
1400 if (fclk_min && fclk_max) {
1401 ret = smu_v14_0_set_soft_freq_limited_range(smu,
1402 SMU_FCLK,
1403 fclk_min,
1404 fclk_max,
1405 auto_level);
1406 if (ret)
1407 return ret;
1408
1409 pstate_table->fclk_pstate.curr.min = fclk_min;
1410 pstate_table->fclk_pstate.curr.max = fclk_max;
1411 }
1412
1413 return ret;
1414 }
1415
smu_v14_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1416 int smu_v14_0_set_power_source(struct smu_context *smu,
1417 enum smu_power_src_type power_src)
1418 {
1419 int pwr_source;
1420
1421 pwr_source = smu_cmn_to_asic_specific_index(smu,
1422 CMN2ASIC_MAPPING_PWR,
1423 (uint32_t)power_src);
1424 if (pwr_source < 0)
1425 return -EINVAL;
1426
1427 return smu_cmn_send_smc_msg_with_param(smu,
1428 SMU_MSG_NotifyPowerSource,
1429 pwr_source,
1430 NULL);
1431 }
1432
smu_v14_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1433 static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
1434 enum smu_clk_type clk_type,
1435 uint16_t level,
1436 uint32_t *value)
1437 {
1438 int ret = 0, clk_id = 0;
1439 uint32_t param;
1440
1441 if (!value)
1442 return -EINVAL;
1443
1444 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1445 return 0;
1446
1447 clk_id = smu_cmn_to_asic_specific_index(smu,
1448 CMN2ASIC_MAPPING_CLK,
1449 clk_type);
1450 if (clk_id < 0)
1451 return clk_id;
1452
1453 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1454
1455 ret = smu_cmn_send_smc_msg_with_param(smu,
1456 SMU_MSG_GetDpmFreqByIndex,
1457 param,
1458 value);
1459 if (ret)
1460 return ret;
1461
1462 *value = *value & 0x7fffffff;
1463
1464 return ret;
1465 }
1466
smu_v14_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1467 static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
1468 enum smu_clk_type clk_type,
1469 uint32_t *value)
1470 {
1471 int ret;
1472
1473 ret = smu_v14_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1474
1475 return ret;
1476 }
1477
smu_v14_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1478 static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
1479 enum smu_clk_type clk_type,
1480 bool *is_fine_grained_dpm)
1481 {
1482 int ret = 0, clk_id = 0;
1483 uint32_t param;
1484 uint32_t value;
1485
1486 if (!is_fine_grained_dpm)
1487 return -EINVAL;
1488
1489 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1490 return 0;
1491
1492 clk_id = smu_cmn_to_asic_specific_index(smu,
1493 CMN2ASIC_MAPPING_CLK,
1494 clk_type);
1495 if (clk_id < 0)
1496 return clk_id;
1497
1498 param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1499
1500 ret = smu_cmn_send_smc_msg_with_param(smu,
1501 SMU_MSG_GetDpmFreqByIndex,
1502 param,
1503 &value);
1504 if (ret)
1505 return ret;
1506
1507 /*
1508 * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM
1509 * now, we un-support it
1510 */
1511 *is_fine_grained_dpm = value & 0x80000000;
1512
1513 return 0;
1514 }
1515
smu_v14_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_dpm_table * single_dpm_table)1516 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
1517 enum smu_clk_type clk_type,
1518 struct smu_dpm_table *single_dpm_table)
1519 {
1520 int ret = 0;
1521 uint32_t clk;
1522 int i;
1523 bool is_fine_grained;
1524
1525 ret = smu_v14_0_get_dpm_level_count(smu,
1526 clk_type,
1527 &single_dpm_table->count);
1528 if (ret) {
1529 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1530 return ret;
1531 }
1532
1533 ret = smu_v14_0_get_fine_grained_status(smu, clk_type,
1534 &is_fine_grained);
1535 if (ret) {
1536 dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1537 return ret;
1538 }
1539 if (is_fine_grained)
1540 single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
1541
1542 for (i = 0; i < single_dpm_table->count; i++) {
1543 ret = smu_v14_0_get_dpm_freq_by_index(smu,
1544 clk_type,
1545 i,
1546 &clk);
1547 if (ret) {
1548 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1549 return ret;
1550 }
1551
1552 single_dpm_table->dpm_levels[i].value = clk;
1553 single_dpm_table->dpm_levels[i].enabled = true;
1554 }
1555
1556 return 0;
1557 }
1558
smu_v14_0_set_vcn_enable(struct smu_context * smu,bool enable,int inst)1559 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
1560 bool enable,
1561 int inst)
1562 {
1563 struct amdgpu_device *adev = smu->adev;
1564 int ret = 0;
1565
1566 if (adev->vcn.harvest_config & (1 << inst))
1567 return ret;
1568
1569 if (smu->is_apu) {
1570 if (inst == 0)
1571 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1572 SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
1573 inst << 16U, NULL);
1574 else if (inst == 1)
1575 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1576 SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
1577 inst << 16U, NULL);
1578 } else {
1579 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1580 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1581 inst << 16U, NULL);
1582 }
1583
1584 return ret;
1585 }
1586
smu_v14_0_set_jpeg_enable(struct smu_context * smu,bool enable)1587 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
1588 bool enable)
1589 {
1590 struct amdgpu_device *adev = smu->adev;
1591 int i, ret = 0;
1592
1593 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
1594 if (adev->jpeg.harvest_config & (1 << i))
1595 continue;
1596
1597 if (smu->is_apu) {
1598 if (i == 0)
1599 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1600 SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,
1601 i << 16U, NULL);
1602 else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1603 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1604 SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1,
1605 i << 16U, NULL);
1606 } else {
1607 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1608 SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1609 i << 16U, NULL);
1610 }
1611
1612 if (ret)
1613 return ret;
1614 }
1615
1616 return ret;
1617 }
1618
smu_v14_0_run_btc(struct smu_context * smu)1619 int smu_v14_0_run_btc(struct smu_context *smu)
1620 {
1621 int res;
1622
1623 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1624 if (res)
1625 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
1626
1627 return res;
1628 }
1629
smu_v14_0_gpo_control(struct smu_context * smu,bool enablement)1630 int smu_v14_0_gpo_control(struct smu_context *smu,
1631 bool enablement)
1632 {
1633 int res;
1634
1635 res = smu_cmn_send_smc_msg_with_param(smu,
1636 SMU_MSG_AllowGpo,
1637 enablement ? 1 : 0,
1638 NULL);
1639 if (res)
1640 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
1641
1642 return res;
1643 }
1644
smu_v14_0_deep_sleep_control(struct smu_context * smu,bool enablement)1645 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
1646 bool enablement)
1647 {
1648 struct amdgpu_device *adev = smu->adev;
1649 int ret = 0;
1650
1651 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
1652 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
1653 if (ret) {
1654 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
1655 return ret;
1656 }
1657 }
1658
1659 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
1660 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
1661 if (ret) {
1662 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
1663 return ret;
1664 }
1665 }
1666
1667 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
1668 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
1669 if (ret) {
1670 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
1671 return ret;
1672 }
1673 }
1674
1675 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
1676 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
1677 if (ret) {
1678 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
1679 return ret;
1680 }
1681 }
1682
1683 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
1684 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
1685 if (ret) {
1686 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
1687 return ret;
1688 }
1689 }
1690
1691 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
1692 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
1693 if (ret) {
1694 dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
1695 return ret;
1696 }
1697 }
1698
1699 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
1700 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
1701 if (ret) {
1702 dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
1703 return ret;
1704 }
1705 }
1706
1707 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
1708 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
1709 if (ret) {
1710 dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
1711 return ret;
1712 }
1713 }
1714
1715 return ret;
1716 }
1717
smu_v14_0_gfx_ulv_control(struct smu_context * smu,bool enablement)1718 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
1719 bool enablement)
1720 {
1721 int ret = 0;
1722
1723 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
1724 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
1725
1726 return ret;
1727 }
1728
smu_v14_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1729 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
1730 enum smu_baco_seq baco_seq)
1731 {
1732 struct smu_baco_context *smu_baco = &smu->smu_baco;
1733 int ret;
1734
1735 ret = smu_cmn_send_smc_msg_with_param(smu,
1736 SMU_MSG_ArmD3,
1737 baco_seq,
1738 NULL);
1739 if (ret)
1740 return ret;
1741
1742 if (baco_seq == BACO_SEQ_BAMACO ||
1743 baco_seq == BACO_SEQ_BACO)
1744 smu_baco->state = SMU_BACO_STATE_ENTER;
1745 else
1746 smu_baco->state = SMU_BACO_STATE_EXIT;
1747
1748 return 0;
1749 }
1750
smu_v14_0_get_bamaco_support(struct smu_context * smu)1751 int smu_v14_0_get_bamaco_support(struct smu_context *smu)
1752 {
1753 struct smu_baco_context *smu_baco = &smu->smu_baco;
1754 int bamaco_support = 0;
1755
1756 if (amdgpu_sriov_vf(smu->adev) ||
1757 !smu_baco->platform_support)
1758 return 0;
1759
1760 if (smu_baco->maco_support)
1761 bamaco_support |= MACO_SUPPORT;
1762
1763 /* return true if ASIC is in BACO state already */
1764 if (smu_v14_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1765 return (bamaco_support |= BACO_SUPPORT);
1766
1767 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1768 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1769 return 0;
1770
1771 return (bamaco_support |= BACO_SUPPORT);
1772 }
1773
smu_v14_0_baco_get_state(struct smu_context * smu)1774 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
1775 {
1776 struct smu_baco_context *smu_baco = &smu->smu_baco;
1777
1778 return smu_baco->state;
1779 }
1780
smu_v14_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1781 int smu_v14_0_baco_set_state(struct smu_context *smu,
1782 enum smu_baco_state state)
1783 {
1784 struct smu_baco_context *smu_baco = &smu->smu_baco;
1785 struct amdgpu_device *adev = smu->adev;
1786 int ret = 0;
1787
1788 if (smu_v14_0_baco_get_state(smu) == state)
1789 return 0;
1790
1791 if (state == SMU_BACO_STATE_ENTER) {
1792 ret = smu_cmn_send_smc_msg_with_param(smu,
1793 SMU_MSG_EnterBaco,
1794 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ?
1795 BACO_SEQ_BAMACO : BACO_SEQ_BACO,
1796 NULL);
1797 } else {
1798 ret = smu_cmn_send_smc_msg(smu,
1799 SMU_MSG_ExitBaco,
1800 NULL);
1801 if (ret)
1802 return ret;
1803
1804 /* clear vbios scratch 6 and 7 for coming asic reinit */
1805 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1806 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1807 }
1808
1809 if (!ret)
1810 smu_baco->state = state;
1811
1812 return ret;
1813 }
1814
smu_v14_0_baco_enter(struct smu_context * smu)1815 int smu_v14_0_baco_enter(struct smu_context *smu)
1816 {
1817 int ret = 0;
1818
1819 ret = smu_v14_0_baco_set_state(smu,
1820 SMU_BACO_STATE_ENTER);
1821 if (ret)
1822 return ret;
1823
1824 msleep(10);
1825
1826 return ret;
1827 }
1828
smu_v14_0_baco_exit(struct smu_context * smu)1829 int smu_v14_0_baco_exit(struct smu_context *smu)
1830 {
1831 return smu_v14_0_baco_set_state(smu,
1832 SMU_BACO_STATE_EXIT);
1833 }
1834
smu_v14_0_set_gfx_power_up_by_imu(struct smu_context * smu)1835 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
1836 {
1837 struct smu_msg_ctl *ctl = &smu->msg_ctl;
1838 struct amdgpu_device *adev = smu->adev;
1839 int ret;
1840
1841 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1842 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
1843 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
1844 }
1845
1846 mutex_lock(&ctl->lock);
1847 ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu,
1848 ENABLE_IMU_ARG_GFXOFF_ENABLE);
1849 mutex_unlock(&ctl->lock);
1850
1851 return ret;
1852 }
1853
smu_v14_0_set_default_dpm_tables(struct smu_context * smu)1854 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
1855 {
1856 struct smu_table_context *smu_table = &smu->smu_table;
1857
1858 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
1859 smu_table->clocks_table, false);
1860 }
1861
smu_v14_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1862 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
1863 enum PP_OD_DPM_TABLE_COMMAND type,
1864 long input[], uint32_t size)
1865 {
1866 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1867 int ret = 0;
1868
1869 /* Only allowed in manual mode */
1870 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1871 return -EINVAL;
1872
1873 switch (type) {
1874 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1875 if (size != 2) {
1876 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1877 return -EINVAL;
1878 }
1879
1880 if (input[0] == 0) {
1881 if (input[1] < smu->gfx_default_hard_min_freq) {
1882 dev_warn(smu->adev->dev,
1883 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1884 input[1], smu->gfx_default_hard_min_freq);
1885 return -EINVAL;
1886 }
1887 smu->gfx_actual_hard_min_freq = input[1];
1888 } else if (input[0] == 1) {
1889 if (input[1] > smu->gfx_default_soft_max_freq) {
1890 dev_warn(smu->adev->dev,
1891 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1892 input[1], smu->gfx_default_soft_max_freq);
1893 return -EINVAL;
1894 }
1895 smu->gfx_actual_soft_max_freq = input[1];
1896 } else {
1897 return -EINVAL;
1898 }
1899 break;
1900 case PP_OD_RESTORE_DEFAULT_TABLE:
1901 if (size != 0) {
1902 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1903 return -EINVAL;
1904 }
1905 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1906 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1907 break;
1908 case PP_OD_COMMIT_DPM_TABLE:
1909 if (size != 0) {
1910 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1911 return -EINVAL;
1912 }
1913 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1914 dev_err(smu->adev->dev,
1915 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1916 smu->gfx_actual_hard_min_freq,
1917 smu->gfx_actual_soft_max_freq);
1918 return -EINVAL;
1919 }
1920
1921 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1922 smu->gfx_actual_hard_min_freq,
1923 NULL);
1924 if (ret) {
1925 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1926 return ret;
1927 }
1928
1929 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1930 smu->gfx_actual_soft_max_freq,
1931 NULL);
1932 if (ret) {
1933 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1934 return ret;
1935 }
1936 if (smu->gfx_actual_hard_min_freq != smu->gfx_default_hard_min_freq ||
1937 smu->gfx_actual_soft_max_freq != smu->gfx_default_soft_max_freq)
1938 smu->user_dpm_profile.user_od = true;
1939 else
1940 smu->user_dpm_profile.user_od = false;
1941 break;
1942 default:
1943 return -ENOSYS;
1944 }
1945
1946 return ret;
1947 }
1948
smu_v14_0_allow_ih_interrupt(struct smu_context * smu)1949 static int smu_v14_0_allow_ih_interrupt(struct smu_context *smu)
1950 {
1951 return smu_cmn_send_smc_msg(smu,
1952 SMU_MSG_AllowIHHostInterrupt,
1953 NULL);
1954 }
1955
smu_v14_0_enable_thermal_alert(struct smu_context * smu)1956 int smu_v14_0_enable_thermal_alert(struct smu_context *smu)
1957 {
1958 int ret = 0;
1959
1960 if (!smu->irq_source.num_types)
1961 return 0;
1962
1963 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1964 if (ret)
1965 return ret;
1966
1967 return smu_v14_0_allow_ih_interrupt(smu);
1968 }
1969
smu_v14_0_disable_thermal_alert(struct smu_context * smu)1970 int smu_v14_0_disable_thermal_alert(struct smu_context *smu)
1971 {
1972 if (!smu->irq_source.num_types)
1973 return 0;
1974
1975 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1976 }
1977