1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file implements dp specific link capability retrieval sequence. It is 28 * responsible for retrieving, parsing, overriding, deciding capability obtained 29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers, 30 * usb and all other possible backend capabilities. Other components should 31 * include this header file in order to access link capability. Accessing link 32 * capability by dereferencing dc_link outside dp_link_capability is not a 33 * recommended method as it makes the component dependent on the underlying data 34 * structure used to represent link capability instead of function interfaces. 35 */ 36 37 #include "link_dp_capability.h" 38 #include "link_ddc.h" 39 #include "link_dpcd.h" 40 #include "link_dp_dpia.h" 41 #include "link_dp_phy.h" 42 #include "link_edp_panel_control.h" 43 #include "link_dp_irq_handler.h" 44 #include "link/accessories/link_dp_trace.h" 45 #include "link/link_detection.h" 46 #include "link/link_validation.h" 47 #include "link_dp_training.h" 48 #include "atomfirmware.h" 49 #include "resource.h" 50 #include "link_enc_cfg.h" 51 #include "dc_dmub_srv.h" 52 #include "gpio_service_interface.h" 53 54 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 55 56 #define DC_LOGGER \ 57 link->ctx->logger 58 59 #ifndef MAX 60 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) 61 #endif 62 #ifndef MIN 63 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 64 #endif 65 66 struct dp_lt_fallback_entry { 67 enum dc_lane_count lane_count; 68 enum dc_link_rate link_rate; 69 }; 70 71 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = { 72 /* This link training fallback array is ordered by 73 * link bandwidth from highest to lowest. 74 * DP specs makes it a normative policy to always 75 * choose the next highest link bandwidth during 76 * link training fallback. 77 */ 78 {LANE_COUNT_FOUR, LINK_RATE_UHBR20}, 79 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5}, 80 {LANE_COUNT_TWO, LINK_RATE_UHBR20}, 81 {LANE_COUNT_FOUR, LINK_RATE_UHBR10}, 82 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5}, 83 {LANE_COUNT_FOUR, LINK_RATE_HIGH3}, 84 {LANE_COUNT_ONE, LINK_RATE_UHBR20}, 85 {LANE_COUNT_TWO, LINK_RATE_UHBR10}, 86 {LANE_COUNT_FOUR, LINK_RATE_HIGH2}, 87 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5}, 88 {LANE_COUNT_TWO, LINK_RATE_HIGH3}, 89 {LANE_COUNT_ONE, LINK_RATE_UHBR10}, 90 {LANE_COUNT_TWO, LINK_RATE_HIGH2}, 91 {LANE_COUNT_FOUR, LINK_RATE_HIGH}, 92 {LANE_COUNT_ONE, LINK_RATE_HIGH3}, 93 {LANE_COUNT_FOUR, LINK_RATE_LOW}, 94 {LANE_COUNT_ONE, LINK_RATE_HIGH2}, 95 {LANE_COUNT_TWO, LINK_RATE_HIGH}, 96 {LANE_COUNT_TWO, LINK_RATE_LOW}, 97 {LANE_COUNT_ONE, LINK_RATE_HIGH}, 98 {LANE_COUNT_ONE, LINK_RATE_LOW}, 99 }; 100 101 static const struct dc_link_settings fail_safe_link_settings = { 102 .lane_count = LANE_COUNT_ONE, 103 .link_rate = LINK_RATE_LOW, 104 .link_spread = LINK_SPREAD_DISABLED, 105 }; 106 107 bool is_dp_active_dongle(const struct dc_link *link) 108 { 109 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && 110 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); 111 } 112 113 bool is_dp_branch_device(const struct dc_link *link) 114 { 115 return link->dpcd_caps.is_branch_dev; 116 } 117 118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc) 119 { 120 switch (bpc) { 121 case DOWN_STREAM_MAX_8BPC: 122 return 8; 123 case DOWN_STREAM_MAX_10BPC: 124 return 10; 125 case DOWN_STREAM_MAX_12BPC: 126 return 12; 127 case DOWN_STREAM_MAX_16BPC: 128 return 16; 129 default: 130 break; 131 } 132 133 return -1; 134 } 135 136 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) 137 { 138 switch (lttpr_repeater_count) { 139 case 0x80: // 1 lttpr repeater 140 return 1; 141 case 0x40: // 2 lttpr repeaters 142 return 2; 143 case 0x20: // 3 lttpr repeaters 144 return 3; 145 case 0x10: // 4 lttpr repeaters 146 return 4; 147 case 0x08: // 5 lttpr repeaters 148 return 5; 149 case 0x04: // 6 lttpr repeaters 150 return 6; 151 case 0x02: // 7 lttpr repeaters 152 return 7; 153 case 0x01: // 8 lttpr repeaters 154 return 8; 155 default: 156 break; 157 } 158 return 0; // invalid value 159 } 160 161 uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) 162 { 163 /* Calculate offset for LTTPR closest to DPTX which is highest in the chain 164 * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 165 */ 166 return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); 167 } 168 169 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) 170 { 171 switch (bw) { 172 case 0b001: 173 return 9000000; 174 case 0b010: 175 return 18000000; 176 case 0b011: 177 return 24000000; 178 case 0b100: 179 return 32000000; 180 case 0b101: 181 return 40000000; 182 case 0b110: 183 return 48000000; 184 } 185 186 return 0; 187 } 188 189 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) 190 { 191 enum dc_link_rate link_rate; 192 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. 193 switch (link_rate_in_khz) { 194 case 1620000: 195 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane 196 break; 197 case 2160000: 198 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane 199 break; 200 case 2430000: 201 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane 202 break; 203 case 2700000: 204 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane 205 break; 206 case 3240000: 207 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane 208 break; 209 case 4320000: 210 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane 211 break; 212 case 5400000: 213 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane 214 break; 215 case 6750000: 216 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane 217 break; 218 case 8100000: 219 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane 220 break; 221 case 10000000: 222 link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane 223 break; 224 case 13500000: 225 link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane 226 break; 227 case 20000000: 228 link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane 229 break; 230 231 default: 232 link_rate = LINK_RATE_UNKNOWN; 233 break; 234 } 235 return link_rate; 236 } 237 238 static union dp_cable_id intersect_cable_id( 239 union dp_cable_id *a, union dp_cable_id *b) 240 { 241 union dp_cable_id out; 242 243 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY, 244 b->bits.UHBR10_20_CAPABILITY); 245 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY, 246 b->bits.UHBR13_5_CAPABILITY); 247 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE); 248 249 return out; 250 } 251 252 /* 253 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. 254 */ 255 static uint32_t intersect_frl_link_bw_support( 256 const uint32_t max_supported_frl_bw_in_kbps, 257 const union hdmi_encoded_link_bw hdmi_encoded_link_bw) 258 { 259 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps; 260 261 /* Skip checking FRL_MODE bit, as certain PCON will clear 262 * it despite supporting the link BW indicated in the other bits. 263 */ 264 if (hdmi_encoded_link_bw.bits.BW_48Gbps) 265 supported_bw_in_kbps = 48000000; 266 else if (hdmi_encoded_link_bw.bits.BW_40Gbps) 267 supported_bw_in_kbps = 40000000; 268 else if (hdmi_encoded_link_bw.bits.BW_32Gbps) 269 supported_bw_in_kbps = 32000000; 270 else if (hdmi_encoded_link_bw.bits.BW_24Gbps) 271 supported_bw_in_kbps = 24000000; 272 else if (hdmi_encoded_link_bw.bits.BW_18Gbps) 273 supported_bw_in_kbps = 18000000; 274 else if (hdmi_encoded_link_bw.bits.BW_9Gbps) 275 supported_bw_in_kbps = 9000000; 276 else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED) 277 supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */ 278 279 return supported_bw_in_kbps; 280 } 281 282 static enum clock_source_id get_clock_source_id(struct dc_link *link) 283 { 284 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED; 285 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; 286 287 if (dp_cs != NULL) { 288 dp_cs_id = dp_cs->id; 289 } else { 290 /* 291 * dp clock source is not initialized for some reason. 292 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used 293 */ 294 ASSERT(dp_cs); 295 } 296 297 return dp_cs_id; 298 } 299 300 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, 301 int length) 302 { 303 int retry = 0; 304 305 if (!link->dpcd_caps.dpcd_rev.raw) { 306 do { 307 dpcd_write_rx_power_ctrl(link, true); 308 core_link_read_dpcd(link, DP_DPCD_REV, 309 dpcd_data, length); 310 link->dpcd_caps.dpcd_rev.raw = dpcd_data[ 311 DP_DPCD_REV - 312 DP_DPCD_REV]; 313 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw); 314 } 315 316 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) { 317 switch (link->dpcd_caps.branch_dev_id) { 318 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down 319 * all internal circuits including AUX communication preventing 320 * reading DPCD table and EDID (spec violation). 321 * Encoder will skip DP RX power down on disable_output to 322 * keep receiver powered all the time.*/ 323 case DP_BRANCH_DEVICE_ID_0010FA: 324 case DP_BRANCH_DEVICE_ID_0080E1: 325 case DP_BRANCH_DEVICE_ID_00E04C: 326 link->wa_flags.dp_keep_receiver_powered = true; 327 break; 328 329 /* TODO: May need work around for other dongles. */ 330 default: 331 link->wa_flags.dp_keep_receiver_powered = false; 332 break; 333 } 334 } else 335 link->wa_flags.dp_keep_receiver_powered = false; 336 } 337 338 bool dp_is_fec_supported(const struct dc_link *link) 339 { 340 /* TODO - use asic cap instead of link_enc->features 341 * we no longer know which link enc to use for this link before commit 342 */ 343 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 344 struct resource_pool *res_pool = link->dc->res_pool; 345 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 346 347 if (!link->dc->config.unify_link_enc_assignment) 348 link_enc = link_enc_cfg_get_link_enc(link); 349 ASSERT(link_enc); 350 351 return (dc_is_dp_signal(link->connector_signal) && link_enc && 352 link_enc->features.fec_supported && 353 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE); 354 } 355 356 bool dp_should_enable_fec(const struct dc_link *link) 357 { 358 bool force_disable = false; 359 360 if (link->dc->debug.disable_fec) 361 force_disable = true; 362 else if (link->fec_state == dc_link_fec_enabled) 363 force_disable = false; 364 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST && 365 link->local_sink && 366 link->local_sink->edid_caps.panel_patch.disable_fec) 367 force_disable = true; 368 else if (link->connector_signal == SIGNAL_TYPE_EDP 369 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields. 370 dsc_support.DSC_SUPPORT == false 371 || link->panel_config.dsc.disable_dsc_edp 372 || !link->dc->caps.edp_dsc_support)) 373 force_disable = true; 374 375 return !force_disable && dp_is_fec_supported(link); 376 } 377 378 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx) 379 { 380 /* If this assert is hit then we have a link encoder dynamic management issue */ 381 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); 382 return (pipe_ctx->stream_res.hpo_dp_stream_enc && 383 pipe_ctx->link_res.hpo_dp_link_enc && 384 dc_is_dp_signal(pipe_ctx->stream->signal)); 385 } 386 387 bool dp_is_lttpr_present(struct dc_link *link) 388 { 389 /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */ 390 uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 391 bool is_lttpr_present = (lttpr_count > 0 && 392 link->dpcd_caps.lttpr_caps.max_lane_count > 0 && 393 link->dpcd_caps.lttpr_caps.max_lane_count <= 4); 394 395 if (lttpr_count > 0 && !is_lttpr_present) 396 DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n"); 397 398 return is_lttpr_present; 399 } 400 401 /* in DP compliance test, DPR-120 may have 402 * a random value in its MAX_LINK_BW dpcd field. 403 * We map it to the maximum supported link rate that 404 * is smaller than MAX_LINK_BW in this case. 405 */ 406 static enum dc_link_rate get_link_rate_from_max_link_bw( 407 uint8_t max_link_bw) 408 { 409 enum dc_link_rate link_rate; 410 411 if (max_link_bw >= LINK_RATE_HIGH3) { 412 link_rate = LINK_RATE_HIGH3; 413 } else if (max_link_bw < LINK_RATE_HIGH3 414 && max_link_bw >= LINK_RATE_HIGH2) { 415 link_rate = LINK_RATE_HIGH2; 416 } else if (max_link_bw < LINK_RATE_HIGH2 417 && max_link_bw >= LINK_RATE_HIGH) { 418 link_rate = LINK_RATE_HIGH; 419 } else if (max_link_bw < LINK_RATE_HIGH 420 && max_link_bw >= LINK_RATE_LOW) { 421 link_rate = LINK_RATE_LOW; 422 } else { 423 link_rate = LINK_RATE_UNKNOWN; 424 } 425 426 return link_rate; 427 } 428 429 static enum dc_lane_count get_lttpr_max_lane_count(struct dc_link *link) 430 { 431 enum dc_lane_count lttpr_max_lane_count = LANE_COUNT_UNKNOWN; 432 433 if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX) 434 lttpr_max_lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; 435 436 /* if bw_allocation is enabled and nrd_max_lane_count is set, use it */ 437 if (link->dpia_bw_alloc_config.bw_alloc_enabled && 438 link->dpia_bw_alloc_config.nrd_max_lane_count > 0) 439 lttpr_max_lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; 440 441 return lttpr_max_lane_count; 442 } 443 444 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) 445 { 446 447 enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN; 448 449 switch (link->dpcd_caps.lttpr_caps.max_link_rate) { 450 case LINK_RATE_LOW: 451 case LINK_RATE_HIGH: 452 case LINK_RATE_HIGH2: 453 case LINK_RATE_HIGH3: 454 lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate; 455 break; 456 } 457 458 /* if bw_allocation is enabled and nrd_max_link_rate is set, use it */ 459 if (link->dpia_bw_alloc_config.bw_alloc_enabled && 460 link->dpia_bw_alloc_config.nrd_max_link_rate > 0) 461 lttpr_max_link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate; 462 463 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20) 464 lttpr_max_link_rate = LINK_RATE_UHBR20; 465 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) 466 lttpr_max_link_rate = LINK_RATE_UHBR13_5; 467 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10) 468 lttpr_max_link_rate = LINK_RATE_UHBR10; 469 470 return lttpr_max_link_rate; 471 } 472 473 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) 474 { 475 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; 476 477 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) { 478 cable_max_link_rate = LINK_RATE_UHBR20; 479 } else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) { 480 cable_max_link_rate = LINK_RATE_UHBR13_5; 481 } else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) { 482 // allow DP40 cables to do UHBR13.5 for passive or unknown cable type 483 if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) { 484 cable_max_link_rate = LINK_RATE_UHBR13_5; 485 } else { 486 cable_max_link_rate = LINK_RATE_UHBR10; 487 } 488 } 489 490 return cable_max_link_rate; 491 } 492 493 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) 494 { 495 return lane_count <= LANE_COUNT_ONE; 496 } 497 498 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate) 499 { 500 return link_rate <= LINK_RATE_LOW; 501 } 502 503 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) 504 { 505 switch (lane_count) { 506 case LANE_COUNT_FOUR: 507 return LANE_COUNT_TWO; 508 case LANE_COUNT_TWO: 509 return LANE_COUNT_ONE; 510 case LANE_COUNT_ONE: 511 return LANE_COUNT_UNKNOWN; 512 default: 513 return LANE_COUNT_UNKNOWN; 514 } 515 } 516 517 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate) 518 { 519 // NEEDSWORK: provide some details about why this function never returns some of the 520 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended. 521 // 522 523 switch (link_rate) { 524 case LINK_RATE_UHBR20: 525 return LINK_RATE_UHBR13_5; 526 case LINK_RATE_UHBR13_5: 527 return LINK_RATE_UHBR10; 528 case LINK_RATE_UHBR10: 529 return LINK_RATE_HIGH3; 530 case LINK_RATE_HIGH3: 531 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5) 532 return LINK_RATE_RATE_8; 533 return LINK_RATE_HIGH2; 534 case LINK_RATE_RATE_8: 535 return LINK_RATE_HIGH2; 536 case LINK_RATE_HIGH2: 537 return LINK_RATE_HIGH; 538 case LINK_RATE_RATE_6: 539 case LINK_RATE_RBR2: 540 return LINK_RATE_HIGH; 541 case LINK_RATE_HIGH: 542 return LINK_RATE_LOW; 543 case LINK_RATE_RATE_3: 544 case LINK_RATE_RATE_2: 545 return LINK_RATE_LOW; 546 case LINK_RATE_LOW: 547 default: 548 return LINK_RATE_UNKNOWN; 549 } 550 } 551 552 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) 553 { 554 switch (lane_count) { 555 case LANE_COUNT_ONE: 556 return LANE_COUNT_TWO; 557 case LANE_COUNT_TWO: 558 return LANE_COUNT_FOUR; 559 default: 560 return LANE_COUNT_UNKNOWN; 561 } 562 } 563 564 static enum dc_link_rate increase_link_rate(struct dc_link *link, 565 enum dc_link_rate link_rate) 566 { 567 switch (link_rate) { 568 case LINK_RATE_LOW: 569 return LINK_RATE_HIGH; 570 case LINK_RATE_HIGH: 571 return LINK_RATE_HIGH2; 572 case LINK_RATE_HIGH2: 573 return LINK_RATE_HIGH3; 574 case LINK_RATE_HIGH3: 575 return LINK_RATE_UHBR10; 576 case LINK_RATE_UHBR10: 577 /* upto DP2.x specs UHBR13.5 is the only link rate that could be 578 * not supported by DPRX when higher link rate is supported. 579 * so we treat it as a special case for code simplicity. When we 580 * have new specs with more link rates like this, we should 581 * consider a more generic solution to handle discrete link 582 * rate capabilities. 583 */ 584 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ? 585 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20; 586 case LINK_RATE_UHBR13_5: 587 return LINK_RATE_UHBR20; 588 default: 589 return LINK_RATE_UNKNOWN; 590 } 591 } 592 593 static void increase_edp_link_rate(struct dc_link *link, 594 struct dc_link_settings *current_link_setting) 595 { 596 if (current_link_setting->use_link_rate_set) { 597 if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 598 current_link_setting->link_rate_set++; 599 current_link_setting->link_rate = 600 link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set]; 601 } else { 602 current_link_setting->use_link_rate_set = false; 603 current_link_setting->link_rate = LINK_RATE_UHBR10; 604 } 605 } else { 606 current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate); 607 } 608 } 609 610 static bool decide_fallback_link_setting_max_bw_policy( 611 struct dc_link *link, 612 const struct dc_link_settings *max, 613 struct dc_link_settings *cur, 614 enum link_training_result training_result) 615 { 616 uint32_t cur_idx = 0, next_idx; 617 bool found = false; 618 619 if (training_result == LINK_TRAINING_ABORT) 620 return false; 621 622 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks)) 623 /* find current index */ 624 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && 625 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate) 626 break; 627 else 628 cur_idx++; 629 630 next_idx = cur_idx + 1; 631 632 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) 633 /* find next index */ 634 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || 635 dp_lt_fallbacks[next_idx].link_rate > max->link_rate) 636 next_idx++; 637 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 && 638 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0) 639 /* upto DP2.x specs UHBR13.5 is the only link rate that 640 * could be not supported by DPRX when higher link rate 641 * is supported. so we treat it as a special case for 642 * code simplicity. When we have new specs with more 643 * link rates like this, we should consider a more 644 * generic solution to handle discrete link rate 645 * capabilities. 646 */ 647 next_idx++; 648 else 649 break; 650 651 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) { 652 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; 653 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate; 654 found = true; 655 } 656 657 return found; 658 } 659 660 /* 661 * function: set link rate and lane count fallback based 662 * on current link setting and last link training result 663 * return value: 664 * true - link setting could be set 665 * false - has reached minimum setting 666 * and no further fallback could be done 667 */ 668 bool decide_fallback_link_setting( 669 struct dc_link *link, 670 struct dc_link_settings *max, 671 struct dc_link_settings *cur, 672 enum link_training_result training_result) 673 { 674 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING || 675 link->dc->debug.force_dp2_lt_fallback_method) 676 return decide_fallback_link_setting_max_bw_policy(link, max, 677 cur, training_result); 678 679 switch (training_result) { 680 case LINK_TRAINING_CR_FAIL_LANE0: 681 case LINK_TRAINING_CR_FAIL_LANE1: 682 case LINK_TRAINING_CR_FAIL_LANE23: 683 case LINK_TRAINING_LQA_FAIL: 684 { 685 if (!reached_minimum_link_rate(cur->link_rate)) { 686 cur->link_rate = reduce_link_rate(link, cur->link_rate); 687 } else if (!reached_minimum_lane_count(cur->lane_count)) { 688 cur->link_rate = max->link_rate; 689 if (training_result == LINK_TRAINING_CR_FAIL_LANE0) 690 return false; 691 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1) 692 cur->lane_count = LANE_COUNT_ONE; 693 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23) 694 cur->lane_count = LANE_COUNT_TWO; 695 else 696 cur->lane_count = reduce_lane_count(cur->lane_count); 697 } else { 698 return false; 699 } 700 break; 701 } 702 case LINK_TRAINING_EQ_FAIL_EQ: 703 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL: 704 { 705 if (!reached_minimum_lane_count(cur->lane_count)) { 706 cur->lane_count = reduce_lane_count(cur->lane_count); 707 } else if (!reached_minimum_link_rate(cur->link_rate)) { 708 cur->link_rate = reduce_link_rate(link, cur->link_rate); 709 /* Reduce max link rate to avoid potential infinite loop. 710 * Needed so that any subsequent CR_FAIL fallback can't 711 * re-set the link rate higher than the link rate from 712 * the latest EQ_FAIL fallback. 713 */ 714 max->link_rate = cur->link_rate; 715 cur->lane_count = max->lane_count; 716 } else { 717 return false; 718 } 719 break; 720 } 721 case LINK_TRAINING_EQ_FAIL_CR: 722 { 723 if (!reached_minimum_link_rate(cur->link_rate)) { 724 cur->link_rate = reduce_link_rate(link, cur->link_rate); 725 /* Reduce max link rate to avoid potential infinite loop. 726 * Needed so that any subsequent CR_FAIL fallback can't 727 * re-set the link rate higher than the link rate from 728 * the latest EQ_FAIL fallback. 729 */ 730 max->link_rate = cur->link_rate; 731 cur->lane_count = max->lane_count; 732 } else { 733 return false; 734 } 735 break; 736 } 737 default: 738 return false; 739 } 740 return true; 741 } 742 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw) 743 { 744 struct dc_link_settings initial_link_setting = { 745 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; 746 struct dc_link_settings current_link_setting = 747 initial_link_setting; 748 uint32_t link_bw; 749 750 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 751 return false; 752 753 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) 754 initial_link_setting.link_rate = link->preferred_link_setting.link_rate; 755 756 /* search for the minimum link setting that: 757 * 1. is supported according to the link training result 758 * 2. could support the b/w requested by the timing 759 */ 760 while (current_link_setting.link_rate <= 761 link->verified_link_cap.link_rate) { 762 link_bw = dp_link_bandwidth_kbps( 763 link, 764 ¤t_link_setting); 765 if (req_bw <= link_bw) { 766 *link_setting = current_link_setting; 767 return true; 768 } 769 770 if (current_link_setting.lane_count < 771 link->verified_link_cap.lane_count) { 772 current_link_setting.lane_count = 773 increase_lane_count( 774 current_link_setting.lane_count); 775 } else { 776 current_link_setting.link_rate = 777 increase_link_rate(link, 778 current_link_setting.link_rate); 779 current_link_setting.lane_count = 780 initial_link_setting.lane_count; 781 } 782 } 783 784 return false; 785 } 786 787 bool edp_decide_link_settings(struct dc_link *link, 788 struct dc_link_settings *link_setting, uint32_t req_bw) 789 { 790 struct dc_link_settings initial_link_setting; 791 struct dc_link_settings current_link_setting; 792 uint32_t link_bw; 793 794 /* 795 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 796 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 797 */ 798 if (!edp_is_ilr_optimization_enabled(link)) { 799 *link_setting = link->verified_link_cap; 800 return true; 801 } 802 803 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 804 initial_link_setting.lane_count = LANE_COUNT_ONE; 805 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 806 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 807 initial_link_setting.use_link_rate_set = true; 808 initial_link_setting.link_rate_set = 0; 809 current_link_setting = initial_link_setting; 810 811 /* search for the minimum link setting that: 812 * 1. is supported according to the link training result 813 * 2. could support the b/w requested by the timing 814 */ 815 while (current_link_setting.link_rate <= 816 link->verified_link_cap.link_rate) { 817 link_bw = dp_link_bandwidth_kbps( 818 link, 819 ¤t_link_setting); 820 if (req_bw <= link_bw) { 821 *link_setting = current_link_setting; 822 return true; 823 } 824 825 if (current_link_setting.lane_count < 826 link->verified_link_cap.lane_count) { 827 current_link_setting.lane_count = 828 increase_lane_count( 829 current_link_setting.lane_count); 830 } else { 831 increase_edp_link_rate(link, ¤t_link_setting); 832 } 833 } 834 return false; 835 } 836 837 bool decide_edp_link_settings_with_dsc(struct dc_link *link, 838 struct dc_link_settings *link_setting, 839 uint32_t req_bw, 840 enum dc_link_rate max_link_rate) 841 { 842 struct dc_link_settings initial_link_setting; 843 struct dc_link_settings current_link_setting; 844 uint32_t link_bw; 845 846 unsigned int policy = 0; 847 848 policy = link->panel_config.dsc.force_dsc_edp_policy; 849 if (max_link_rate == LINK_RATE_UNKNOWN) 850 max_link_rate = link->verified_link_cap.link_rate; 851 /* 852 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 853 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 854 */ 855 if (!edp_is_ilr_optimization_enabled(link)) { 856 /* for DSC enabled case, we search for minimum lane count */ 857 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 858 initial_link_setting.lane_count = LANE_COUNT_ONE; 859 initial_link_setting.link_rate = LINK_RATE_LOW; 860 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 861 initial_link_setting.use_link_rate_set = false; 862 initial_link_setting.link_rate_set = 0; 863 current_link_setting = initial_link_setting; 864 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap)) 865 return false; 866 867 /* search for the minimum link setting that: 868 * 1. is supported according to the link training result 869 * 2. could support the b/w requested by the timing 870 */ 871 while (current_link_setting.link_rate <= 872 max_link_rate) { 873 link_bw = dp_link_bandwidth_kbps( 874 link, 875 ¤t_link_setting); 876 if (req_bw <= link_bw) { 877 *link_setting = current_link_setting; 878 return true; 879 } 880 if (policy) { 881 /* minimize lane */ 882 if (current_link_setting.link_rate < max_link_rate) { 883 increase_edp_link_rate(link, ¤t_link_setting); 884 } else { 885 if (current_link_setting.lane_count < 886 link->verified_link_cap.lane_count) { 887 current_link_setting.lane_count = 888 increase_lane_count( 889 current_link_setting.lane_count); 890 current_link_setting.link_rate = initial_link_setting.link_rate; 891 } else 892 break; 893 } 894 } else { 895 /* minimize link rate */ 896 if (current_link_setting.lane_count < 897 link->verified_link_cap.lane_count) { 898 current_link_setting.lane_count = 899 increase_lane_count( 900 current_link_setting.lane_count); 901 } else { 902 increase_edp_link_rate(link, ¤t_link_setting); 903 current_link_setting.lane_count = 904 initial_link_setting.lane_count; 905 } 906 } 907 } 908 return false; 909 } 910 911 /* if optimize edp link is supported */ 912 memset(&initial_link_setting, 0, sizeof(initial_link_setting)); 913 initial_link_setting.lane_count = LANE_COUNT_ONE; 914 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0]; 915 initial_link_setting.link_spread = LINK_SPREAD_DISABLED; 916 initial_link_setting.use_link_rate_set = true; 917 initial_link_setting.link_rate_set = 0; 918 current_link_setting = initial_link_setting; 919 920 /* search for the minimum link setting that: 921 * 1. is supported according to the link training result 922 * 2. could support the b/w requested by the timing 923 */ 924 while (current_link_setting.link_rate <= 925 max_link_rate) { 926 link_bw = dp_link_bandwidth_kbps( 927 link, 928 ¤t_link_setting); 929 if (req_bw <= link_bw) { 930 *link_setting = current_link_setting; 931 return true; 932 } 933 if (policy) { 934 /* minimize lane */ 935 if (current_link_setting.link_rate < max_link_rate) { 936 increase_edp_link_rate(link, ¤t_link_setting); 937 } else { 938 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { 939 current_link_setting.lane_count = 940 increase_lane_count( 941 current_link_setting.lane_count); 942 current_link_setting.link_rate_set = initial_link_setting.link_rate_set; 943 current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set; 944 current_link_setting.link_rate = 945 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; 946 } else 947 break; 948 } 949 } else { 950 /* minimize link rate */ 951 if (current_link_setting.lane_count < 952 link->verified_link_cap.lane_count) { 953 current_link_setting.lane_count = 954 increase_lane_count( 955 current_link_setting.lane_count); 956 } else { 957 increase_edp_link_rate(link, ¤t_link_setting); 958 if (current_link_setting.link_rate == LINK_RATE_UNKNOWN) 959 break; 960 } 961 } 962 } 963 return false; 964 } 965 966 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) 967 { 968 *link_setting = link->verified_link_cap; 969 return true; 970 } 971 972 bool link_decide_link_settings(struct dc_stream_state *stream, 973 struct dc_link_settings *link_setting) 974 { 975 struct dc_link *link = stream->link; 976 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link)); 977 978 memset(link_setting, 0, sizeof(*link_setting)); 979 980 if (dc_is_dp_signal(stream->signal) && 981 link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 982 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) { 983 /* if preferred is specified through AMDDP, use it, if it's enough 984 * to drive the mode 985 */ 986 *link_setting = link->preferred_link_setting; 987 } else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 988 /* MST doesn't perform link training for now 989 * TODO: add MST specific link training routine 990 */ 991 decide_mst_link_settings(link, link_setting); 992 } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) { 993 link_setting->lane_count = LANE_COUNT_FOUR; 994 link_setting->link_rate = LINK_RATE_HIGH3; 995 } else if (link->connector_signal == SIGNAL_TYPE_EDP) { 996 /* enable edp link optimization for DSC eDP case */ 997 if (stream->timing.flags.DSC) { 998 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN; 999 1000 if (link->panel_config.dsc.force_dsc_edp_policy) { 1001 /* calculate link max link rate cap*/ 1002 struct dc_link_settings tmp_link_setting; 1003 struct dc_crtc_timing tmp_timing = stream->timing; 1004 uint32_t orig_req_bw; 1005 1006 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN; 1007 tmp_timing.flags.DSC = 0; 1008 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing, 1009 dc_link_get_highest_encoding_format(link)); 1010 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw); 1011 max_link_rate = tmp_link_setting.link_rate; 1012 } 1013 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate); 1014 } else { 1015 edp_decide_link_settings(link, link_setting, req_bw); 1016 } 1017 } else { 1018 decide_dp_link_settings(link, link_setting, req_bw); 1019 } 1020 1021 return link_setting->lane_count != LANE_COUNT_UNKNOWN && 1022 link_setting->link_rate != LINK_RATE_UNKNOWN; 1023 } 1024 1025 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings) 1026 { 1027 if ((link_settings->link_rate >= LINK_RATE_LOW) && 1028 (link_settings->link_rate <= LINK_RATE_HIGH3)) 1029 return DP_8b_10b_ENCODING; 1030 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) && 1031 (link_settings->link_rate <= LINK_RATE_UHBR20)) 1032 return DP_128b_132b_ENCODING; 1033 return DP_UNKNOWN_ENCODING; 1034 } 1035 1036 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link) 1037 { 1038 struct dc_link_settings link_settings = {0}; 1039 1040 if (!dc_is_dp_signal(link->connector_signal)) 1041 return DP_UNKNOWN_ENCODING; 1042 1043 if (link->preferred_link_setting.lane_count != 1044 LANE_COUNT_UNKNOWN && 1045 link->preferred_link_setting.link_rate != 1046 LINK_RATE_UNKNOWN) { 1047 link_settings = link->preferred_link_setting; 1048 } else { 1049 decide_mst_link_settings(link, &link_settings); 1050 } 1051 1052 return link_dp_get_encoding_format(&link_settings); 1053 } 1054 1055 static void read_dp_device_vendor_id(struct dc_link *link) 1056 { 1057 struct dp_device_vendor_id dp_id = {0}; 1058 1059 /* read IEEE branch device id */ 1060 core_link_read_dpcd( 1061 link, 1062 DP_BRANCH_OUI, 1063 (uint8_t *)&dp_id, 1064 sizeof(dp_id)); 1065 1066 link->dpcd_caps.branch_dev_id = 1067 (dp_id.ieee_oui[0] << 16) + 1068 (dp_id.ieee_oui[1] << 8) + 1069 dp_id.ieee_oui[2]; 1070 1071 memmove( 1072 link->dpcd_caps.branch_dev_name, 1073 dp_id.ieee_device_id, 1074 sizeof(dp_id.ieee_device_id)); 1075 } 1076 1077 static enum dc_status wake_up_aux_channel(struct dc_link *link) 1078 { 1079 enum dc_status status = DC_ERROR_UNEXPECTED; 1080 uint32_t aux_channel_retry_cnt = 0; 1081 uint8_t dpcd_power_state = '\0'; 1082 1083 while (status != DC_OK && aux_channel_retry_cnt < 10) { 1084 status = core_link_read_dpcd(link, DP_SET_POWER, 1085 &dpcd_power_state, sizeof(dpcd_power_state)); 1086 1087 /* Delay 1 ms if AUX CH is in power down state. Based on spec 1088 * section 2.3.1.2, if AUX CH may be powered down due to 1089 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential 1090 * signal and may need up to 1 ms before being able to reply. 1091 */ 1092 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) { 1093 fsleep(1000); 1094 aux_channel_retry_cnt++; 1095 } 1096 } 1097 1098 if (status != DC_OK) { 1099 dpcd_power_state = DP_SET_POWER_D0; 1100 status = core_link_write_dpcd( 1101 link, 1102 DP_SET_POWER, 1103 &dpcd_power_state, 1104 sizeof(dpcd_power_state)); 1105 1106 dpcd_power_state = DP_SET_POWER_D3; 1107 status = core_link_write_dpcd( 1108 link, 1109 DP_SET_POWER, 1110 &dpcd_power_state, 1111 sizeof(dpcd_power_state)); 1112 DC_LOG_DC("%s: Failed to power up sink\n", __func__); 1113 return DC_ERROR_UNEXPECTED; 1114 } 1115 1116 return DC_OK; 1117 } 1118 1119 static void read_and_intersect_post_frl_lt_status( 1120 struct dc_link *link) 1121 { 1122 union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0}; 1123 union hdmi_tx_link_status hdmi_tx_link_status = {0}; 1124 union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0}; 1125 1126 /* Check if dongle supports regulated autonomous mode. */ 1127 core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS, 1128 &autonomous_mode_caps.raw, sizeof(autonomous_mode_caps)); 1129 1130 link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support = 1131 autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED; 1132 1133 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) { 1134 DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__); 1135 1136 core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS, 1137 &hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status)); 1138 } 1139 1140 // Intersect reported max link bw support with the supported link rate post FRL link training 1141 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS, 1142 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) { 1143 1144 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support && 1145 (!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS || 1146 !hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) { 1147 DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__); 1148 1149 /* Link training not finished, ignore values from this DPCD reg. */ 1150 return; 1151 } 1152 1153 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support( 1154 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps, 1155 hdmi_encoded_link_bw); 1156 DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__, 1157 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps); 1158 } 1159 } 1160 1161 static void get_active_converter_info( 1162 uint8_t data, struct dc_link *link) 1163 { 1164 union dp_downstream_port_present ds_port = { .byte = data }; 1165 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps)); 1166 1167 /* decode converter info*/ 1168 if (!ds_port.fields.PORT_PRESENT) { 1169 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1170 set_dongle_type(link->ddc, 1171 link->dpcd_caps.dongle_type); 1172 link->dpcd_caps.is_branch_dev = false; 1173 return; 1174 } 1175 1176 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ 1177 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; 1178 1179 switch (ds_port.fields.PORT_TYPE) { 1180 case DOWNSTREAM_VGA: 1181 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; 1182 break; 1183 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: 1184 /* At this point we don't know is it DVI or HDMI or DP++, 1185 * assume DVI.*/ 1186 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; 1187 break; 1188 default: 1189 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1190 break; 1191 } 1192 1193 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) { 1194 uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ 1195 union dwnstream_port_caps_byte0 *port_caps = 1196 (union dwnstream_port_caps_byte0 *)det_caps; 1197 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, 1198 det_caps, sizeof(det_caps)) == DC_OK) { 1199 1200 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { 1201 /*Handle DP case as DONGLE_NONE*/ 1202 case DOWN_STREAM_DETAILED_DP: 1203 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; 1204 break; 1205 case DOWN_STREAM_DETAILED_VGA: 1206 link->dpcd_caps.dongle_type = 1207 DISPLAY_DONGLE_DP_VGA_CONVERTER; 1208 break; 1209 case DOWN_STREAM_DETAILED_DVI: 1210 link->dpcd_caps.dongle_type = 1211 DISPLAY_DONGLE_DP_DVI_CONVERTER; 1212 break; 1213 case DOWN_STREAM_DETAILED_HDMI: 1214 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: 1215 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ 1216 link->dpcd_caps.dongle_type = 1217 DISPLAY_DONGLE_DP_HDMI_CONVERTER; 1218 1219 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; 1220 if (ds_port.fields.DETAILED_CAPS) { 1221 1222 union dwnstream_port_caps_byte3_hdmi 1223 hdmi_caps = {.raw = det_caps[3] }; 1224 union dwnstream_port_caps_byte2 1225 hdmi_color_caps = {.raw = det_caps[2] }; 1226 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = 1227 det_caps[1] * 2500; 1228 1229 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = 1230 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; 1231 /*YCBCR capability only for HDMI case*/ 1232 if (port_caps->bits.DWN_STRM_PORTX_TYPE 1233 == DOWN_STREAM_DETAILED_HDMI) { 1234 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = 1235 hdmi_caps.bits.YCrCr422_PASS_THROUGH; 1236 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = 1237 hdmi_caps.bits.YCrCr420_PASS_THROUGH; 1238 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = 1239 hdmi_caps.bits.YCrCr422_CONVERSION; 1240 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = 1241 hdmi_caps.bits.YCrCr420_CONVERSION; 1242 } 1243 1244 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = 1245 translate_dpcd_max_bpc( 1246 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); 1247 1248 if (link->dc->caps.dp_hdmi21_pcon_support) { 1249 1250 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = 1251 link_bw_kbps_from_raw_frl_link_rate_data( 1252 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); 1253 1254 read_and_intersect_post_frl_lt_status(link); 1255 1256 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) 1257 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1258 } 1259 1260 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) 1261 link->dpcd_caps.dongle_caps.extendedCapValid = true; 1262 } 1263 1264 break; 1265 } 1266 } 1267 } 1268 1269 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type); 1270 1271 { 1272 struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0}; 1273 1274 core_link_read_dpcd( 1275 link, 1276 DP_BRANCH_REVISION_START, 1277 (uint8_t *)&dp_hw_fw_revision, 1278 sizeof(dp_hw_fw_revision)); 1279 1280 link->dpcd_caps.branch_hw_revision = 1281 dp_hw_fw_revision.ieee_hw_rev; 1282 1283 memmove( 1284 link->dpcd_caps.branch_fw_revision, 1285 dp_hw_fw_revision.ieee_fw_rev, 1286 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1287 } 1288 1289 core_link_read_dpcd( 1290 link, 1291 DP_BRANCH_VENDOR_SPECIFIC_START, 1292 (uint8_t *)link->dpcd_caps.branch_vendor_specific_data, 1293 sizeof(link->dpcd_caps.branch_vendor_specific_data)); 1294 1295 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && 1296 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 1297 union dp_dfp_cap_ext dfp_cap_ext; 1298 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext)); 1299 core_link_read_dpcd( 1300 link, 1301 DP_DFP_CAPABILITY_EXTENSION_SUPPORT, 1302 dfp_cap_ext.raw, 1303 sizeof(dfp_cap_ext.raw)); 1304 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported; 1305 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps = 1306 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] + 1307 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8); 1308 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width = 1309 dfp_cap_ext.fields.max_video_h_active_width[0] + 1310 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8); 1311 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height = 1312 dfp_cap_ext.fields.max_video_v_active_height[0] + 1313 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8); 1314 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps = 1315 dfp_cap_ext.fields.encoding_format_caps; 1316 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps = 1317 dfp_cap_ext.fields.rgb_color_depth_caps; 1318 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps = 1319 dfp_cap_ext.fields.ycbcr444_color_depth_caps; 1320 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps = 1321 dfp_cap_ext.fields.ycbcr422_color_depth_caps; 1322 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps = 1323 dfp_cap_ext.fields.ycbcr420_color_depth_caps; 1324 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index); 1325 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false"); 1326 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps); 1327 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width); 1328 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height); 1329 } 1330 } 1331 1332 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link, 1333 struct dc_link_settings *link_settings) 1334 { 1335 /* Temporary Renoir-specific workaround PHY will sometimes be in bad 1336 * state on hotplugging display from certain USB-C dongle, so add extra 1337 * cycle of enabling and disabling the PHY before first link training. 1338 */ 1339 struct link_resource link_res = {0}; 1340 enum clock_source_id dp_cs_id = get_clock_source_id(link); 1341 1342 dp_enable_link_phy(link, &link_res, link->connector_signal, 1343 dp_cs_id, link_settings); 1344 dp_disable_link_phy(link, &link_res, link->connector_signal); 1345 } 1346 1347 bool dp_overwrite_extended_receiver_cap(struct dc_link *link) 1348 { 1349 uint8_t dpcd_data[16] = {0}; 1350 uint32_t read_dpcd_retry_cnt = 3; 1351 enum dc_status status = DC_ERROR_UNEXPECTED; 1352 union dp_downstream_port_present ds_port = { 0 }; 1353 union down_stream_port_count down_strm_port_count; 1354 union edp_configuration_cap edp_config_cap; 1355 1356 unsigned int i; 1357 1358 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1359 status = core_link_read_dpcd( 1360 link, 1361 DP_DPCD_REV, 1362 dpcd_data, 1363 sizeof(dpcd_data)); 1364 if (status == DC_OK) 1365 break; 1366 } 1367 1368 link->dpcd_caps.dpcd_rev.raw = 1369 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1370 1371 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1372 return false; 1373 1374 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1375 DP_DPCD_REV]; 1376 1377 get_active_converter_info(ds_port.byte, link); 1378 1379 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1380 DP_DPCD_REV]; 1381 1382 link->dpcd_caps.allow_invalid_MSA_timing_param = 1383 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1384 1385 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1386 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1387 1388 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1389 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1390 1391 link->reported_link_cap.lane_count = 1392 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1393 link->reported_link_cap.link_rate = dpcd_data[ 1394 DP_MAX_LINK_RATE - DP_DPCD_REV]; 1395 link->reported_link_cap.link_spread = 1396 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1397 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1398 1399 edp_config_cap.raw = dpcd_data[ 1400 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1401 link->dpcd_caps.panel_mode_edp = 1402 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1403 link->dpcd_caps.dpcd_display_control_capable = 1404 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1405 1406 return true; 1407 } 1408 1409 void dpcd_set_source_specific_data(struct dc_link *link) 1410 { 1411 if (!link->dc->vendor_signature.is_valid) { 1412 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED; 1413 struct dpcd_amd_signature amd_signature = {0}; 1414 struct dpcd_amd_device_id amd_device_id = {0}; 1415 1416 if (link->is_dds) { 1417 uint8_t dpcd_dp_edp_backlight_mode = 0; 1418 1419 /* 1420 * Write 0 to bits 0:1 for dp_edp_backlight_mode_set register 1421 * if platform is DDS 1422 */ 1423 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, 1424 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t)); 1425 dpcd_dp_edp_backlight_mode &= ~0x3; 1426 1427 core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, 1428 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t)); 1429 } 1430 1431 amd_device_id.device_id_byte1 = 1432 (uint8_t)(link->ctx->asic_id.chip_id); 1433 amd_device_id.device_id_byte2 = 1434 (uint8_t)(link->ctx->asic_id.chip_id >> 8); 1435 amd_device_id.dce_version = 1436 (uint8_t)(link->ctx->dce_version); 1437 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get? 1438 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get? 1439 1440 core_link_read_dpcd(link, DP_SOURCE_OUI, 1441 (uint8_t *)(&amd_signature), 1442 sizeof(amd_signature)); 1443 1444 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) && 1445 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) && 1446 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) { 1447 1448 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0; 1449 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0; 1450 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A; 1451 1452 core_link_write_dpcd(link, DP_SOURCE_OUI, 1453 (uint8_t *)(&amd_signature), 1454 sizeof(amd_signature)); 1455 } 1456 1457 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03, 1458 (uint8_t *)(&amd_device_id), 1459 sizeof(amd_device_id)); 1460 1461 if (link->ctx->dce_version >= DCN_VERSION_2_0 && 1462 link->dc->caps.min_horizontal_blanking_period != 0) { 1463 1464 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period; 1465 1466 result_write_min_hblank = core_link_write_dpcd(link, 1467 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size), 1468 sizeof(hblank_size)); 1469 } 1470 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, 1471 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS, 1472 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'", 1473 result_write_min_hblank, 1474 link->link_index, 1475 link->ctx->dce_version, 1476 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, 1477 link->dc->caps.min_horizontal_blanking_period, 1478 link->dpcd_caps.branch_dev_id, 1479 link->dpcd_caps.branch_dev_name[0], 1480 link->dpcd_caps.branch_dev_name[1], 1481 link->dpcd_caps.branch_dev_name[2], 1482 link->dpcd_caps.branch_dev_name[3], 1483 link->dpcd_caps.branch_dev_name[4], 1484 link->dpcd_caps.branch_dev_name[5]); 1485 } else { 1486 core_link_write_dpcd(link, DP_SOURCE_OUI, 1487 link->dc->vendor_signature.data.raw, 1488 sizeof(link->dc->vendor_signature.data.raw)); 1489 } 1490 } 1491 1492 void dpcd_write_cable_id_to_dprx(struct dc_link *link) 1493 { 1494 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED || 1495 link->dpcd_caps.cable_id.raw == 0 || 1496 link->dprx_states.cable_id_written) 1497 return; 1498 1499 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX, 1500 &link->dpcd_caps.cable_id.raw, 1501 sizeof(link->dpcd_caps.cable_id.raw)); 1502 1503 link->dprx_states.cable_id_written = 1; 1504 } 1505 1506 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) 1507 { 1508 union dmub_rb_cmd cmd; 1509 1510 if (!link->ctx->dmub_srv || 1511 link->ep_type != DISPLAY_ENDPOINT_PHY || 1512 link->link_enc->features.flags.bits.DP_IS_USB_C == 0) 1513 return false; 1514 1515 memset(&cmd, 0, sizeof(cmd)); 1516 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID; 1517 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data); 1518 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx( 1519 link->dc, link->link_enc->transmitter); 1520 if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) && 1521 cmd.cable_id.header.ret_status == 1) { 1522 cable_id->raw = cmd.cable_id.data.output_raw; 1523 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); 1524 } 1525 return cmd.cable_id.header.ret_status == 1; 1526 } 1527 1528 static void retrieve_cable_id(struct dc_link *link) 1529 { 1530 union dp_cable_id usbc_cable_id = {0}; 1531 1532 link->dpcd_caps.cable_id.raw = 0; 1533 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX, 1534 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t)); 1535 1536 if (get_usbc_cable_id(link, &usbc_cable_id)) 1537 link->dpcd_caps.cable_id = intersect_cable_id( 1538 &link->dpcd_caps.cable_id, &usbc_cable_id); 1539 } 1540 1541 bool read_is_mst_supported(struct dc_link *link) 1542 { 1543 bool mst = false; 1544 enum dc_status st = DC_OK; 1545 union dpcd_rev rev; 1546 union mstm_cap cap; 1547 1548 if (link->preferred_training_settings.mst_enable && 1549 *link->preferred_training_settings.mst_enable == false) { 1550 return false; 1551 } 1552 1553 rev.raw = 0; 1554 cap.raw = 0; 1555 1556 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, 1557 sizeof(rev)); 1558 1559 if (st == DC_OK && rev.raw >= DPCD_REV_12) { 1560 1561 st = core_link_read_dpcd(link, DP_MSTM_CAP, 1562 &cap.raw, sizeof(cap)); 1563 if (st == DC_OK && cap.bits.MST_CAP == 1) 1564 mst = true; 1565 } 1566 return mst; 1567 1568 } 1569 1570 /* Read additional sink caps defined in source specific DPCD area 1571 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP) 1572 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well 1573 */ 1574 static bool dpcd_read_sink_ext_caps(struct dc_link *link) 1575 { 1576 uint8_t dpcd_data = 0; 1577 uint8_t edp_general_cap2 = 0; 1578 1579 if (!link) 1580 return false; 1581 1582 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) 1583 return false; 1584 1585 link->dpcd_sink_ext_caps.raw = dpcd_data; 1586 if (link->is_dds && !link->dpcd_sink_ext_caps.bits.oled) { 1587 link->dpcd_sink_ext_caps.raw = 0; 1588 return false; 1589 } 1590 1591 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK) 1592 return false; 1593 1594 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0; 1595 1596 return true; 1597 } 1598 1599 static void retrieve_vesa_replay_su_info(struct dc_link *link) 1600 { 1601 uint8_t dpcd_data = 0; 1602 1603 core_link_read_dpcd(link, 1604 DP_PR_SU_X_GRANULARITY_LOW, 1605 &dpcd_data, 1606 sizeof(dpcd_data)); 1607 link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity = dpcd_data; 1608 1609 core_link_read_dpcd(link, 1610 DP_PR_SU_X_GRANULARITY_HIGH, 1611 &dpcd_data, 1612 sizeof(dpcd_data)); 1613 link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity |= (dpcd_data << 8); 1614 1615 core_link_read_dpcd(link, 1616 DP_PR_SU_Y_GRANULARITY, 1617 &dpcd_data, 1618 sizeof(dpcd_data)); 1619 link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity = dpcd_data; 1620 1621 core_link_read_dpcd(link, 1622 DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW, 1623 &dpcd_data, 1624 sizeof(dpcd_data)); 1625 link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps = dpcd_data; 1626 1627 core_link_read_dpcd(link, 1628 DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH, 1629 &dpcd_data, 1630 sizeof(dpcd_data)); 1631 link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps |= (dpcd_data << 8); 1632 } 1633 1634 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) 1635 { 1636 uint8_t lttpr_dpcd_data[10] = {0}; 1637 enum dc_status status; 1638 bool is_lttpr_present; 1639 uint32_t lttpr_count; 1640 uint32_t closest_lttpr_offset; 1641 1642 /* Logic to determine LTTPR support*/ 1643 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware; 1644 1645 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support) 1646 return DC_NOT_SUPPORTED; 1647 1648 /* By reading LTTPR capability, RX assumes that we will enable 1649 * LTTPR extended aux timeout if LTTPR is present. 1650 */ 1651 status = core_link_read_dpcd( 1652 link, 1653 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 1654 lttpr_dpcd_data, 1655 sizeof(lttpr_dpcd_data)); 1656 1657 link->dpcd_caps.lttpr_caps.revision.raw = 1658 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV - 1659 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1660 1661 link->dpcd_caps.lttpr_caps.max_link_rate = 1662 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER - 1663 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1664 1665 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 1666 lttpr_dpcd_data[DP_PHY_REPEATER_CNT - 1667 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1668 1669 link->dpcd_caps.lttpr_caps.max_lane_count = 1670 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER - 1671 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1672 1673 link->dpcd_caps.lttpr_caps.mode = 1674 lttpr_dpcd_data[DP_PHY_REPEATER_MODE - 1675 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1676 1677 link->dpcd_caps.lttpr_caps.max_ext_timeout = 1678 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - 1679 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1680 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw = 1681 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 1682 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1683 1684 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = 1685 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - 1686 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1687 1688 link->dpcd_caps.lttpr_caps.alpm.raw = 1689 lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES - 1690 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 1691 1692 lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1693 1694 /* If this chip cap is set, at least one retimer must exist in the chain 1695 * Override count to 1 if we receive a known bad count (0 or an invalid value) */ 1696 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 1697 lttpr_count == 0) { 1698 /* If you see this message consistently, either the host platform has FIXED_VS flag 1699 * incorrectly configured or the sink device is returning an invalid count. 1700 */ 1701 DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.", 1702 link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1703 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80; 1704 lttpr_count = 1; 1705 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 1706 } 1707 1708 is_lttpr_present = dp_is_lttpr_present(link); 1709 1710 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present); 1711 1712 if (is_lttpr_present) { 1713 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); 1714 1715 // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR 1716 closest_lttpr_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count); 1717 1718 core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset), 1719 link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui)); 1720 core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset), 1721 link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id)); 1722 1723 if (lttpr_count > 1) { 1724 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), 1725 "Closest LTTPR To Host's IEEE OUI: "); 1726 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), 1727 "Closest LTTPR To Host's LTTPR Device ID: "); 1728 } else { 1729 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), 1730 "LTTPR IEEE OUI: "); 1731 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), 1732 "LTTPR Device ID: "); 1733 } 1734 } 1735 1736 return status; 1737 } 1738 1739 static bool retrieve_link_cap(struct dc_link *link) 1740 { 1741 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16, 1742 * which means size 16 will be good for both of those DPCD register block reads 1743 */ 1744 uint8_t dpcd_data[16]; 1745 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST. 1746 */ 1747 uint8_t dpcd_dprx_data = '\0'; 1748 1749 struct dp_device_vendor_id sink_id; 1750 union down_stream_port_count down_strm_port_count; 1751 union edp_configuration_cap edp_config_cap; 1752 union dp_downstream_port_present ds_port = { 0 }; 1753 enum dc_status status = DC_ERROR_UNEXPECTED; 1754 uint32_t read_dpcd_retry_cnt = 20; 1755 unsigned int i; 1756 struct dp_sink_hw_fw_revision dp_hw_fw_revision; 1757 const uint32_t post_oui_delay = 30; // 30ms 1758 bool is_fec_supported = false; 1759 bool is_dsc_basic_supported = false; 1760 bool is_dsc_passthrough_supported = false; 1761 1762 memset(dpcd_data, '\0', sizeof(dpcd_data)); 1763 memset(&down_strm_port_count, 1764 '\0', sizeof(union down_stream_port_count)); 1765 memset(&edp_config_cap, '\0', 1766 sizeof(union edp_configuration_cap)); 1767 1768 /* if extended timeout is supported in hardware, 1769 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1770 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1771 */ 1772 try_to_configure_aux_timeout(link->ddc, 1773 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1774 1775 status = dp_retrieve_lttpr_cap(link); 1776 1777 if (status != DC_OK) { 1778 status = wake_up_aux_channel(link); 1779 if (status == DC_OK) 1780 dp_retrieve_lttpr_cap(link); 1781 else 1782 return false; 1783 } 1784 1785 if (dp_is_lttpr_present(link)) { 1786 configure_lttpr_mode_transparent(link); 1787 1788 // Echo TOTAL_LTTPR_CNT back downstream 1789 core_link_write_dpcd( 1790 link, 1791 DP_TOTAL_LTTPR_CNT, 1792 &link->dpcd_caps.lttpr_caps.phy_repeater_cnt, 1793 sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt)); 1794 } 1795 1796 dpcd_set_source_specific_data(link); 1797 1798 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1799 /* 1800 * Sink may need to configure internals based on vendor, so allow some 1801 * time before proceeding with possibly vendor specific transactions 1802 */ 1803 msleep(post_oui_delay); 1804 status = core_link_read_dpcd( 1805 link, 1806 DP_DPCD_REV, 1807 dpcd_data, 1808 sizeof(dpcd_data)); 1809 if (status == DC_OK) 1810 break; 1811 } 1812 1813 1814 if (status != DC_OK) { 1815 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__); 1816 return false; 1817 } 1818 1819 if (!dp_is_lttpr_present(link)) 1820 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1821 1822 1823 { 1824 union training_aux_rd_interval aux_rd_interval; 1825 1826 aux_rd_interval.raw = 1827 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL]; 1828 1829 link->dpcd_caps.ext_receiver_cap_field_present = 1830 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1; 1831 1832 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) { 1833 uint8_t ext_cap_data[16]; 1834 1835 memset(ext_cap_data, '\0', sizeof(ext_cap_data)); 1836 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1837 status = core_link_read_dpcd( 1838 link, 1839 DP_DP13_DPCD_REV, 1840 ext_cap_data, 1841 sizeof(ext_cap_data)); 1842 if (status == DC_OK) { 1843 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data)); 1844 break; 1845 } 1846 } 1847 if (status != DC_OK) 1848 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__); 1849 } 1850 } 1851 1852 link->dpcd_caps.dpcd_rev.raw = 1853 dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; 1854 1855 if (link->dpcd_caps.ext_receiver_cap_field_present) { 1856 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1857 status = core_link_read_dpcd( 1858 link, 1859 DP_DPRX_FEATURE_ENUMERATION_LIST, 1860 &dpcd_dprx_data, 1861 sizeof(dpcd_dprx_data)); 1862 if (status == DC_OK) 1863 break; 1864 } 1865 1866 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data; 1867 1868 if (status != DC_OK) 1869 dm_error("%s: Read DPRX feature list failed.\n", __func__); 1870 1871 /* AdaptiveSyncCapability */ 1872 dpcd_dprx_data = 0; 1873 for (i = 0; i < read_dpcd_retry_cnt; i++) { 1874 status = core_link_read_dpcd( 1875 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 1876 &dpcd_dprx_data, sizeof(dpcd_dprx_data)); 1877 if (status == DC_OK) 1878 break; 1879 } 1880 1881 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data; 1882 1883 if (status != DC_OK) 1884 dm_error("%s: Read DPRX feature list_1 failed. Addr:%#x\n", 1885 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1); 1886 } 1887 else { 1888 link->dpcd_caps.dprx_feature.raw = 0; 1889 } 1890 1891 /* Error condition checking... 1892 * It is impossible for Sink to report Max Lane Count = 0. 1893 * It is possible for Sink to report Max Link Rate = 0, if it is 1894 * an eDP device that is reporting specialized link rates in the 1895 * SUPPORTED_LINK_RATE table. 1896 */ 1897 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0) 1898 return false; 1899 1900 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT - 1901 DP_DPCD_REV]; 1902 1903 read_dp_device_vendor_id(link); 1904 1905 /* TODO - decouple raw mst capability from policy decision */ 1906 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link); 1907 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable)); 1908 1909 /* Some MST docks seem to NAK I2C writes to segment pointer with mot=0. */ 1910 if (link->dpcd_caps.is_mst_capable) 1911 link->wa_flags.dp_mot_reset_segment = true; 1912 else 1913 link->wa_flags.dp_mot_reset_segment = false; 1914 1915 get_active_converter_info(ds_port.byte, link); 1916 1917 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); 1918 1919 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT - 1920 DP_DPCD_REV]; 1921 1922 link->dpcd_caps.allow_invalid_MSA_timing_param = 1923 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM; 1924 1925 link->dpcd_caps.max_ln_count.raw = dpcd_data[ 1926 DP_MAX_LANE_COUNT - DP_DPCD_REV]; 1927 1928 link->dpcd_caps.max_down_spread.raw = dpcd_data[ 1929 DP_MAX_DOWNSPREAD - DP_DPCD_REV]; 1930 1931 link->reported_link_cap.lane_count = 1932 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT; 1933 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw( 1934 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]); 1935 link->reported_link_cap.link_spread = 1936 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ? 1937 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 1938 1939 edp_config_cap.raw = dpcd_data[ 1940 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV]; 1941 link->dpcd_caps.panel_mode_edp = 1942 edp_config_cap.bits.ALT_SCRAMBLER_RESET; 1943 link->dpcd_caps.dpcd_display_control_capable = 1944 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE; 1945 link->dpcd_caps.channel_coding_cap.raw = 1946 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV]; 1947 link->test_pattern_enabled = false; 1948 link->compliance_test_state.raw = 0; 1949 1950 link->dpcd_caps.receive_port0_cap.raw[0] = 1951 dpcd_data[DP_RECEIVE_PORT_0_CAP_0 - DP_DPCD_REV]; 1952 link->dpcd_caps.receive_port0_cap.raw[1] = 1953 dpcd_data[DP_RECEIVE_PORT_0_BUFFER_SIZE - DP_DPCD_REV]; 1954 1955 /* read sink count */ 1956 core_link_read_dpcd(link, 1957 DP_SINK_COUNT, 1958 &link->dpcd_caps.sink_count.raw, 1959 sizeof(link->dpcd_caps.sink_count.raw)); 1960 1961 /* read sink ieee oui */ 1962 core_link_read_dpcd(link, 1963 DP_SINK_OUI, 1964 (uint8_t *)(&sink_id), 1965 sizeof(sink_id)); 1966 1967 link->dpcd_caps.sink_dev_id = 1968 (sink_id.ieee_oui[0] << 16) + 1969 (sink_id.ieee_oui[1] << 8) + 1970 (sink_id.ieee_oui[2]); 1971 1972 memmove( 1973 link->dpcd_caps.sink_dev_id_str, 1974 sink_id.ieee_device_id, 1975 sizeof(sink_id.ieee_device_id)); 1976 1977 core_link_read_dpcd( 1978 link, 1979 DP_SINK_HW_REVISION_START, 1980 (uint8_t *)&dp_hw_fw_revision, 1981 sizeof(dp_hw_fw_revision)); 1982 1983 link->dpcd_caps.sink_hw_revision = 1984 dp_hw_fw_revision.ieee_hw_rev; 1985 1986 memmove( 1987 link->dpcd_caps.sink_fw_revision, 1988 dp_hw_fw_revision.ieee_fw_rev, 1989 sizeof(dp_hw_fw_revision.ieee_fw_rev)); 1990 1991 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */ 1992 { 1993 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 }; 1994 uint8_t fwrev_mbp_2018[] = { 7, 4 }; 1995 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 }; 1996 1997 /* We also check for the firmware revision as 16,1 models have an 1998 * identical device id and are incorrectly quirked otherwise. 1999 */ 2000 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) && 2001 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018, 2002 sizeof(str_mbp_2018)) && 2003 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018, 2004 sizeof(fwrev_mbp_2018)) || 2005 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega, 2006 sizeof(fwrev_mbp_2018_vega)))) { 2007 link->reported_link_cap.link_rate = LINK_RATE_RBR2; 2008 } 2009 } 2010 2011 memset(&link->dpcd_caps.dsc_caps, '\0', 2012 sizeof(link->dpcd_caps.dsc_caps)); 2013 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 2014 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ 2015 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { 2016 status = core_link_read_dpcd( 2017 link, 2018 DP_FEC_CAPABILITY, 2019 &link->dpcd_caps.fec_cap.raw, 2020 sizeof(link->dpcd_caps.fec_cap.raw)); 2021 if (status != DC_OK) 2022 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__); 2023 2024 status = core_link_read_dpcd( 2025 link, 2026 DP_DSC_SUPPORT, 2027 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 2028 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); 2029 if (status == DC_OK) { 2030 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE; 2031 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT; 2032 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT; 2033 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__, 2034 str_yes_no(is_fec_supported)); 2035 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__, 2036 str_yes_no(is_dsc_basic_supported)); 2037 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__, 2038 str_yes_no(is_dsc_passthrough_supported)); 2039 } 2040 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { 2041 status = core_link_read_dpcd( 2042 link, 2043 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, 2044 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 2045 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw)); 2046 if (status != DC_OK) 2047 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__); 2048 2049 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index); 2050 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x", 2051 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0); 2052 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x", 2053 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1); 2054 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x", 2055 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH); 2056 } 2057 2058 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode 2059 * only if required. 2060 */ 2061 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2062 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around && 2063 link->dpcd_caps.is_branch_dev && 2064 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 2065 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 && 2066 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE || 2067 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) { 2068 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA. 2069 * Clear FEC and DSC capabilities as a work around if that is not the case. 2070 */ 2071 link->wa_flags.dpia_forced_tbt3_mode = true; 2072 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); 2073 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); 2074 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index); 2075 } else 2076 link->wa_flags.dpia_forced_tbt3_mode = false; 2077 } 2078 2079 if (!dpcd_read_sink_ext_caps(link)) 2080 link->dpcd_sink_ext_caps.raw = 0; 2081 2082 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) { 2083 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index); 2084 2085 /* Read 128b/132b suppoerted link rates */ 2086 core_link_read_dpcd(link, 2087 DP_128B132B_SUPPORTED_LINK_RATES, 2088 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw, 2089 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw)); 2090 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20) 2091 link->reported_link_cap.link_rate = LINK_RATE_UHBR20; 2092 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5) 2093 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5; 2094 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10) 2095 link->reported_link_cap.link_rate = LINK_RATE_UHBR10; 2096 else 2097 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__); 2098 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index); 2099 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz", 2100 link->reported_link_cap.link_rate / 100, 2101 link->reported_link_cap.link_rate % 100); 2102 2103 core_link_read_dpcd(link, 2104 DP_SINK_VIDEO_FALLBACK_FORMATS, 2105 &link->dpcd_caps.fallback_formats.raw, 2106 sizeof(link->dpcd_caps.fallback_formats.raw)); 2107 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index); 2108 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support) 2109 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported"); 2110 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support) 2111 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported"); 2112 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support) 2113 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported"); 2114 if (link->dpcd_caps.fallback_formats.raw == 0) { 2115 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported"); 2116 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1; 2117 } 2118 2119 core_link_read_dpcd(link, 2120 DP_FEC_CAPABILITY_1, 2121 &link->dpcd_caps.fec_cap1.raw, 2122 sizeof(link->dpcd_caps.fec_cap1.raw)); 2123 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index); 2124 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE) 2125 DC_LOG_DP2("\tFEC aggregated error counters are supported"); 2126 } 2127 2128 core_link_read_dpcd(link, 2129 DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP, 2130 link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw, 2131 sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw)); 2132 2133 core_link_read_dpcd(link, 2134 DP_PANEL_REPLAY_CAPABILITY_SUPPORT, 2135 &link->dpcd_caps.vesa_replay_caps_supported.raw, 2136 sizeof(link->dpcd_caps.vesa_replay_caps_supported.raw)); 2137 2138 core_link_read_dpcd(link, 2139 DP_PANEL_REPLAY_CAPABILITY, 2140 &link->dpcd_caps.vesa_replay_caps.raw, 2141 sizeof(link->dpcd_caps.vesa_replay_caps.raw)); 2142 2143 /* Read VESA Panel Replay Selective Update caps */ 2144 retrieve_vesa_replay_su_info(link); 2145 2146 /* Read DP tunneling information. */ 2147 status = dpcd_get_tunneling_device_data(link); 2148 if (status != DC_OK) 2149 DC_LOG_DP2("%s: Read DP tunneling device data failed.\n", __func__); 2150 2151 retrieve_cable_id(link); 2152 dpcd_write_cable_id_to_dprx(link); 2153 2154 /* Connectivity log: detection */ 2155 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: "); 2156 2157 return true; 2158 } 2159 2160 bool detect_dp_sink_caps(struct dc_link *link) 2161 { 2162 return retrieve_link_cap(link); 2163 } 2164 2165 void detect_edp_sink_caps(struct dc_link *link) 2166 { 2167 uint8_t supported_link_rates[16]; 2168 uint32_t entry; 2169 uint32_t link_rate_in_khz; 2170 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; 2171 uint8_t backlight_adj_cap = 0; 2172 uint8_t general_edp_cap = 0; 2173 2174 retrieve_link_cap(link); 2175 link->dpcd_caps.edp_supported_link_rates_count = 0; 2176 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2177 2178 /* 2179 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher. 2180 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h" 2181 */ 2182 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) { 2183 // Read DPCD 00010h - 0001Fh 16 bytes at one shot 2184 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES, 2185 supported_link_rates, sizeof(supported_link_rates)); 2186 2187 for (entry = 0; entry < 16; entry += 2) { 2188 // DPCD register reports per-lane link rate = 16-bit link rate capability 2189 // value X 200 kHz. Need multiplier to find link rate in kHz. 2190 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2191 supported_link_rates[entry]) * 200; 2192 2193 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__, 2194 entry / 2, link_rate_in_khz); 2195 2196 if (link_rate_in_khz != 0) { 2197 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz); 2198 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate; 2199 link->dpcd_caps.edp_supported_link_rates_count++; 2200 } 2201 } 2202 } 2203 2204 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP, 2205 &backlight_adj_cap, sizeof(backlight_adj_cap)); 2206 2207 link->dpcd_caps.dynamic_backlight_capable_edp = 2208 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false; 2209 2210 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1, 2211 &general_edp_cap, sizeof(general_edp_cap)); 2212 2213 link->dpcd_caps.set_power_state_capable_edp = 2214 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false; 2215 2216 set_default_brightness_aux(link); 2217 2218 core_link_read_dpcd(link, DP_EDP_DPCD_REV, 2219 &link->dpcd_caps.edp_rev, 2220 sizeof(link->dpcd_caps.edp_rev)); 2221 /* 2222 * PSR is only valid for eDP v1.3 or higher. 2223 */ 2224 if (link->dpcd_caps.edp_rev >= DP_EDP_13) { 2225 core_link_read_dpcd(link, DP_PSR_SUPPORT, 2226 &link->dpcd_caps.psr_info.psr_version, 2227 sizeof(link->dpcd_caps.psr_info.psr_version)); 2228 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8) 2229 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY, 2230 &link->dpcd_caps.psr_info.force_psrsu_cap, 2231 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap)); 2232 core_link_read_dpcd(link, DP_PSR_CAPS, 2233 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2234 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw)); 2235 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) { 2236 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY, 2237 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap, 2238 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)); 2239 } 2240 } 2241 2242 /* 2243 * ALPM is only valid for eDP v1.4 or higher. 2244 */ 2245 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14) 2246 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP, 2247 &link->dpcd_caps.alpm_caps.raw, 2248 sizeof(link->dpcd_caps.alpm_caps.raw)); 2249 2250 /* 2251 * Read REPLAY info 2252 */ 2253 core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE, 2254 &link->dpcd_caps.pr_info.pixel_deviation_per_line, 2255 sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line)); 2256 core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE, 2257 &link->dpcd_caps.pr_info.max_deviation_line, 2258 sizeof(link->dpcd_caps.pr_info.max_deviation_line)); 2259 2260 /* 2261 * OLED Emission Rate info 2262 */ 2263 if (link->dpcd_sink_ext_caps.bits.emission_output) 2264 core_link_read_dpcd(link, DP_SINK_EMISSION_RATE, 2265 (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate, 2266 sizeof(link->dpcd_caps.edp_oled_emission_rate)); 2267 2268 /* 2269 * Read DRR granularity 2270 */ 2271 core_link_read_dpcd(link, DP_SINK_DRR_GRANULARITY, 2272 (uint8_t *)&link->dpcd_caps.drr_granularity, 2273 sizeof(link->dpcd_caps.drr_granularity)); 2274 2275 /* 2276 * Read Multi-SST (Single Stream Transport) capability 2277 * for eDP version 1.4 or higher. 2278 */ 2279 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14) 2280 core_link_read_dpcd( 2281 link, 2282 DP_EDP_MSO_LINK_CAPABILITIES, 2283 (uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported, 2284 sizeof(link->dpcd_caps.mso_cap_sst_links_supported)); 2285 /* 2286 * Read eDP general capability 2 2287 */ 2288 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, 2289 (uint8_t *)&link->dpcd_caps.dp_edp_general_cap_2, 2290 sizeof(link->dpcd_caps.dp_edp_general_cap_2)); 2291 } 2292 2293 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) 2294 { 2295 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 2296 struct resource_pool *res_pool = link->dc->res_pool; 2297 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 2298 2299 if (!max_link_enc_cap) { 2300 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__); 2301 return false; 2302 } 2303 2304 if (!link->dc->config.unify_link_enc_assignment) 2305 link_enc = link_enc_cfg_get_link_enc(link); 2306 ASSERT(link_enc); 2307 2308 if (link_enc && link_enc->funcs->get_max_link_cap) { 2309 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap); 2310 return true; 2311 } 2312 2313 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__); 2314 max_link_enc_cap->lane_count = 1; 2315 max_link_enc_cap->link_rate = 6; 2316 return false; 2317 } 2318 2319 const struct dc_link_settings *dp_get_verified_link_cap( 2320 const struct dc_link *link) 2321 { 2322 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 2323 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) 2324 return &link->preferred_link_setting; 2325 return &link->verified_link_cap; 2326 } 2327 2328 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) 2329 { 2330 struct dc_link_settings max_link_cap = {0}; 2331 enum dc_lane_count lttpr_max_lane_count; 2332 enum dc_link_rate lttpr_max_link_rate; 2333 enum dc_link_rate cable_max_link_rate; 2334 struct resource_context *res_ctx = &link->dc->current_state->res_ctx; 2335 struct resource_pool *res_pool = link->dc->res_pool; 2336 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link); 2337 bool is_uhbr13_5_supported = true; 2338 2339 if (!link->dc->config.unify_link_enc_assignment) 2340 link_enc = link_enc_cfg_get_link_enc(link); 2341 ASSERT(link_enc); 2342 2343 /* get max link encoder capability */ 2344 if (link_enc) 2345 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); 2346 2347 /* Lower link settings based on sink's link cap */ 2348 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) 2349 max_link_cap.lane_count = 2350 link->reported_link_cap.lane_count; 2351 if (link->reported_link_cap.link_rate < max_link_cap.link_rate) 2352 max_link_cap.link_rate = 2353 link->reported_link_cap.link_rate; 2354 if (link->reported_link_cap.link_spread < 2355 max_link_cap.link_spread) 2356 max_link_cap.link_spread = 2357 link->reported_link_cap.link_spread; 2358 2359 if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5) 2360 is_uhbr13_5_supported = false; 2361 2362 /* Lower link settings based on cable attributes 2363 * Cable ID is a DP2 feature to identify max certified link rate that 2364 * a cable can carry. The cable identification method requires both 2365 * cable and display hardware support. Since the specs comes late, it is 2366 * anticipated that the first round of DP2 cables and displays may not 2367 * be fully compatible to reliably return cable ID data. Therefore the 2368 * decision of our cable id policy is that if the cable can return non 2369 * zero cable id data, we will take cable's link rate capability into 2370 * account. However if we get zero data, the cable link rate capability 2371 * is considered inconclusive. In this case, we will not take cable's 2372 * capability into account to avoid of over limiting hardware capability 2373 * from users. The max overall link rate capability is still determined 2374 * after actual dp pre-training. Cable id is considered as an auxiliary 2375 * method of determining max link bandwidth capability. 2376 */ 2377 cable_max_link_rate = get_cable_max_link_rate(link); 2378 2379 if (!link->dc->debug.ignore_cable_id && 2380 cable_max_link_rate != LINK_RATE_UNKNOWN) { 2381 if (cable_max_link_rate < max_link_cap.link_rate) 2382 max_link_cap.link_rate = cable_max_link_rate; 2383 2384 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY && 2385 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2) 2386 is_uhbr13_5_supported = false; 2387 } 2388 2389 /* account for lttpr repeaters cap 2390 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). 2391 */ 2392 if (dp_is_lttpr_present(link)) { 2393 2394 /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */ 2395 if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) { 2396 lttpr_max_lane_count = get_lttpr_max_lane_count(link); 2397 2398 if (lttpr_max_lane_count < max_link_cap.lane_count) 2399 max_link_cap.lane_count = lttpr_max_lane_count; 2400 2401 lttpr_max_link_rate = get_lttpr_max_link_rate(link); 2402 2403 if (lttpr_max_link_rate < max_link_cap.link_rate) 2404 max_link_cap.link_rate = lttpr_max_link_rate; 2405 2406 if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) 2407 is_uhbr13_5_supported = false; 2408 } 2409 2410 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n", 2411 __func__, 2412 max_link_cap.lane_count, 2413 max_link_cap.link_rate); 2414 } 2415 2416 if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 && 2417 !is_uhbr13_5_supported) 2418 max_link_cap.link_rate = LINK_RATE_UHBR10; 2419 2420 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING && 2421 link->dc->debug.disable_uhbr) 2422 max_link_cap.link_rate = LINK_RATE_HIGH3; 2423 2424 return max_link_cap; 2425 } 2426 2427 static bool dp_verify_link_cap( 2428 struct dc_link *link, 2429 struct dc_link_settings *known_limit_link_setting, 2430 int *fail_count) 2431 { 2432 struct dc_link_settings cur_link_settings = {0}; 2433 struct dc_link_settings max_link_settings = *known_limit_link_setting; 2434 bool success = false; 2435 bool skip_video_pattern; 2436 enum clock_source_id dp_cs_id = get_clock_source_id(link); 2437 enum link_training_result status = LINK_TRAINING_SUCCESS; 2438 union hpd_irq_data irq_data; 2439 struct link_resource link_res; 2440 2441 memset(&irq_data, 0, sizeof(irq_data)); 2442 cur_link_settings = max_link_settings; 2443 2444 /* Grant extended timeout request */ 2445 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { 2446 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; 2447 2448 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); 2449 } 2450 2451 do { 2452 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings)) 2453 continue; 2454 2455 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW; 2456 dp_enable_link_phy( 2457 link, 2458 &link_res, 2459 link->connector_signal, 2460 dp_cs_id, 2461 &cur_link_settings); 2462 2463 status = dp_perform_link_training( 2464 link, 2465 &link_res, 2466 &cur_link_settings, 2467 skip_video_pattern); 2468 2469 if (status == LINK_TRAINING_SUCCESS) { 2470 success = true; 2471 fsleep(1000); 2472 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK && 2473 dp_parse_link_loss_status( 2474 link, 2475 &irq_data)) 2476 (*fail_count)++; 2477 } else if (status == LINK_TRAINING_LINK_LOSS) { 2478 success = true; 2479 (*fail_count)++; 2480 } else { 2481 (*fail_count)++; 2482 } 2483 dp_trace_lt_total_count_increment(link, true); 2484 dp_trace_lt_result_update(link, status, true); 2485 dp_disable_link_phy(link, &link_res, link->connector_signal); 2486 } while (!success && decide_fallback_link_setting(link, 2487 &max_link_settings, &cur_link_settings, status)); 2488 2489 link->verified_link_cap = success ? 2490 cur_link_settings : fail_safe_link_settings; 2491 return success; 2492 } 2493 2494 bool dp_verify_link_cap_with_retries( 2495 struct dc_link *link, 2496 struct dc_link_settings *known_limit_link_setting, 2497 int attempts) 2498 { 2499 int i = 0; 2500 bool success = false; 2501 int fail_count = 0; 2502 struct dc_link_settings last_verified_link_cap = fail_safe_link_settings; 2503 2504 dp_trace_detect_lt_init(link); 2505 2506 DC_LOG_HW_LINK_TRAINING("%s: Link[%d] LinkRate=0x%x LaneCount=%d", 2507 __func__, link->link_index, 2508 known_limit_link_setting->link_rate, 2509 known_limit_link_setting->lane_count); 2510 2511 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C && 2512 link->dc->debug.usbc_combo_phy_reset_wa) 2513 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting); 2514 2515 dp_trace_set_lt_start_timestamp(link, false); 2516 for (i = 0; i < attempts; i++) { 2517 enum dc_connection_type type = dc_connection_none; 2518 2519 memset(&link->verified_link_cap, 0, 2520 sizeof(struct dc_link_settings)); 2521 if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) { 2522 link->verified_link_cap = fail_safe_link_settings; 2523 break; 2524 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) { 2525 last_verified_link_cap = link->verified_link_cap; 2526 if (fail_count == 0) { 2527 success = true; 2528 break; 2529 } 2530 } else { 2531 link->verified_link_cap = last_verified_link_cap; 2532 } 2533 2534 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2535 * current link and processing the pending HPD. Since the training is failed, we should just brak 2536 * the loop so that we have chance to process the pending HPD. 2537 */ 2538 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) 2539 break; 2540 2541 fsleep(10 * 1000); 2542 } 2543 2544 dp_trace_lt_fail_count_update(link, fail_count, true); 2545 dp_trace_set_lt_end_timestamp(link, true); 2546 2547 DC_LOG_HW_LINK_TRAINING("%s: Link[%d] Exit. is_success=%d fail_count=%d", 2548 __func__, link->link_index, 2549 success, 2550 fail_count); 2551 2552 return success; 2553 } 2554 2555 /* 2556 * Check if there is a native DP or passive DP-HDMI dongle connected 2557 */ 2558 bool dp_is_sink_present(struct dc_link *link) 2559 { 2560 enum gpio_result gpio_result; 2561 uint32_t clock_pin = 0; 2562 uint8_t retry = 0; 2563 struct ddc *ddc; 2564 2565 enum connector_id connector_id = 2566 dal_graphics_object_id_get_connector_id(link->link_id); 2567 2568 bool present = 2569 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 2570 (connector_id == CONNECTOR_ID_EDP) || 2571 (connector_id == CONNECTOR_ID_USBC)); 2572 2573 /* We can't perform the step below for ASICs with no Native 2574 * I2C signaling support on DP connectors, so skip it. 2575 */ 2576 if (link->ctx->dc->config.dp_connector_no_native_i2c && link->no_ddc_pin) 2577 return present; 2578 2579 ddc = get_ddc_pin(link->ddc); 2580 2581 if (!ddc) { 2582 BREAK_TO_DEBUGGER(); 2583 return present; 2584 } 2585 2586 /* Open GPIO and set it to I2C mode */ 2587 /* Note: this GpioMode_Input will be converted 2588 * to GpioConfigType_I2cAuxDualMode in GPIO component, 2589 * which indicates we need additional delay 2590 */ 2591 2592 if (dal_ddc_open(ddc, GPIO_MODE_INPUT, 2593 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) { 2594 dal_ddc_close(ddc); 2595 2596 return present; 2597 } 2598 2599 /* 2600 * Read GPIO: DP sink is present if both clock and data pins are zero 2601 * 2602 * [W/A] plug-unplug DP cable, sometimes customer board has 2603 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI 2604 * then monitor can't br light up. Add retry 3 times 2605 * But in real passive dongle, it need additional 3ms to detect 2606 */ 2607 do { 2608 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin); 2609 ASSERT(gpio_result == GPIO_RESULT_OK); 2610 if (clock_pin) 2611 fsleep(1000); 2612 else 2613 break; 2614 } while (retry++ < 3); 2615 2616 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin; 2617 2618 dal_ddc_close(ddc); 2619 2620 return present; 2621 } 2622 2623 uint8_t dp_get_lttpr_count(struct dc_link *link) 2624 { 2625 if (dp_is_lttpr_present(link)) 2626 return dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); 2627 2628 return 0; 2629 } 2630 2631 void edp_get_alpm_support(struct dc_link *link, 2632 bool *auxless_support, 2633 bool *auxwake_support) 2634 { 2635 bool lttpr_present = dp_is_lttpr_present(link); 2636 2637 if (auxless_support == NULL || auxwake_support == NULL) 2638 return; 2639 2640 *auxless_support = false; 2641 *auxwake_support = false; 2642 2643 if (!dc_is_embedded_signal(link->connector_signal)) 2644 return; 2645 2646 if (link->dpcd_caps.alpm_caps.bits.AUX_LESS_ALPM_CAP) { 2647 if (lttpr_present) { 2648 if (link->dpcd_caps.lttpr_caps.alpm.bits.AUX_LESS_ALPM_SUPPORTED) 2649 *auxless_support = true; 2650 } else 2651 *auxless_support = true; 2652 } 2653 2654 if (link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP) { 2655 if (!lttpr_present) 2656 *auxwake_support = true; 2657 } 2658 } 2659