1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28
29 #include "core_types.h"
30 #include "link_encoder.h"
31 #include "dcn31/dcn31_dio_link_encoder.h"
32 #include "dcn32/dcn32_dio_link_encoder.h"
33 #include "dcn401_dio_link_encoder.h"
34 #include "stream_encoder.h"
35 #include "dc_bios_types.h"
36
37 #include "gpio_service_interface.h"
38
39 #ifndef MIN
40 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
41 #endif
42
43 #define CTX \
44 enc10->base.ctx
45 #define DC_LOGGER \
46 enc10->base.ctx->logger
47
48 #define REG(reg)\
49 (enc10->link_regs->reg)
50
51 #undef FN
52 #define FN(reg_name, field_name) \
53 enc10->link_shift->field_name, enc10->link_mask->field_name
54
55 #define AUX_REG(reg)\
56 (enc10->aux_regs->reg)
57
58 #define AUX_REG_READ(reg_name) \
59 dm_read_reg(CTX, AUX_REG(reg_name))
60
61 #define AUX_REG_WRITE(reg_name, val) \
62 dm_write_reg(CTX, AUX_REG(reg_name), val)
63
64 #ifndef MIN
65 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
66 #endif
67
enc401_hw_init(struct link_encoder * enc)68 void enc401_hw_init(struct link_encoder *enc)
69 {
70 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
71
72 /*
73 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
74 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
75 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
76 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
77 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
78 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
79 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
80 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
81 */
82
83 /*
84 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
85 AUX_RX_START_WINDOW = 1 [6:4]
86 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
87 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
88 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
89 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
90 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
91 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
92 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
93 AUX_RX_DETECTION_THRESHOLD [30:28] = 1
94 */
95 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
96
97 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
98
99 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
100 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
101 // 27MHz -> 0xd
102 // 100MHz -> 0x32
103 // 48MHz -> 0x18
104
105 // Set TMDS_CTL0 to 1. This is a legacy setting.
106 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
107
108 dcn10_aux_initialize(enc10);
109 }
110
111
dcn401_link_encoder_enable_dp_output(struct link_encoder * enc,const struct dc_link_settings * link_settings,enum clock_source_id clock_source)112 void dcn401_link_encoder_enable_dp_output(
113 struct link_encoder *enc,
114 const struct dc_link_settings *link_settings,
115 enum clock_source_id clock_source)
116 {
117 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
118 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
119 return;
120 }
121 }
122
dcn401_link_encoder_setup(struct link_encoder * enc,enum signal_type signal)123 void dcn401_link_encoder_setup(
124 struct link_encoder *enc,
125 enum signal_type signal)
126 {
127 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
128
129 switch (signal) {
130 case SIGNAL_TYPE_EDP:
131 case SIGNAL_TYPE_DISPLAY_PORT:
132 /* DP SST */
133 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);
134 break;
135 case SIGNAL_TYPE_DVI_SINGLE_LINK:
136 case SIGNAL_TYPE_DVI_DUAL_LINK:
137 /* TMDS-DVI */
138 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);
139 break;
140 case SIGNAL_TYPE_HDMI_TYPE_A:
141 /* TMDS-HDMI */
142 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);
143 break;
144 case SIGNAL_TYPE_DISPLAY_PORT_MST:
145 /* DP MST */
146 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);
147 break;
148 default:
149 ASSERT_CRITICAL(false);
150 /* invalid mode ! */
151 break;
152 }
153 REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);
154 REG_UPDATE(DIG_BE_EN_CNTL, DIG_BE_ENABLE, 1);
155 }
156
dcn401_is_dig_enabled(struct link_encoder * enc)157 bool dcn401_is_dig_enabled(struct link_encoder *enc)
158 {
159 uint32_t clk_enabled;
160 uint32_t dig_enabled;
161 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
162
163 REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &clk_enabled);
164 REG_GET(DIG_BE_EN_CNTL, DIG_BE_ENABLE, &dig_enabled);
165 return (clk_enabled == 1 && dig_enabled == 1);
166 }
167
dcn401_get_dig_mode(struct link_encoder * enc)168 enum signal_type dcn401_get_dig_mode(
169 struct link_encoder *enc)
170 {
171 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
172 uint32_t value;
173 REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value);
174 switch (value) {
175 case 0:
176 return SIGNAL_TYPE_DISPLAY_PORT;
177 case 2:
178 return SIGNAL_TYPE_DVI_SINGLE_LINK;
179 case 3:
180 return SIGNAL_TYPE_HDMI_TYPE_A;
181 case 5:
182 return SIGNAL_TYPE_DISPLAY_PORT_MST;
183 default:
184 return SIGNAL_TYPE_NONE;
185 }
186 }
187
188 static const struct link_encoder_funcs dcn401_link_enc_funcs = {
189 .read_state = link_enc2_read_state,
190 .validate_output_with_stream =
191 dcn30_link_encoder_validate_output_with_stream,
192 .hw_init = enc401_hw_init,
193 .setup = dcn401_link_encoder_setup,
194 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
195 .enable_dp_output = dcn401_link_encoder_enable_dp_output,
196 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
197 .disable_output = dcn10_link_encoder_disable_output,
198 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
199 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
200 .update_mst_stream_allocation_table =
201 dcn10_link_encoder_update_mst_stream_allocation_table,
202 .psr_program_dp_dphy_fast_training =
203 dcn10_psr_program_dp_dphy_fast_training,
204 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
205 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
206 .enable_hpd = dcn10_link_encoder_enable_hpd,
207 .disable_hpd = dcn10_link_encoder_disable_hpd,
208 .is_dig_enabled = dcn401_is_dig_enabled,
209 .destroy = dcn10_link_encoder_destroy,
210 .fec_set_enable = enc2_fec_set_enable,
211 .fec_set_ready = enc2_fec_set_ready,
212 .fec_is_active = enc2_fec_is_active,
213 .get_dig_frontend = dcn10_get_dig_frontend,
214 .get_dig_mode = dcn401_get_dig_mode,
215 .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
216 .get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
217 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
218 };
219
dcn401_link_encoder_construct(struct dcn20_link_encoder * enc20,const struct encoder_init_data * init_data,const struct encoder_feature_support * enc_features,const struct dcn10_link_enc_registers * link_regs,const struct dcn10_link_enc_aux_registers * aux_regs,const struct dcn10_link_enc_hpd_registers * hpd_regs,const struct dcn10_link_enc_shift * link_shift,const struct dcn10_link_enc_mask * link_mask)220 void dcn401_link_encoder_construct(
221 struct dcn20_link_encoder *enc20,
222 const struct encoder_init_data *init_data,
223 const struct encoder_feature_support *enc_features,
224 const struct dcn10_link_enc_registers *link_regs,
225 const struct dcn10_link_enc_aux_registers *aux_regs,
226 const struct dcn10_link_enc_hpd_registers *hpd_regs,
227 const struct dcn10_link_enc_shift *link_shift,
228 const struct dcn10_link_enc_mask *link_mask)
229 {
230 struct bp_connector_speed_cap_info bp_cap_info = {0};
231 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
232 enum bp_result result = BP_RESULT_OK;
233 struct dcn10_link_encoder *enc10 = &enc20->enc10;
234
235 enc10->base.funcs = &dcn401_link_enc_funcs;
236 enc10->base.ctx = init_data->ctx;
237 enc10->base.id = init_data->encoder;
238
239 enc10->base.hpd_source = init_data->hpd_source;
240 enc10->base.connector = init_data->connector;
241
242
243 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
244
245 enc10->base.features = *enc_features;
246 if (enc10->base.connector.id == CONNECTOR_ID_USBC)
247 enc10->base.features.flags.bits.DP_IS_USB_C = 1;
248
249 enc10->base.transmitter = init_data->transmitter;
250
251 /* set the flag to indicate whether driver poll the I2C data pin
252 * while doing the DP sink detect
253 */
254
255 /* if (dal_adapter_service_is_feature_supported(as,
256 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
257 enc10->base.features.flags.bits.
258 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
259
260 enc10->base.output_signals =
261 SIGNAL_TYPE_DVI_SINGLE_LINK |
262 SIGNAL_TYPE_DVI_DUAL_LINK |
263 SIGNAL_TYPE_LVDS |
264 SIGNAL_TYPE_DISPLAY_PORT |
265 SIGNAL_TYPE_DISPLAY_PORT_MST |
266 SIGNAL_TYPE_EDP |
267 SIGNAL_TYPE_HDMI_TYPE_A;
268
269 enc10->link_regs = link_regs;
270 enc10->aux_regs = aux_regs;
271 enc10->hpd_regs = hpd_regs;
272 enc10->link_shift = link_shift;
273 enc10->link_mask = link_mask;
274
275 switch (enc10->base.transmitter) {
276 case TRANSMITTER_UNIPHY_A:
277 enc10->base.preferred_engine = ENGINE_ID_DIGA;
278 break;
279 case TRANSMITTER_UNIPHY_B:
280 enc10->base.preferred_engine = ENGINE_ID_DIGB;
281 break;
282 case TRANSMITTER_UNIPHY_C:
283 enc10->base.preferred_engine = ENGINE_ID_DIGC;
284 break;
285 case TRANSMITTER_UNIPHY_D:
286 enc10->base.preferred_engine = ENGINE_ID_DIGD;
287 break;
288 case TRANSMITTER_UNIPHY_E:
289 enc10->base.preferred_engine = ENGINE_ID_DIGE;
290 break;
291 default:
292 ASSERT_CRITICAL(false);
293 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
294 }
295
296 /* default to one to mirror Windows behavior */
297 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
298
299 if (bp_funcs->get_connector_speed_cap_info)
300 result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
301 enc10->base.connector, &bp_cap_info);
302
303 /* Override features with DCE-specific values */
304 if (result == BP_RESULT_OK) {
305 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
306 bp_cap_info.DP_HBR2_EN;
307 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
308 bp_cap_info.DP_HBR3_EN;
309 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
310 enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
311 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
312 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
313 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
314 } else {
315 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
316 __func__,
317 result);
318 }
319 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
320 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
321 }
322 }
323