1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dccg.h"
6 #include "clk_mgr_internal.h"
7 #include "dcn401/dcn401_clk_mgr_smu_msg.h"
8 #include "dcn20/dcn20_clk_mgr.h"
9 #include "dce100/dce_clk_mgr.h"
10 #include "dcn31/dcn31_clk_mgr.h"
11 #include "dcn32/dcn32_clk_mgr.h"
12 #include "dcn401/dcn401_clk_mgr.h"
13 #include "reg_helper.h"
14 #include "core_types.h"
15 #include "dm_helpers.h"
16 #include "link.h"
17 #include "dc_state_priv.h"
18 #include "atomfirmware.h"
19
20 #include "dcn401_smu14_driver_if.h"
21
22 #include "dcn/dcn_4_1_0_offset.h"
23 #include "dcn/dcn_4_1_0_sh_mask.h"
24
25 #include "dml/dcn401/dcn401_fpu.h"
26
27 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
28 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E69
29 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E6C
30 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6F
31 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E72
32 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E75
33 #define mmCLK20_CLK2_CLK2_DFS_CNTL 0x1B051
34
35 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
36 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
37 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
38 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
39 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
40 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
45
46 #define REG(reg) \
47 (clk_mgr->regs->reg)
48
49 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
50
51 #define BASE(seg) BASE_INNER(seg)
52
53 #define SR(reg_name)\
54 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
55 reg ## reg_name
56
57 #define CLK_SR_DCN401(reg_name, block, inst)\
58 .reg_name = mm ## block ## _ ## reg_name
59
60 static const struct clk_mgr_registers clk_mgr_regs_dcn401 = {
61 CLK_REG_LIST_DCN401()
62 };
63
64 static const struct clk_mgr_shift clk_mgr_shift_dcn401 = {
65 CLK_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
66 };
67
68 static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {
69 CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)
70 };
71
72 #define TO_DCN401_CLK_MGR(clk_mgr)\
73 container_of(clk_mgr, struct dcn401_clk_mgr, base)
74
dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)75 static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
76 {
77 bool ppclk_dpm_enabled = false;
78
79 switch (clk) {
80 case PPCLK_SOCCLK:
81 ppclk_dpm_enabled =
82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1;
83 break;
84 case PPCLK_UCLK:
85 ppclk_dpm_enabled =
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1;
87 break;
88 case PPCLK_FCLK:
89 ppclk_dpm_enabled =
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1;
91 break;
92 case PPCLK_DISPCLK:
93 ppclk_dpm_enabled =
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1;
95 break;
96 case PPCLK_DPPCLK:
97 ppclk_dpm_enabled =
98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1;
99 break;
100 case PPCLK_DPREFCLK:
101 ppclk_dpm_enabled = false;
102 break;
103 case PPCLK_DCFCLK:
104 ppclk_dpm_enabled =
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1;
106 break;
107 case PPCLK_DTBCLK:
108 ppclk_dpm_enabled =
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1;
110 break;
111 default:
112 ppclk_dpm_enabled = false;
113 }
114
115 ppclk_dpm_enabled &= clk_mgr->smu_present;
116
117 return ppclk_dpm_enabled;
118 }
119
dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)120 static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
121 {
122 bool ppclk_idle_dpm_enabled = false;
123
124 switch (clk) {
125 case PPCLK_UCLK:
126 case PPCLK_FCLK:
127 if (ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
128 clk_mgr->smu_ver >= 0x681800) {
129 ppclk_idle_dpm_enabled = true;
130 } else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
131 clk_mgr->smu_ver >= 0x661300) {
132 ppclk_idle_dpm_enabled = true;
133 }
134 break;
135 default:
136 ppclk_idle_dpm_enabled = false;
137 }
138
139 ppclk_idle_dpm_enabled &= clk_mgr->smu_present;
140
141 return ppclk_idle_dpm_enabled;
142 }
143
dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal * clk_mgr)144 static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)
145 {
146 bool is_df_throttle_opt_enabled = false;
147
148 if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
149 clk_mgr->smu_ver >= 0x663500) {
150 is_df_throttle_opt_enabled = !clk_mgr->base.ctx->dc->debug.force_subvp_df_throttle;
151 }
152
153 is_df_throttle_opt_enabled &= clk_mgr->smu_present;
154
155 return is_df_throttle_opt_enabled;
156 }
157
158 /* Query SMU for all clock states for a particular clock */
dcn401_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)159 static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
160 unsigned int *num_levels)
161 {
162 unsigned int i;
163 char *entry_i = (char *)entry_0;
164
165 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
166
167 if (ret & (1 << 31))
168 /* fine-grained, only min and max */
169 *num_levels = 2;
170 else
171 /* discrete, a number of fixed states */
172 /* will set num_levels to 0 on failure */
173 *num_levels = ret & 0xFF;
174
175 /* if the initial message failed, num_levels will be 0 */
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
177 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
178 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
179 }
180 }
181
dcn401_build_wm_range_table(struct clk_mgr * clk_mgr)182 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
183 {
184 /* legacy */
185 DC_FP_START();
186 dcn401_build_wm_range_table_fpu(clk_mgr);
187 DC_FP_END();
188
189 if (clk_mgr->ctx->dc->debug.using_dml21) {
190 /* For min clocks use as reported by PM FW and report those as min */
191 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
192 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
193
194 /* Set A - Normal - default values */
195 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
196 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
197 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
198 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
199 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
200 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
201
202 /* Set B - Unused on dcn4 */
203 clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
204
205 /* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
206 /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
207 if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
208 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
209 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
210 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
211 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
212 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
213 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
214 } else {
215 clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
216 }
217
218 /* Set 1B - Unused on dcn4 */
219 clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
220 }
221 }
222
dcn401_init_clocks(struct clk_mgr * clk_mgr_base)223 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
224 {
225 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
226 struct clk_limit_num_entries *num_entries_per_clk;
227 unsigned int i;
228
229 if (!clk_mgr_base->bw_params)
230 return;
231
232 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
233
234 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
235 clk_mgr_base->clks.p_state_change_support = true;
236 clk_mgr_base->clks.prev_p_state_change_support = true;
237 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
238 clk_mgr->smu_present = false;
239 clk_mgr->dpm_present = false;
240
241 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
242 clk_mgr->smu_present = true;
243
244 if (!clk_mgr->smu_present)
245 return;
246
247 dcn30_smu_check_driver_if_version(clk_mgr);
248 dcn30_smu_check_msg_header_version(clk_mgr);
249
250 /* DCFCLK */
251 dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
252 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
253 &num_entries_per_clk->num_dcfclk_levels);
254 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
255 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
256 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz)
257 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
258
259 /* SOCCLK */
260 dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
261 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
262 &num_entries_per_clk->num_socclk_levels);
263 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
264 if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
265 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz)
266 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
267
268 /* DTBCLK */
269 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
270 dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
271 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
272 &num_entries_per_clk->num_dtbclk_levels);
273 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
274 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
275 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz)
276 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
277 }
278
279 /* DISPCLK */
280 dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
281 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
282 &num_entries_per_clk->num_dispclk_levels);
283 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
284 if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
285 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz)
286 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
287
288 /* DPPCLK */
289 dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,
290 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
291 &num_entries_per_clk->num_dppclk_levels);
292
293 if (num_entries_per_clk->num_dcfclk_levels &&
294 num_entries_per_clk->num_dtbclk_levels &&
295 num_entries_per_clk->num_dispclk_levels)
296 clk_mgr->dpm_present = true;
297
298 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
299 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++)
300 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
301 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
302 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
303 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
304 }
305
306 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
307 for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++)
308 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
309 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
310 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
311 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
312 }
313
314 /* Get UCLK, update bounding box */
315 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
316
317 /* WM range table */
318 dcn401_build_wm_range_table(clk_mgr_base);
319 }
320
dcn401_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)321 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
322 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
323 {
324 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
325 uint32_t dprefclk_did = 0;
326 uint32_t dcfclk_did = 0;
327 uint32_t dtbclk_did = 0;
328 uint32_t dispclk_did = 0;
329 uint32_t dppclk_did = 0;
330 uint32_t fclk_did = 0;
331 uint32_t target_div = 0;
332
333 /* DFS Slice 0 is used for DISPCLK */
334 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
335 /* DFS Slice 1 is used for DPPCLK */
336 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
337 /* DFS Slice 2 is used for DPREFCLK */
338 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
339 /* DFS Slice 3 is used for DCFCLK */
340 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
341 /* DFS Slice 4 is used for DTBCLK */
342 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
343 /* DFS Slice _ is used for FCLK */
344 fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);
345
346 /* Convert DISPCLK DFS Slice DID to divider*/
347 target_div = dentist_get_divider_from_did(dispclk_did);
348 //Get dispclk in khz
349 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
350 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
351
352 /* Convert DISPCLK DFS Slice DID to divider*/
353 target_div = dentist_get_divider_from_did(dppclk_did);
354 //Get dppclk in khz
355 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
356 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
357
358 /* Convert DPREFCLK DFS Slice DID to divider*/
359 target_div = dentist_get_divider_from_did(dprefclk_did);
360 //Get dprefclk in khz
361 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
362 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
363
364 /* Convert DCFCLK DFS Slice DID to divider*/
365 target_div = dentist_get_divider_from_did(dcfclk_did);
366 //Get dcfclk in khz
367 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
368 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
369
370 /* Convert DTBCLK DFS Slice DID to divider*/
371 target_div = dentist_get_divider_from_did(dtbclk_did);
372 //Get dtbclk in khz
373 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
374 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
375
376 /* Convert DTBCLK DFS Slice DID to divider*/
377 target_div = dentist_get_divider_from_did(fclk_did);
378 //Get fclk in khz
379 regs_and_bypass->fclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
380 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
381 }
382
dcn401_check_native_scaling(struct pipe_ctx * pipe)383 static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)
384 {
385 bool is_native_scaling = false;
386 int width = pipe->plane_state->src_rect.width;
387 int height = pipe->plane_state->src_rect.height;
388
389 if (pipe->stream->timing.h_addressable == width &&
390 pipe->stream->timing.v_addressable == height &&
391 pipe->plane_state->dst_rect.width == width &&
392 pipe->plane_state->dst_rect.height == height)
393 is_native_scaling = true;
394
395 return is_native_scaling;
396 }
397
dcn401_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)398 static void dcn401_auto_dpm_test_log(
399 struct dc_clocks *new_clocks,
400 struct clk_mgr_internal *clk_mgr,
401 struct dc_state *context)
402 {
403 unsigned int mall_ss_size_bytes;
404 int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
405
406 struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
407 int active_pipe_count = 0;
408
409 for (int i = 0; i < MAX_PIPES; i++) {
410 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
411
412 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
413 pipe_ctx_list[active_pipe_count] = pipe_ctx;
414 active_pipe_count++;
415 }
416 }
417
418 msleep(5);
419
420 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
421
422 struct clk_log_info log_info = {0};
423 struct clk_state_registers_and_bypass clk_register_dump;
424
425 dcn401_dump_clk_registers(&clk_register_dump, &clk_mgr->base, &log_info);
426
427 // Overrides for these clocks in case there is no p_state change support
428 dramclk_khz_override = new_clocks->dramclk_khz;
429 fclk_khz_override = new_clocks->fclk_khz;
430
431 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
432
433 if (!new_clocks->p_state_change_support)
434 dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
435
436 if (!new_clocks->fclk_p_state_change_support)
437 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
438
439
440 ////////////////////////////////////////////////////////////////////////////
441 // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
442 // anywhere other than at the very end of the string.
443 //
444 // Formatting example (make sure to have " - " between each entry):
445 //
446 // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
447 ////////////////////////////////////////////////////////////////////////////
448 if (active_pipe_count > 0 &&
449 new_clocks->dramclk_khz > 0 &&
450 new_clocks->fclk_khz > 0 &&
451 new_clocks->dcfclk_khz > 0 &&
452 new_clocks->dppclk_khz > 0) {
453
454 uint32_t pix_clk_list[MAX_PIPES] = {0};
455 int p_state_list[MAX_PIPES] = {0};
456 int disp_src_width_list[MAX_PIPES] = {0};
457 int disp_src_height_list[MAX_PIPES] = {0};
458 uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
459 bool is_scaled_list[MAX_PIPES] = {0};
460
461 for (int i = 0; i < active_pipe_count; i++) {
462 struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
463 uint64_t refresh_rate;
464
465 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
466 p_state_list[i] = curr_pipe_ctx->p_state_type;
467
468 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
469 curr_pipe_ctx->stream->timing.v_total
470 * (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
471 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
472 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
473 disp_src_refresh_list[i] = refresh_rate;
474
475 if (curr_pipe_ctx->plane_state) {
476 is_scaled_list[i] = !(dcn401_check_native_scaling(curr_pipe_ctx));
477 disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
478 disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
479 }
480 }
481
482 DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
483 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
484 "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
485 "dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
486 "pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
487 "p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
488 "pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
489 "pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
490 "pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
491 "pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
492 dramclk_khz_override,
493 fclk_khz_override,
494 new_clocks->dcfclk_khz,
495 new_clocks->dppclk_khz,
496 clk_register_dump.dispclk,
497 clk_register_dump.dppclk,
498 clk_register_dump.dprefclk,
499 clk_register_dump.dcfclk,
500 clk_register_dump.dtbclk,
501 clk_register_dump.fclk,
502 pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
503 mall_ss_size_bytes,
504 p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
505 disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
506 disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
507 disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
508 disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
509 }
510 }
511
dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)512 static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
513 struct dc_state *context,
514 int ref_dtbclk_khz)
515 {
516 int i;
517 struct dccg *dccg = clk_mgr->dccg;
518 struct pipe_ctx *otg_master;
519 bool use_hpo_encoder;
520
521
522 for (i = 0; i < context->stream_count; i++) {
523 otg_master = resource_get_otg_master_for_stream(
524 &context->res_ctx, context->streams[i]);
525 ASSERT(otg_master);
526 ASSERT(otg_master->clock_source);
527 ASSERT(otg_master->clock_source->funcs->program_pix_clk);
528 ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
529
530 use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
531 if (!use_hpo_encoder)
532 continue;
533
534 if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
535 otg_master->clock_source->funcs->program_pix_clk(
536 otg_master->clock_source,
537 &otg_master->stream_res.pix_clk_params,
538 dccg->ctx->dc->link_srv->dp_get_encoding_format(
539 &otg_master->link_config.dp_link_settings),
540 &otg_master->pll_settings);
541 }
542 }
543
dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower,int ref_dppclk_khz)544 static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
545 struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
546 {
547 int i;
548
549 clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
550 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
551 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
552
553 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
554
555 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
556 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
557 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
558 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
559 * In this case just continue in loop
560 */
561 continue;
562 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
563 /* The software state is not valid if dpp resource is NULL and
564 * dppclk_khz > 0.
565 */
566 ASSERT(false);
567 continue;
568 }
569
570 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
571
572 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
573 clk_mgr->dccg->funcs->update_dpp_dto(
574 clk_mgr->dccg, dpp_inst, dppclk_khz);
575 }
576 }
577
dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,int requested_clk_khz)578 static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
579 {
580 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
581 return 0;
582
583 /*
584 * SMU set hard min interface takes requested clock in mhz and return
585 * actual clock configured in khz. If we floor requested clk to mhz,
586 * there is a chance that the actual clock configured in khz is less
587 * than requested. If we ceil it to mhz, there is a chance that it
588 * unnecessarily dumps up to a higher dpm level, which burns more power.
589 * The solution is to set by flooring it to mhz first. If the actual
590 * clock returned is less than requested, then we will ceil the
591 * requested value to mhz and call it again.
592 */
593 int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
594
595 if (actual_clk_khz < requested_clk_khz)
596 actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
597
598 return actual_clk_khz;
599 }
600
dcn401_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)601 static void dcn401_update_clocks_update_dentist(
602 struct clk_mgr_internal *clk_mgr,
603 struct dc_state *context)
604 {
605 uint32_t new_disp_divider = 0;
606 uint32_t new_dispclk_wdivider = 0;
607 uint32_t dentist_dispclk_wdivider_readback = 0;
608 struct dc *dc = clk_mgr->base.ctx->dc;
609
610 if (clk_mgr->base.clks.dispclk_khz == 0)
611 return;
612
613 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
614 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
615
616 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
617
618 if (dc->debug.override_dispclk_programming) {
619 REG_GET(DENTIST_DISPCLK_CNTL,
620 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
621
622 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
623 REG_UPDATE(DENTIST_DISPCLK_CNTL,
624 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
625 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
626 }
627 }
628
629 }
630
dcn401_execute_block_sequence(struct clk_mgr * clk_mgr_base,unsigned int num_steps)631 static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
632 {
633 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
634 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
635
636 unsigned int i;
637 union dcn401_clk_mgr_block_sequence_params *params;
638
639 /* execute sequence */
640 for (i = 0; i < num_steps; i++) {
641 params = &clk_mgr401->block_sequence[i].params;
642
643 switch (clk_mgr401->block_sequence[i].func) {
644 case CLK_MGR401_READ_CLOCKS_FROM_DENTIST:
645 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
646 break;
647 case CLK_MGR401_UPDATE_NUM_DISPLAYS:
648 dcn401_smu_set_num_of_displays(clk_mgr_internal,
649 params->update_num_displays_params.num_displays);
650 break;
651 case CLK_MGR401_UPDATE_HARDMIN_PPCLK:
652 if (params->update_hardmin_params.response)
653 *params->update_hardmin_params.response = dcn401_smu_set_hard_min_by_freq(
654 clk_mgr_internal,
655 params->update_hardmin_params.ppclk,
656 params->update_hardmin_params.freq_mhz);
657 else
658 dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,
659 params->update_hardmin_params.ppclk,
660 params->update_hardmin_params.freq_mhz);
661 break;
662 case CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED:
663 if (params->update_hardmin_optimized_params.response)
664 *params->update_hardmin_optimized_params.response = dcn401_set_hard_min_by_freq_optimized(
665 clk_mgr_internal,
666 params->update_hardmin_optimized_params.ppclk,
667 params->update_hardmin_optimized_params.freq_khz);
668 else
669 dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,
670 params->update_hardmin_optimized_params.ppclk,
671 params->update_hardmin_optimized_params.freq_khz);
672 break;
673 case CLK_MGR401_UPDATE_ACTIVE_HARDMINS:
674 dcn401_smu_set_active_uclk_fclk_hardmin(
675 clk_mgr_internal,
676 params->update_idle_hardmin_params.uclk_mhz,
677 params->update_idle_hardmin_params.fclk_mhz);
678 break;
679 case CLK_MGR401_UPDATE_IDLE_HARDMINS:
680 dcn401_smu_set_idle_uclk_fclk_hardmin(
681 clk_mgr_internal,
682 params->update_idle_hardmin_params.uclk_mhz,
683 params->update_idle_hardmin_params.fclk_mhz);
684 break;
685 case CLK_MGR401_UPDATE_SUBVP_HARDMINS:
686 dcn401_smu_set_subvp_uclk_fclk_hardmin(
687 clk_mgr_internal,
688 params->update_idle_hardmin_params.uclk_mhz,
689 params->update_idle_hardmin_params.fclk_mhz);
690 break;
691 case CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK:
692 dcn401_smu_set_min_deep_sleep_dcef_clk(
693 clk_mgr_internal,
694 params->update_deep_sleep_dcfclk_params.freq_mhz);
695 break;
696 case CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT:
697 dcn401_smu_send_fclk_pstate_message(
698 clk_mgr_internal,
699 params->update_pstate_support_params.support);
700 break;
701 case CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT:
702 dcn401_smu_send_uclk_pstate_message(
703 clk_mgr_internal,
704 params->update_pstate_support_params.support);
705 break;
706 case CLK_MGR401_UPDATE_CAB_FOR_UCLK:
707 dcn401_smu_send_cab_for_uclk_message(
708 clk_mgr_internal,
709 params->update_cab_for_uclk_params.num_ways);
710 break;
711 case CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK:
712 dcn401_smu_wait_for_dmub_ack_mclk(
713 clk_mgr_internal,
714 params->update_wait_for_dmub_ack_params.enable);
715 break;
716 case CLK_MGR401_INDICATE_DRR_STATUS:
717 dcn401_smu_indicate_drr_status(
718 clk_mgr_internal,
719 params->indicate_drr_status_params.mod_drr_for_pstate);
720 break;
721 case CLK_MGR401_UPDATE_DPPCLK_DTO:
722 dcn401_update_clocks_update_dpp_dto(
723 clk_mgr_internal,
724 params->update_dppclk_dto_params.context,
725 params->update_dppclk_dto_params.safe_to_lower,
726 *params->update_dppclk_dto_params.ref_dppclk_khz);
727 break;
728 case CLK_MGR401_UPDATE_DTBCLK_DTO:
729 dcn401_update_clocks_update_dtb_dto(
730 clk_mgr_internal,
731 params->update_dtbclk_dto_params.context,
732 *params->update_dtbclk_dto_params.ref_dtbclk_khz);
733 break;
734 case CLK_MGR401_UPDATE_DENTIST:
735 dcn401_update_clocks_update_dentist(
736 clk_mgr_internal,
737 params->update_dentist_params.context);
738 break;
739 case CLK_MGR401_UPDATE_PSR_WAIT_LOOP:
740 params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(
741 params->update_psr_wait_loop_params.dmcu,
742 params->update_psr_wait_loop_params.wait);
743 break;
744 default:
745 /* this should never happen */
746 BREAK_TO_DEBUGGER();
747 break;
748 }
749 }
750 }
751
dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)752 static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
753 struct clk_mgr *clk_mgr_base,
754 struct dc_state *context,
755 struct dc_clocks *new_clocks,
756 bool safe_to_lower)
757 {
758 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
759 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
760 struct dc *dc = clk_mgr_base->ctx->dc;
761 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
762 bool enter_display_off = false;
763 bool update_active_fclk = false;
764 bool update_active_uclk = false;
765 bool update_idle_fclk = false;
766 bool update_idle_uclk = false;
767 bool update_subvp_prefetch_dramclk = false;
768 bool update_subvp_prefetch_fclk = false;
769 bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
770 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&
771 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
772 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);
773 bool is_df_throttle_opt_enabled = is_idle_dpm_enabled &&
774 dcn401_is_df_throttle_opt_enabled(clk_mgr_internal);
775 int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
776 int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
777 int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
778 int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
779 int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
780 int subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);
781 int subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);
782
783 unsigned int num_steps = 0;
784
785 int display_count;
786 bool fclk_p_state_change_support, uclk_p_state_change_support;
787
788 /* CLK_MGR401_UPDATE_NUM_DISPLAYS */
789 if (clk_mgr_internal->smu_present) {
790 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
791
792 if (display_count == 0)
793 enter_display_off = true;
794
795 if (enter_display_off == safe_to_lower) {
796 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;
797 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;
798 num_steps++;
799 }
800 }
801
802 /* CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT */
803 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
804 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
805 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
806 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
807 update_active_fclk = true;
808 update_idle_fclk = true;
809
810 /* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW (message not supported on DCN401)*/
811 // if (clk_mgr_base->clks.fclk_p_state_change_support) {
812 // /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
813 // if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
814 // block_sequence[num_steps].params.update_pstate_support_params.support = true;
815 // block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
816 // num_steps++;
817 // }
818 // }
819 }
820
821 if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
822 /* when P-State switching disabled, set UCLK min = max */
823 idle_fclk_mhz =
824 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
825 active_fclk_mhz = idle_fclk_mhz;
826 }
827
828 /* UPDATE DCFCLK */
829 if (dc->debug.force_min_dcfclk_mhz > 0)
830 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
831 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
832
833 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
834 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
835 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
836 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
837 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
838 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
839 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
840 num_steps++;
841 }
842 }
843
844 /* CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK */
845 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
846 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
847 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
848 block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
849 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
850 num_steps++;
851 }
852 }
853
854 /* SOCCLK */
855 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
856 /* We don't actually care about socclk, don't notify SMU of hard min */
857 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
858
859 /* UCLK */
860 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
861 new_clocks->fw_based_mclk_switching) {
862 /* enable FAMS features */
863 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
864
865 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
866 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
867 num_steps++;
868
869 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
870 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
871 num_steps++;
872 }
873
874 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
875 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
876 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
877 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
878 /* increase num ways for subvp */
879 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
880 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
881 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
882 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
883 num_steps++;
884 }
885 }
886
887 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
888 uclk_p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
889 if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
890 clk_mgr_base->clks.p_state_change_support = uclk_p_state_change_support;
891 update_active_uclk = true;
892 update_idle_uclk = true;
893
894 if (clk_mgr_base->clks.p_state_change_support) {
895 /* enable UCLK switching */
896 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
897 block_sequence[num_steps].params.update_pstate_support_params.support = true;
898 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
899 num_steps++;
900 }
901 }
902 }
903
904 if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
905 /* when P-State switching disabled, set UCLK min = max */
906 if (dc->clk_mgr->dc_mode_softmax_enabled) {
907 /* will never have the functional UCLK min above the softmax
908 * since we calculate mode support based on softmax being the max UCLK
909 * frequency.
910 */
911 active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
912 } else {
913 active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
914 }
915 idle_uclk_mhz = active_uclk_mhz;
916 }
917
918 /* Always update saved value, even if new value not set due to P-State switching unsupported */
919 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
920 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
921
922 if (clk_mgr_base->clks.p_state_change_support) {
923 update_active_uclk = true;
924 active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
925 }
926 }
927
928 if (should_set_clock(safe_to_lower, new_clocks->idle_dramclk_khz, clk_mgr_base->clks.idle_dramclk_khz)) {
929 clk_mgr_base->clks.idle_dramclk_khz = new_clocks->idle_dramclk_khz;
930
931 if (clk_mgr_base->clks.p_state_change_support) {
932 update_idle_uclk = true;
933 idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
934 }
935 }
936
937 if (should_set_clock(safe_to_lower, new_clocks->subvp_prefetch_dramclk_khz, clk_mgr_base->clks.subvp_prefetch_dramclk_khz)) {
938 clk_mgr_base->clks.subvp_prefetch_dramclk_khz = new_clocks->subvp_prefetch_dramclk_khz;
939 update_subvp_prefetch_dramclk = true;
940 subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);
941 }
942
943 /* FCLK */
944 /* Always update saved value, even if new value not set due to P-State switching unsupported */
945 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
946 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
947
948 if (clk_mgr_base->clks.fclk_p_state_change_support) {
949 update_active_fclk = true;
950 active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
951 }
952 }
953
954 if (should_set_clock(safe_to_lower, new_clocks->idle_fclk_khz, clk_mgr_base->clks.idle_fclk_khz)) {
955 clk_mgr_base->clks.idle_fclk_khz = new_clocks->idle_fclk_khz;
956
957 if (clk_mgr_base->clks.fclk_p_state_change_support) {
958 update_idle_fclk = true;
959 idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
960 }
961 }
962
963 if (should_set_clock(safe_to_lower, new_clocks->subvp_prefetch_fclk_khz, clk_mgr_base->clks.subvp_prefetch_fclk_khz)) {
964 clk_mgr_base->clks.subvp_prefetch_fclk_khz = new_clocks->subvp_prefetch_fclk_khz;
965 update_subvp_prefetch_fclk = true;
966 subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);
967 }
968
969 /* When idle DPM is enabled, need to send active and idle hardmins separately */
970 /* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
971 if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
972 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
973 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
974 block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
975 num_steps++;
976 }
977
978 /* CLK_MGR401_UPDATE_IDLE_HARDMINS */
979 if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
980 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
981 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
982 block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
983 num_steps++;
984 }
985
986 /* CLK_MGR401_UPDATE_SUBVP_HARDMINS */
987 if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) {
988 block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;
989 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;
990 block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
991 num_steps++;
992 }
993
994 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
995 if (update_active_uclk || update_idle_uclk) {
996 if (!is_idle_dpm_enabled) {
997 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
998 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
999 block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1000 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1001 num_steps++;
1002 }
1003
1004 /* disable UCLK P-State support if needed */
1005 if (!uclk_p_state_change_support &&
1006 should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support) &&
1007 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1008 block_sequence[num_steps].params.update_pstate_support_params.support = false;
1009 block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1010 num_steps++;
1011 }
1012 }
1013
1014 /* set FCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1015 if (update_active_fclk || update_idle_fclk) {
1016 /* No need to send active FCLK hardmin, automatically set based on DCFCLK */
1017 // if (!is_idle_dpm_enabled) {
1018 // block_sequence[*num_steps].update_hardmin_params.clk_mgr = clk_mgr;
1019 // block_sequence[*num_steps].update_hardmin_params.ppclk = PPCLK_FCLK;
1020 // block_sequence[*num_steps].update_hardmin_params.freq_mhz = active_fclk_mhz;
1021 // block_sequence[*num_steps].update_hardmin_params.response = NULL;
1022 // block_sequence[*num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1023 // (*num_steps)++;
1024 // }
1025
1026 /* disable FCLK P-State support if needed (message not supported on DCN401)*/
1027 // if (!fclk_p_state_change_support &&
1028 // should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
1029 // dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
1030 // block_sequence[num_steps].params.update_pstate_support_params.support = false;
1031 // block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
1032 // num_steps++;
1033 // }
1034 }
1035
1036 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1037 safe_to_lower && !new_clocks->fw_based_mclk_switching) {
1038 /* disable FAMS features */
1039 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1040
1041 block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1042 block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1043 num_steps++;
1044
1045 block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1046 block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1047 num_steps++;
1048 }
1049
1050 /* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1051 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1052 safe_to_lower && clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
1053 /* decrease num ways for subvp */
1054 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1055 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1056 block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1057 block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1058 num_steps++;
1059 }
1060 }
1061
1062 return num_steps;
1063 }
1064
dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)1065 static unsigned int dcn401_build_update_display_clocks_sequence(
1066 struct clk_mgr *clk_mgr_base,
1067 struct dc_state *context,
1068 struct dc_clocks *new_clocks,
1069 bool safe_to_lower)
1070 {
1071 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1072 struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
1073 struct dc *dc = clk_mgr_base->ctx->dc;
1074 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
1075 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
1076 bool force_reset = false;
1077 bool update_dispclk = false;
1078 bool update_dppclk = false;
1079 bool dppclk_lowered = false;
1080
1081 unsigned int num_steps = 0;
1082
1083 /* CLK_MGR401_READ_CLOCKS_FROM_DENTIST */
1084 if (clk_mgr_base->clks.dispclk_khz == 0 ||
1085 (dc->debug.force_clock_mode & 0x1)) {
1086 /* This is from resume or boot up, if forced_clock cfg option used,
1087 * we bypass program dispclk and DPPCLK, but need set them for S3.
1088 * Force_clock_mode 0x1: force reset the clock even it is the same clock
1089 * as long as it is in Passive level.
1090 */
1091 force_reset = true;
1092
1093 clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk;
1094 clk_mgr_base->clks.actual_dispclk_khz = clk_mgr_base->clks.dispclk_khz;
1095
1096 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk;
1097 clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.dppclk_khz;
1098 }
1099
1100 /* DTBCLK */
1101 if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1102 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
1103 }
1104
1105 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
1106 if (!dc->debug.disable_dtb_ref_clk_switch &&
1107 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) && //TODO these should be ceiled
1108 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1109 /* DCCG requires KHz precision for DTBCLK */
1110 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
1111 block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
1112 block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
1113 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1114 num_steps++;
1115
1116 /* Update DTO in DCCG */
1117 block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
1118 block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
1119 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
1120 num_steps++;
1121 }
1122
1123 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
1124 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
1125 dppclk_lowered = true;
1126
1127 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
1128 clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
1129
1130 update_dppclk = true;
1131 }
1132
1133 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
1134 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
1135
1136 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
1137 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;
1138 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;
1139 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1140 num_steps++;
1141
1142 update_dispclk = true;
1143 }
1144
1145 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
1146 if (dppclk_lowered) {
1147 /* if clock is being lowered, increase DTO before lowering refclk */
1148 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1149 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
1150 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1151 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1152 num_steps++;
1153
1154 block_sequence[num_steps].params.update_dentist_params.context = context;
1155 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1156 num_steps++;
1157
1158 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1159 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1160 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1161 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1162 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1163 num_steps++;
1164
1165 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1166 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1167 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1168 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1169 num_steps++;
1170 }
1171 } else {
1172 /* if clock is being raised, increase refclk before lowering DTO */
1173 if (update_dppclk && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1174 block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1175 block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1176 block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1177 block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1178 num_steps++;
1179 }
1180
1181 if (update_dppclk || update_dispclk) {
1182 block_sequence[num_steps].params.update_dentist_params.context = context;
1183 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1184 num_steps++;
1185 }
1186
1187 block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1188 block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1189 block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1190 block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1191 num_steps++;
1192 }
1193 }
1194
1195 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
1196 /*update dmcu for wait_loop count*/
1197 block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;
1198 block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;
1199 block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;
1200 num_steps++;
1201 }
1202
1203 return num_steps;
1204 }
1205
dcn401_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)1206 static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
1207 struct dc_state *context,
1208 bool safe_to_lower)
1209 {
1210 struct dc *dc = clk_mgr_base->ctx->dc;
1211
1212 unsigned int num_steps = 0;
1213
1214 /* build bandwidth related clocks update sequence */
1215 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1216 context,
1217 &context->bw_ctx.bw.dcn.clk,
1218 safe_to_lower);
1219
1220 /* execute sequence */
1221 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1222
1223 /* build display related clocks update sequence */
1224 num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,
1225 context,
1226 &context->bw_ctx.bw.dcn.clk,
1227 safe_to_lower);
1228
1229 /* execute sequence */
1230 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1231
1232 if (dc->config.enable_auto_dpm_test_logs)
1233 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);
1234
1235 }
1236
1237
dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)1238 static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
1239 {
1240 struct fixed31_32 pll_req;
1241 uint32_t pll_req_reg = 0;
1242
1243 /* get FbMult value */
1244 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
1245
1246 /* set up a fixed-point number
1247 * this works because the int part is on the right edge of the register
1248 * and the frac part is on the left edge
1249 */
1250 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
1251 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
1252
1253 /* multiply by REFCLK period */
1254 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
1255
1256 return dc_fixpt_floor(pll_req);
1257 }
1258
dcn401_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)1259 static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
1260 {
1261 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
1262 int ss_info_num = bp->funcs->get_ss_entry_number(
1263 bp, AS_SIGNAL_TYPE_GPU_PLL);
1264
1265 if (ss_info_num) {
1266 struct spread_spectrum_info info = { { 0 } };
1267 enum bp_result result = bp->funcs->get_spread_spectrum_info(
1268 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
1269
1270 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
1271 * that SS is enabled
1272 */
1273 if (result == BP_RESULT_OK &&
1274 info.spread_spectrum_percentage != 0) {
1275 clk_mgr->ss_on_dprefclk = true;
1276 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
1277
1278 if (info.type.CENTER_MODE == 0) {
1279 /* Currently for DP Reference clock we
1280 * need only SS percentage for
1281 * downspread
1282 */
1283 clk_mgr->dprefclk_ss_percentage =
1284 info.spread_spectrum_percentage;
1285 }
1286 }
1287 }
1288 }
dcn401_notify_wm_ranges(struct clk_mgr * clk_mgr_base)1289 static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
1290 {
1291 unsigned int i;
1292 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1293 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
1294
1295 if (!clk_mgr->smu_present)
1296 return;
1297
1298 if (!table)
1299 return;
1300
1301 memset(table, 0, sizeof(*table));
1302
1303 /* collect valid ranges, place in pmfw table */
1304 for (i = 0; i < WM_SET_COUNT; i++)
1305 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
1306 table->Watermarks.WatermarkRow[i].WmSetting = i;
1307 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
1308 }
1309 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1310 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
1311 dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
1312 }
1313
1314 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn401_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)1315 static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
1316 {
1317 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1318 const struct dc *dc = clk_mgr->base.ctx->dc;
1319 struct dc_state *context = dc->current_state;
1320 struct dc_clocks new_clocks;
1321 int num_steps;
1322
1323 if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
1324 return;
1325
1326 /* build clock update */
1327 memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
1328
1329 if (current_mode) {
1330 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;
1331 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;
1332 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1333 } else {
1334 new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000;
1335 new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;
1336 new_clocks.p_state_change_support = true;
1337 }
1338
1339 num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1340 context,
1341 &new_clocks,
1342 true);
1343
1344 /* execute sequence */
1345 dcn401_execute_block_sequence(clk_mgr_base, num_steps);
1346 }
1347
dcn401_get_hard_min_memclk(struct clk_mgr * clk_mgr_base)1348 static int dcn401_get_hard_min_memclk(struct clk_mgr *clk_mgr_base)
1349 {
1350 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1351
1352 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;
1353 }
1354
dcn401_get_hard_min_fclk(struct clk_mgr * clk_mgr_base)1355 static int dcn401_get_hard_min_fclk(struct clk_mgr *clk_mgr_base)
1356 {
1357 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1358
1359 return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;
1360 }
1361
1362 /* Get current memclk states, update bounding box */
dcn401_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)1363 static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
1364 {
1365 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1366 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1367 unsigned int num_levels;
1368
1369 if (!clk_mgr->smu_present)
1370 return;
1371
1372 /* Refresh memclk and fclk states */
1373 dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,
1374 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1375 &num_entries_per_clk->num_memclk_levels);
1376 if (num_entries_per_clk->num_memclk_levels) {
1377 clk_mgr_base->bw_params->max_memclk_mhz =
1378 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1379 }
1380
1381 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1382 if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
1383 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz)
1384 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
1385 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1386
1387 dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
1388 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1389 &num_entries_per_clk->num_fclk_levels);
1390 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1391 if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
1392 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz)
1393 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;
1394
1395 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
1396 num_levels = num_entries_per_clk->num_memclk_levels;
1397 } else {
1398 num_levels = num_entries_per_clk->num_fclk_levels;
1399 }
1400
1401 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1402
1403 if (clk_mgr->dpm_present && !num_levels)
1404 clk_mgr->dpm_present = false;
1405
1406 clk_mgr_base->bw_params->num_channels = dcn401_smu_get_num_of_umc_channels(clk_mgr);
1407 if (clk_mgr_base->ctx->dc_bios) {
1408 /* use BIOS values if none provided by PMFW */
1409 if (clk_mgr_base->bw_params->num_channels == 0) {
1410 clk_mgr_base->bw_params->num_channels = clk_mgr_base->ctx->dc_bios->vram_info.num_chans;
1411 }
1412 clk_mgr_base->bw_params->dram_channel_width_bytes = clk_mgr_base->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1413 }
1414
1415 /* Refresh bounding box */
1416 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1417 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1418 }
1419
dcn401_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1420 static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
1421 struct dc_clocks *b)
1422 {
1423 if (a->dispclk_khz != b->dispclk_khz)
1424 return false;
1425 else if (a->dppclk_khz != b->dppclk_khz)
1426 return false;
1427 else if (a->dcfclk_khz != b->dcfclk_khz)
1428 return false;
1429 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1430 return false;
1431 else if (a->dramclk_khz != b->dramclk_khz)
1432 return false;
1433 else if (a->p_state_change_support != b->p_state_change_support)
1434 return false;
1435 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1436 return false;
1437
1438 return true;
1439 }
1440
dcn401_enable_pme_wa(struct clk_mgr * clk_mgr_base)1441 static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1442 {
1443 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1444
1445 if (!clk_mgr->smu_present)
1446 return;
1447
1448 dcn401_smu_set_pme_workaround(clk_mgr);
1449 }
1450
dcn401_is_smu_present(struct clk_mgr * clk_mgr_base)1451 static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
1452 {
1453 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1454 return clk_mgr->smu_present;
1455 }
1456
1457
dcn401_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)1458 static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
1459 {
1460 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1461
1462 int dtb_ref_clk_khz = 0;
1463
1464 if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
1465 /* DPM enabled, use currently set value */
1466 dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz;
1467 } else {
1468 /* DPM disabled, so use boot snapshot */
1469 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk;
1470 }
1471
1472 return dtb_ref_clk_khz;
1473 }
1474
dcn401_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)1475 static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
1476 {
1477 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1478 uint32_t dispclk_wdivider;
1479 int disp_divider;
1480
1481 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
1482 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
1483
1484 /* Return DISPCLK freq in Khz */
1485 if (disp_divider)
1486 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
1487
1488 return 0;
1489 }
1490
1491 static struct clk_mgr_funcs dcn401_funcs = {
1492 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1493 .get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
1494 .update_clocks = dcn401_update_clocks,
1495 .dump_clk_registers = dcn401_dump_clk_registers,
1496 .init_clocks = dcn401_init_clocks,
1497 .notify_wm_ranges = dcn401_notify_wm_ranges,
1498 .set_hard_min_memclk = dcn401_set_hard_min_memclk,
1499 .get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,
1500 .are_clock_states_equal = dcn401_are_clock_states_equal,
1501 .enable_pme_wa = dcn401_enable_pme_wa,
1502 .is_smu_present = dcn401_is_smu_present,
1503 .get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
1504 .get_hard_min_memclk = dcn401_get_hard_min_memclk,
1505 .get_hard_min_fclk = dcn401_get_hard_min_fclk,
1506 };
1507
dcn401_clk_mgr_construct(struct dc_context * ctx,struct dccg * dccg)1508 struct clk_mgr_internal *dcn401_clk_mgr_construct(
1509 struct dc_context *ctx,
1510 struct dccg *dccg)
1511 {
1512 struct clk_log_info log_info = {0};
1513 struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);
1514 struct clk_mgr_internal *clk_mgr;
1515
1516 if (!clk_mgr401)
1517 return NULL;
1518
1519 clk_mgr = &clk_mgr401->base;
1520 clk_mgr->base.ctx = ctx;
1521 clk_mgr->base.funcs = &dcn401_funcs;
1522 clk_mgr->regs = &clk_mgr_regs_dcn401;
1523 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn401;
1524 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;
1525
1526 clk_mgr->dccg = dccg;
1527 clk_mgr->dfs_bypass_disp_clk = 0;
1528
1529 clk_mgr->dprefclk_ss_percentage = 0;
1530 clk_mgr->dprefclk_ss_divider = 1000;
1531 clk_mgr->ss_on_dprefclk = false;
1532 clk_mgr->dfs_ref_freq_khz = 100000;
1533
1534 /* Changed from DCN3.2_clock_frequency doc to match
1535 * dcn401_dump_clk_registers from 4 * dentist_vco_freq_khz /
1536 * dprefclk DID divider
1537 */
1538 clk_mgr->base.dprefclk_khz = 720000; //TODO update from VBIOS
1539
1540 /* integer part is now VCO frequency in kHz */
1541 clk_mgr->base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);
1542
1543 /* in case we don't get a value from the register, use default */
1544 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1545 clk_mgr->base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS
1546
1547 dcn401_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1548
1549 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1550 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1551 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1552 }
1553
1554 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1555 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1556 }
1557 dcn401_clock_read_ss_info(clk_mgr);
1558
1559 clk_mgr->dfs_bypass_enabled = false;
1560
1561 clk_mgr->smu_present = false;
1562
1563 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1564 if (!clk_mgr->base.bw_params) {
1565 BREAK_TO_DEBUGGER();
1566 kfree(clk_mgr);
1567 return NULL;
1568 }
1569
1570 /* need physical address of table to give to PMFW */
1571 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1572 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1573 &clk_mgr->wm_range_table_addr);
1574 if (!clk_mgr->wm_range_table) {
1575 BREAK_TO_DEBUGGER();
1576 kfree(clk_mgr->base.bw_params);
1577 return NULL;
1578 }
1579
1580 return &clk_mgr401->base;
1581 }
1582
dcn401_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1583 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1584 {
1585 kfree(clk_mgr->base.bw_params);
1586
1587 if (clk_mgr->wm_range_table)
1588 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1589 clk_mgr->wm_range_table);
1590 }
1591
1592