1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright 2025 Advanced Micro Devices, Inc. */ 3 4 #include "dm_services.h" 5 #include "dc.h" 6 7 #include "dcn31/dcn31_init.h" 8 #include "dcn35/dcn35_init.h" 9 #include "dcn36/dcn36_resource.h" 10 11 #include "resource.h" 12 #include "include/irq_service_interface.h" 13 #include "dcn36_resource.h" 14 #include "dml2_0/dml2_wrapper.h" 15 16 #include "dcn20/dcn20_resource.h" 17 #include "dcn30/dcn30_resource.h" 18 #include "dcn31/dcn31_resource.h" 19 #include "dcn32/dcn32_resource.h" 20 #include "dcn35/dcn35_resource.h" 21 22 #include "dcn10/dcn10_ipp.h" 23 #include "dcn30/dcn30_hubbub.h" 24 #include "dcn31/dcn31_hubbub.h" 25 #include "dcn35/dcn35_hubbub.h" 26 #include "dcn32/dcn32_mpc.h" 27 #include "dcn35/dcn35_hubp.h" 28 #include "irq/dcn36/irq_service_dcn36.h" 29 #include "dcn35/dcn35_dpp.h" 30 #include "dcn35/dcn35_optc.h" 31 #include "dcn20/dcn20_hwseq.h" 32 #include "dcn30/dcn30_hwseq.h" 33 #include "dce110/dce110_hwseq.h" 34 #include "dcn35/dcn35_opp.h" 35 #include "dcn35/dcn35_dsc.h" 36 #include "dcn30/dcn30_vpg.h" 37 #include "dcn30/dcn30_afmt.h" 38 #include "dcn31/dcn31_dio_link_encoder.h" 39 #include "dcn35/dcn35_dio_stream_encoder.h" 40 #include "dcn30/dcn30_hpo_frl_stream_encoder.h" 41 #include "dcn30/dcn30_hpo_frl_link_encoder.h" 42 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 43 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 44 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 45 #include "link_service.h" 46 #include "dcn31/dcn31_apg.h" 47 #include "dcn32/dcn32_dio_link_encoder.h" 48 #include "dcn31/dcn31_vpg.h" 49 #include "dcn31/dcn31_afmt.h" 50 #include "dce/dce_clock_source.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_hwseq.h" 53 #include "clk_mgr.h" 54 #include "dio/virtual/virtual_stream_encoder.h" 55 #include "dio/dcn10/dcn10_dio.h" 56 #include "dce110/dce110_resource.h" 57 #include "dml/display_mode_vba.h" 58 #include "dcn35/dcn35_dccg.h" 59 #include "dcn35/dcn35_pg_cntl.h" 60 #include "dcn10/dcn10_resource.h" 61 #include "dcn31/dcn31_panel_cntl.h" 62 #include "dcn35/dcn35_hwseq.h" 63 #include "dcn35/dcn35_dio_link_encoder.h" 64 #include "dml/dcn31/dcn31_fpu.h" /*todo*/ 65 #include "dml/dcn35/dcn35_fpu.h" 66 #include "dcn35/dcn35_dwb.h" 67 #include "dcn35/dcn35_mmhubbub.h" 68 69 #include "dcn/dcn_3_6_0_offset.h" 70 #include "dcn/dcn_3_6_0_sh_mask.h" 71 72 #define regBIF_BX2_BIOS_SCRATCH_2 0x2ffc004e 73 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 5 74 75 #define regBIF_BX2_BIOS_SCRATCH_3 0x2ffc004f 76 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 5 77 78 #define regBIF_BX2_BIOS_SCRATCH_6 0x2ffc0052 79 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 5 80 81 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 82 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 83 84 #include "reg_helper.h" 85 #include "dce/dmub_abm.h" 86 #include "dce/dmub_psr.h" 87 #include "dce/dmub_replay.h" 88 #include "dce/dce_aux.h" 89 #include "dce/dce_i2c.h" 90 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/ 91 #include "vm_helper.h" 92 #include "dcn20/dcn20_vmid.h" 93 94 #include "dc_state_priv.h" 95 96 #include "link_enc_cfg.h" 97 #define DC_LOGGER_INIT(logger) 98 99 enum dcn36_clk_src_array_id { 100 DCN36_CLK_SRC_PLL0, 101 DCN36_CLK_SRC_PLL1, 102 DCN36_CLK_SRC_PLL2, 103 DCN36_CLK_SRC_PLL3, 104 DCN36_CLK_SRC_PLL4, 105 DCN36_CLK_SRC_TOTAL 106 }; 107 108 /* begin ********************* 109 * macros to expend register list macro defined in HW object header file 110 */ 111 112 /* DCN */ 113 /* TODO awful hack. fixup dcn20_dwb.h */ 114 #undef BASE_INNER 115 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 116 117 #define BASE(seg) BASE_INNER(seg) 118 119 #define SR(reg_name)\ 120 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 121 reg ## reg_name 122 123 #define SR_ARR(reg_name, id) \ 124 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 125 126 #define SR_ARR_INIT(reg_name, id, value) \ 127 REG_STRUCT[id].reg_name = value 128 129 #define SRI(reg_name, block, id)\ 130 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 131 reg ## block ## id ## _ ## reg_name 132 133 #define SRI_ARR(reg_name, block, id)\ 134 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 reg ## block ## id ## _ ## reg_name 136 137 #define SR_ARR_I2C(reg_name, id) \ 138 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 139 140 #define SRI_ARR_I2C(reg_name, block, id)\ 141 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 reg ## block ## id ## _ ## reg_name 143 144 #define SRI_ARR_DME(reg_name, block, id, offset)\ 145 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 146 reg ## block ## id ## _ ## reg_name 147 148 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 149 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 150 reg ## block ## id ## _ ## reg_name 151 152 #define SRI2(reg_name, block, id)\ 153 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 154 reg ## reg_name 155 156 #define SRI2_ARR(reg_name, block, id)\ 157 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 158 reg ## reg_name 159 160 #define SRIR(var_name, reg_name, block, id)\ 161 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 162 reg ## block ## id ## _ ## reg_name 163 164 #define SRII(reg_name, block, id)\ 165 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 166 reg ## block ## id ## _ ## reg_name 167 168 #define SRII_ARR_2(reg_name, block, id, inst)\ 169 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 170 reg ## block ## id ## _ ## reg_name 171 172 #define SRII_MPC_RMU(reg_name, block, id)\ 173 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 174 reg ## block ## id ## _ ## reg_name 175 176 #define SRII_DWB(reg_name, temp_name, block, id)\ 177 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## temp_name 179 180 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 181 .field_name = reg_name ## __ ## field_name ## post_fix 182 183 #define DCCG_SRII(reg_name, block, id)\ 184 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## reg_name 186 187 #define VUPDATE_SRII(reg_name, block, id)\ 188 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 189 reg ## reg_name ## _ ## block ## id 190 191 /* NBIO */ 192 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 193 194 #define NBIO_BASE(seg) \ 195 NBIO_BASE_INNER(seg) 196 197 #define NBIO_SR(reg_name)\ 198 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 199 regBIF_BX2_ ## reg_name 200 201 #define NBIO_SR_ARR(reg_name, id)\ 202 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 203 regBIF_BX2_ ## reg_name 204 205 #define bios_regs_init() \ 206 ( \ 207 NBIO_SR(BIOS_SCRATCH_3),\ 208 NBIO_SR(BIOS_SCRATCH_6)\ 209 ) 210 211 static struct bios_registers bios_regs; 212 213 #define clk_src_regs_init(index, pllid)\ 214 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 215 216 static struct dce110_clk_src_regs clk_src_regs[5]; 217 218 static const struct dce110_clk_src_shift cs_shift = { 219 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 220 }; 221 222 static const struct dce110_clk_src_mask cs_mask = { 223 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 224 }; 225 226 #define abm_regs_init(id)\ 227 ABM_DCN32_REG_LIST_RI(id) 228 229 static struct dce_abm_registers abm_regs[4]; 230 231 static const struct dce_abm_shift abm_shift = { 232 ABM_MASK_SH_LIST_DCN35(__SHIFT) 233 }; 234 235 static const struct dce_abm_mask abm_mask = { 236 ABM_MASK_SH_LIST_DCN35(_MASK) 237 }; 238 239 #define audio_regs_init(id)\ 240 AUD_COMMON_REG_LIST_RI(id) 241 242 static struct dce_audio_registers audio_regs[7]; 243 244 245 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 246 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 247 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 248 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 249 250 static const struct dce_audio_shift audio_shift = { 251 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 252 }; 253 254 static const struct dce_audio_mask audio_mask = { 255 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 256 }; 257 258 #define vpg_regs_init(id)\ 259 VPG_DCN31_REG_LIST_RI(id) 260 261 static struct dcn31_vpg_registers vpg_regs[10]; 262 263 static const struct dcn31_vpg_shift vpg_shift = { 264 DCN31_VPG_MASK_SH_LIST(__SHIFT) 265 }; 266 267 static const struct dcn31_vpg_mask vpg_mask = { 268 DCN31_VPG_MASK_SH_LIST(_MASK) 269 }; 270 271 #define afmt_regs_init(id)\ 272 AFMT_DCN31_REG_LIST_RI(id) 273 274 static struct dcn31_afmt_registers afmt_regs[6]; 275 276 static const struct dcn31_afmt_shift afmt_shift = { 277 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 278 }; 279 280 static const struct dcn31_afmt_mask afmt_mask = { 281 DCN31_AFMT_MASK_SH_LIST(_MASK) 282 }; 283 284 #define apg_regs_init(id)\ 285 APG_DCN31_REG_LIST_RI(id) 286 287 static struct dcn31_apg_registers apg_regs[4]; 288 289 static const struct dcn31_apg_shift apg_shift = { 290 DCN31_APG_MASK_SH_LIST(__SHIFT) 291 }; 292 293 static const struct dcn31_apg_mask apg_mask = { 294 DCN31_APG_MASK_SH_LIST(_MASK) 295 }; 296 297 #define stream_enc_regs_init(id)\ 298 SE_DCN35_REG_LIST_RI(id) 299 300 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 301 302 static const struct dcn10_stream_encoder_shift se_shift = { 303 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 304 }; 305 306 static const struct dcn10_stream_encoder_mask se_mask = { 307 SE_COMMON_MASK_SH_LIST_DCN35(_MASK) 308 }; 309 310 #define aux_regs_init(id)\ 311 DCN2_AUX_REG_LIST_RI(id) 312 313 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 314 315 #define hpd_regs_init(id)\ 316 HPD_REG_LIST_RI(id) 317 318 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 319 320 321 static const struct dce110_aux_registers_shift aux_shift = { 322 DCN_AUX_MASK_SH_LIST(__SHIFT) 323 }; 324 325 static const struct dce110_aux_registers_mask aux_mask = { 326 DCN_AUX_MASK_SH_LIST(_MASK) 327 }; 328 329 #define link_regs_init(id, phyid)\ 330 ( \ 331 LE_DCN35_REG_LIST_RI(id), \ 332 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 333 ) 334 335 static struct dcn10_link_enc_registers link_enc_regs[5]; 336 337 static const struct dcn10_link_enc_shift le_shift = { 338 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \ 339 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 340 }; 341 342 static const struct dcn10_link_enc_mask le_mask = { 343 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \ 344 //DPCS_DCN31_MASK_SH_LIST(_MASK) 345 }; 346 347 #define hpo_frl_stream_encoder_dme_reg_list(id)\ 348 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6) 349 350 #define hpo_frl_stream_encoder_reg_list(id)\ 351 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) 352 353 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2]; 354 355 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = { 356 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = { 360 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK) 361 }; 362 363 #define hpo_frl_link_encoder_reg_list(id)\ 364 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id) 365 366 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1]; 367 368 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = { 369 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT) 370 }; 371 372 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = { 373 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK) 374 }; 375 376 #define hpo_dp_stream_encoder_reg_init(id)\ 377 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 378 379 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 380 381 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 382 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 383 }; 384 385 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 386 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 387 }; 388 389 #define hpo_dp_link_encoder_reg_init(id)\ 390 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 391 392 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 393 394 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 395 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT) 396 }; 397 398 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 399 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) 400 }; 401 402 #define dpp_regs_init(id)\ 403 DPP_REG_LIST_DCN35_RI(id) 404 405 static struct dcn3_dpp_registers dpp_regs[4]; 406 407 static const struct dcn35_dpp_shift tf_shift = { 408 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT) 409 }; 410 411 static const struct dcn35_dpp_mask tf_mask = { 412 DPP_REG_LIST_SH_MASK_DCN35(_MASK) 413 }; 414 415 #define opp_regs_init(id)\ 416 OPP_REG_LIST_DCN35_RI(id) 417 418 static struct dcn35_opp_registers opp_regs[4]; 419 420 static const struct dcn35_opp_shift opp_shift = { 421 OPP_MASK_SH_LIST_DCN35(__SHIFT) 422 }; 423 424 static const struct dcn35_opp_mask opp_mask = { 425 OPP_MASK_SH_LIST_DCN35(_MASK) 426 }; 427 428 #define aux_engine_regs_init(id)\ 429 ( \ 430 AUX_COMMON_REG_LIST0_RI(id), \ 431 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 432 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 433 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \ 434 ) 435 436 static struct dce110_aux_registers aux_engine_regs[5]; 437 438 #define dwbc_regs_dcn3_init(id)\ 439 DWBC_COMMON_REG_LIST_DCN30_RI(id) 440 441 static struct dcn30_dwbc_registers dwbc35_regs[1]; 442 443 static const struct dcn35_dwbc_shift dwbc35_shift = { 444 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 445 }; 446 447 static const struct dcn35_dwbc_mask dwbc35_mask = { 448 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK) 449 }; 450 451 #define mcif_wb_regs_dcn3_init(id)\ 452 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) 453 454 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; 455 456 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { 457 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 458 }; 459 460 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { 461 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 462 }; 463 464 #define dsc_regsDCN35_init(id)\ 465 DSC_REG_LIST_DCN20_RI(id) 466 467 static struct dcn20_dsc_registers dsc_regs[4]; 468 469 static const struct dcn35_dsc_shift dsc_shift = { 470 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT) 471 }; 472 473 static const struct dcn35_dsc_mask dsc_mask = { 474 DSC_REG_LIST_SH_MASK_DCN35(_MASK) 475 }; 476 477 static struct dcn30_mpc_registers mpc_regs; 478 479 #define dcn_mpc_regs_init() \ 480 MPC_REG_LIST_DCN3_2_RI(0),\ 481 MPC_REG_LIST_DCN3_2_RI(1),\ 482 MPC_REG_LIST_DCN3_2_RI(2),\ 483 MPC_REG_LIST_DCN3_2_RI(3),\ 484 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 485 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 486 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 487 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 488 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 489 490 static const struct dcn30_mpc_shift mpc_shift = { 491 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 492 }; 493 494 static const struct dcn30_mpc_mask mpc_mask = { 495 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 496 }; 497 498 #define optc_regs_init(id)\ 499 OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\ 500 SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\ 501 SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\ 502 SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\ 503 SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\ 504 SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\ 505 SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id) 506 507 static struct dcn_optc_registers optc_regs[4]; 508 509 static const struct dcn_optc_shift optc_shift = { 510 OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT) 511 }; 512 513 static const struct dcn_optc_mask optc_mask = { 514 OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK) 515 }; 516 517 #define hubp_regs_init(id)\ 518 HUBP_REG_LIST_DCN30_RI(id) 519 520 static struct dcn_hubp2_registers hubp_regs[4]; 521 522 523 static const struct dcn35_hubp2_shift hubp_shift = { 524 HUBP_MASK_SH_LIST_DCN35(__SHIFT) 525 }; 526 527 static const struct dcn35_hubp2_mask hubp_mask = { 528 HUBP_MASK_SH_LIST_DCN35(_MASK) 529 }; 530 531 static struct dcn_hubbub_registers hubbub_reg; 532 533 #define hubbub_reg_init()\ 534 HUBBUB_REG_LIST_DCN35(0) 535 536 static const struct dcn_hubbub_shift hubbub_shift = { 537 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT) 538 }; 539 540 static const struct dcn_hubbub_mask hubbub_mask = { 541 HUBBUB_MASK_SH_LIST_DCN35(_MASK) 542 }; 543 544 static struct dccg_registers dccg_regs; 545 546 #define dccg_regs_init()\ 547 DCCG_REG_LIST_DCN35() 548 549 static const struct dccg_shift dccg_shift = { 550 DCCG_MASK_SH_LIST_DCN35(__SHIFT) 551 }; 552 553 static const struct dccg_mask dccg_mask = { 554 DCCG_MASK_SH_LIST_DCN35(_MASK) 555 }; 556 557 static struct pg_cntl_registers pg_cntl_regs; 558 559 #define pg_cntl_dcn35_regs_init() \ 560 PG_CNTL_REG_LIST_DCN35() 561 562 static const struct pg_cntl_shift pg_cntl_shift = { 563 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT) 564 }; 565 566 static const struct pg_cntl_mask pg_cntl_mask = { 567 PG_CNTL_MASK_SH_LIST_DCN35(_MASK) 568 }; 569 570 #define SRII2(reg_name_pre, reg_name_post, id)\ 571 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 572 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 573 reg ## reg_name_pre ## id ## _ ## reg_name_post 574 575 static struct dce_hwseq_registers hwseq_reg; 576 577 #define hwseq_reg_init()\ 578 HWSEQ_DCN36_REG_LIST() 579 580 #define HWSEQ_DCN36_MASK_SH_LIST(mask_sh)\ 581 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 582 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 583 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 584 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 585 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 586 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 587 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 588 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 589 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 590 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 591 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 592 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 593 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 594 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 595 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 596 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 597 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 598 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 607 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 608 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 609 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 610 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 611 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 612 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 613 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 614 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 615 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 616 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 617 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 618 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 619 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 620 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 621 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 622 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 623 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 624 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 625 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 626 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\ 627 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ 628 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ 629 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ 630 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 631 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 632 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 633 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 634 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 635 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ 636 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 637 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 638 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 639 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 640 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 641 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 642 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 643 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 644 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 645 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ 646 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 647 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 648 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 649 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 650 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 651 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 652 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 653 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 654 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 655 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ 656 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ 657 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 658 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 659 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 660 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 661 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 662 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 663 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ 664 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ 665 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ 666 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ 667 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh) 668 669 static const struct dce_hwseq_shift hwseq_shift = { 670 HWSEQ_DCN36_MASK_SH_LIST(__SHIFT) 671 }; 672 673 static const struct dce_hwseq_mask hwseq_mask = { 674 HWSEQ_DCN36_MASK_SH_LIST(_MASK) 675 }; 676 677 #define vmid_regs_init(id)\ 678 DCN20_VMID_REG_LIST_RI(id) 679 680 static struct dcn_vmid_registers vmid_regs[16]; 681 682 static const struct dcn20_vmid_shift vmid_shifts = { 683 DCN20_VMID_MASK_SH_LIST(__SHIFT) 684 }; 685 686 static const struct dcn20_vmid_mask vmid_masks = { 687 DCN20_VMID_MASK_SH_LIST(_MASK) 688 }; 689 690 static struct dcn_dio_registers dio_regs; 691 692 #define DIO_MASK_SH_LIST(mask_sh)\ 693 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 694 695 static const struct dcn_dio_shift dio_shift = { 696 DIO_MASK_SH_LIST(__SHIFT) 697 }; 698 699 static const struct dcn_dio_mask dio_mask = { 700 DIO_MASK_SH_LIST(_MASK) 701 }; 702 703 static const struct resource_caps res_cap_dcn36 = { 704 .num_timing_generator = 4, 705 .num_opp = 4, 706 .num_video_plane = 4, 707 .num_audio = 5, 708 .num_stream_encoder = 5, 709 .num_dig_link_enc = 5, 710 .num_hpo_frl = 1, 711 .num_hpo_dp_stream_encoder = 4, 712 .num_hpo_dp_link_encoder = 2, 713 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ 714 .num_dwb = 1, 715 .num_ddc = 5, 716 .num_vmid = 16, 717 .num_mpc_3dlut = 2, 718 .num_dsc = 4, 719 }; 720 721 static const struct dc_plane_cap plane_cap = { 722 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 723 .per_pixel_alpha = true, 724 725 .pixel_format_support = { 726 .argb8888 = true, 727 .nv12 = true, 728 .fp16 = true, 729 .p010 = true, 730 .ayuv = false, 731 }, 732 733 .max_upscale_factor = { 734 .argb8888 = 16000, 735 .nv12 = 16000, 736 .fp16 = 16000 737 }, 738 739 // 6:1 downscaling ratio: 1000/6 = 166.666 740 .max_downscale_factor = { 741 .argb8888 = 250, 742 .nv12 = 167, 743 .fp16 = 167 744 }, 745 64, 746 64 747 }; 748 749 static const struct dc_debug_options debug_defaults_drv = { 750 .disable_dmcu = true, 751 .force_abm_enable = false, 752 .clock_trace = true, 753 .disable_pplib_clock_request = false, 754 .pipe_split_policy = MPC_SPLIT_AVOID, 755 .force_single_disp_pipe_split = false, 756 .disable_dcc = DCC_ENABLE, 757 .disable_dpp_power_gate = true, 758 .disable_hubp_power_gate = true, 759 .disable_optc_power_gate = true, /*should the same as above two*/ 760 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/ 761 .disable_clock_gate = false, 762 .disable_dsc_power_gate = true, 763 .vsr_support = true, 764 .performance_trace = false, 765 .max_downscale_src_width = 4096,/*upto true 4k*/ 766 .disable_pplib_wm_range = false, 767 .scl_reset_length10 = true, 768 .sanity_checks = false, 769 .underflow_assert_delay_us = 0xFFFFFFFF, 770 .dwb_fi_phase = -1, // -1 = disable, 771 .dmub_command_table = true, 772 .pstate_enabled = true, 773 .use_max_lb = true, 774 .enable_mem_low_power = { 775 .bits = { 776 .vga = false, 777 .i2c = true, 778 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 779 .dscl = true, 780 .cm = true, 781 .mpc = true, 782 .optc = true, 783 .vpg = true, 784 .afmt = true, 785 } 786 }, 787 .root_clock_optimization = { 788 .bits = { 789 .dpp = true, 790 .dsc = true,/*dscclk and dsc pg*/ 791 .hdmistream = true, 792 .hdmichar = true, 793 .dpstream = true, 794 .symclk32_se = true, 795 .symclk32_le = true, 796 .symclk_fe = true, 797 .physymclk = false, 798 .dpiasymclk = true, 799 } 800 }, 801 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 802 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 803 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ 804 .using_dml2 = true, 805 .support_eDP1_5 = true, 806 .enable_hpo_pg_support = false, 807 .enable_single_display_2to1_odm_policy = true, 808 .disable_idle_power_optimizations = false, 809 .dmcub_emulation = false, 810 .disable_boot_optimizations = false, 811 .disable_unbounded_requesting = false, 812 .disable_mem_low_power = false, 813 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 814 .enable_double_buffered_dsc_pg_support = true, 815 .enable_dp_dig_pixel_rate_div_policy = 1, 816 .disable_z10 = false, 817 .ignore_pg = true, 818 .psp_disabled_wa = true, 819 .ips2_eval_delay_us = 2000, 820 .ips2_entry_delay_us = 800, 821 .disable_dmub_reallow_idle = false, 822 .static_screen_wait_frames = 2, 823 .disable_timeout = true, 824 .min_disp_clk_khz = 50000, 825 }; 826 827 static const struct dc_check_config config_defaults = { 828 .enable_legacy_fast_update = false, 829 }; 830 831 static const struct dc_panel_config panel_config_defaults = { 832 .psr = { 833 .disable_psr = false, 834 .disallow_psrsu = false, 835 .disallow_replay = false, 836 }, 837 .ilr = { 838 .optimize_edp_link_rate = true, 839 }, 840 }; 841 842 static void dcn35_dpp_destroy(struct dpp **dpp) 843 { 844 kfree(TO_DCN20_DPP(*dpp)); 845 *dpp = NULL; 846 } 847 848 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) 849 { 850 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); 851 bool success = (dpp != NULL); 852 853 if (!success) 854 return NULL; 855 856 #undef REG_STRUCT 857 #define REG_STRUCT dpp_regs 858 dpp_regs_init(0), 859 dpp_regs_init(1), 860 dpp_regs_init(2), 861 dpp_regs_init(3); 862 863 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, 864 &tf_mask); 865 if (success) { 866 dpp35_set_fgcg( 867 dpp, 868 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); 869 return &dpp->base; 870 } 871 872 BREAK_TO_DEBUGGER(); 873 kfree(dpp); 874 return NULL; 875 } 876 877 static struct output_pixel_processor *dcn35_opp_create( 878 struct dc_context *ctx, uint32_t inst) 879 { 880 struct dcn20_opp *opp = 881 kzalloc_obj(struct dcn20_opp); 882 883 if (!opp) { 884 BREAK_TO_DEBUGGER(); 885 return NULL; 886 } 887 888 #undef REG_STRUCT 889 #define REG_STRUCT opp_regs 890 opp_regs_init(0), 891 opp_regs_init(1), 892 opp_regs_init(2), 893 opp_regs_init(3); 894 895 dcn35_opp_construct(opp, ctx, inst, 896 &opp_regs[inst], &opp_shift, &opp_mask); 897 898 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); 899 900 return &opp->base; 901 } 902 903 static struct dce_aux *dcn31_aux_engine_create( 904 struct dc_context *ctx, 905 uint32_t inst) 906 { 907 struct aux_engine_dce110 *aux_engine = 908 kzalloc_obj(struct aux_engine_dce110); 909 910 if (!aux_engine) 911 return NULL; 912 913 #undef REG_STRUCT 914 #define REG_STRUCT aux_engine_regs 915 aux_engine_regs_init(0), 916 aux_engine_regs_init(1), 917 aux_engine_regs_init(2), 918 aux_engine_regs_init(3), 919 aux_engine_regs_init(4); 920 921 dce110_aux_engine_construct(aux_engine, ctx, inst, 922 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 923 &aux_engine_regs[inst], 924 &aux_mask, 925 &aux_shift, 926 ctx->dc->caps.extended_aux_timeout_support); 927 928 return &aux_engine->base; 929 } 930 931 #define i2c_inst_regs_init(id)\ 932 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 933 934 static struct dce_i2c_registers i2c_hw_regs[5]; 935 936 static const struct dce_i2c_shift i2c_shifts = { 937 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 938 }; 939 940 static const struct dce_i2c_mask i2c_masks = { 941 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) 942 }; 943 944 /* ========================================================== */ 945 946 /* 947 * DPIA index | Preferred Encoder | Host Router 948 * 0 | C | 0 949 * 1 | First Available | 0 950 * 2 | D | 1 951 * 3 | First Available | 1 952 */ 953 /* ========================================================== */ 954 static const enum engine_id dpia_to_preferred_enc_id_table[] = { 955 ENGINE_ID_DIGC, 956 ENGINE_ID_DIGC, 957 ENGINE_ID_DIGD, 958 ENGINE_ID_DIGD 959 }; 960 961 static enum engine_id dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index) 962 { 963 return dpia_to_preferred_enc_id_table[dpia_index]; 964 } 965 966 static struct dce_i2c_hw *dcn31_i2c_hw_create( 967 struct dc_context *ctx, 968 uint32_t inst) 969 { 970 struct dce_i2c_hw *dce_i2c_hw = 971 kzalloc_obj(struct dce_i2c_hw); 972 973 if (!dce_i2c_hw) 974 return NULL; 975 976 #undef REG_STRUCT 977 #define REG_STRUCT i2c_hw_regs 978 i2c_inst_regs_init(1), 979 i2c_inst_regs_init(2), 980 i2c_inst_regs_init(3), 981 i2c_inst_regs_init(4), 982 i2c_inst_regs_init(5); 983 984 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 985 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 986 987 return dce_i2c_hw; 988 } 989 static struct mpc *dcn35_mpc_create( 990 struct dc_context *ctx, 991 int num_mpcc, 992 int num_rmu) 993 { 994 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc); 995 996 if (!mpc30) 997 return NULL; 998 999 #undef REG_STRUCT 1000 #define REG_STRUCT mpc_regs 1001 dcn_mpc_regs_init(); 1002 1003 dcn32_mpc_construct(mpc30, ctx, 1004 &mpc_regs, 1005 &mpc_shift, 1006 &mpc_mask, 1007 num_mpcc, 1008 num_rmu); 1009 1010 return &mpc30->base; 1011 } 1012 1013 static struct dio *dcn36_dio_create(struct dc_context *ctx) 1014 { 1015 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1016 1017 if (!dio10) 1018 return NULL; 1019 1020 #undef REG_STRUCT 1021 #define REG_STRUCT dio_regs 1022 DIO_REG_LIST_DCN10(); 1023 1024 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1025 1026 return &dio10->base; 1027 } 1028 1029 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) 1030 { 1031 int i; 1032 1033 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub); 1034 1035 if (!hubbub3) 1036 return NULL; 1037 1038 #undef REG_STRUCT 1039 #define REG_STRUCT hubbub_reg 1040 hubbub_reg_init(); 1041 1042 #undef REG_STRUCT 1043 #define REG_STRUCT vmid_regs 1044 vmid_regs_init(0), 1045 vmid_regs_init(1), 1046 vmid_regs_init(2), 1047 vmid_regs_init(3), 1048 vmid_regs_init(4), 1049 vmid_regs_init(5), 1050 vmid_regs_init(6), 1051 vmid_regs_init(7), 1052 vmid_regs_init(8), 1053 vmid_regs_init(9), 1054 vmid_regs_init(10), 1055 vmid_regs_init(11), 1056 vmid_regs_init(12), 1057 vmid_regs_init(13), 1058 vmid_regs_init(14), 1059 vmid_regs_init(15); 1060 1061 hubbub35_construct(hubbub3, ctx, 1062 &hubbub_reg, 1063 &hubbub_shift, 1064 &hubbub_mask, 1065 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/ 1066 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/ 1067 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/); 1068 1069 1070 for (i = 0; i < res_cap_dcn36.num_vmid; i++) { 1071 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1072 1073 vmid->ctx = ctx; 1074 1075 vmid->regs = &vmid_regs[i]; 1076 vmid->shifts = &vmid_shifts; 1077 vmid->masks = &vmid_masks; 1078 } 1079 1080 return &hubbub3->base; 1081 } 1082 1083 static struct timing_generator *dcn35_timing_generator_create( 1084 struct dc_context *ctx, 1085 uint32_t instance) 1086 { 1087 struct optc *tgn10 = 1088 kzalloc_obj(struct optc); 1089 1090 if (!tgn10) 1091 return NULL; 1092 1093 #undef REG_STRUCT 1094 #define REG_STRUCT optc_regs 1095 optc_regs_init(0), 1096 optc_regs_init(1), 1097 optc_regs_init(2), 1098 optc_regs_init(3); 1099 1100 tgn10->base.inst = instance; 1101 tgn10->base.ctx = ctx; 1102 1103 tgn10->tg_regs = &optc_regs[instance]; 1104 tgn10->tg_shift = &optc_shift; 1105 tgn10->tg_mask = &optc_mask; 1106 1107 dcn35_timing_generator_init(tgn10); 1108 1109 return &tgn10->base; 1110 } 1111 1112 static const struct encoder_feature_support link_enc_feature = { 1113 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1114 .max_hdmi_pixel_clock = 600000, 1115 .hdmi_ycbcr420_supported = true, 1116 .dp_ycbcr420_supported = true, 1117 .fec_supported = true, 1118 .flags.bits.IS_HBR2_CAPABLE = true, 1119 .flags.bits.IS_HBR3_CAPABLE = true, 1120 .flags.bits.IS_TPS3_CAPABLE = true, 1121 .flags.bits.IS_TPS4_CAPABLE = true 1122 }; 1123 1124 static struct link_encoder *dcn35_link_encoder_create( 1125 struct dc_context *ctx, 1126 const struct encoder_init_data *enc_init_data) 1127 { 1128 struct dcn20_link_encoder *enc20 = 1129 kzalloc_obj(struct dcn20_link_encoder); 1130 1131 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1132 return NULL; 1133 1134 #undef REG_STRUCT 1135 #define REG_STRUCT link_enc_aux_regs 1136 aux_regs_init(0), 1137 aux_regs_init(1), 1138 aux_regs_init(2), 1139 aux_regs_init(3), 1140 aux_regs_init(4); 1141 1142 #undef REG_STRUCT 1143 #define REG_STRUCT link_enc_hpd_regs 1144 hpd_regs_init(0), 1145 hpd_regs_init(1), 1146 hpd_regs_init(2), 1147 hpd_regs_init(3), 1148 hpd_regs_init(4); 1149 1150 #undef REG_STRUCT 1151 #define REG_STRUCT link_enc_regs 1152 link_regs_init(0, A), 1153 link_regs_init(1, B), 1154 link_regs_init(2, C), 1155 link_regs_init(3, D), 1156 link_regs_init(4, E); 1157 1158 dcn35_link_encoder_construct(enc20, 1159 enc_init_data, 1160 &link_enc_feature, 1161 &link_enc_regs[enc_init_data->transmitter], 1162 &link_enc_aux_regs[enc_init_data->channel - 1], 1163 &link_enc_hpd_regs[enc_init_data->hpd_source], 1164 &le_shift, 1165 &le_mask); 1166 1167 return &enc20->enc10.base; 1168 } 1169 1170 /* Create a minimal link encoder object not associated with a particular 1171 * physical connector. 1172 * resource_funcs.link_enc_create_minimal 1173 */ 1174 static struct link_encoder *dcn31_link_enc_create_minimal( 1175 struct dc_context *ctx, enum engine_id eng_id) 1176 { 1177 struct dcn20_link_encoder *enc20; 1178 1179 if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1180 return NULL; 1181 1182 enc20 = kzalloc_obj(struct dcn20_link_encoder); 1183 if (!enc20) 1184 return NULL; 1185 1186 dcn31_link_encoder_construct_minimal( 1187 enc20, 1188 ctx, 1189 &link_enc_feature, 1190 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1191 eng_id); 1192 1193 return &enc20->enc10.base; 1194 } 1195 1196 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1197 { 1198 struct dcn31_panel_cntl *panel_cntl = 1199 kzalloc_obj(struct dcn31_panel_cntl); 1200 1201 if (!panel_cntl) 1202 return NULL; 1203 1204 dcn31_panel_cntl_construct(panel_cntl, init_data); 1205 1206 return &panel_cntl->base; 1207 } 1208 1209 static void read_dce_straps( 1210 struct dc_context *ctx, 1211 struct resource_straps *straps) 1212 { 1213 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1214 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1215 1216 } 1217 1218 static struct audio *dcn31_create_audio( 1219 struct dc_context *ctx, unsigned int inst) 1220 { 1221 1222 #undef REG_STRUCT 1223 #define REG_STRUCT audio_regs 1224 audio_regs_init(0), 1225 audio_regs_init(1), 1226 audio_regs_init(2), 1227 audio_regs_init(3), 1228 audio_regs_init(4); 1229 audio_regs_init(5); 1230 audio_regs_init(6); 1231 1232 return dce_audio_create(ctx, inst, 1233 &audio_regs[inst], &audio_shift, &audio_mask); 1234 } 1235 1236 static struct vpg *dcn31_vpg_create( 1237 struct dc_context *ctx, 1238 uint32_t inst) 1239 { 1240 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg); 1241 1242 if (!vpg31) 1243 return NULL; 1244 1245 #undef REG_STRUCT 1246 #define REG_STRUCT vpg_regs 1247 vpg_regs_init(0), 1248 vpg_regs_init(1), 1249 vpg_regs_init(2), 1250 vpg_regs_init(3), 1251 vpg_regs_init(4), 1252 vpg_regs_init(5), 1253 vpg_regs_init(6), 1254 vpg_regs_init(7), 1255 vpg_regs_init(8), 1256 vpg_regs_init(9); 1257 1258 vpg31_construct(vpg31, ctx, inst, 1259 &vpg_regs[inst], 1260 &vpg_shift, 1261 &vpg_mask); 1262 1263 return &vpg31->base; 1264 } 1265 1266 static struct afmt *dcn31_afmt_create( 1267 struct dc_context *ctx, 1268 uint32_t inst) 1269 { 1270 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt); 1271 1272 if (!afmt31) 1273 return NULL; 1274 1275 #undef REG_STRUCT 1276 #define REG_STRUCT afmt_regs 1277 afmt_regs_init(0), 1278 afmt_regs_init(1), 1279 afmt_regs_init(2), 1280 afmt_regs_init(3), 1281 afmt_regs_init(4), 1282 afmt_regs_init(5); 1283 1284 afmt31_construct(afmt31, ctx, inst, 1285 &afmt_regs[inst], 1286 &afmt_shift, 1287 &afmt_mask); 1288 1289 // Light sleep by default, no need to power down here 1290 1291 return &afmt31->base; 1292 } 1293 1294 static struct apg *dcn31_apg_create( 1295 struct dc_context *ctx, 1296 uint32_t inst) 1297 { 1298 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg); 1299 1300 if (!apg31) 1301 return NULL; 1302 1303 #undef REG_STRUCT 1304 #define REG_STRUCT apg_regs 1305 apg_regs_init(0), 1306 apg_regs_init(1), 1307 apg_regs_init(2), 1308 apg_regs_init(3); 1309 1310 apg31_construct(apg31, ctx, inst, 1311 &apg_regs[inst], 1312 &apg_shift, 1313 &apg_mask); 1314 1315 return &apg31->base; 1316 } 1317 1318 static struct stream_encoder *dcn35_stream_encoder_create( 1319 enum engine_id eng_id, 1320 struct dc_context *ctx) 1321 { 1322 struct dcn10_stream_encoder *enc1; 1323 struct vpg *vpg; 1324 struct afmt *afmt; 1325 int vpg_inst; 1326 int afmt_inst; 1327 1328 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1329 if (eng_id <= ENGINE_ID_DIGF) { 1330 vpg_inst = eng_id; 1331 afmt_inst = eng_id; 1332 } else 1333 return NULL; 1334 1335 enc1 = kzalloc_obj(struct dcn10_stream_encoder); 1336 vpg = dcn31_vpg_create(ctx, vpg_inst); 1337 afmt = dcn31_afmt_create(ctx, afmt_inst); 1338 1339 if (!enc1 || !vpg || !afmt) { 1340 kfree(enc1); 1341 kfree(vpg); 1342 kfree(afmt); 1343 return NULL; 1344 } 1345 1346 #undef REG_STRUCT 1347 #define REG_STRUCT stream_enc_regs 1348 stream_enc_regs_init(0), 1349 stream_enc_regs_init(1), 1350 stream_enc_regs_init(2), 1351 stream_enc_regs_init(3), 1352 stream_enc_regs_init(4); 1353 1354 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1355 eng_id, vpg, afmt, 1356 &stream_enc_regs[eng_id], 1357 &se_shift, &se_mask); 1358 1359 return &enc1->base; 1360 } 1361 1362 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create( 1363 enum engine_id eng_id, 1364 struct dc_context *ctx) 1365 { 1366 struct dcn30_hpo_frl_stream_encoder *hpo_enc3; 1367 struct vpg *vpg; 1368 struct afmt *afmt; 1369 int vpg_inst; 1370 int afmt_inst; 1371 1372 #undef REG_STRUCT 1373 #define REG_STRUCT hpo_frl_stream_enc_regs 1374 hpo_frl_stream_encoder_reg_list(0), 1375 hpo_frl_stream_encoder_dme_reg_list(6); 1376 1377 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */ 1378 if (eng_id == ENGINE_ID_HPO_0) { 1379 vpg_inst = 5; 1380 afmt_inst = 5; 1381 } else 1382 return NULL; 1383 1384 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */ 1385 hpo_enc3 = kzalloc(sizeof(struct dcn30_hpo_frl_stream_encoder), GFP_KERNEL); 1386 vpg = dcn31_vpg_create(ctx, vpg_inst); 1387 afmt = dcn31_afmt_create(ctx, afmt_inst); 1388 1389 if (!hpo_enc3 || !vpg || !afmt) { 1390 kfree(hpo_enc3); 1391 kfree(vpg); 1392 kfree(afmt); 1393 return NULL; 1394 } 1395 1396 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios, 1397 eng_id, vpg, afmt, 1398 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0], 1399 &hpo_se_shift, &hpo_se_mask); 1400 1401 return &hpo_enc3->base; 1402 } 1403 1404 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create( 1405 enum engine_id eng_id, 1406 struct dc_context *ctx) 1407 { 1408 struct dcn30_hpo_frl_link_encoder *hpo_enc3; 1409 1410 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1)); 1411 1412 #undef REG_STRUCT 1413 #define REG_STRUCT hpo_frl_link_enc_regs 1414 hpo_frl_link_encoder_reg_list(0); 1415 1416 /* allocate HPO link encoder */ 1417 hpo_enc3 = kzalloc(sizeof(struct dcn30_hpo_frl_link_encoder), GFP_KERNEL); 1418 if (!hpo_enc3) 1419 return NULL; /* out of memory */ 1420 1421 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0, 1422 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0], 1423 &hpo_le_shift, &hpo_le_mask); 1424 1425 return &hpo_enc3->base; 1426 } 1427 1428 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1429 enum engine_id eng_id, 1430 struct dc_context *ctx) 1431 { 1432 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1433 struct vpg *vpg; 1434 struct apg *apg; 1435 uint32_t hpo_dp_inst; 1436 uint32_t vpg_inst; 1437 uint32_t apg_inst; 1438 1439 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1440 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1441 1442 /* Mapping of VPG register blocks to HPO DP block instance: 1443 * VPG[6] -> HPO_DP[0] 1444 * VPG[7] -> HPO_DP[1] 1445 * VPG[8] -> HPO_DP[2] 1446 * VPG[9] -> HPO_DP[3] 1447 */ 1448 vpg_inst = hpo_dp_inst + 6; 1449 1450 /* Mapping of APG register blocks to HPO DP block instance: 1451 * APG[0] -> HPO_DP[0] 1452 * APG[1] -> HPO_DP[1] 1453 * APG[2] -> HPO_DP[2] 1454 * APG[3] -> HPO_DP[3] 1455 */ 1456 apg_inst = hpo_dp_inst; 1457 1458 /* allocate HPO stream encoder and create VPG sub-block */ 1459 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder); 1460 vpg = dcn31_vpg_create(ctx, vpg_inst); 1461 apg = dcn31_apg_create(ctx, apg_inst); 1462 1463 if (!hpo_dp_enc31 || !vpg || !apg) { 1464 kfree(hpo_dp_enc31); 1465 kfree(vpg); 1466 kfree(apg); 1467 return NULL; 1468 } 1469 1470 #undef REG_STRUCT 1471 #define REG_STRUCT hpo_dp_stream_enc_regs 1472 hpo_dp_stream_encoder_reg_init(0), 1473 hpo_dp_stream_encoder_reg_init(1), 1474 hpo_dp_stream_encoder_reg_init(2), 1475 hpo_dp_stream_encoder_reg_init(3); 1476 1477 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1478 hpo_dp_inst, eng_id, vpg, apg, 1479 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1480 &hpo_dp_se_shift, &hpo_dp_se_mask); 1481 1482 return &hpo_dp_enc31->base; 1483 } 1484 1485 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1486 uint8_t inst, 1487 struct dc_context *ctx) 1488 { 1489 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1490 1491 /* allocate HPO link encoder */ 1492 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder); 1493 if (!hpo_dp_enc31) 1494 return NULL; /* out of memory */ 1495 1496 #undef REG_STRUCT 1497 #define REG_STRUCT hpo_dp_link_enc_regs 1498 hpo_dp_link_encoder_reg_init(0), 1499 hpo_dp_link_encoder_reg_init(1); 1500 1501 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1502 &hpo_dp_link_enc_regs[inst], 1503 &hpo_dp_le_shift, &hpo_dp_le_mask); 1504 1505 return &hpo_dp_enc31->base; 1506 } 1507 1508 static struct dce_hwseq *dcn36_hwseq_create( 1509 struct dc_context *ctx) 1510 { 1511 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 1512 1513 #undef REG_STRUCT 1514 #define REG_STRUCT hwseq_reg 1515 hwseq_reg_init(); 1516 1517 if (hws) { 1518 hws->ctx = ctx; 1519 hws->regs = &hwseq_reg; 1520 hws->shifts = &hwseq_shift; 1521 hws->masks = &hwseq_mask; 1522 } 1523 return hws; 1524 } 1525 static const struct resource_create_funcs res_create_funcs = { 1526 .read_dce_straps = read_dce_straps, 1527 .create_audio = dcn31_create_audio, 1528 .create_stream_encoder = dcn35_stream_encoder_create, 1529 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create, 1530 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1531 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1532 .create_hwseq = dcn36_hwseq_create, 1533 }; 1534 1535 static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) 1536 { 1537 unsigned int i; 1538 1539 for (i = 0; i < pool->base.stream_enc_count; i++) { 1540 if (pool->base.stream_enc[i] != NULL) { 1541 if (pool->base.stream_enc[i]->vpg != NULL) { 1542 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1543 pool->base.stream_enc[i]->vpg = NULL; 1544 } 1545 if (pool->base.stream_enc[i]->afmt != NULL) { 1546 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1547 pool->base.stream_enc[i]->afmt = NULL; 1548 } 1549 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1550 pool->base.stream_enc[i] = NULL; 1551 } 1552 } 1553 1554 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) { 1555 if (pool->base.hpo_frl_stream_enc[i] != NULL) { 1556 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) { 1557 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg)); 1558 pool->base.hpo_frl_stream_enc[i]->vpg = NULL; 1559 } 1560 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) { 1561 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt)); 1562 pool->base.hpo_frl_stream_enc[i]->afmt = NULL; 1563 } 1564 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i])); 1565 pool->base.hpo_frl_stream_enc[i] = NULL; 1566 } 1567 } 1568 1569 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1570 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1571 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1572 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1573 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1574 } 1575 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1576 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1577 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1578 } 1579 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1580 pool->base.hpo_dp_stream_enc[i] = NULL; 1581 } 1582 } 1583 1584 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1585 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1586 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1587 pool->base.hpo_dp_link_enc[i] = NULL; 1588 } 1589 } 1590 1591 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { 1592 if (pool->base.dscs[i] != NULL) 1593 dcn20_dsc_destroy(&pool->base.dscs[i]); 1594 } 1595 1596 if (pool->base.mpc != NULL) { 1597 kfree(TO_DCN20_MPC(pool->base.mpc)); 1598 pool->base.mpc = NULL; 1599 } 1600 if (pool->base.hubbub != NULL) { 1601 kfree(pool->base.hubbub); 1602 pool->base.hubbub = NULL; 1603 } 1604 for (i = 0; i < pool->base.pipe_count; i++) { 1605 if (pool->base.dpps[i] != NULL) 1606 dcn35_dpp_destroy(&pool->base.dpps[i]); 1607 1608 if (pool->base.ipps[i] != NULL) 1609 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1610 1611 if (pool->base.hubps[i] != NULL) { 1612 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1613 pool->base.hubps[i] = NULL; 1614 } 1615 1616 if (pool->base.irqs != NULL) { 1617 dal_irq_service_destroy(&pool->base.irqs); 1618 } 1619 } 1620 1621 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 1622 if (pool->base.engines[i] != NULL) 1623 dce110_engine_destroy(&pool->base.engines[i]); 1624 if (pool->base.hw_i2cs[i] != NULL) { 1625 kfree(pool->base.hw_i2cs[i]); 1626 pool->base.hw_i2cs[i] = NULL; 1627 } 1628 if (pool->base.sw_i2cs[i] != NULL) { 1629 kfree(pool->base.sw_i2cs[i]); 1630 pool->base.sw_i2cs[i] = NULL; 1631 } 1632 } 1633 1634 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { 1635 if (pool->base.opps[i] != NULL) 1636 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1637 } 1638 1639 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1640 if (pool->base.timing_generators[i] != NULL) { 1641 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1642 pool->base.timing_generators[i] = NULL; 1643 } 1644 } 1645 1646 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { 1647 if (pool->base.dwbc[i] != NULL) { 1648 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1649 pool->base.dwbc[i] = NULL; 1650 } 1651 if (pool->base.mcif_wb[i] != NULL) { 1652 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1653 pool->base.mcif_wb[i] = NULL; 1654 } 1655 } 1656 1657 for (i = 0; i < pool->base.audio_count; i++) { 1658 if (pool->base.audios[i]) 1659 dce_aud_destroy(&pool->base.audios[i]); 1660 } 1661 1662 for (i = 0; i < pool->base.clk_src_count; i++) { 1663 if (pool->base.clock_sources[i] != NULL) { 1664 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1665 pool->base.clock_sources[i] = NULL; 1666 } 1667 } 1668 1669 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { 1670 if (pool->base.mpc_lut[i] != NULL) { 1671 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1672 pool->base.mpc_lut[i] = NULL; 1673 } 1674 if (pool->base.mpc_shaper[i] != NULL) { 1675 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1676 pool->base.mpc_shaper[i] = NULL; 1677 } 1678 } 1679 1680 if (pool->base.dp_clock_source != NULL) { 1681 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1682 pool->base.dp_clock_source = NULL; 1683 } 1684 1685 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1686 if (pool->base.multiple_abms[i] != NULL) 1687 dce_abm_destroy(&pool->base.multiple_abms[i]); 1688 } 1689 1690 if (pool->base.psr != NULL) 1691 dmub_psr_destroy(&pool->base.psr); 1692 1693 if (pool->base.replay != NULL) 1694 dmub_replay_destroy(&pool->base.replay); 1695 1696 if (pool->base.pg_cntl != NULL) 1697 dcn_pg_cntl_destroy(&pool->base.pg_cntl); 1698 1699 if (pool->base.dccg != NULL) 1700 dcn_dccg_destroy(&pool->base.dccg); 1701 1702 if (pool->base.dio != NULL) { 1703 kfree(TO_DCN10_DIO(pool->base.dio)); 1704 pool->base.dio = NULL; 1705 } 1706 } 1707 1708 static struct hubp *dcn35_hubp_create( 1709 struct dc_context *ctx, 1710 uint32_t inst) 1711 { 1712 struct dcn20_hubp *hubp2 = 1713 kzalloc_obj(struct dcn20_hubp); 1714 1715 if (!hubp2) 1716 return NULL; 1717 1718 #undef REG_STRUCT 1719 #define REG_STRUCT hubp_regs 1720 hubp_regs_init(0), 1721 hubp_regs_init(1), 1722 hubp_regs_init(2), 1723 hubp_regs_init(3); 1724 1725 if (hubp35_construct(hubp2, ctx, inst, 1726 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1727 return &hubp2->base; 1728 1729 BREAK_TO_DEBUGGER(); 1730 kfree(hubp2); 1731 return NULL; 1732 } 1733 1734 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) 1735 { 1736 dcn35_dwbc_set_fgcg( 1737 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); 1738 } 1739 1740 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1741 { 1742 unsigned int i; 1743 uint32_t pipe_count = pool->res_cap->num_dwb; 1744 1745 for (i = 0; i < pipe_count; i++) { 1746 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); 1747 1748 if (!dwbc30) { 1749 dm_error("DC: failed to create dwbc30!\n"); 1750 return false; 1751 } 1752 1753 #undef REG_STRUCT 1754 #define REG_STRUCT dwbc35_regs 1755 dwbc_regs_dcn3_init(0); 1756 1757 dcn35_dwbc_construct(dwbc30, ctx, 1758 &dwbc35_regs[i], 1759 &dwbc35_shift, 1760 &dwbc35_mask, 1761 i); 1762 1763 pool->dwbc[i] = &dwbc30->base; 1764 1765 dcn35_dwbc_init(dwbc30, ctx); 1766 } 1767 return true; 1768 } 1769 1770 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, 1771 struct dc_context *ctx) 1772 { 1773 dcn35_mmhubbub_set_fgcg( 1774 mcif_wb30, 1775 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); 1776 } 1777 1778 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1779 { 1780 unsigned int i; 1781 uint32_t pipe_count = pool->res_cap->num_dwb; 1782 1783 for (i = 0; i < pipe_count; i++) { 1784 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub); 1785 1786 if (!mcif_wb30) { 1787 dm_error("DC: failed to create mcif_wb30!\n"); 1788 return false; 1789 } 1790 1791 #undef REG_STRUCT 1792 #define REG_STRUCT mcif_wb35_regs 1793 mcif_wb_regs_dcn3_init(0); 1794 1795 dcn35_mmhubbub_construct(mcif_wb30, ctx, 1796 &mcif_wb35_regs[i], 1797 &mcif_wb35_shift, 1798 &mcif_wb35_mask, 1799 i); 1800 1801 dcn35_mmhubbub_init(mcif_wb30, ctx); 1802 1803 pool->mcif_wb[i] = &mcif_wb30->base; 1804 } 1805 return true; 1806 } 1807 1808 static struct display_stream_compressor *dcn35_dsc_create( 1809 struct dc_context *ctx, uint32_t inst) 1810 { 1811 struct dcn20_dsc *dsc = 1812 kzalloc_obj(struct dcn20_dsc); 1813 1814 if (!dsc) { 1815 BREAK_TO_DEBUGGER(); 1816 return NULL; 1817 } 1818 1819 #undef REG_STRUCT 1820 #define REG_STRUCT dsc_regs 1821 dsc_regsDCN35_init(0), 1822 dsc_regsDCN35_init(1), 1823 dsc_regsDCN35_init(2), 1824 dsc_regsDCN35_init(3); 1825 1826 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1827 dsc35_set_fgcg(dsc, 1828 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); 1829 return &dsc->base; 1830 } 1831 1832 static void dcn36_destroy_resource_pool(struct resource_pool **pool) 1833 { 1834 struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool); 1835 1836 dcn36_resource_destruct(dcn36_pool); 1837 kfree(dcn36_pool); 1838 *pool = NULL; 1839 } 1840 1841 static struct clock_source *dcn35_clock_source_create( 1842 struct dc_context *ctx, 1843 struct dc_bios *bios, 1844 enum clock_source_id id, 1845 const struct dce110_clk_src_regs *regs, 1846 bool dp_clk_src) 1847 { 1848 struct dce110_clk_src *clk_src = 1849 kzalloc_obj(struct dce110_clk_src); 1850 1851 if (!clk_src) 1852 return NULL; 1853 1854 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1855 regs, &cs_shift, &cs_mask)) { 1856 clk_src->base.dp_clk_src = dp_clk_src; 1857 return &clk_src->base; 1858 } 1859 1860 kfree(clk_src); 1861 BREAK_TO_DEBUGGER(); 1862 return NULL; 1863 } 1864 1865 static struct dc_cap_funcs cap_funcs = { 1866 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1867 }; 1868 1869 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config) 1870 { 1871 *panel_config = panel_config_defaults; 1872 } 1873 1874 1875 static enum dc_status dcn35_validate_bandwidth(struct dc *dc, 1876 struct dc_state *context, 1877 enum dc_validate_mode validate_mode) 1878 { 1879 bool out = false; 1880 1881 DC_FP_START(); 1882 out = dml2_validate(dc, context, 1883 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1884 validate_mode); 1885 DC_FP_END(); 1886 1887 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) 1888 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1889 1890 DC_FP_START(); 1891 dcn35_decide_zstate_support(dc, context); 1892 DC_FP_END(); 1893 1894 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1895 } 1896 1897 1898 static int populate_dml_pipes_from_context_fpu(struct dc *dc, 1899 struct dc_state *context, 1900 display_e2e_pipe_params_st *pipes, 1901 enum dc_validate_mode validate_mode) 1902 { 1903 int ret; 1904 1905 DC_FP_START(); 1906 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); 1907 DC_FP_END(); 1908 1909 return ret; 1910 } 1911 1912 static struct resource_funcs dcn36_res_pool_funcs = { 1913 .destroy = dcn36_destroy_resource_pool, 1914 .link_enc_create = dcn35_link_encoder_create, 1915 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1916 .link_encs_assign = link_enc_cfg_link_encs_assign, 1917 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1918 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create, 1919 .panel_cntl_create = dcn31_panel_cntl_create, 1920 .validate_bandwidth = dcn35_validate_bandwidth, 1921 .calculate_wm_and_dlg = NULL, 1922 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1923 .populate_dml_pipes = populate_dml_pipes_from_context_fpu, 1924 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1925 .release_pipe = dcn20_release_pipe, 1926 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1927 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1928 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1929 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1930 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1931 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1932 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1933 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1934 .update_bw_bounding_box = dcn35_update_bw_bounding_box, 1935 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1936 .get_panel_config_defaults = dcn35_get_panel_config_defaults, 1937 .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, 1938 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 1939 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, 1940 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, 1941 .get_default_tiling_info = dcn10_get_default_tiling_info, 1942 }; 1943 1944 static bool dcn36_resource_construct( 1945 uint8_t num_virtual_links, 1946 struct dc *dc, 1947 struct dcn36_resource_pool *pool) 1948 { 1949 int i; 1950 struct dc_context *ctx = dc->ctx; 1951 struct irq_service_init_data init_data; 1952 1953 #undef REG_STRUCT 1954 #define REG_STRUCT bios_regs 1955 bios_regs_init(); 1956 1957 #undef REG_STRUCT 1958 #define REG_STRUCT clk_src_regs 1959 clk_src_regs_init(0, A), 1960 clk_src_regs_init(1, B), 1961 clk_src_regs_init(2, C), 1962 clk_src_regs_init(3, D), 1963 clk_src_regs_init(4, E); 1964 1965 #undef REG_STRUCT 1966 #define REG_STRUCT abm_regs 1967 abm_regs_init(0), 1968 abm_regs_init(1), 1969 abm_regs_init(2), 1970 abm_regs_init(3); 1971 1972 #undef REG_STRUCT 1973 #define REG_STRUCT dccg_regs 1974 dccg_regs_init(); 1975 1976 ctx->dc_bios->regs = &bios_regs; 1977 1978 pool->base.res_cap = &res_cap_dcn36; 1979 1980 pool->base.funcs = &dcn36_res_pool_funcs; 1981 1982 /************************************************* 1983 * Resource + asic cap harcoding * 1984 *************************************************/ 1985 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; 1986 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1987 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1988 dc->caps.max_downscale_ratio = 600; 1989 dc->caps.i2c_speed_in_khz = 100; 1990 dc->caps.i2c_speed_in_khz_hdcp = 100; 1991 dc->caps.max_cursor_size = 256; 1992 dc->caps.min_horizontal_blanking_period = 80; 1993 dc->caps.dmdata_alloc_size = 2048; 1994 dc->caps.max_slave_planes = 3; 1995 dc->caps.max_slave_yuv_planes = 3; 1996 dc->caps.max_slave_rgb_planes = 3; 1997 dc->caps.post_blend_color_processing = true; 1998 dc->caps.force_dp_tps4_for_cp2520 = true; 1999 if (dc->config.forceHBR2CP2520) 2000 dc->caps.force_dp_tps4_for_cp2520 = false; 2001 dc->caps.hdmi_hpo = true; 2002 dc->config.skip_frl_pretraining = true; 2003 dc->caps.dp_hpo = true; 2004 dc->caps.dp_hdmi21_pcon_support = true; 2005 2006 dc->caps.edp_dsc_support = true; 2007 dc->caps.extended_aux_timeout_support = true; 2008 dc->caps.dmcub_support = true; 2009 dc->caps.is_apu = true; 2010 dc->caps.seamless_odm = true; 2011 2012 dc->caps.zstate_support = true; 2013 dc->caps.ips_support = true; 2014 dc->caps.max_v_total = (1 << 15) - 1; 2015 dc->caps.vtotal_limited_by_fp2 = true; 2016 2017 /* Color pipeline capabilities */ 2018 dc->caps.color.dpp.dcn_arch = 1; 2019 dc->caps.color.dpp.input_lut_shared = 0; 2020 dc->caps.color.dpp.icsc = 1; 2021 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2022 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2023 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2024 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2025 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2026 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2027 dc->caps.color.dpp.post_csc = 1; 2028 dc->caps.color.dpp.gamma_corr = 1; 2029 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2030 2031 dc->caps.color.dpp.hw_3d_lut = 0; 2032 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2033 // no OGAM ROM on DCN301 2034 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2035 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2036 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2037 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2038 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2039 dc->caps.color.dpp.ocsc = 0; 2040 2041 dc->caps.color.mpc.gamut_remap = 1; 2042 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 2043 dc->caps.color.mpc.ogam_ram = 1; 2044 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2045 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2046 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2047 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2048 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2049 dc->caps.color.mpc.ocsc = 1; 2050 dc->caps.color.mpc.preblend = true; 2051 2052 dc->caps.num_of_host_routers = 2; 2053 dc->caps.num_of_dpias_per_host_router = 2; 2054 2055 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 2056 * to provide some margin. 2057 * It's expected for furture ASIC to have equal or higher value, in order to 2058 * have determinstic power improvement from generate to genration. 2059 * (i.e., we should not expect new ASIC generation with lower vmin rate) 2060 */ 2061 dc->caps.max_disp_clock_khz_at_vmin = 650000; 2062 2063 /* Sequential ONO is based on ASIC. */ 2064 if (dc->ctx->asic_id.hw_internal_rev >= 0x40) 2065 dc->caps.sequential_ono = true; 2066 2067 /* Use pipe context based otg sync logic */ 2068 dc->config.use_pipe_ctx_sync_logic = true; 2069 2070 dc->config.disable_hbr_audio_dp2 = true; 2071 /* read VBIOS LTTPR caps */ 2072 { 2073 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2074 enum bp_result bp_query_result; 2075 uint8_t is_vbios_lttpr_enable = 0; 2076 2077 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2078 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2079 } 2080 2081 /* interop bit is implicit */ 2082 { 2083 dc->caps.vbios_lttpr_aware = true; 2084 } 2085 } 2086 dc->check_config = config_defaults; 2087 2088 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2089 dc->debug = debug_defaults_drv; 2090 2091 /*HW default is to have all the FGCG enabled, SW no need to program them*/ 2092 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; 2093 // Init the vm_helper 2094 if (dc->vm_helper) 2095 vm_helper_init(dc->vm_helper, 16); 2096 2097 /************************************************* 2098 * Create resources * 2099 *************************************************/ 2100 2101 /* Clock Sources for Pixel Clock*/ 2102 pool->base.clock_sources[DCN36_CLK_SRC_PLL0] = 2103 dcn35_clock_source_create(ctx, ctx->dc_bios, 2104 CLOCK_SOURCE_COMBO_PHY_PLL0, 2105 &clk_src_regs[0], false); 2106 pool->base.clock_sources[DCN36_CLK_SRC_PLL1] = 2107 dcn35_clock_source_create(ctx, ctx->dc_bios, 2108 CLOCK_SOURCE_COMBO_PHY_PLL1, 2109 &clk_src_regs[1], false); 2110 pool->base.clock_sources[DCN36_CLK_SRC_PLL2] = 2111 dcn35_clock_source_create(ctx, ctx->dc_bios, 2112 CLOCK_SOURCE_COMBO_PHY_PLL2, 2113 &clk_src_regs[2], false); 2114 pool->base.clock_sources[DCN36_CLK_SRC_PLL3] = 2115 dcn35_clock_source_create(ctx, ctx->dc_bios, 2116 CLOCK_SOURCE_COMBO_PHY_PLL3, 2117 &clk_src_regs[3], false); 2118 pool->base.clock_sources[DCN36_CLK_SRC_PLL4] = 2119 dcn35_clock_source_create(ctx, ctx->dc_bios, 2120 CLOCK_SOURCE_COMBO_PHY_PLL4, 2121 &clk_src_regs[4], false); 2122 2123 pool->base.clk_src_count = DCN36_CLK_SRC_TOTAL; 2124 2125 /* todo: not reuse phy_pll registers */ 2126 pool->base.dp_clock_source = 2127 dcn35_clock_source_create(ctx, ctx->dc_bios, 2128 CLOCK_SOURCE_ID_DP_DTO, 2129 &clk_src_regs[0], true); 2130 2131 for (i = 0; i < (int)pool->base.clk_src_count; i++) { 2132 if (pool->base.clock_sources[i] == NULL) { 2133 dm_error("DC: failed to create clock sources!\n"); 2134 BREAK_TO_DEBUGGER(); 2135 goto create_fail; 2136 } 2137 } 2138 /*temp till dml2 fully work without dml1*/ 2139 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); 2140 2141 /* TODO: DCCG */ 2142 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2143 if (pool->base.dccg == NULL) { 2144 dm_error("DC: failed to create dccg!\n"); 2145 BREAK_TO_DEBUGGER(); 2146 goto create_fail; 2147 } 2148 2149 #undef REG_STRUCT 2150 #define REG_STRUCT pg_cntl_regs 2151 pg_cntl_dcn35_regs_init(); 2152 2153 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); 2154 if (pool->base.pg_cntl == NULL) { 2155 dm_error("DC: failed to create power gate control!\n"); 2156 BREAK_TO_DEBUGGER(); 2157 goto create_fail; 2158 } 2159 2160 /* TODO: IRQ */ 2161 init_data.ctx = dc->ctx; 2162 pool->base.irqs = dal_irq_service_dcn36_create(&init_data); 2163 if (!pool->base.irqs) 2164 goto create_fail; 2165 2166 /* HUBBUB */ 2167 pool->base.hubbub = dcn35_hubbub_create(ctx); 2168 if (pool->base.hubbub == NULL) { 2169 BREAK_TO_DEBUGGER(); 2170 dm_error("DC: failed to create hubbub!\n"); 2171 goto create_fail; 2172 } 2173 2174 /* DIO */ 2175 pool->base.dio = dcn36_dio_create(ctx); 2176 if (pool->base.dio == NULL) { 2177 BREAK_TO_DEBUGGER(); 2178 dm_error("DC: failed to create dio!\n"); 2179 goto create_fail; 2180 } 2181 2182 /* HUBPs, DPPs, OPPs and TGs */ 2183 for (i = 0; i < (int)pool->base.pipe_count; i++) { 2184 pool->base.hubps[i] = dcn35_hubp_create(ctx, i); 2185 if (pool->base.hubps[i] == NULL) { 2186 BREAK_TO_DEBUGGER(); 2187 dm_error( 2188 "DC: failed to create hubps!\n"); 2189 goto create_fail; 2190 } 2191 2192 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); 2193 if (pool->base.dpps[i] == NULL) { 2194 BREAK_TO_DEBUGGER(); 2195 dm_error( 2196 "DC: failed to create dpps!\n"); 2197 goto create_fail; 2198 } 2199 } 2200 2201 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2202 pool->base.opps[i] = dcn35_opp_create(ctx, i); 2203 if (pool->base.opps[i] == NULL) { 2204 BREAK_TO_DEBUGGER(); 2205 dm_error( 2206 "DC: failed to create output pixel processor!\n"); 2207 goto create_fail; 2208 } 2209 } 2210 2211 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2212 pool->base.timing_generators[i] = dcn35_timing_generator_create( 2213 ctx, i); 2214 if (pool->base.timing_generators[i] == NULL) { 2215 BREAK_TO_DEBUGGER(); 2216 dm_error("DC: failed to create tg!\n"); 2217 goto create_fail; 2218 } 2219 } 2220 pool->base.timing_generator_count = i; 2221 2222 /* PSR */ 2223 pool->base.psr = dmub_psr_create(ctx); 2224 if (pool->base.psr == NULL) { 2225 dm_error("DC: failed to create psr obj!\n"); 2226 BREAK_TO_DEBUGGER(); 2227 goto create_fail; 2228 } 2229 2230 /* Replay */ 2231 pool->base.replay = dmub_replay_create(ctx); 2232 if (pool->base.replay == NULL) { 2233 dm_error("DC: failed to create replay obj!\n"); 2234 BREAK_TO_DEBUGGER(); 2235 goto create_fail; 2236 } 2237 2238 /* ABM */ 2239 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2240 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2241 &abm_regs[i], 2242 &abm_shift, 2243 &abm_mask); 2244 if (pool->base.multiple_abms[i] == NULL) { 2245 dm_error("DC: failed to create abm for pipe %d!\n", i); 2246 BREAK_TO_DEBUGGER(); 2247 goto create_fail; 2248 } 2249 } 2250 2251 /* MPC and DSC */ 2252 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2253 if (pool->base.mpc == NULL) { 2254 BREAK_TO_DEBUGGER(); 2255 dm_error("DC: failed to create mpc!\n"); 2256 goto create_fail; 2257 } 2258 2259 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2260 pool->base.dscs[i] = dcn35_dsc_create(ctx, i); 2261 if (pool->base.dscs[i] == NULL) { 2262 BREAK_TO_DEBUGGER(); 2263 dm_error("DC: failed to create display stream compressor %d!\n", i); 2264 goto create_fail; 2265 } 2266 } 2267 2268 /* DWB and MMHUBBUB */ 2269 if (!dcn35_dwbc_create(ctx, &pool->base)) { 2270 BREAK_TO_DEBUGGER(); 2271 dm_error("DC: failed to create dwbc!\n"); 2272 goto create_fail; 2273 } 2274 2275 if (!dcn35_mmhubbub_create(ctx, &pool->base)) { 2276 BREAK_TO_DEBUGGER(); 2277 dm_error("DC: failed to create mcif_wb!\n"); 2278 goto create_fail; 2279 } 2280 2281 /* AUX and I2C */ 2282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2283 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2284 if (pool->base.engines[i] == NULL) { 2285 BREAK_TO_DEBUGGER(); 2286 dm_error( 2287 "DC:failed to create aux engine!!\n"); 2288 goto create_fail; 2289 } 2290 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2291 if (pool->base.hw_i2cs[i] == NULL) { 2292 BREAK_TO_DEBUGGER(); 2293 dm_error( 2294 "DC:failed to create hw i2c!!\n"); 2295 goto create_fail; 2296 } 2297 pool->base.sw_i2cs[i] = NULL; 2298 } 2299 2300 /* DCN3.5 has 6 DPIA */ 2301 pool->base.usb4_dpia_count = 4; 2302 if (dc->debug.dpia_debug.bits.disable_dpia) 2303 pool->base.usb4_dpia_count = 0; 2304 2305 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2306 if (!resource_construct(num_virtual_links, dc, &pool->base, 2307 &res_create_funcs)) 2308 goto create_fail; 2309 2310 /* HW Sequencer and Plane caps */ 2311 dcn35_hw_sequencer_construct(dc); 2312 2313 dc->caps.max_planes = pool->base.pipe_count; 2314 2315 for (i = 0; i < (int)dc->caps.max_planes; ++i) 2316 dc->caps.planes[i] = plane_cap; 2317 2318 dc->caps.max_odm_combine_factor = 4; 2319 2320 dc->cap_funcs = cap_funcs; 2321 2322 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 2323 2324 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2325 dc->dml2_options.use_native_soc_bb_construction = true; 2326 dc->dml2_options.minimize_dispclk_using_odm = false; 2327 if (dc->config.EnableMinDispClkODM) 2328 dc->dml2_options.minimize_dispclk_using_odm = true; 2329 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; 2330 2331 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2332 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2333 2334 dc->dml2_options.max_segments_per_hubp = 24; 2335 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ 2336 dc->dml2_options.override_det_buffer_size_kbytes = true; 2337 2338 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2339 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/ 2340 2341 return true; 2342 2343 create_fail: 2344 2345 dcn36_resource_destruct(pool); 2346 2347 return false; 2348 } 2349 2350 struct resource_pool *dcn36_create_resource_pool( 2351 const struct dc_init_data *init_data, 2352 struct dc *dc) 2353 { 2354 struct dcn36_resource_pool *pool = 2355 kzalloc_obj(struct dcn36_resource_pool); 2356 2357 if (!pool) 2358 return NULL; 2359 2360 if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) 2361 return &pool->base; 2362 2363 BREAK_TO_DEBUGGER(); 2364 kfree(pool); 2365 return NULL; 2366 } 2367