1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 #include "dcn35/dcn35_init.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dcn35_resource.h" 36 #include "dml2_0/dml2_wrapper.h" 37 38 #include "dcn20/dcn20_resource.h" 39 #include "dcn30/dcn30_resource.h" 40 #include "dcn31/dcn31_resource.h" 41 #include "dcn32/dcn32_resource.h" 42 43 #include "dcn10/dcn10_ipp.h" 44 #include "dcn30/dcn30_hubbub.h" 45 #include "dcn31/dcn31_hubbub.h" 46 #include "dcn35/dcn35_hubbub.h" 47 #include "dcn32/dcn32_mpc.h" 48 #include "dcn35/dcn35_hubp.h" 49 #include "irq/dcn35/irq_service_dcn35.h" 50 #include "dcn35/dcn35_dpp.h" 51 #include "dcn35/dcn35_optc.h" 52 #include "dcn20/dcn20_hwseq.h" 53 #include "dcn30/dcn30_hwseq.h" 54 #include "dce110/dce110_hwseq.h" 55 #include "dcn35/dcn35_opp.h" 56 #include "dcn35/dcn35_dsc.h" 57 #include "dcn30/dcn30_vpg.h" 58 #include "dcn30/dcn30_afmt.h" 59 #include "dcn31/dcn31_dio_link_encoder.h" 60 #include "dcn35/dcn35_dio_stream_encoder.h" 61 #include "dcn30/dcn30_hpo_frl_stream_encoder.h" 62 #include "dcn30/dcn30_hpo_frl_link_encoder.h" 63 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 64 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 65 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 66 #include "link_service.h" 67 #include "dcn31/dcn31_apg.h" 68 #include "dcn32/dcn32_dio_link_encoder.h" 69 #include "dcn31/dcn31_vpg.h" 70 #include "dcn31/dcn31_afmt.h" 71 #include "dce/dce_clock_source.h" 72 #include "dce/dce_audio.h" 73 #include "dce/dce_hwseq.h" 74 #include "clk_mgr.h" 75 #include "dio/virtual/virtual_stream_encoder.h" 76 #include "dio/dcn10/dcn10_dio.h" 77 #include "dce110/dce110_resource.h" 78 #include "dml/display_mode_vba.h" 79 #include "dcn35/dcn35_dccg.h" 80 #include "dcn35/dcn35_pg_cntl.h" 81 #include "dcn10/dcn10_resource.h" 82 #include "dcn31/dcn31_panel_cntl.h" 83 #include "dcn35/dcn35_hwseq.h" 84 #include "dcn35/dcn35_dio_link_encoder.h" 85 #include "dml/dcn31/dcn31_fpu.h" /*todo*/ 86 #include "dml/dcn35/dcn35_fpu.h" 87 #include "dcn35/dcn35_dwb.h" 88 #include "dcn35/dcn35_mmhubbub.h" 89 90 #include "dcn/dcn_3_5_0_offset.h" 91 #include "dcn/dcn_3_5_0_sh_mask.h" 92 #include "nbio/nbio_7_11_0_offset.h" 93 #include "mmhub/mmhub_3_3_0_offset.h" 94 #include "mmhub/mmhub_3_3_0_sh_mask.h" 95 96 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 97 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL 98 99 #include "reg_helper.h" 100 #include "dce/dmub_abm.h" 101 #include "dce/dmub_psr.h" 102 #include "dce/dmub_replay.h" 103 #include "dce/dce_aux.h" 104 #include "dce/dce_i2c.h" 105 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/ 106 #include "vm_helper.h" 107 #include "dcn20/dcn20_vmid.h" 108 109 #include "dc_state_priv.h" 110 111 #include "link_enc_cfg.h" 112 #define DC_LOGGER_INIT(logger) 113 114 enum dcn35_clk_src_array_id { 115 DCN35_CLK_SRC_PLL0, 116 DCN35_CLK_SRC_PLL1, 117 DCN35_CLK_SRC_PLL2, 118 DCN35_CLK_SRC_PLL3, 119 DCN35_CLK_SRC_PLL4, 120 DCN35_CLK_SRC_TOTAL 121 }; 122 123 /* begin ********************* 124 * macros to expend register list macro defined in HW object header file 125 */ 126 127 /* DCN */ 128 /* TODO awful hack. fixup dcn20_dwb.h */ 129 #undef BASE_INNER 130 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 131 132 #define BASE(seg) BASE_INNER(seg) 133 134 #define SR(reg_name)\ 135 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 136 reg ## reg_name 137 138 #define SR_ARR(reg_name, id) \ 139 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 140 141 #define SR_ARR_INIT(reg_name, id, value) \ 142 REG_STRUCT[id].reg_name = value 143 144 #define SRI(reg_name, block, id)\ 145 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 146 reg ## block ## id ## _ ## reg_name 147 148 #define SRI_ARR(reg_name, block, id)\ 149 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 150 reg ## block ## id ## _ ## reg_name 151 152 #define SR_ARR_I2C(reg_name, id) \ 153 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 154 155 #define SRI_ARR_I2C(reg_name, block, id)\ 156 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 157 reg ## block ## id ## _ ## reg_name 158 159 #define SRI_ARR_DME(reg_name, block, id, offset)\ 160 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 164 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 reg ## block ## id ## _ ## reg_name 166 167 #define SRI2(reg_name, block, id)\ 168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 169 reg ## reg_name 170 171 #define SRI2_ARR(reg_name, block, id)\ 172 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 173 reg ## reg_name 174 175 #define SRIR(var_name, reg_name, block, id)\ 176 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 reg ## block ## id ## _ ## reg_name 178 179 #define SRII(reg_name, block, id)\ 180 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 181 reg ## block ## id ## _ ## reg_name 182 183 #define SRII_ARR_2(reg_name, block, id, inst)\ 184 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 185 reg ## block ## id ## _ ## reg_name 186 187 #define SRII_MPC_RMU(reg_name, block, id)\ 188 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 reg ## block ## id ## _ ## reg_name 190 191 #define SRII_DWB(reg_name, temp_name, block, id)\ 192 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 193 reg ## block ## id ## _ ## temp_name 194 195 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 196 .field_name = reg_name ## __ ## field_name ## post_fix 197 198 #define DCCG_SRII(reg_name, block, id)\ 199 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 200 reg ## block ## id ## _ ## reg_name 201 202 #define VUPDATE_SRII(reg_name, block, id)\ 203 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 204 reg ## reg_name ## _ ## block ## id 205 206 /* NBIO */ 207 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 208 209 #define NBIO_BASE(seg) \ 210 NBIO_BASE_INNER(seg) 211 212 #define NBIO_SR(reg_name)\ 213 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 214 regBIF_BX1_ ## reg_name 215 216 #define NBIO_SR_ARR(reg_name, id)\ 217 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 218 regBIF_BX1_ ## reg_name 219 220 #define bios_regs_init() \ 221 ( \ 222 NBIO_SR(BIOS_SCRATCH_3),\ 223 NBIO_SR(BIOS_SCRATCH_6)\ 224 ) 225 226 static struct bios_registers bios_regs; 227 228 #define clk_src_regs_init(index, pllid)\ 229 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 230 231 static struct dce110_clk_src_regs clk_src_regs[5]; 232 233 static const struct dce110_clk_src_shift cs_shift = { 234 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) 235 }; 236 237 static const struct dce110_clk_src_mask cs_mask = { 238 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) 239 }; 240 241 #define abm_regs_init(id)\ 242 ABM_DCN32_REG_LIST_RI(id) 243 244 static struct dce_abm_registers abm_regs[4]; 245 246 static const struct dce_abm_shift abm_shift = { 247 ABM_MASK_SH_LIST_DCN35(__SHIFT) 248 }; 249 250 static const struct dce_abm_mask abm_mask = { 251 ABM_MASK_SH_LIST_DCN35(_MASK) 252 }; 253 254 #define audio_regs_init(id)\ 255 AUD_COMMON_REG_LIST_RI(id) 256 257 static struct dce_audio_registers audio_regs[7]; 258 259 260 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 263 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 264 265 static const struct dce_audio_shift audio_shift = { 266 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 267 }; 268 269 static const struct dce_audio_mask audio_mask = { 270 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 271 }; 272 273 #define vpg_regs_init(id)\ 274 VPG_DCN31_REG_LIST_RI(id) 275 276 static struct dcn31_vpg_registers vpg_regs[10]; 277 278 static const struct dcn31_vpg_shift vpg_shift = { 279 DCN31_VPG_MASK_SH_LIST(__SHIFT) 280 }; 281 282 static const struct dcn31_vpg_mask vpg_mask = { 283 DCN31_VPG_MASK_SH_LIST(_MASK) 284 }; 285 286 #define afmt_regs_init(id)\ 287 AFMT_DCN31_REG_LIST_RI(id) 288 289 static struct dcn31_afmt_registers afmt_regs[6]; 290 291 static const struct dcn31_afmt_shift afmt_shift = { 292 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 293 }; 294 295 static const struct dcn31_afmt_mask afmt_mask = { 296 DCN31_AFMT_MASK_SH_LIST(_MASK) 297 }; 298 299 #define apg_regs_init(id)\ 300 APG_DCN31_REG_LIST_RI(id) 301 302 static struct dcn31_apg_registers apg_regs[4]; 303 304 static const struct dcn31_apg_shift apg_shift = { 305 DCN31_APG_MASK_SH_LIST(__SHIFT) 306 }; 307 308 static const struct dcn31_apg_mask apg_mask = { 309 DCN31_APG_MASK_SH_LIST(_MASK) 310 }; 311 312 #define stream_enc_regs_init(id)\ 313 SE_DCN35_REG_LIST_RI(id) 314 315 static struct dcn10_stream_enc_registers stream_enc_regs[5]; 316 317 static const struct dcn10_stream_encoder_shift se_shift = { 318 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 319 }; 320 321 static const struct dcn10_stream_encoder_mask se_mask = { 322 SE_COMMON_MASK_SH_LIST_DCN35(_MASK) 323 }; 324 325 #define aux_regs_init(id)\ 326 DCN2_AUX_REG_LIST_RI(id) 327 328 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 329 330 #define hpd_regs_init(id)\ 331 HPD_REG_LIST_RI(id) 332 333 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 334 335 336 static const struct dce110_aux_registers_shift aux_shift = { 337 DCN_AUX_MASK_SH_LIST(__SHIFT) 338 }; 339 340 static const struct dce110_aux_registers_mask aux_mask = { 341 DCN_AUX_MASK_SH_LIST(_MASK) 342 }; 343 344 #define link_regs_init(id, phyid)\ 345 ( \ 346 LE_DCN35_REG_LIST_RI(id), \ 347 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\ 348 ) 349 350 static struct dcn10_link_enc_registers link_enc_regs[5]; 351 352 static const struct dcn10_link_enc_shift le_shift = { 353 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \ 354 //DPCS_DCN31_MASK_SH_LIST(__SHIFT) 355 }; 356 357 static const struct dcn10_link_enc_mask le_mask = { 358 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \ 359 //DPCS_DCN31_MASK_SH_LIST(_MASK) 360 }; 361 362 #define hpo_frl_stream_encoder_dme_reg_list(id)\ 363 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6) 364 365 #define hpo_frl_stream_encoder_reg_list(id)\ 366 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) 367 368 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2]; 369 370 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = { 371 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT) 372 }; 373 374 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = { 375 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK) 376 }; 377 378 #define hpo_frl_link_encoder_reg_list(id)\ 379 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id) 380 381 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1]; 382 383 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = { 384 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT) 385 }; 386 387 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = { 388 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK) 389 }; 390 391 #define hpo_dp_stream_encoder_reg_init(id)\ 392 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 393 394 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 395 396 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 397 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 398 }; 399 400 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 401 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 402 }; 403 404 #define hpo_dp_link_encoder_reg_init(id)\ 405 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 406 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 407 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 408 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 409 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 410 411 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; 412 413 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 414 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT) 415 }; 416 417 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 418 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK) 419 }; 420 421 #define dpp_regs_init(id)\ 422 DPP_REG_LIST_DCN35_RI(id) 423 424 static struct dcn3_dpp_registers dpp_regs[4]; 425 426 static const struct dcn35_dpp_shift tf_shift = { 427 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT) 428 }; 429 430 static const struct dcn35_dpp_mask tf_mask = { 431 DPP_REG_LIST_SH_MASK_DCN35(_MASK) 432 }; 433 434 #define opp_regs_init(id)\ 435 OPP_REG_LIST_DCN35_RI(id) 436 437 static struct dcn35_opp_registers opp_regs[4]; 438 439 static const struct dcn35_opp_shift opp_shift = { 440 OPP_MASK_SH_LIST_DCN35(__SHIFT) 441 }; 442 443 static const struct dcn35_opp_mask opp_mask = { 444 OPP_MASK_SH_LIST_DCN35(_MASK) 445 }; 446 447 #define aux_engine_regs_init(id)\ 448 ( \ 449 AUX_COMMON_REG_LIST0_RI(id), \ 450 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 451 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 452 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \ 453 ) 454 455 static struct dce110_aux_registers aux_engine_regs[5]; 456 457 #define dwbc_regs_dcn3_init(id)\ 458 DWBC_COMMON_REG_LIST_DCN30_RI(id) 459 460 static struct dcn30_dwbc_registers dwbc35_regs[1]; 461 462 static const struct dcn35_dwbc_shift dwbc35_shift = { 463 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 464 }; 465 466 static const struct dcn35_dwbc_mask dwbc35_mask = { 467 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK) 468 }; 469 470 #define mcif_wb_regs_dcn3_init(id)\ 471 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) 472 473 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; 474 475 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { 476 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 477 }; 478 479 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { 480 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 481 }; 482 483 #define dsc_regsDCN35_init(id)\ 484 DSC_REG_LIST_DCN20_RI(id) 485 486 static struct dcn20_dsc_registers dsc_regs[4]; 487 488 static const struct dcn35_dsc_shift dsc_shift = { 489 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT) 490 }; 491 492 static const struct dcn35_dsc_mask dsc_mask = { 493 DSC_REG_LIST_SH_MASK_DCN35(_MASK) 494 }; 495 496 static struct dcn30_mpc_registers mpc_regs; 497 498 #define dcn_mpc_regs_init() \ 499 MPC_REG_LIST_DCN3_2_RI(0),\ 500 MPC_REG_LIST_DCN3_2_RI(1),\ 501 MPC_REG_LIST_DCN3_2_RI(2),\ 502 MPC_REG_LIST_DCN3_2_RI(3),\ 503 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 504 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 505 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 506 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\ 507 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0) 508 509 static const struct dcn30_mpc_shift mpc_shift = { 510 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 511 }; 512 513 static const struct dcn30_mpc_mask mpc_mask = { 514 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK) 515 }; 516 517 #define optc_regs_init(id)\ 518 OPTC_COMMON_REG_LIST_DCN3_5_RI(id) 519 520 static struct dcn_optc_registers optc_regs[4]; 521 522 static const struct dcn_optc_shift optc_shift = { 523 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 524 }; 525 526 static const struct dcn_optc_mask optc_mask = { 527 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 528 }; 529 530 #define hubp_regs_init(id)\ 531 HUBP_REG_LIST_DCN30_RI(id) 532 533 static struct dcn_hubp2_registers hubp_regs[4]; 534 535 536 static const struct dcn35_hubp2_shift hubp_shift = { 537 HUBP_MASK_SH_LIST_DCN35(__SHIFT) 538 }; 539 540 static const struct dcn35_hubp2_mask hubp_mask = { 541 HUBP_MASK_SH_LIST_DCN35(_MASK) 542 }; 543 544 static struct dcn_hubbub_registers hubbub_reg; 545 546 #define hubbub_reg_init()\ 547 HUBBUB_REG_LIST_DCN35(0) 548 549 static const struct dcn_hubbub_shift hubbub_shift = { 550 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT) 551 }; 552 553 static const struct dcn_hubbub_mask hubbub_mask = { 554 HUBBUB_MASK_SH_LIST_DCN35(_MASK) 555 }; 556 557 static struct dccg_registers dccg_regs; 558 559 #define dccg_regs_init()\ 560 DCCG_REG_LIST_DCN35() 561 562 static const struct dccg_shift dccg_shift = { 563 DCCG_MASK_SH_LIST_DCN35(__SHIFT) 564 }; 565 566 static const struct dccg_mask dccg_mask = { 567 DCCG_MASK_SH_LIST_DCN35(_MASK) 568 }; 569 570 static struct pg_cntl_registers pg_cntl_regs; 571 572 #define pg_cntl_dcn35_regs_init() \ 573 PG_CNTL_REG_LIST_DCN35() 574 575 static const struct pg_cntl_shift pg_cntl_shift = { 576 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT) 577 }; 578 579 static const struct pg_cntl_mask pg_cntl_mask = { 580 PG_CNTL_MASK_SH_LIST_DCN35(_MASK) 581 }; 582 583 #define SRII2(reg_name_pre, reg_name_post, id)\ 584 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 585 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 586 reg ## reg_name_pre ## id ## _ ## reg_name_post 587 588 static struct dce_hwseq_registers hwseq_reg; 589 590 #define hwseq_reg_init()\ 591 HWSEQ_DCN35_REG_LIST() 592 593 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\ 594 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 595 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 596 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 597 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 598 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 599 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 600 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 601 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 602 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 603 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 604 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 605 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 606 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 607 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 608 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 609 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 610 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 611 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 612 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 613 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 614 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 615 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 616 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 617 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 618 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 619 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 620 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 621 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 622 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 623 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 624 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 625 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 626 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 627 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 628 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 629 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 630 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 631 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 632 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 633 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 634 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 635 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 636 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 637 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 638 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 639 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\ 640 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ 641 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ 642 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ 643 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 644 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 645 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 646 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 647 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ 648 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ 649 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 650 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 651 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 652 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 653 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 654 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 655 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 656 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 657 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 658 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ 659 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 660 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 661 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 662 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 663 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 664 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 665 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 666 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 667 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 668 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ 669 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ 670 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ 671 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ 672 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ 673 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ 674 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ 675 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ 676 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ 677 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ 678 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ 679 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ 680 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh) 681 682 static const struct dce_hwseq_shift hwseq_shift = { 683 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT) 684 }; 685 686 static const struct dce_hwseq_mask hwseq_mask = { 687 HWSEQ_DCN35_MASK_SH_LIST(_MASK) 688 }; 689 690 #define vmid_regs_init(id)\ 691 DCN20_VMID_REG_LIST_RI(id) 692 693 static struct dcn_vmid_registers vmid_regs[16]; 694 695 static const struct dcn20_vmid_shift vmid_shifts = { 696 DCN20_VMID_MASK_SH_LIST(__SHIFT) 697 }; 698 699 static const struct dcn20_vmid_mask vmid_masks = { 700 DCN20_VMID_MASK_SH_LIST(_MASK) 701 }; 702 703 static struct dcn_dio_registers dio_regs; 704 705 #define DIO_MASK_SH_LIST(mask_sh)\ 706 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 707 708 static const struct dcn_dio_shift dio_shift = { 709 DIO_MASK_SH_LIST(__SHIFT) 710 }; 711 712 static const struct dcn_dio_mask dio_mask = { 713 DIO_MASK_SH_LIST(_MASK) 714 }; 715 716 static const struct resource_caps res_cap_dcn35 = { 717 .num_timing_generator = 4, 718 .num_opp = 4, 719 .num_video_plane = 4, 720 .num_audio = 5, 721 .num_stream_encoder = 5, 722 .num_dig_link_enc = 5, 723 .num_hpo_frl = 1, 724 .num_hpo_dp_stream_encoder = 4, 725 .num_hpo_dp_link_encoder = 2, 726 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/ 727 .num_dwb = 1, 728 .num_ddc = 5, 729 .num_vmid = 16, 730 .num_mpc_3dlut = 2, 731 .num_dsc = 4, 732 }; 733 734 static const struct dc_plane_cap plane_cap = { 735 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 736 .per_pixel_alpha = true, 737 738 .pixel_format_support = { 739 .argb8888 = true, 740 .nv12 = true, 741 .fp16 = true, 742 .p010 = true, 743 .ayuv = false, 744 }, 745 746 .max_upscale_factor = { 747 .argb8888 = 16000, 748 .nv12 = 16000, 749 .fp16 = 16000 750 }, 751 752 // 6:1 downscaling ratio: 1000/6 = 166.666 753 .max_downscale_factor = { 754 .argb8888 = 250, 755 .nv12 = 167, 756 .fp16 = 167 757 }, 758 64, 759 64 760 }; 761 762 static const struct dc_debug_options debug_defaults_drv = { 763 .disable_dmcu = true, 764 .force_abm_enable = false, 765 .clock_trace = true, 766 .disable_pplib_clock_request = false, 767 .pipe_split_policy = MPC_SPLIT_AVOID, 768 .force_single_disp_pipe_split = false, 769 .disable_dcc = DCC_ENABLE, 770 .disable_dpp_power_gate = true, 771 .disable_hubp_power_gate = true, 772 .disable_optc_power_gate = true, /*should the same as above two*/ 773 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/ 774 .disable_clock_gate = false, 775 .disable_dsc_power_gate = true, 776 .vsr_support = true, 777 .performance_trace = false, 778 .max_downscale_src_width = 4096,/*upto true 4k*/ 779 .disable_pplib_wm_range = false, 780 .scl_reset_length10 = true, 781 .sanity_checks = false, 782 .underflow_assert_delay_us = 0xFFFFFFFF, 783 .dwb_fi_phase = -1, // -1 = disable, 784 .dmub_command_table = true, 785 .pstate_enabled = true, 786 .use_max_lb = true, 787 .enable_mem_low_power = { 788 .bits = { 789 .vga = false, 790 .i2c = true, 791 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 792 .dscl = true, 793 .cm = true, 794 .mpc = true, 795 .optc = true, 796 .vpg = true, 797 .afmt = true, 798 } 799 }, 800 .root_clock_optimization = { 801 .bits = { 802 .dpp = true, 803 .dsc = true,/*dscclk and dsc pg*/ 804 .hdmistream = true, 805 .hdmichar = true, 806 .dpstream = true, 807 .symclk32_se = true, 808 .symclk32_le = true, 809 .symclk_fe = true, 810 .physymclk = false, 811 .dpiasymclk = true, 812 } 813 }, 814 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, 815 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 816 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ 817 .using_dml2 = true, 818 .support_eDP1_5 = true, 819 .enable_hpo_pg_support = false, 820 .enable_single_display_2to1_odm_policy = true, 821 .disable_idle_power_optimizations = false, 822 .dmcub_emulation = false, 823 .disable_boot_optimizations = false, 824 .disable_unbounded_requesting = false, 825 .disable_mem_low_power = false, 826 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 827 .enable_double_buffered_dsc_pg_support = true, 828 .enable_dp_dig_pixel_rate_div_policy = 1, 829 .disable_z10 = false, 830 .ignore_pg = true, 831 .psp_disabled_wa = true, 832 .ips2_eval_delay_us = 2000, 833 .ips2_entry_delay_us = 800, 834 .disable_dmub_reallow_idle = false, 835 .static_screen_wait_frames = 2, 836 .disable_timeout = true, 837 .min_disp_clk_khz = 50000, 838 }; 839 840 static const struct dc_check_config config_defaults = { 841 .enable_legacy_fast_update = false, 842 }; 843 844 static const struct dc_panel_config panel_config_defaults = { 845 .psr = { 846 .disable_psr = false, 847 .disallow_psrsu = false, 848 .disallow_replay = false, 849 }, 850 .ilr = { 851 .optimize_edp_link_rate = true, 852 }, 853 }; 854 855 static void dcn35_dpp_destroy(struct dpp **dpp) 856 { 857 kfree(TO_DCN20_DPP(*dpp)); 858 *dpp = NULL; 859 } 860 861 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) 862 { 863 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); 864 bool success = (dpp != NULL); 865 866 if (!success) 867 return NULL; 868 869 #undef REG_STRUCT 870 #define REG_STRUCT dpp_regs 871 dpp_regs_init(0), 872 dpp_regs_init(1), 873 dpp_regs_init(2), 874 dpp_regs_init(3); 875 876 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, 877 &tf_mask); 878 if (success) { 879 dpp35_set_fgcg( 880 dpp, 881 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); 882 return &dpp->base; 883 } 884 885 BREAK_TO_DEBUGGER(); 886 kfree(dpp); 887 return NULL; 888 } 889 890 static struct output_pixel_processor *dcn35_opp_create( 891 struct dc_context *ctx, uint32_t inst) 892 { 893 struct dcn20_opp *opp = 894 kzalloc_obj(struct dcn20_opp); 895 896 if (!opp) { 897 BREAK_TO_DEBUGGER(); 898 return NULL; 899 } 900 901 #undef REG_STRUCT 902 #define REG_STRUCT opp_regs 903 opp_regs_init(0), 904 opp_regs_init(1), 905 opp_regs_init(2), 906 opp_regs_init(3); 907 908 dcn35_opp_construct(opp, ctx, inst, 909 &opp_regs[inst], &opp_shift, &opp_mask); 910 911 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); 912 913 return &opp->base; 914 } 915 916 static struct dce_aux *dcn31_aux_engine_create( 917 struct dc_context *ctx, 918 uint32_t inst) 919 { 920 struct aux_engine_dce110 *aux_engine = 921 kzalloc_obj(struct aux_engine_dce110); 922 923 if (!aux_engine) 924 return NULL; 925 926 #undef REG_STRUCT 927 #define REG_STRUCT aux_engine_regs 928 aux_engine_regs_init(0), 929 aux_engine_regs_init(1), 930 aux_engine_regs_init(2), 931 aux_engine_regs_init(3), 932 aux_engine_regs_init(4); 933 934 dce110_aux_engine_construct(aux_engine, ctx, inst, 935 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 936 &aux_engine_regs[inst], 937 &aux_mask, 938 &aux_shift, 939 ctx->dc->caps.extended_aux_timeout_support); 940 941 return &aux_engine->base; 942 } 943 944 #define i2c_inst_regs_init(id)\ 945 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 946 947 static struct dce_i2c_registers i2c_hw_regs[5]; 948 949 static const struct dce_i2c_shift i2c_shifts = { 950 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) 951 }; 952 953 static const struct dce_i2c_mask i2c_masks = { 954 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) 955 }; 956 957 /* ========================================================== */ 958 959 /* 960 * DPIA index | Preferred Encoder | Host Router 961 * 0 | C | 0 962 * 1 | First Available | 0 963 * 2 | D | 1 964 * 3 | First Available | 1 965 */ 966 /* ========================================================== */ 967 static const enum engine_id dpia_to_preferred_enc_id_table[] = { 968 ENGINE_ID_DIGC, 969 ENGINE_ID_DIGC, 970 ENGINE_ID_DIGD, 971 ENGINE_ID_DIGD 972 }; 973 974 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index) 975 { 976 return dpia_to_preferred_enc_id_table[dpia_index]; 977 } 978 979 static struct dce_i2c_hw *dcn31_i2c_hw_create( 980 struct dc_context *ctx, 981 uint32_t inst) 982 { 983 struct dce_i2c_hw *dce_i2c_hw = 984 kzalloc_obj(struct dce_i2c_hw); 985 986 if (!dce_i2c_hw) 987 return NULL; 988 989 #undef REG_STRUCT 990 #define REG_STRUCT i2c_hw_regs 991 i2c_inst_regs_init(1), 992 i2c_inst_regs_init(2), 993 i2c_inst_regs_init(3), 994 i2c_inst_regs_init(4), 995 i2c_inst_regs_init(5); 996 997 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 998 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 999 1000 return dce_i2c_hw; 1001 } 1002 static struct mpc *dcn35_mpc_create( 1003 struct dc_context *ctx, 1004 int num_mpcc, 1005 int num_rmu) 1006 { 1007 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc); 1008 1009 if (!mpc30) 1010 return NULL; 1011 1012 #undef REG_STRUCT 1013 #define REG_STRUCT mpc_regs 1014 dcn_mpc_regs_init(); 1015 1016 dcn32_mpc_construct(mpc30, ctx, 1017 &mpc_regs, 1018 &mpc_shift, 1019 &mpc_mask, 1020 num_mpcc, 1021 num_rmu); 1022 1023 return &mpc30->base; 1024 } 1025 1026 static struct dio *dcn35_dio_create(struct dc_context *ctx) 1027 { 1028 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1029 1030 if (!dio10) 1031 return NULL; 1032 1033 #undef REG_STRUCT 1034 #define REG_STRUCT dio_regs 1035 DIO_REG_LIST_DCN10(); 1036 1037 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1038 1039 return &dio10->base; 1040 } 1041 1042 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) 1043 { 1044 int i; 1045 1046 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub); 1047 1048 if (!hubbub3) 1049 return NULL; 1050 1051 #undef REG_STRUCT 1052 #define REG_STRUCT hubbub_reg 1053 hubbub_reg_init(); 1054 1055 #undef REG_STRUCT 1056 #define REG_STRUCT vmid_regs 1057 vmid_regs_init(0), 1058 vmid_regs_init(1), 1059 vmid_regs_init(2), 1060 vmid_regs_init(3), 1061 vmid_regs_init(4), 1062 vmid_regs_init(5), 1063 vmid_regs_init(6), 1064 vmid_regs_init(7), 1065 vmid_regs_init(8), 1066 vmid_regs_init(9), 1067 vmid_regs_init(10), 1068 vmid_regs_init(11), 1069 vmid_regs_init(12), 1070 vmid_regs_init(13), 1071 vmid_regs_init(14), 1072 vmid_regs_init(15); 1073 1074 hubbub35_construct(hubbub3, ctx, 1075 &hubbub_reg, 1076 &hubbub_shift, 1077 &hubbub_mask, 1078 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/ 1079 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/ 1080 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/); 1081 1082 1083 for (i = 0; i < res_cap_dcn35.num_vmid; i++) { 1084 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1085 1086 vmid->ctx = ctx; 1087 1088 vmid->regs = &vmid_regs[i]; 1089 vmid->shifts = &vmid_shifts; 1090 vmid->masks = &vmid_masks; 1091 } 1092 1093 return &hubbub3->base; 1094 } 1095 1096 static struct timing_generator *dcn35_timing_generator_create( 1097 struct dc_context *ctx, 1098 uint32_t instance) 1099 { 1100 struct optc *tgn10 = 1101 kzalloc_obj(struct optc); 1102 1103 if (!tgn10) 1104 return NULL; 1105 1106 #undef REG_STRUCT 1107 #define REG_STRUCT optc_regs 1108 optc_regs_init(0), 1109 optc_regs_init(1), 1110 optc_regs_init(2), 1111 optc_regs_init(3); 1112 1113 tgn10->base.inst = instance; 1114 tgn10->base.ctx = ctx; 1115 1116 tgn10->tg_regs = &optc_regs[instance]; 1117 tgn10->tg_shift = &optc_shift; 1118 tgn10->tg_mask = &optc_mask; 1119 1120 dcn35_timing_generator_init(tgn10); 1121 1122 return &tgn10->base; 1123 } 1124 1125 static const struct encoder_feature_support link_enc_feature = { 1126 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1127 .max_hdmi_pixel_clock = 600000, 1128 .hdmi_ycbcr420_supported = true, 1129 .dp_ycbcr420_supported = true, 1130 .fec_supported = true, 1131 .flags.bits.IS_HBR2_CAPABLE = true, 1132 .flags.bits.IS_HBR3_CAPABLE = true, 1133 .flags.bits.IS_TPS3_CAPABLE = true, 1134 .flags.bits.IS_TPS4_CAPABLE = true 1135 }; 1136 1137 static struct link_encoder *dcn35_link_encoder_create( 1138 struct dc_context *ctx, 1139 const struct encoder_init_data *enc_init_data) 1140 { 1141 struct dcn20_link_encoder *enc20 = 1142 kzalloc_obj(struct dcn20_link_encoder); 1143 1144 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1145 return NULL; 1146 1147 #undef REG_STRUCT 1148 #define REG_STRUCT link_enc_aux_regs 1149 aux_regs_init(0), 1150 aux_regs_init(1), 1151 aux_regs_init(2), 1152 aux_regs_init(3), 1153 aux_regs_init(4); 1154 1155 #undef REG_STRUCT 1156 #define REG_STRUCT link_enc_hpd_regs 1157 hpd_regs_init(0), 1158 hpd_regs_init(1), 1159 hpd_regs_init(2), 1160 hpd_regs_init(3), 1161 hpd_regs_init(4); 1162 1163 #undef REG_STRUCT 1164 #define REG_STRUCT link_enc_regs 1165 link_regs_init(0, A), 1166 link_regs_init(1, B), 1167 link_regs_init(2, C), 1168 link_regs_init(3, D), 1169 link_regs_init(4, E); 1170 1171 dcn35_link_encoder_construct(enc20, 1172 enc_init_data, 1173 &link_enc_feature, 1174 &link_enc_regs[enc_init_data->transmitter], 1175 &link_enc_aux_regs[enc_init_data->channel - 1], 1176 &link_enc_hpd_regs[enc_init_data->hpd_source], 1177 &le_shift, 1178 &le_mask); 1179 1180 return &enc20->enc10.base; 1181 } 1182 1183 /* Create a minimal link encoder object not associated with a particular 1184 * physical connector. 1185 * resource_funcs.link_enc_create_minimal 1186 */ 1187 static struct link_encoder *dcn31_link_enc_create_minimal( 1188 struct dc_context *ctx, enum engine_id eng_id) 1189 { 1190 struct dcn20_link_encoder *enc20; 1191 1192 if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1193 return NULL; 1194 1195 enc20 = kzalloc_obj(struct dcn20_link_encoder); 1196 if (!enc20) 1197 return NULL; 1198 1199 dcn31_link_encoder_construct_minimal( 1200 enc20, 1201 ctx, 1202 &link_enc_feature, 1203 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1204 eng_id); 1205 1206 return &enc20->enc10.base; 1207 } 1208 1209 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1210 { 1211 struct dcn31_panel_cntl *panel_cntl = 1212 kzalloc_obj(struct dcn31_panel_cntl); 1213 1214 if (!panel_cntl) 1215 return NULL; 1216 1217 dcn31_panel_cntl_construct(panel_cntl, init_data); 1218 1219 return &panel_cntl->base; 1220 } 1221 1222 static void read_dce_straps( 1223 struct dc_context *ctx, 1224 struct resource_straps *straps) 1225 { 1226 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1227 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1228 1229 } 1230 1231 static struct audio *dcn31_create_audio( 1232 struct dc_context *ctx, unsigned int inst) 1233 { 1234 1235 #undef REG_STRUCT 1236 #define REG_STRUCT audio_regs 1237 audio_regs_init(0), 1238 audio_regs_init(1), 1239 audio_regs_init(2), 1240 audio_regs_init(3), 1241 audio_regs_init(4); 1242 audio_regs_init(5); 1243 audio_regs_init(6); 1244 1245 return dce_audio_create(ctx, inst, 1246 &audio_regs[inst], &audio_shift, &audio_mask); 1247 } 1248 1249 static struct vpg *dcn31_vpg_create( 1250 struct dc_context *ctx, 1251 uint32_t inst) 1252 { 1253 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg); 1254 1255 if (!vpg31) 1256 return NULL; 1257 1258 #undef REG_STRUCT 1259 #define REG_STRUCT vpg_regs 1260 vpg_regs_init(0), 1261 vpg_regs_init(1), 1262 vpg_regs_init(2), 1263 vpg_regs_init(3), 1264 vpg_regs_init(4), 1265 vpg_regs_init(5), 1266 vpg_regs_init(6), 1267 vpg_regs_init(7), 1268 vpg_regs_init(8), 1269 vpg_regs_init(9); 1270 1271 vpg31_construct(vpg31, ctx, inst, 1272 &vpg_regs[inst], 1273 &vpg_shift, 1274 &vpg_mask); 1275 1276 return &vpg31->base; 1277 } 1278 1279 static struct afmt *dcn31_afmt_create( 1280 struct dc_context *ctx, 1281 uint32_t inst) 1282 { 1283 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt); 1284 1285 if (!afmt31) 1286 return NULL; 1287 1288 #undef REG_STRUCT 1289 #define REG_STRUCT afmt_regs 1290 afmt_regs_init(0), 1291 afmt_regs_init(1), 1292 afmt_regs_init(2), 1293 afmt_regs_init(3), 1294 afmt_regs_init(4), 1295 afmt_regs_init(5); 1296 1297 afmt31_construct(afmt31, ctx, inst, 1298 &afmt_regs[inst], 1299 &afmt_shift, 1300 &afmt_mask); 1301 1302 // Light sleep by default, no need to power down here 1303 1304 return &afmt31->base; 1305 } 1306 1307 static struct apg *dcn31_apg_create( 1308 struct dc_context *ctx, 1309 uint32_t inst) 1310 { 1311 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg); 1312 1313 if (!apg31) 1314 return NULL; 1315 1316 #undef REG_STRUCT 1317 #define REG_STRUCT apg_regs 1318 apg_regs_init(0), 1319 apg_regs_init(1), 1320 apg_regs_init(2), 1321 apg_regs_init(3); 1322 1323 apg31_construct(apg31, ctx, inst, 1324 &apg_regs[inst], 1325 &apg_shift, 1326 &apg_mask); 1327 1328 return &apg31->base; 1329 } 1330 1331 static struct stream_encoder *dcn35_stream_encoder_create( 1332 enum engine_id eng_id, 1333 struct dc_context *ctx) 1334 { 1335 struct dcn10_stream_encoder *enc1; 1336 struct vpg *vpg; 1337 struct afmt *afmt; 1338 int vpg_inst; 1339 int afmt_inst; 1340 1341 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1342 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) 1343 return NULL; 1344 1345 vpg_inst = eng_id; 1346 afmt_inst = eng_id; 1347 1348 enc1 = kzalloc_obj(struct dcn10_stream_encoder); 1349 vpg = dcn31_vpg_create(ctx, vpg_inst); 1350 afmt = dcn31_afmt_create(ctx, afmt_inst); 1351 1352 if (!enc1 || !vpg || !afmt) { 1353 kfree(enc1); 1354 kfree(vpg); 1355 kfree(afmt); 1356 return NULL; 1357 } 1358 1359 #undef REG_STRUCT 1360 #define REG_STRUCT stream_enc_regs 1361 stream_enc_regs_init(0), 1362 stream_enc_regs_init(1), 1363 stream_enc_regs_init(2), 1364 stream_enc_regs_init(3), 1365 stream_enc_regs_init(4); 1366 1367 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1368 eng_id, vpg, afmt, 1369 &stream_enc_regs[eng_id], 1370 &se_shift, &se_mask); 1371 1372 return &enc1->base; 1373 } 1374 1375 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create( 1376 enum engine_id eng_id, 1377 struct dc_context *ctx) 1378 { 1379 struct dcn30_hpo_frl_stream_encoder *hpo_enc3; 1380 struct vpg *vpg; 1381 struct afmt *afmt; 1382 int vpg_inst; 1383 int afmt_inst; 1384 1385 #undef REG_STRUCT 1386 #define REG_STRUCT hpo_frl_stream_enc_regs 1387 hpo_frl_stream_encoder_reg_list(0), 1388 hpo_frl_stream_encoder_dme_reg_list(6); 1389 1390 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */ 1391 if (eng_id == ENGINE_ID_HPO_0) { 1392 vpg_inst = 5; 1393 afmt_inst = 5; 1394 } else 1395 return NULL; 1396 1397 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */ 1398 hpo_enc3 = kzalloc(sizeof(struct dcn30_hpo_frl_stream_encoder), GFP_KERNEL); 1399 vpg = dcn31_vpg_create(ctx, vpg_inst); 1400 afmt = dcn31_afmt_create(ctx, afmt_inst); 1401 1402 if (!hpo_enc3 || !vpg || !afmt) { 1403 kfree(hpo_enc3); 1404 kfree(vpg); 1405 kfree(afmt); 1406 return NULL; 1407 } 1408 1409 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios, 1410 eng_id, vpg, afmt, 1411 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0], 1412 &hpo_se_shift, &hpo_se_mask); 1413 1414 return &hpo_enc3->base; 1415 } 1416 1417 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create( 1418 enum engine_id eng_id, 1419 struct dc_context *ctx) 1420 { 1421 struct dcn30_hpo_frl_link_encoder *hpo_enc3; 1422 1423 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1)); 1424 1425 #undef REG_STRUCT 1426 #define REG_STRUCT hpo_frl_link_enc_regs 1427 hpo_frl_link_encoder_reg_list(0); 1428 1429 /* allocate HPO link encoder */ 1430 hpo_enc3 = kzalloc(sizeof(struct dcn30_hpo_frl_link_encoder), GFP_KERNEL); 1431 if (!hpo_enc3) 1432 return NULL; /* out of memory */ 1433 1434 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0, 1435 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0], 1436 &hpo_le_shift, &hpo_le_mask); 1437 1438 return &hpo_enc3->base; 1439 } 1440 1441 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1442 enum engine_id eng_id, 1443 struct dc_context *ctx) 1444 { 1445 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1446 struct vpg *vpg; 1447 struct apg *apg; 1448 uint32_t hpo_dp_inst; 1449 uint32_t vpg_inst; 1450 uint32_t apg_inst; 1451 1452 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1453 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1454 1455 /* Mapping of VPG register blocks to HPO DP block instance: 1456 * VPG[6] -> HPO_DP[0] 1457 * VPG[7] -> HPO_DP[1] 1458 * VPG[8] -> HPO_DP[2] 1459 * VPG[9] -> HPO_DP[3] 1460 */ 1461 vpg_inst = hpo_dp_inst + 6; 1462 1463 /* Mapping of APG register blocks to HPO DP block instance: 1464 * APG[0] -> HPO_DP[0] 1465 * APG[1] -> HPO_DP[1] 1466 * APG[2] -> HPO_DP[2] 1467 * APG[3] -> HPO_DP[3] 1468 */ 1469 apg_inst = hpo_dp_inst; 1470 1471 /* allocate HPO stream encoder and create VPG sub-block */ 1472 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder); 1473 vpg = dcn31_vpg_create(ctx, vpg_inst); 1474 apg = dcn31_apg_create(ctx, apg_inst); 1475 1476 if (!hpo_dp_enc31 || !vpg || !apg) { 1477 kfree(hpo_dp_enc31); 1478 kfree(vpg); 1479 kfree(apg); 1480 return NULL; 1481 } 1482 1483 #undef REG_STRUCT 1484 #define REG_STRUCT hpo_dp_stream_enc_regs 1485 hpo_dp_stream_encoder_reg_init(0), 1486 hpo_dp_stream_encoder_reg_init(1), 1487 hpo_dp_stream_encoder_reg_init(2), 1488 hpo_dp_stream_encoder_reg_init(3); 1489 1490 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1491 hpo_dp_inst, eng_id, vpg, apg, 1492 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1493 &hpo_dp_se_shift, &hpo_dp_se_mask); 1494 1495 return &hpo_dp_enc31->base; 1496 } 1497 1498 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1499 uint8_t inst, 1500 struct dc_context *ctx) 1501 { 1502 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1503 1504 /* allocate HPO link encoder */ 1505 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder); 1506 if (!hpo_dp_enc31) 1507 return NULL; /* out of memory */ 1508 1509 #undef REG_STRUCT 1510 #define REG_STRUCT hpo_dp_link_enc_regs 1511 hpo_dp_link_encoder_reg_init(0), 1512 hpo_dp_link_encoder_reg_init(1); 1513 1514 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1515 &hpo_dp_link_enc_regs[inst], 1516 &hpo_dp_le_shift, &hpo_dp_le_mask); 1517 1518 return &hpo_dp_enc31->base; 1519 } 1520 1521 static struct dce_hwseq *dcn35_hwseq_create( 1522 struct dc_context *ctx) 1523 { 1524 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 1525 1526 #undef REG_STRUCT 1527 #define REG_STRUCT hwseq_reg 1528 hwseq_reg_init(); 1529 1530 if (hws) { 1531 hws->ctx = ctx; 1532 hws->regs = &hwseq_reg; 1533 hws->shifts = &hwseq_shift; 1534 hws->masks = &hwseq_mask; 1535 } 1536 return hws; 1537 } 1538 static const struct resource_create_funcs res_create_funcs = { 1539 .read_dce_straps = read_dce_straps, 1540 .create_audio = dcn31_create_audio, 1541 .create_stream_encoder = dcn35_stream_encoder_create, 1542 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create, 1543 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1544 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1545 .create_hwseq = dcn35_hwseq_create, 1546 }; 1547 1548 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) 1549 { 1550 unsigned int i; 1551 1552 for (i = 0; i < pool->base.stream_enc_count; i++) { 1553 if (pool->base.stream_enc[i] != NULL) { 1554 if (pool->base.stream_enc[i]->vpg != NULL) { 1555 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1556 pool->base.stream_enc[i]->vpg = NULL; 1557 } 1558 if (pool->base.stream_enc[i]->afmt != NULL) { 1559 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1560 pool->base.stream_enc[i]->afmt = NULL; 1561 } 1562 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1563 pool->base.stream_enc[i] = NULL; 1564 } 1565 } 1566 1567 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) { 1568 if (pool->base.hpo_frl_stream_enc[i] != NULL) { 1569 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) { 1570 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg)); 1571 pool->base.hpo_frl_stream_enc[i]->vpg = NULL; 1572 } 1573 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) { 1574 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt)); 1575 pool->base.hpo_frl_stream_enc[i]->afmt = NULL; 1576 } 1577 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i])); 1578 pool->base.hpo_frl_stream_enc[i] = NULL; 1579 } 1580 } 1581 1582 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1583 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1584 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1585 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1586 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1587 } 1588 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1589 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1590 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1591 } 1592 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1593 pool->base.hpo_dp_stream_enc[i] = NULL; 1594 } 1595 } 1596 1597 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1598 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1599 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1600 pool->base.hpo_dp_link_enc[i] = NULL; 1601 } 1602 } 1603 1604 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { 1605 if (pool->base.dscs[i] != NULL) 1606 dcn20_dsc_destroy(&pool->base.dscs[i]); 1607 } 1608 1609 if (pool->base.mpc != NULL) { 1610 kfree(TO_DCN20_MPC(pool->base.mpc)); 1611 pool->base.mpc = NULL; 1612 } 1613 if (pool->base.hubbub != NULL) { 1614 kfree(pool->base.hubbub); 1615 pool->base.hubbub = NULL; 1616 } 1617 for (i = 0; i < pool->base.pipe_count; i++) { 1618 if (pool->base.dpps[i] != NULL) 1619 dcn35_dpp_destroy(&pool->base.dpps[i]); 1620 1621 if (pool->base.ipps[i] != NULL) 1622 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1623 1624 if (pool->base.hubps[i] != NULL) { 1625 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1626 pool->base.hubps[i] = NULL; 1627 } 1628 1629 if (pool->base.irqs != NULL) { 1630 dal_irq_service_destroy(&pool->base.irqs); 1631 } 1632 } 1633 1634 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 1635 if (pool->base.engines[i] != NULL) 1636 dce110_engine_destroy(&pool->base.engines[i]); 1637 if (pool->base.hw_i2cs[i] != NULL) { 1638 kfree(pool->base.hw_i2cs[i]); 1639 pool->base.hw_i2cs[i] = NULL; 1640 } 1641 if (pool->base.sw_i2cs[i] != NULL) { 1642 kfree(pool->base.sw_i2cs[i]); 1643 pool->base.sw_i2cs[i] = NULL; 1644 } 1645 } 1646 1647 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { 1648 if (pool->base.opps[i] != NULL) 1649 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1650 } 1651 1652 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1653 if (pool->base.timing_generators[i] != NULL) { 1654 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1655 pool->base.timing_generators[i] = NULL; 1656 } 1657 } 1658 1659 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { 1660 if (pool->base.dwbc[i] != NULL) { 1661 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1662 pool->base.dwbc[i] = NULL; 1663 } 1664 if (pool->base.mcif_wb[i] != NULL) { 1665 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1666 pool->base.mcif_wb[i] = NULL; 1667 } 1668 } 1669 1670 for (i = 0; i < pool->base.audio_count; i++) { 1671 if (pool->base.audios[i]) 1672 dce_aud_destroy(&pool->base.audios[i]); 1673 } 1674 1675 for (i = 0; i < pool->base.clk_src_count; i++) { 1676 if (pool->base.clock_sources[i] != NULL) { 1677 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1678 pool->base.clock_sources[i] = NULL; 1679 } 1680 } 1681 1682 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { 1683 if (pool->base.mpc_lut[i] != NULL) { 1684 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1685 pool->base.mpc_lut[i] = NULL; 1686 } 1687 if (pool->base.mpc_shaper[i] != NULL) { 1688 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1689 pool->base.mpc_shaper[i] = NULL; 1690 } 1691 } 1692 1693 if (pool->base.dp_clock_source != NULL) { 1694 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1695 pool->base.dp_clock_source = NULL; 1696 } 1697 1698 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1699 if (pool->base.multiple_abms[i] != NULL) 1700 dce_abm_destroy(&pool->base.multiple_abms[i]); 1701 } 1702 1703 if (pool->base.psr != NULL) 1704 dmub_psr_destroy(&pool->base.psr); 1705 1706 if (pool->base.replay != NULL) 1707 dmub_replay_destroy(&pool->base.replay); 1708 1709 if (pool->base.pg_cntl != NULL) 1710 dcn_pg_cntl_destroy(&pool->base.pg_cntl); 1711 1712 if (pool->base.dccg != NULL) 1713 dcn_dccg_destroy(&pool->base.dccg); 1714 1715 if (pool->base.dio != NULL) { 1716 kfree(TO_DCN10_DIO(pool->base.dio)); 1717 pool->base.dio = NULL; 1718 } 1719 } 1720 1721 static struct hubp *dcn35_hubp_create( 1722 struct dc_context *ctx, 1723 uint32_t inst) 1724 { 1725 struct dcn20_hubp *hubp2 = 1726 kzalloc_obj(struct dcn20_hubp); 1727 1728 if (!hubp2) 1729 return NULL; 1730 1731 #undef REG_STRUCT 1732 #define REG_STRUCT hubp_regs 1733 hubp_regs_init(0), 1734 hubp_regs_init(1), 1735 hubp_regs_init(2), 1736 hubp_regs_init(3); 1737 1738 if (hubp35_construct(hubp2, ctx, inst, 1739 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1740 return &hubp2->base; 1741 1742 BREAK_TO_DEBUGGER(); 1743 kfree(hubp2); 1744 return NULL; 1745 } 1746 1747 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) 1748 { 1749 dcn35_dwbc_set_fgcg( 1750 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb); 1751 } 1752 1753 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1754 { 1755 unsigned int i; 1756 uint32_t pipe_count = pool->res_cap->num_dwb; 1757 1758 for (i = 0; i < pipe_count; i++) { 1759 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc); 1760 1761 if (!dwbc30) { 1762 dm_error("DC: failed to create dwbc30!\n"); 1763 return false; 1764 } 1765 1766 #undef REG_STRUCT 1767 #define REG_STRUCT dwbc35_regs 1768 dwbc_regs_dcn3_init(0); 1769 1770 dcn35_dwbc_construct(dwbc30, ctx, 1771 &dwbc35_regs[i], 1772 &dwbc35_shift, 1773 &dwbc35_mask, 1774 i); 1775 1776 pool->dwbc[i] = &dwbc30->base; 1777 1778 dcn35_dwbc_init(dwbc30, ctx); 1779 } 1780 return true; 1781 } 1782 1783 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, 1784 struct dc_context *ctx) 1785 { 1786 dcn35_mmhubbub_set_fgcg( 1787 mcif_wb30, 1788 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); 1789 } 1790 1791 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1792 { 1793 unsigned int i; 1794 uint32_t pipe_count = pool->res_cap->num_dwb; 1795 1796 for (i = 0; i < pipe_count; i++) { 1797 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub); 1798 1799 if (!mcif_wb30) { 1800 dm_error("DC: failed to create mcif_wb30!\n"); 1801 return false; 1802 } 1803 1804 #undef REG_STRUCT 1805 #define REG_STRUCT mcif_wb35_regs 1806 mcif_wb_regs_dcn3_init(0); 1807 1808 dcn35_mmhubbub_construct(mcif_wb30, ctx, 1809 &mcif_wb35_regs[i], 1810 &mcif_wb35_shift, 1811 &mcif_wb35_mask, 1812 i); 1813 1814 dcn35_mmhubbub_init(mcif_wb30, ctx); 1815 1816 pool->mcif_wb[i] = &mcif_wb30->base; 1817 } 1818 return true; 1819 } 1820 1821 static struct display_stream_compressor *dcn35_dsc_create( 1822 struct dc_context *ctx, uint32_t inst) 1823 { 1824 struct dcn20_dsc *dsc = 1825 kzalloc_obj(struct dcn20_dsc); 1826 1827 if (!dsc) { 1828 BREAK_TO_DEBUGGER(); 1829 return NULL; 1830 } 1831 1832 #undef REG_STRUCT 1833 #define REG_STRUCT dsc_regs 1834 dsc_regsDCN35_init(0), 1835 dsc_regsDCN35_init(1), 1836 dsc_regsDCN35_init(2), 1837 dsc_regsDCN35_init(3); 1838 1839 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1840 dsc35_set_fgcg(dsc, 1841 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); 1842 return &dsc->base; 1843 } 1844 1845 static void dcn35_destroy_resource_pool(struct resource_pool **pool) 1846 { 1847 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool); 1848 1849 dcn35_resource_destruct(dcn35_pool); 1850 kfree(dcn35_pool); 1851 *pool = NULL; 1852 } 1853 1854 static struct clock_source *dcn35_clock_source_create( 1855 struct dc_context *ctx, 1856 struct dc_bios *bios, 1857 enum clock_source_id id, 1858 const struct dce110_clk_src_regs *regs, 1859 bool dp_clk_src) 1860 { 1861 struct dce110_clk_src *clk_src = 1862 kzalloc_obj(struct dce110_clk_src); 1863 1864 if (!clk_src) 1865 return NULL; 1866 1867 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1868 regs, &cs_shift, &cs_mask)) { 1869 clk_src->base.dp_clk_src = dp_clk_src; 1870 return &clk_src->base; 1871 } 1872 1873 kfree(clk_src); 1874 BREAK_TO_DEBUGGER(); 1875 return NULL; 1876 } 1877 1878 static struct dc_cap_funcs cap_funcs = { 1879 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1880 }; 1881 1882 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config) 1883 { 1884 *panel_config = panel_config_defaults; 1885 } 1886 1887 1888 static enum dc_status dcn35_validate_bandwidth(struct dc *dc, 1889 struct dc_state *context, 1890 enum dc_validate_mode validate_mode) 1891 { 1892 bool out = false; 1893 1894 DC_FP_START(); 1895 out = dml2_validate(dc, context, 1896 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, 1897 validate_mode); 1898 DC_FP_END(); 1899 1900 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) 1901 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1902 1903 DC_FP_START(); 1904 dcn35_decide_zstate_support(dc, context); 1905 DC_FP_END(); 1906 1907 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1908 } 1909 1910 enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1911 { 1912 plane_state->tiling_info.gfxversion = DcGfxVersion9; 1913 dcn20_patch_unknown_plane_state(plane_state); 1914 return DC_OK; 1915 } 1916 1917 1918 static int populate_dml_pipes_from_context_fpu(struct dc *dc, 1919 struct dc_state *context, 1920 display_e2e_pipe_params_st *pipes, 1921 enum dc_validate_mode validate_mode) 1922 { 1923 int ret; 1924 1925 DC_FP_START(); 1926 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); 1927 DC_FP_END(); 1928 1929 return ret; 1930 } 1931 1932 void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1933 { 1934 DC_FP_START(); 1935 dcn35_update_bw_bounding_box_fpu(dc, bw_params); 1936 DC_FP_END(); 1937 } 1938 static struct resource_funcs dcn35_res_pool_funcs = { 1939 .destroy = dcn35_destroy_resource_pool, 1940 .link_enc_create = dcn35_link_encoder_create, 1941 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1942 .link_encs_assign = link_enc_cfg_link_encs_assign, 1943 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1944 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create, 1945 .panel_cntl_create = dcn31_panel_cntl_create, 1946 .validate_bandwidth = dcn35_validate_bandwidth, 1947 .calculate_wm_and_dlg = NULL, 1948 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1949 .populate_dml_pipes = populate_dml_pipes_from_context_fpu, 1950 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1951 .release_pipe = dcn20_release_pipe, 1952 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1953 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1954 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1955 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1956 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1957 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1958 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1959 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1960 .update_bw_bounding_box = dcn35_update_bw_bounding_box, 1961 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, 1962 .get_panel_config_defaults = dcn35_get_panel_config_defaults, 1963 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia, 1964 .get_det_buffer_size = dcn31_get_det_buffer_size, 1965 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 1966 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, 1967 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, 1968 .get_default_tiling_info = dcn10_get_default_tiling_info 1969 }; 1970 1971 static bool dcn35_resource_construct( 1972 uint8_t num_virtual_links, 1973 struct dc *dc, 1974 struct dcn35_resource_pool *pool) 1975 { 1976 int i; 1977 struct dc_context *ctx = dc->ctx; 1978 struct irq_service_init_data init_data; 1979 1980 #undef REG_STRUCT 1981 #define REG_STRUCT bios_regs 1982 bios_regs_init(); 1983 1984 #undef REG_STRUCT 1985 #define REG_STRUCT clk_src_regs 1986 clk_src_regs_init(0, A), 1987 clk_src_regs_init(1, B), 1988 clk_src_regs_init(2, C), 1989 clk_src_regs_init(3, D), 1990 clk_src_regs_init(4, E); 1991 1992 /* Enable 4to1MPC by default */ 1993 dc->config.allow_4to1MPC = true; 1994 1995 #undef REG_STRUCT 1996 #define REG_STRUCT abm_regs 1997 abm_regs_init(0), 1998 abm_regs_init(1), 1999 abm_regs_init(2), 2000 abm_regs_init(3); 2001 2002 #undef REG_STRUCT 2003 #define REG_STRUCT dccg_regs 2004 dccg_regs_init(); 2005 2006 ctx->dc_bios->regs = &bios_regs; 2007 2008 pool->base.res_cap = &res_cap_dcn35; 2009 2010 pool->base.funcs = &dcn35_res_pool_funcs; 2011 2012 /************************************************* 2013 * Resource + asic cap harcoding * 2014 *************************************************/ 2015 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; 2016 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2017 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2018 dc->caps.max_downscale_ratio = 600; 2019 dc->caps.i2c_speed_in_khz = 100; 2020 dc->caps.i2c_speed_in_khz_hdcp = 100; 2021 dc->caps.max_cursor_size = 256; 2022 dc->caps.min_horizontal_blanking_period = 80; 2023 dc->caps.dmdata_alloc_size = 2048; 2024 dc->caps.max_slave_planes = 3; 2025 dc->caps.max_slave_yuv_planes = 3; 2026 dc->caps.max_slave_rgb_planes = 3; 2027 dc->caps.post_blend_color_processing = true; 2028 dc->caps.force_dp_tps4_for_cp2520 = true; 2029 if (dc->config.forceHBR2CP2520) 2030 dc->caps.force_dp_tps4_for_cp2520 = false; 2031 dc->caps.hdmi_hpo = true; 2032 dc->config.skip_frl_pretraining = true; 2033 dc->caps.dp_hpo = true; 2034 dc->caps.dp_hdmi21_pcon_support = true; 2035 2036 dc->caps.edp_dsc_support = true; 2037 dc->caps.extended_aux_timeout_support = true; 2038 dc->caps.dmcub_support = true; 2039 dc->caps.is_apu = true; 2040 dc->caps.seamless_odm = true; 2041 2042 dc->caps.zstate_support = true; 2043 dc->caps.ips_support = true; 2044 dc->caps.max_v_total = (1 << 15) - 1; 2045 dc->caps.vtotal_limited_by_fp2 = true; 2046 2047 /* Color pipeline capabilities */ 2048 dc->caps.color.dpp.dcn_arch = 1; 2049 dc->caps.color.dpp.input_lut_shared = 0; 2050 dc->caps.color.dpp.icsc = 1; 2051 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2052 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2053 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2054 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2055 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2056 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2057 dc->caps.color.dpp.post_csc = 1; 2058 dc->caps.color.dpp.gamma_corr = 1; 2059 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2060 2061 dc->caps.color.dpp.hw_3d_lut = 0; 2062 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 2063 // no OGAM ROM on DCN301 2064 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2065 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2066 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2067 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2068 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2069 dc->caps.color.dpp.ocsc = 0; 2070 2071 dc->caps.color.mpc.gamut_remap = 1; 2072 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2 2073 dc->caps.color.mpc.ogam_ram = 1; 2074 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2075 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2076 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2077 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2078 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2079 dc->caps.color.mpc.ocsc = 1; 2080 dc->caps.color.mpc.preblend = true; 2081 2082 dc->caps.num_of_host_routers = 2; 2083 dc->caps.num_of_dpias_per_host_router = 2; 2084 2085 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 2086 * to provide some margin. 2087 * It's expected for furture ASIC to have equal or higher value, in order to 2088 * have determinstic power improvement from generate to genration. 2089 * (i.e., we should not expect new ASIC generation with lower vmin rate) 2090 */ 2091 dc->caps.max_disp_clock_khz_at_vmin = 650000; 2092 2093 /* Sequential ONO is based on ASIC. */ 2094 if (dc->ctx->asic_id.hw_internal_rev >= 0x40) 2095 dc->caps.sequential_ono = true; 2096 2097 /* Use pipe context based otg sync logic */ 2098 dc->config.use_pipe_ctx_sync_logic = true; 2099 2100 2101 dc->config.disable_hbr_audio_dp2 = true; 2102 /* read VBIOS LTTPR caps */ 2103 { 2104 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2105 enum bp_result bp_query_result; 2106 uint8_t is_vbios_lttpr_enable = 0; 2107 2108 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2109 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2110 } 2111 2112 /* interop bit is implicit */ 2113 { 2114 dc->caps.vbios_lttpr_aware = true; 2115 } 2116 } 2117 dc->check_config = config_defaults; 2118 2119 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2120 dc->debug = debug_defaults_drv; 2121 /*HW default is to have all the FGCG enabled, SW no need to program them*/ 2122 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; 2123 // Init the vm_helper 2124 if (dc->vm_helper) 2125 vm_helper_init(dc->vm_helper, 16); 2126 2127 /************************************************* 2128 * Create resources * 2129 *************************************************/ 2130 2131 /* Clock Sources for Pixel Clock*/ 2132 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] = 2133 dcn35_clock_source_create(ctx, ctx->dc_bios, 2134 CLOCK_SOURCE_COMBO_PHY_PLL0, 2135 &clk_src_regs[0], false); 2136 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] = 2137 dcn35_clock_source_create(ctx, ctx->dc_bios, 2138 CLOCK_SOURCE_COMBO_PHY_PLL1, 2139 &clk_src_regs[1], false); 2140 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] = 2141 dcn35_clock_source_create(ctx, ctx->dc_bios, 2142 CLOCK_SOURCE_COMBO_PHY_PLL2, 2143 &clk_src_regs[2], false); 2144 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] = 2145 dcn35_clock_source_create(ctx, ctx->dc_bios, 2146 CLOCK_SOURCE_COMBO_PHY_PLL3, 2147 &clk_src_regs[3], false); 2148 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] = 2149 dcn35_clock_source_create(ctx, ctx->dc_bios, 2150 CLOCK_SOURCE_COMBO_PHY_PLL4, 2151 &clk_src_regs[4], false); 2152 2153 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL; 2154 2155 /* todo: not reuse phy_pll registers */ 2156 pool->base.dp_clock_source = 2157 dcn35_clock_source_create(ctx, ctx->dc_bios, 2158 CLOCK_SOURCE_ID_DP_DTO, 2159 &clk_src_regs[0], true); 2160 2161 for (i = 0; i < (int)pool->base.clk_src_count; i++) { 2162 if (pool->base.clock_sources[i] == NULL) { 2163 dm_error("DC: failed to create clock sources!\n"); 2164 BREAK_TO_DEBUGGER(); 2165 goto create_fail; 2166 } 2167 } 2168 /*temp till dml2 fully work without dml1*/ 2169 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); 2170 2171 /* TODO: DCCG */ 2172 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2173 if (pool->base.dccg == NULL) { 2174 dm_error("DC: failed to create dccg!\n"); 2175 BREAK_TO_DEBUGGER(); 2176 goto create_fail; 2177 } 2178 2179 #undef REG_STRUCT 2180 #define REG_STRUCT pg_cntl_regs 2181 pg_cntl_dcn35_regs_init(); 2182 2183 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); 2184 if (pool->base.pg_cntl == NULL) { 2185 dm_error("DC: failed to create power gate control!\n"); 2186 BREAK_TO_DEBUGGER(); 2187 goto create_fail; 2188 } 2189 2190 /* TODO: IRQ */ 2191 init_data.ctx = dc->ctx; 2192 pool->base.irqs = dal_irq_service_dcn35_create(&init_data); 2193 if (!pool->base.irqs) 2194 goto create_fail; 2195 2196 /* HUBBUB */ 2197 pool->base.hubbub = dcn35_hubbub_create(ctx); 2198 if (pool->base.hubbub == NULL) { 2199 BREAK_TO_DEBUGGER(); 2200 dm_error("DC: failed to create hubbub!\n"); 2201 goto create_fail; 2202 } 2203 2204 /* DIO */ 2205 pool->base.dio = dcn35_dio_create(ctx); 2206 if (pool->base.dio == NULL) { 2207 BREAK_TO_DEBUGGER(); 2208 dm_error("DC: failed to create dio!\n"); 2209 goto create_fail; 2210 } 2211 2212 /* HUBPs, DPPs, OPPs and TGs */ 2213 for (i = 0; i < (int)pool->base.pipe_count; i++) { 2214 pool->base.hubps[i] = dcn35_hubp_create(ctx, i); 2215 if (pool->base.hubps[i] == NULL) { 2216 BREAK_TO_DEBUGGER(); 2217 dm_error( 2218 "DC: failed to create hubps!\n"); 2219 goto create_fail; 2220 } 2221 2222 pool->base.dpps[i] = dcn35_dpp_create(ctx, i); 2223 if (pool->base.dpps[i] == NULL) { 2224 BREAK_TO_DEBUGGER(); 2225 dm_error( 2226 "DC: failed to create dpps!\n"); 2227 goto create_fail; 2228 } 2229 } 2230 2231 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2232 pool->base.opps[i] = dcn35_opp_create(ctx, i); 2233 if (pool->base.opps[i] == NULL) { 2234 BREAK_TO_DEBUGGER(); 2235 dm_error( 2236 "DC: failed to create output pixel processor!\n"); 2237 goto create_fail; 2238 } 2239 } 2240 2241 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2242 pool->base.timing_generators[i] = dcn35_timing_generator_create( 2243 ctx, i); 2244 if (pool->base.timing_generators[i] == NULL) { 2245 BREAK_TO_DEBUGGER(); 2246 dm_error("DC: failed to create tg!\n"); 2247 goto create_fail; 2248 } 2249 } 2250 pool->base.timing_generator_count = i; 2251 2252 /* PSR */ 2253 pool->base.psr = dmub_psr_create(ctx); 2254 if (pool->base.psr == NULL) { 2255 dm_error("DC: failed to create psr obj!\n"); 2256 BREAK_TO_DEBUGGER(); 2257 goto create_fail; 2258 } 2259 2260 /* Replay */ 2261 pool->base.replay = dmub_replay_create(ctx); 2262 if (pool->base.replay == NULL) { 2263 dm_error("DC: failed to create replay obj!\n"); 2264 BREAK_TO_DEBUGGER(); 2265 goto create_fail; 2266 } 2267 2268 /* ABM */ 2269 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2270 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2271 &abm_regs[i], 2272 &abm_shift, 2273 &abm_mask); 2274 if (pool->base.multiple_abms[i] == NULL) { 2275 dm_error("DC: failed to create abm for pipe %d!\n", i); 2276 BREAK_TO_DEBUGGER(); 2277 goto create_fail; 2278 } 2279 } 2280 2281 /* MPC and DSC */ 2282 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2283 if (pool->base.mpc == NULL) { 2284 BREAK_TO_DEBUGGER(); 2285 dm_error("DC: failed to create mpc!\n"); 2286 goto create_fail; 2287 } 2288 2289 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2290 pool->base.dscs[i] = dcn35_dsc_create(ctx, i); 2291 if (pool->base.dscs[i] == NULL) { 2292 BREAK_TO_DEBUGGER(); 2293 dm_error("DC: failed to create display stream compressor %d!\n", i); 2294 goto create_fail; 2295 } 2296 } 2297 2298 /* DWB and MMHUBBUB */ 2299 if (!dcn35_dwbc_create(ctx, &pool->base)) { 2300 BREAK_TO_DEBUGGER(); 2301 dm_error("DC: failed to create dwbc!\n"); 2302 goto create_fail; 2303 } 2304 2305 if (!dcn35_mmhubbub_create(ctx, &pool->base)) { 2306 BREAK_TO_DEBUGGER(); 2307 dm_error("DC: failed to create mcif_wb!\n"); 2308 goto create_fail; 2309 } 2310 2311 /* AUX and I2C */ 2312 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2313 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2314 if (pool->base.engines[i] == NULL) { 2315 BREAK_TO_DEBUGGER(); 2316 dm_error( 2317 "DC:failed to create aux engine!!\n"); 2318 goto create_fail; 2319 } 2320 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2321 if (pool->base.hw_i2cs[i] == NULL) { 2322 BREAK_TO_DEBUGGER(); 2323 dm_error( 2324 "DC:failed to create hw i2c!!\n"); 2325 goto create_fail; 2326 } 2327 pool->base.sw_i2cs[i] = NULL; 2328 } 2329 2330 /* DCN3.5 has 6 DPIA */ 2331 pool->base.usb4_dpia_count = 4; 2332 if (dc->debug.dpia_debug.bits.disable_dpia) 2333 pool->base.usb4_dpia_count = 0; 2334 2335 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2336 if (!resource_construct(num_virtual_links, dc, &pool->base, 2337 &res_create_funcs)) 2338 goto create_fail; 2339 2340 /* HW Sequencer and Plane caps */ 2341 dcn35_hw_sequencer_construct(dc); 2342 2343 dc->caps.max_planes = pool->base.pipe_count; 2344 2345 for (i = 0; i < (int)dc->caps.max_planes; ++i) 2346 dc->caps.planes[i] = plane_cap; 2347 2348 dc->caps.max_odm_combine_factor = 4; 2349 2350 dc->cap_funcs = cap_funcs; 2351 2352 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 2353 2354 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2355 dc->dml2_options.use_native_soc_bb_construction = true; 2356 dc->dml2_options.minimize_dispclk_using_odm = false; 2357 if (dc->config.EnableMinDispClkODM) 2358 dc->dml2_options.minimize_dispclk_using_odm = true; 2359 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; 2360 2361 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2362 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2363 2364 dc->dml2_options.max_segments_per_hubp = 24; 2365 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ 2366 dc->dml2_options.override_det_buffer_size_kbytes = true; 2367 2368 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2369 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/ 2370 2371 return true; 2372 2373 create_fail: 2374 2375 dcn35_resource_destruct(pool); 2376 2377 return false; 2378 } 2379 2380 struct resource_pool *dcn35_create_resource_pool( 2381 const struct dc_init_data *init_data, 2382 struct dc *dc) 2383 { 2384 struct dcn35_resource_pool *pool = 2385 kzalloc_obj(struct dcn35_resource_pool); 2386 2387 if (!pool) 2388 return NULL; 2389 2390 if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) 2391 return &pool->base; 2392 2393 BREAK_TO_DEBUGGER(); 2394 kfree(pool); 2395 return NULL; 2396 } 2397