1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31 #include "dcn35/dcn35_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dcn35_resource.h"
36 #include "dml2/dml2_wrapper.h"
37
38 #include "dcn20/dcn20_resource.h"
39 #include "dcn30/dcn30_resource.h"
40 #include "dcn31/dcn31_resource.h"
41 #include "dcn32/dcn32_resource.h"
42
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn30/dcn30_hubbub.h"
45 #include "dcn31/dcn31_hubbub.h"
46 #include "dcn35/dcn35_hubbub.h"
47 #include "dcn32/dcn32_mpc.h"
48 #include "dcn35/dcn35_hubp.h"
49 #include "irq/dcn35/irq_service_dcn35.h"
50 #include "dcn35/dcn35_dpp.h"
51 #include "dcn35/dcn35_optc.h"
52 #include "dcn20/dcn20_hwseq.h"
53 #include "dcn30/dcn30_hwseq.h"
54 #include "dce110/dce110_hwseq.h"
55 #include "dcn35/dcn35_opp.h"
56 #include "dcn35/dcn35_dsc.h"
57 #include "dcn30/dcn30_vpg.h"
58 #include "dcn30/dcn30_afmt.h"
59 #include "dcn31/dcn31_dio_link_encoder.h"
60 #include "dcn35/dcn35_dio_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
62 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
63 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
64 #include "link.h"
65 #include "dcn31/dcn31_apg.h"
66 #include "dcn32/dcn32_dio_link_encoder.h"
67 #include "dcn31/dcn31_vpg.h"
68 #include "dcn31/dcn31_afmt.h"
69 #include "dce/dce_clock_source.h"
70 #include "dce/dce_audio.h"
71 #include "dce/dce_hwseq.h"
72 #include "clk_mgr.h"
73 #include "virtual/virtual_stream_encoder.h"
74 #include "dce110/dce110_resource.h"
75 #include "dml/display_mode_vba.h"
76 #include "dcn35/dcn35_dccg.h"
77 #include "dcn35/dcn35_pg_cntl.h"
78 #include "dcn10/dcn10_resource.h"
79 #include "dcn31/dcn31_panel_cntl.h"
80 #include "dcn35/dcn35_hwseq.h"
81 #include "dcn35/dcn35_dio_link_encoder.h"
82 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
83 #include "dml/dcn35/dcn35_fpu.h"
84 #include "dcn35/dcn35_dwb.h"
85 #include "dcn35/dcn35_mmhubbub.h"
86
87 #include "dcn/dcn_3_5_0_offset.h"
88 #include "dcn/dcn_3_5_0_sh_mask.h"
89 #include "nbio/nbio_7_11_0_offset.h"
90 #include "mmhub/mmhub_3_3_0_offset.h"
91 #include "mmhub/mmhub_3_3_0_sh_mask.h"
92
93 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
94 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
95
96 #include "reg_helper.h"
97 #include "dce/dmub_abm.h"
98 #include "dce/dmub_psr.h"
99 #include "dce/dmub_replay.h"
100 #include "dce/dce_aux.h"
101 #include "dce/dce_i2c.h"
102 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
103 #include "vm_helper.h"
104 #include "dcn20/dcn20_vmid.h"
105
106 #include "dc_state_priv.h"
107
108 #include "link_enc_cfg.h"
109 #define DC_LOGGER_INIT(logger)
110
111 enum dcn35_clk_src_array_id {
112 DCN35_CLK_SRC_PLL0,
113 DCN35_CLK_SRC_PLL1,
114 DCN35_CLK_SRC_PLL2,
115 DCN35_CLK_SRC_PLL3,
116 DCN35_CLK_SRC_PLL4,
117 DCN35_CLK_SRC_TOTAL
118 };
119
120 /* begin *********************
121 * macros to expend register list macro defined in HW object header file
122 */
123
124 /* DCN */
125 /* TODO awful hack. fixup dcn20_dwb.h */
126 #undef BASE_INNER
127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
128
129 #define BASE(seg) BASE_INNER(seg)
130
131 #define SR(reg_name)\
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
133 reg ## reg_name
134
135 #define SR_ARR(reg_name, id) \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
137
138 #define SR_ARR_INIT(reg_name, id, value) \
139 REG_STRUCT[id].reg_name = value
140
141 #define SRI(reg_name, block, id)\
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRI_ARR(reg_name, block, id)\
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SR_ARR_I2C(reg_name, id) \
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
151
152 #define SRI_ARR_I2C(reg_name, block, id)\
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRI2(reg_name, block, id)\
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
162 reg ## reg_name
163
164 #define SRI2_ARR(reg_name, block, id)\
165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
166 reg ## reg_name
167
168 #define SRIR(var_name, reg_name, block, id)\
169 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SRII(reg_name, block, id)\
173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## reg_name
175
176 #define SRII_ARR_2(reg_name, block, id, inst)\
177 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## reg_name
179
180 #define SRII_MPC_RMU(reg_name, block, id)\
181 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## reg_name
183
184 #define SRII_DWB(reg_name, temp_name, block, id)\
185 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
186 reg ## block ## id ## _ ## temp_name
187
188 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
189 .field_name = reg_name ## __ ## field_name ## post_fix
190
191 #define DCCG_SRII(reg_name, block, id)\
192 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
193 reg ## block ## id ## _ ## reg_name
194
195 #define VUPDATE_SRII(reg_name, block, id)\
196 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
197 reg ## reg_name ## _ ## block ## id
198
199 /* NBIO */
200 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
201
202 #define NBIO_BASE(seg) \
203 NBIO_BASE_INNER(seg)
204
205 #define NBIO_SR(reg_name)\
206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
207 regBIF_BX2_ ## reg_name
208
209 #define NBIO_SR_ARR(reg_name, id)\
210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
211 regBIF_BX2_ ## reg_name
212
213 #define bios_regs_init() \
214 ( \
215 NBIO_SR(BIOS_SCRATCH_3),\
216 NBIO_SR(BIOS_SCRATCH_6)\
217 )
218
219 static struct bios_registers bios_regs;
220
221 #define clk_src_regs_init(index, pllid)\
222 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
223
224 static struct dce110_clk_src_regs clk_src_regs[5];
225
226 static const struct dce110_clk_src_shift cs_shift = {
227 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
228 };
229
230 static const struct dce110_clk_src_mask cs_mask = {
231 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
232 };
233
234 #define abm_regs_init(id)\
235 ABM_DCN32_REG_LIST_RI(id)
236
237 static struct dce_abm_registers abm_regs[4];
238
239 static const struct dce_abm_shift abm_shift = {
240 ABM_MASK_SH_LIST_DCN35(__SHIFT)
241 };
242
243 static const struct dce_abm_mask abm_mask = {
244 ABM_MASK_SH_LIST_DCN35(_MASK)
245 };
246
247 #define audio_regs_init(id)\
248 AUD_COMMON_REG_LIST_RI(id)
249
250 static struct dce_audio_registers audio_regs[7];
251
252
253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
257
258 static const struct dce_audio_shift audio_shift = {
259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
260 };
261
262 static const struct dce_audio_mask audio_mask = {
263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
264 };
265
266 #define vpg_regs_init(id)\
267 VPG_DCN31_REG_LIST_RI(id)
268
269 static struct dcn31_vpg_registers vpg_regs[10];
270
271 static const struct dcn31_vpg_shift vpg_shift = {
272 DCN31_VPG_MASK_SH_LIST(__SHIFT)
273 };
274
275 static const struct dcn31_vpg_mask vpg_mask = {
276 DCN31_VPG_MASK_SH_LIST(_MASK)
277 };
278
279 #define afmt_regs_init(id)\
280 AFMT_DCN31_REG_LIST_RI(id)
281
282 static struct dcn31_afmt_registers afmt_regs[6];
283
284 static const struct dcn31_afmt_shift afmt_shift = {
285 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dcn31_afmt_mask afmt_mask = {
289 DCN31_AFMT_MASK_SH_LIST(_MASK)
290 };
291
292 #define apg_regs_init(id)\
293 APG_DCN31_REG_LIST_RI(id)
294
295 static struct dcn31_apg_registers apg_regs[4];
296
297 static const struct dcn31_apg_shift apg_shift = {
298 DCN31_APG_MASK_SH_LIST(__SHIFT)
299 };
300
301 static const struct dcn31_apg_mask apg_mask = {
302 DCN31_APG_MASK_SH_LIST(_MASK)
303 };
304
305 #define stream_enc_regs_init(id)\
306 SE_DCN35_REG_LIST_RI(id)
307
308 static struct dcn10_stream_enc_registers stream_enc_regs[5];
309
310 static const struct dcn10_stream_encoder_shift se_shift = {
311 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
312 };
313
314 static const struct dcn10_stream_encoder_mask se_mask = {
315 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
316 };
317
318 #define aux_regs_init(id)\
319 DCN2_AUX_REG_LIST_RI(id)
320
321 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
322
323 #define hpd_regs_init(id)\
324 HPD_REG_LIST_RI(id)
325
326 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
327
328
329 static const struct dce110_aux_registers_shift aux_shift = {
330 DCN_AUX_MASK_SH_LIST(__SHIFT)
331 };
332
333 static const struct dce110_aux_registers_mask aux_mask = {
334 DCN_AUX_MASK_SH_LIST(_MASK)
335 };
336
337 #define link_regs_init(id, phyid)\
338 ( \
339 LE_DCN35_REG_LIST_RI(id), \
340 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
341 )
342
343 static struct dcn10_link_enc_registers link_enc_regs[5];
344
345 static const struct dcn10_link_enc_shift le_shift = {
346 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
347 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
348 };
349
350 static const struct dcn10_link_enc_mask le_mask = {
351 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
352 //DPCS_DCN31_MASK_SH_LIST(_MASK)
353 };
354
355 #define hpo_dp_stream_encoder_reg_init(id)\
356 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
357
358 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
359
360 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
361 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
362 };
363
364 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
365 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
366 };
367
368 #define hpo_dp_link_encoder_reg_init(id)\
369 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
370 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
371 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
372 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
373 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
374
375 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
376
377 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
378 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
379 };
380
381 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
382 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
383 };
384
385 #define dpp_regs_init(id)\
386 DPP_REG_LIST_DCN35_RI(id)
387
388 static struct dcn3_dpp_registers dpp_regs[4];
389
390 static const struct dcn35_dpp_shift tf_shift = {
391 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
392 };
393
394 static const struct dcn35_dpp_mask tf_mask = {
395 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
396 };
397
398 #define opp_regs_init(id)\
399 OPP_REG_LIST_DCN35_RI(id)
400
401 static struct dcn35_opp_registers opp_regs[4];
402
403 static const struct dcn35_opp_shift opp_shift = {
404 OPP_MASK_SH_LIST_DCN35(__SHIFT)
405 };
406
407 static const struct dcn35_opp_mask opp_mask = {
408 OPP_MASK_SH_LIST_DCN35(_MASK)
409 };
410
411 #define aux_engine_regs_init(id)\
412 ( \
413 AUX_COMMON_REG_LIST0_RI(id), \
414 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
415 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
416 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
417 )
418
419 static struct dce110_aux_registers aux_engine_regs[5];
420
421 #define dwbc_regs_dcn3_init(id)\
422 DWBC_COMMON_REG_LIST_DCN30_RI(id)
423
424 static struct dcn30_dwbc_registers dwbc35_regs[1];
425
426 static const struct dcn35_dwbc_shift dwbc35_shift = {
427 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
428 };
429
430 static const struct dcn35_dwbc_mask dwbc35_mask = {
431 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
432 };
433
434 #define mcif_wb_regs_dcn3_init(id)\
435 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
436
437 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
438
439 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
440 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
441 };
442
443 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
444 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
445 };
446
447 #define dsc_regsDCN35_init(id)\
448 DSC_REG_LIST_DCN20_RI(id)
449
450 static struct dcn20_dsc_registers dsc_regs[4];
451
452 static const struct dcn35_dsc_shift dsc_shift = {
453 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
454 };
455
456 static const struct dcn35_dsc_mask dsc_mask = {
457 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
458 };
459
460 static struct dcn30_mpc_registers mpc_regs;
461
462 #define dcn_mpc_regs_init() \
463 MPC_REG_LIST_DCN3_2_RI(0),\
464 MPC_REG_LIST_DCN3_2_RI(1),\
465 MPC_REG_LIST_DCN3_2_RI(2),\
466 MPC_REG_LIST_DCN3_2_RI(3),\
467 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
468 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
469 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
470 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
471 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
472
473 static const struct dcn30_mpc_shift mpc_shift = {
474 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
475 };
476
477 static const struct dcn30_mpc_mask mpc_mask = {
478 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
479 };
480
481 #define optc_regs_init(id)\
482 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
483
484 static struct dcn_optc_registers optc_regs[4];
485
486 static const struct dcn_optc_shift optc_shift = {
487 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
488 };
489
490 static const struct dcn_optc_mask optc_mask = {
491 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
492 };
493
494 #define hubp_regs_init(id)\
495 HUBP_REG_LIST_DCN30_RI(id)
496
497 static struct dcn_hubp2_registers hubp_regs[4];
498
499
500 static const struct dcn35_hubp2_shift hubp_shift = {
501 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
502 };
503
504 static const struct dcn35_hubp2_mask hubp_mask = {
505 HUBP_MASK_SH_LIST_DCN35(_MASK)
506 };
507
508 static struct dcn_hubbub_registers hubbub_reg;
509
510 #define hubbub_reg_init()\
511 HUBBUB_REG_LIST_DCN35(0)
512
513 static const struct dcn_hubbub_shift hubbub_shift = {
514 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
515 };
516
517 static const struct dcn_hubbub_mask hubbub_mask = {
518 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
519 };
520
521 static struct dccg_registers dccg_regs;
522
523 #define dccg_regs_init()\
524 DCCG_REG_LIST_DCN35()
525
526 static const struct dccg_shift dccg_shift = {
527 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
528 };
529
530 static const struct dccg_mask dccg_mask = {
531 DCCG_MASK_SH_LIST_DCN35(_MASK)
532 };
533
534 static struct pg_cntl_registers pg_cntl_regs;
535
536 #define pg_cntl_dcn35_regs_init() \
537 PG_CNTL_REG_LIST_DCN35()
538
539 static const struct pg_cntl_shift pg_cntl_shift = {
540 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
541 };
542
543 static const struct pg_cntl_mask pg_cntl_mask = {
544 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
545 };
546
547 #define SRII2(reg_name_pre, reg_name_post, id)\
548 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
549 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
550 reg ## reg_name_pre ## id ## _ ## reg_name_post
551
552 static struct dce_hwseq_registers hwseq_reg;
553
554 #define hwseq_reg_init()\
555 HWSEQ_DCN35_REG_LIST()
556
557 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
558 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
559 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
560 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
561 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
562 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
563 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
564 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
565 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
566 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
567 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
568 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
569 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
570 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
571 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
572 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
573 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
574 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
575 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
576 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
577 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
578 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
579 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
580 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
581 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
582 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
583 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
584 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
585 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
586 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
587 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
588 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
589 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
590 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
591 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
592 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
593 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
594 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
595 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
596 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
597 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
598 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
599 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
600 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
601 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
602 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
603 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
604 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
605 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
606 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
607 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
608 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
609 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
610 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
611 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
612 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
613 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
614 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
627 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
628 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
629 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
630 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
631 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
632 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
633 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
634 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
635 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
636 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
637 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
638 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
639 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
640 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
641 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
642 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
643 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
644 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
645
646 static const struct dce_hwseq_shift hwseq_shift = {
647 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
648 };
649
650 static const struct dce_hwseq_mask hwseq_mask = {
651 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
652 };
653
654 #define vmid_regs_init(id)\
655 DCN20_VMID_REG_LIST_RI(id)
656
657 static struct dcn_vmid_registers vmid_regs[16];
658
659 static const struct dcn20_vmid_shift vmid_shifts = {
660 DCN20_VMID_MASK_SH_LIST(__SHIFT)
661 };
662
663 static const struct dcn20_vmid_mask vmid_masks = {
664 DCN20_VMID_MASK_SH_LIST(_MASK)
665 };
666
667 static const struct resource_caps res_cap_dcn35 = {
668 .num_timing_generator = 4,
669 .num_opp = 4,
670 .num_video_plane = 4,
671 .num_audio = 5,
672 .num_stream_encoder = 5,
673 .num_dig_link_enc = 5,
674 .num_hpo_dp_stream_encoder = 4,
675 .num_hpo_dp_link_encoder = 2,
676 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
677 .num_dwb = 1,
678 .num_ddc = 5,
679 .num_vmid = 16,
680 .num_mpc_3dlut = 2,
681 .num_dsc = 4,
682 };
683
684 static const struct dc_plane_cap plane_cap = {
685 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
686 .per_pixel_alpha = true,
687
688 .pixel_format_support = {
689 .argb8888 = true,
690 .nv12 = true,
691 .fp16 = true,
692 .p010 = true,
693 .ayuv = false,
694 },
695
696 .max_upscale_factor = {
697 .argb8888 = 16000,
698 .nv12 = 16000,
699 .fp16 = 16000
700 },
701
702 // 6:1 downscaling ratio: 1000/6 = 166.666
703 .max_downscale_factor = {
704 .argb8888 = 250,
705 .nv12 = 167,
706 .fp16 = 167
707 },
708 64,
709 64
710 };
711
712 static const struct dc_debug_options debug_defaults_drv = {
713 .disable_dmcu = true,
714 .force_abm_enable = false,
715 .clock_trace = true,
716 .disable_pplib_clock_request = false,
717 .pipe_split_policy = MPC_SPLIT_AVOID,
718 .force_single_disp_pipe_split = false,
719 .disable_dcc = DCC_ENABLE,
720 .disable_dpp_power_gate = true,
721 .disable_hubp_power_gate = true,
722 .disable_optc_power_gate = true, /*should the same as above two*/
723 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
724 .disable_clock_gate = false,
725 .disable_dsc_power_gate = true,
726 .vsr_support = true,
727 .performance_trace = false,
728 .max_downscale_src_width = 4096,/*upto true 4k*/
729 .disable_pplib_wm_range = false,
730 .scl_reset_length10 = true,
731 .sanity_checks = false,
732 .underflow_assert_delay_us = 0xFFFFFFFF,
733 .dwb_fi_phase = -1, // -1 = disable,
734 .dmub_command_table = true,
735 .pstate_enabled = true,
736 .use_max_lb = true,
737 .enable_mem_low_power = {
738 .bits = {
739 .vga = false,
740 .i2c = true,
741 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
742 .dscl = true,
743 .cm = true,
744 .mpc = true,
745 .optc = true,
746 .vpg = true,
747 .afmt = true,
748 }
749 },
750 .root_clock_optimization = {
751 .bits = {
752 .dpp = true,
753 .dsc = true,/*dscclk and dsc pg*/
754 .hdmistream = true,
755 .hdmichar = true,
756 .dpstream = true,
757 .symclk32_se = true,
758 .symclk32_le = true,
759 .symclk_fe = true,
760 .physymclk = false,
761 .dpiasymclk = true,
762 }
763 },
764 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
765 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
766 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
767 .using_dml2 = true,
768 .support_eDP1_5 = true,
769 .enable_hpo_pg_support = false,
770 .enable_legacy_fast_update = true,
771 .enable_single_display_2to1_odm_policy = true,
772 .disable_idle_power_optimizations = false,
773 .dmcub_emulation = false,
774 .disable_boot_optimizations = false,
775 .disable_unbounded_requesting = false,
776 .disable_mem_low_power = false,
777 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
778 .enable_double_buffered_dsc_pg_support = true,
779 .enable_dp_dig_pixel_rate_div_policy = 1,
780 .disable_z10 = false,
781 .ignore_pg = true,
782 .psp_disabled_wa = true,
783 .ips2_eval_delay_us = 2000,
784 .ips2_entry_delay_us = 800,
785 .disable_dmub_reallow_idle = false,
786 .static_screen_wait_frames = 2,
787 .disable_timeout = true,
788 .min_disp_clk_khz = 50000,
789 };
790
791 static const struct dc_panel_config panel_config_defaults = {
792 .psr = {
793 .disable_psr = false,
794 .disallow_psrsu = false,
795 .disallow_replay = false,
796 },
797 .ilr = {
798 .optimize_edp_link_rate = true,
799 },
800 };
801
dcn35_dpp_destroy(struct dpp ** dpp)802 static void dcn35_dpp_destroy(struct dpp **dpp)
803 {
804 kfree(TO_DCN20_DPP(*dpp));
805 *dpp = NULL;
806 }
807
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)808 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
809 {
810 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
811 bool success = (dpp != NULL);
812
813 if (!success)
814 return NULL;
815
816 #undef REG_STRUCT
817 #define REG_STRUCT dpp_regs
818 dpp_regs_init(0),
819 dpp_regs_init(1),
820 dpp_regs_init(2),
821 dpp_regs_init(3);
822
823 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
824 &tf_mask);
825 if (success) {
826 dpp35_set_fgcg(
827 dpp,
828 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
829 return &dpp->base;
830 }
831
832 BREAK_TO_DEBUGGER();
833 kfree(dpp);
834 return NULL;
835 }
836
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)837 static struct output_pixel_processor *dcn35_opp_create(
838 struct dc_context *ctx, uint32_t inst)
839 {
840 struct dcn20_opp *opp =
841 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
842
843 if (!opp) {
844 BREAK_TO_DEBUGGER();
845 return NULL;
846 }
847
848 #undef REG_STRUCT
849 #define REG_STRUCT opp_regs
850 opp_regs_init(0),
851 opp_regs_init(1),
852 opp_regs_init(2),
853 opp_regs_init(3);
854
855 dcn35_opp_construct(opp, ctx, inst,
856 &opp_regs[inst], &opp_shift, &opp_mask);
857
858 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
859
860 return &opp->base;
861 }
862
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)863 static struct dce_aux *dcn31_aux_engine_create(
864 struct dc_context *ctx,
865 uint32_t inst)
866 {
867 struct aux_engine_dce110 *aux_engine =
868 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
869
870 if (!aux_engine)
871 return NULL;
872
873 #undef REG_STRUCT
874 #define REG_STRUCT aux_engine_regs
875 aux_engine_regs_init(0),
876 aux_engine_regs_init(1),
877 aux_engine_regs_init(2),
878 aux_engine_regs_init(3),
879 aux_engine_regs_init(4);
880
881 dce110_aux_engine_construct(aux_engine, ctx, inst,
882 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
883 &aux_engine_regs[inst],
884 &aux_mask,
885 &aux_shift,
886 ctx->dc->caps.extended_aux_timeout_support);
887
888 return &aux_engine->base;
889 }
890
891 #define i2c_inst_regs_init(id)\
892 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
893
894 static struct dce_i2c_registers i2c_hw_regs[5];
895
896 static const struct dce_i2c_shift i2c_shifts = {
897 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
898 };
899
900 static const struct dce_i2c_mask i2c_masks = {
901 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
902 };
903
904 /* ========================================================== */
905
906 /*
907 * DPIA index | Preferred Encoder | Host Router
908 * 0 | C | 0
909 * 1 | First Available | 0
910 * 2 | D | 1
911 * 3 | First Available | 1
912 */
913 /* ========================================================== */
914 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
915 ENGINE_ID_DIGC,
916 ENGINE_ID_DIGC,
917 ENGINE_ID_DIGD,
918 ENGINE_ID_DIGD
919 };
920
dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)921 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
922 {
923 return dpia_to_preferred_enc_id_table[dpia_index];
924 }
925
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)926 static struct dce_i2c_hw *dcn31_i2c_hw_create(
927 struct dc_context *ctx,
928 uint32_t inst)
929 {
930 struct dce_i2c_hw *dce_i2c_hw =
931 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
932
933 if (!dce_i2c_hw)
934 return NULL;
935
936 #undef REG_STRUCT
937 #define REG_STRUCT i2c_hw_regs
938 i2c_inst_regs_init(1),
939 i2c_inst_regs_init(2),
940 i2c_inst_regs_init(3),
941 i2c_inst_regs_init(4),
942 i2c_inst_regs_init(5);
943
944 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
945 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
946
947 return dce_i2c_hw;
948 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)949 static struct mpc *dcn35_mpc_create(
950 struct dc_context *ctx,
951 int num_mpcc,
952 int num_rmu)
953 {
954 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
955
956 if (!mpc30)
957 return NULL;
958
959 #undef REG_STRUCT
960 #define REG_STRUCT mpc_regs
961 dcn_mpc_regs_init();
962
963 dcn32_mpc_construct(mpc30, ctx,
964 &mpc_regs,
965 &mpc_shift,
966 &mpc_mask,
967 num_mpcc,
968 num_rmu);
969
970 return &mpc30->base;
971 }
972
dcn35_hubbub_create(struct dc_context * ctx)973 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
974 {
975 int i;
976
977 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
978 GFP_KERNEL);
979
980 if (!hubbub3)
981 return NULL;
982
983 #undef REG_STRUCT
984 #define REG_STRUCT hubbub_reg
985 hubbub_reg_init();
986
987 #undef REG_STRUCT
988 #define REG_STRUCT vmid_regs
989 vmid_regs_init(0),
990 vmid_regs_init(1),
991 vmid_regs_init(2),
992 vmid_regs_init(3),
993 vmid_regs_init(4),
994 vmid_regs_init(5),
995 vmid_regs_init(6),
996 vmid_regs_init(7),
997 vmid_regs_init(8),
998 vmid_regs_init(9),
999 vmid_regs_init(10),
1000 vmid_regs_init(11),
1001 vmid_regs_init(12),
1002 vmid_regs_init(13),
1003 vmid_regs_init(14),
1004 vmid_regs_init(15);
1005
1006 hubbub35_construct(hubbub3, ctx,
1007 &hubbub_reg,
1008 &hubbub_shift,
1009 &hubbub_mask,
1010 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1011 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1012 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1013
1014
1015 for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
1016 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1017
1018 vmid->ctx = ctx;
1019
1020 vmid->regs = &vmid_regs[i];
1021 vmid->shifts = &vmid_shifts;
1022 vmid->masks = &vmid_masks;
1023 }
1024
1025 return &hubbub3->base;
1026 }
1027
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1028 static struct timing_generator *dcn35_timing_generator_create(
1029 struct dc_context *ctx,
1030 uint32_t instance)
1031 {
1032 struct optc *tgn10 =
1033 kzalloc(sizeof(struct optc), GFP_KERNEL);
1034
1035 if (!tgn10)
1036 return NULL;
1037
1038 #undef REG_STRUCT
1039 #define REG_STRUCT optc_regs
1040 optc_regs_init(0),
1041 optc_regs_init(1),
1042 optc_regs_init(2),
1043 optc_regs_init(3);
1044
1045 tgn10->base.inst = instance;
1046 tgn10->base.ctx = ctx;
1047
1048 tgn10->tg_regs = &optc_regs[instance];
1049 tgn10->tg_shift = &optc_shift;
1050 tgn10->tg_mask = &optc_mask;
1051
1052 dcn35_timing_generator_init(tgn10);
1053
1054 return &tgn10->base;
1055 }
1056
1057 static const struct encoder_feature_support link_enc_feature = {
1058 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1059 .max_hdmi_pixel_clock = 600000,
1060 .hdmi_ycbcr420_supported = true,
1061 .dp_ycbcr420_supported = true,
1062 .fec_supported = true,
1063 .flags.bits.IS_HBR2_CAPABLE = true,
1064 .flags.bits.IS_HBR3_CAPABLE = true,
1065 .flags.bits.IS_TPS3_CAPABLE = true,
1066 .flags.bits.IS_TPS4_CAPABLE = true
1067 };
1068
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1069 static struct link_encoder *dcn35_link_encoder_create(
1070 struct dc_context *ctx,
1071 const struct encoder_init_data *enc_init_data)
1072 {
1073 struct dcn20_link_encoder *enc20 =
1074 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1075
1076 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1077 return NULL;
1078
1079 #undef REG_STRUCT
1080 #define REG_STRUCT link_enc_aux_regs
1081 aux_regs_init(0),
1082 aux_regs_init(1),
1083 aux_regs_init(2),
1084 aux_regs_init(3),
1085 aux_regs_init(4);
1086
1087 #undef REG_STRUCT
1088 #define REG_STRUCT link_enc_hpd_regs
1089 hpd_regs_init(0),
1090 hpd_regs_init(1),
1091 hpd_regs_init(2),
1092 hpd_regs_init(3),
1093 hpd_regs_init(4);
1094
1095 #undef REG_STRUCT
1096 #define REG_STRUCT link_enc_regs
1097 link_regs_init(0, A),
1098 link_regs_init(1, B),
1099 link_regs_init(2, C),
1100 link_regs_init(3, D),
1101 link_regs_init(4, E);
1102
1103 dcn35_link_encoder_construct(enc20,
1104 enc_init_data,
1105 &link_enc_feature,
1106 &link_enc_regs[enc_init_data->transmitter],
1107 &link_enc_aux_regs[enc_init_data->channel - 1],
1108 &link_enc_hpd_regs[enc_init_data->hpd_source],
1109 &le_shift,
1110 &le_mask);
1111
1112 return &enc20->enc10.base;
1113 }
1114
1115 /* Create a minimal link encoder object not associated with a particular
1116 * physical connector.
1117 * resource_funcs.link_enc_create_minimal
1118 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1119 static struct link_encoder *dcn31_link_enc_create_minimal(
1120 struct dc_context *ctx, enum engine_id eng_id)
1121 {
1122 struct dcn20_link_encoder *enc20;
1123
1124 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1125 return NULL;
1126
1127 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1128 if (!enc20)
1129 return NULL;
1130
1131 dcn31_link_encoder_construct_minimal(
1132 enc20,
1133 ctx,
1134 &link_enc_feature,
1135 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1136 eng_id);
1137
1138 return &enc20->enc10.base;
1139 }
1140
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1141 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1142 {
1143 struct dcn31_panel_cntl *panel_cntl =
1144 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1145
1146 if (!panel_cntl)
1147 return NULL;
1148
1149 dcn31_panel_cntl_construct(panel_cntl, init_data);
1150
1151 return &panel_cntl->base;
1152 }
1153
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1154 static void read_dce_straps(
1155 struct dc_context *ctx,
1156 struct resource_straps *straps)
1157 {
1158 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1159 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1160
1161 }
1162
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1163 static struct audio *dcn31_create_audio(
1164 struct dc_context *ctx, unsigned int inst)
1165 {
1166
1167 #undef REG_STRUCT
1168 #define REG_STRUCT audio_regs
1169 audio_regs_init(0),
1170 audio_regs_init(1),
1171 audio_regs_init(2),
1172 audio_regs_init(3),
1173 audio_regs_init(4);
1174 audio_regs_init(5);
1175 audio_regs_init(6);
1176
1177 return dce_audio_create(ctx, inst,
1178 &audio_regs[inst], &audio_shift, &audio_mask);
1179 }
1180
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1181 static struct vpg *dcn31_vpg_create(
1182 struct dc_context *ctx,
1183 uint32_t inst)
1184 {
1185 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1186
1187 if (!vpg31)
1188 return NULL;
1189
1190 #undef REG_STRUCT
1191 #define REG_STRUCT vpg_regs
1192 vpg_regs_init(0),
1193 vpg_regs_init(1),
1194 vpg_regs_init(2),
1195 vpg_regs_init(3),
1196 vpg_regs_init(4),
1197 vpg_regs_init(5),
1198 vpg_regs_init(6),
1199 vpg_regs_init(7),
1200 vpg_regs_init(8),
1201 vpg_regs_init(9);
1202
1203 vpg31_construct(vpg31, ctx, inst,
1204 &vpg_regs[inst],
1205 &vpg_shift,
1206 &vpg_mask);
1207
1208 return &vpg31->base;
1209 }
1210
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1211 static struct afmt *dcn31_afmt_create(
1212 struct dc_context *ctx,
1213 uint32_t inst)
1214 {
1215 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1216
1217 if (!afmt31)
1218 return NULL;
1219
1220 #undef REG_STRUCT
1221 #define REG_STRUCT afmt_regs
1222 afmt_regs_init(0),
1223 afmt_regs_init(1),
1224 afmt_regs_init(2),
1225 afmt_regs_init(3),
1226 afmt_regs_init(4),
1227 afmt_regs_init(5);
1228
1229 afmt31_construct(afmt31, ctx, inst,
1230 &afmt_regs[inst],
1231 &afmt_shift,
1232 &afmt_mask);
1233
1234 // Light sleep by default, no need to power down here
1235
1236 return &afmt31->base;
1237 }
1238
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1239 static struct apg *dcn31_apg_create(
1240 struct dc_context *ctx,
1241 uint32_t inst)
1242 {
1243 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1244
1245 if (!apg31)
1246 return NULL;
1247
1248 #undef REG_STRUCT
1249 #define REG_STRUCT apg_regs
1250 apg_regs_init(0),
1251 apg_regs_init(1),
1252 apg_regs_init(2),
1253 apg_regs_init(3);
1254
1255 apg31_construct(apg31, ctx, inst,
1256 &apg_regs[inst],
1257 &apg_shift,
1258 &apg_mask);
1259
1260 return &apg31->base;
1261 }
1262
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1263 static struct stream_encoder *dcn35_stream_encoder_create(
1264 enum engine_id eng_id,
1265 struct dc_context *ctx)
1266 {
1267 struct dcn10_stream_encoder *enc1;
1268 struct vpg *vpg;
1269 struct afmt *afmt;
1270 int vpg_inst;
1271 int afmt_inst;
1272
1273 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1274 if (eng_id <= ENGINE_ID_DIGF) {
1275 vpg_inst = eng_id;
1276 afmt_inst = eng_id;
1277 } else
1278 return NULL;
1279
1280 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1281 vpg = dcn31_vpg_create(ctx, vpg_inst);
1282 afmt = dcn31_afmt_create(ctx, afmt_inst);
1283
1284 if (!enc1 || !vpg || !afmt) {
1285 kfree(enc1);
1286 kfree(vpg);
1287 kfree(afmt);
1288 return NULL;
1289 }
1290
1291 #undef REG_STRUCT
1292 #define REG_STRUCT stream_enc_regs
1293 stream_enc_regs_init(0),
1294 stream_enc_regs_init(1),
1295 stream_enc_regs_init(2),
1296 stream_enc_regs_init(3),
1297 stream_enc_regs_init(4);
1298
1299 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1300 eng_id, vpg, afmt,
1301 &stream_enc_regs[eng_id],
1302 &se_shift, &se_mask);
1303
1304 return &enc1->base;
1305 }
1306
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1307 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1308 enum engine_id eng_id,
1309 struct dc_context *ctx)
1310 {
1311 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1312 struct vpg *vpg;
1313 struct apg *apg;
1314 uint32_t hpo_dp_inst;
1315 uint32_t vpg_inst;
1316 uint32_t apg_inst;
1317
1318 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1319 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1320
1321 /* Mapping of VPG register blocks to HPO DP block instance:
1322 * VPG[6] -> HPO_DP[0]
1323 * VPG[7] -> HPO_DP[1]
1324 * VPG[8] -> HPO_DP[2]
1325 * VPG[9] -> HPO_DP[3]
1326 */
1327 vpg_inst = hpo_dp_inst + 6;
1328
1329 /* Mapping of APG register blocks to HPO DP block instance:
1330 * APG[0] -> HPO_DP[0]
1331 * APG[1] -> HPO_DP[1]
1332 * APG[2] -> HPO_DP[2]
1333 * APG[3] -> HPO_DP[3]
1334 */
1335 apg_inst = hpo_dp_inst;
1336
1337 /* allocate HPO stream encoder and create VPG sub-block */
1338 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1339 vpg = dcn31_vpg_create(ctx, vpg_inst);
1340 apg = dcn31_apg_create(ctx, apg_inst);
1341
1342 if (!hpo_dp_enc31 || !vpg || !apg) {
1343 kfree(hpo_dp_enc31);
1344 kfree(vpg);
1345 kfree(apg);
1346 return NULL;
1347 }
1348
1349 #undef REG_STRUCT
1350 #define REG_STRUCT hpo_dp_stream_enc_regs
1351 hpo_dp_stream_encoder_reg_init(0),
1352 hpo_dp_stream_encoder_reg_init(1),
1353 hpo_dp_stream_encoder_reg_init(2),
1354 hpo_dp_stream_encoder_reg_init(3);
1355
1356 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1357 hpo_dp_inst, eng_id, vpg, apg,
1358 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1359 &hpo_dp_se_shift, &hpo_dp_se_mask);
1360
1361 return &hpo_dp_enc31->base;
1362 }
1363
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1364 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1365 uint8_t inst,
1366 struct dc_context *ctx)
1367 {
1368 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1369
1370 /* allocate HPO link encoder */
1371 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1372 if (!hpo_dp_enc31)
1373 return NULL; /* out of memory */
1374
1375 #undef REG_STRUCT
1376 #define REG_STRUCT hpo_dp_link_enc_regs
1377 hpo_dp_link_encoder_reg_init(0),
1378 hpo_dp_link_encoder_reg_init(1);
1379
1380 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1381 &hpo_dp_link_enc_regs[inst],
1382 &hpo_dp_le_shift, &hpo_dp_le_mask);
1383
1384 return &hpo_dp_enc31->base;
1385 }
1386
dcn35_hwseq_create(struct dc_context * ctx)1387 static struct dce_hwseq *dcn35_hwseq_create(
1388 struct dc_context *ctx)
1389 {
1390 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1391
1392 #undef REG_STRUCT
1393 #define REG_STRUCT hwseq_reg
1394 hwseq_reg_init();
1395
1396 if (hws) {
1397 hws->ctx = ctx;
1398 hws->regs = &hwseq_reg;
1399 hws->shifts = &hwseq_shift;
1400 hws->masks = &hwseq_mask;
1401 }
1402 return hws;
1403 }
1404 static const struct resource_create_funcs res_create_funcs = {
1405 .read_dce_straps = read_dce_straps,
1406 .create_audio = dcn31_create_audio,
1407 .create_stream_encoder = dcn35_stream_encoder_create,
1408 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1409 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1410 .create_hwseq = dcn35_hwseq_create,
1411 };
1412
dcn35_resource_destruct(struct dcn35_resource_pool * pool)1413 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1414 {
1415 unsigned int i;
1416
1417 for (i = 0; i < pool->base.stream_enc_count; i++) {
1418 if (pool->base.stream_enc[i] != NULL) {
1419 if (pool->base.stream_enc[i]->vpg != NULL) {
1420 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1421 pool->base.stream_enc[i]->vpg = NULL;
1422 }
1423 if (pool->base.stream_enc[i]->afmt != NULL) {
1424 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1425 pool->base.stream_enc[i]->afmt = NULL;
1426 }
1427 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1428 pool->base.stream_enc[i] = NULL;
1429 }
1430 }
1431
1432 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1433 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1434 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1435 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1436 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1437 }
1438 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1439 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1440 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1441 }
1442 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1443 pool->base.hpo_dp_stream_enc[i] = NULL;
1444 }
1445 }
1446
1447 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1448 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1449 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1450 pool->base.hpo_dp_link_enc[i] = NULL;
1451 }
1452 }
1453
1454 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1455 if (pool->base.dscs[i] != NULL)
1456 dcn20_dsc_destroy(&pool->base.dscs[i]);
1457 }
1458
1459 if (pool->base.mpc != NULL) {
1460 kfree(TO_DCN20_MPC(pool->base.mpc));
1461 pool->base.mpc = NULL;
1462 }
1463 if (pool->base.hubbub != NULL) {
1464 kfree(pool->base.hubbub);
1465 pool->base.hubbub = NULL;
1466 }
1467 for (i = 0; i < pool->base.pipe_count; i++) {
1468 if (pool->base.dpps[i] != NULL)
1469 dcn35_dpp_destroy(&pool->base.dpps[i]);
1470
1471 if (pool->base.ipps[i] != NULL)
1472 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1473
1474 if (pool->base.hubps[i] != NULL) {
1475 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1476 pool->base.hubps[i] = NULL;
1477 }
1478
1479 if (pool->base.irqs != NULL) {
1480 dal_irq_service_destroy(&pool->base.irqs);
1481 }
1482 }
1483
1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1485 if (pool->base.engines[i] != NULL)
1486 dce110_engine_destroy(&pool->base.engines[i]);
1487 if (pool->base.hw_i2cs[i] != NULL) {
1488 kfree(pool->base.hw_i2cs[i]);
1489 pool->base.hw_i2cs[i] = NULL;
1490 }
1491 if (pool->base.sw_i2cs[i] != NULL) {
1492 kfree(pool->base.sw_i2cs[i]);
1493 pool->base.sw_i2cs[i] = NULL;
1494 }
1495 }
1496
1497 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1498 if (pool->base.opps[i] != NULL)
1499 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1500 }
1501
1502 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1503 if (pool->base.timing_generators[i] != NULL) {
1504 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1505 pool->base.timing_generators[i] = NULL;
1506 }
1507 }
1508
1509 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1510 if (pool->base.dwbc[i] != NULL) {
1511 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1512 pool->base.dwbc[i] = NULL;
1513 }
1514 if (pool->base.mcif_wb[i] != NULL) {
1515 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1516 pool->base.mcif_wb[i] = NULL;
1517 }
1518 }
1519
1520 for (i = 0; i < pool->base.audio_count; i++) {
1521 if (pool->base.audios[i])
1522 dce_aud_destroy(&pool->base.audios[i]);
1523 }
1524
1525 for (i = 0; i < pool->base.clk_src_count; i++) {
1526 if (pool->base.clock_sources[i] != NULL) {
1527 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1528 pool->base.clock_sources[i] = NULL;
1529 }
1530 }
1531
1532 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1533 if (pool->base.mpc_lut[i] != NULL) {
1534 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1535 pool->base.mpc_lut[i] = NULL;
1536 }
1537 if (pool->base.mpc_shaper[i] != NULL) {
1538 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1539 pool->base.mpc_shaper[i] = NULL;
1540 }
1541 }
1542
1543 if (pool->base.dp_clock_source != NULL) {
1544 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1545 pool->base.dp_clock_source = NULL;
1546 }
1547
1548 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1549 if (pool->base.multiple_abms[i] != NULL)
1550 dce_abm_destroy(&pool->base.multiple_abms[i]);
1551 }
1552
1553 if (pool->base.psr != NULL)
1554 dmub_psr_destroy(&pool->base.psr);
1555
1556 if (pool->base.replay != NULL)
1557 dmub_replay_destroy(&pool->base.replay);
1558
1559 if (pool->base.pg_cntl != NULL)
1560 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1561
1562 if (pool->base.dccg != NULL)
1563 dcn_dccg_destroy(&pool->base.dccg);
1564 }
1565
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1566 static struct hubp *dcn35_hubp_create(
1567 struct dc_context *ctx,
1568 uint32_t inst)
1569 {
1570 struct dcn20_hubp *hubp2 =
1571 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1572
1573 if (!hubp2)
1574 return NULL;
1575
1576 #undef REG_STRUCT
1577 #define REG_STRUCT hubp_regs
1578 hubp_regs_init(0),
1579 hubp_regs_init(1),
1580 hubp_regs_init(2),
1581 hubp_regs_init(3);
1582
1583 if (hubp35_construct(hubp2, ctx, inst,
1584 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1585 return &hubp2->base;
1586
1587 BREAK_TO_DEBUGGER();
1588 kfree(hubp2);
1589 return NULL;
1590 }
1591
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1592 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1593 {
1594 dcn35_dwbc_set_fgcg(
1595 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1596 }
1597
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1598 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1599 {
1600 int i;
1601 uint32_t pipe_count = pool->res_cap->num_dwb;
1602
1603 for (i = 0; i < pipe_count; i++) {
1604 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1605 GFP_KERNEL);
1606
1607 if (!dwbc30) {
1608 dm_error("DC: failed to create dwbc30!\n");
1609 return false;
1610 }
1611
1612 #undef REG_STRUCT
1613 #define REG_STRUCT dwbc35_regs
1614 dwbc_regs_dcn3_init(0);
1615
1616 dcn35_dwbc_construct(dwbc30, ctx,
1617 &dwbc35_regs[i],
1618 &dwbc35_shift,
1619 &dwbc35_mask,
1620 i);
1621
1622 pool->dwbc[i] = &dwbc30->base;
1623
1624 dcn35_dwbc_init(dwbc30, ctx);
1625 }
1626 return true;
1627 }
1628
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1629 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1630 struct dc_context *ctx)
1631 {
1632 dcn35_mmhubbub_set_fgcg(
1633 mcif_wb30,
1634 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1635 }
1636
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1637 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1638 {
1639 int i;
1640 uint32_t pipe_count = pool->res_cap->num_dwb;
1641
1642 for (i = 0; i < pipe_count; i++) {
1643 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1644 GFP_KERNEL);
1645
1646 if (!mcif_wb30) {
1647 dm_error("DC: failed to create mcif_wb30!\n");
1648 return false;
1649 }
1650
1651 #undef REG_STRUCT
1652 #define REG_STRUCT mcif_wb35_regs
1653 mcif_wb_regs_dcn3_init(0);
1654
1655 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1656 &mcif_wb35_regs[i],
1657 &mcif_wb35_shift,
1658 &mcif_wb35_mask,
1659 i);
1660
1661 dcn35_mmhubbub_init(mcif_wb30, ctx);
1662
1663 pool->mcif_wb[i] = &mcif_wb30->base;
1664 }
1665 return true;
1666 }
1667
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1668 static struct display_stream_compressor *dcn35_dsc_create(
1669 struct dc_context *ctx, uint32_t inst)
1670 {
1671 struct dcn20_dsc *dsc =
1672 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1673
1674 if (!dsc) {
1675 BREAK_TO_DEBUGGER();
1676 return NULL;
1677 }
1678
1679 #undef REG_STRUCT
1680 #define REG_STRUCT dsc_regs
1681 dsc_regsDCN35_init(0),
1682 dsc_regsDCN35_init(1),
1683 dsc_regsDCN35_init(2),
1684 dsc_regsDCN35_init(3);
1685
1686 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1687 dsc35_set_fgcg(dsc,
1688 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1689 return &dsc->base;
1690 }
1691
dcn35_destroy_resource_pool(struct resource_pool ** pool)1692 static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1693 {
1694 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1695
1696 dcn35_resource_destruct(dcn35_pool);
1697 kfree(dcn35_pool);
1698 *pool = NULL;
1699 }
1700
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1701 static struct clock_source *dcn35_clock_source_create(
1702 struct dc_context *ctx,
1703 struct dc_bios *bios,
1704 enum clock_source_id id,
1705 const struct dce110_clk_src_regs *regs,
1706 bool dp_clk_src)
1707 {
1708 struct dce110_clk_src *clk_src =
1709 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1710
1711 if (!clk_src)
1712 return NULL;
1713
1714 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1715 regs, &cs_shift, &cs_mask)) {
1716 clk_src->base.dp_clk_src = dp_clk_src;
1717 return &clk_src->base;
1718 }
1719
1720 kfree(clk_src);
1721 BREAK_TO_DEBUGGER();
1722 return NULL;
1723 }
1724
1725 static struct dc_cap_funcs cap_funcs = {
1726 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1727 };
1728
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1729 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1730 {
1731 *panel_config = panel_config_defaults;
1732 }
1733
1734
dcn35_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1735 static bool dcn35_validate_bandwidth(struct dc *dc,
1736 struct dc_state *context,
1737 bool fast_validate)
1738 {
1739 bool out = false;
1740
1741 out = dml2_validate(dc, context,
1742 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1743 fast_validate);
1744
1745 if (fast_validate)
1746 return out;
1747
1748 DC_FP_START();
1749 dcn35_decide_zstate_support(dc, context);
1750 DC_FP_END();
1751
1752 return out;
1753 }
1754
dcn35_patch_unknown_plane_state(struct dc_plane_state * plane_state)1755 enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1756 {
1757 plane_state->tiling_info.gfxversion = DcGfxVersion9;
1758 dcn20_patch_unknown_plane_state(plane_state);
1759 return DC_OK;
1760 }
1761
1762
1763 static struct resource_funcs dcn35_res_pool_funcs = {
1764 .destroy = dcn35_destroy_resource_pool,
1765 .link_enc_create = dcn35_link_encoder_create,
1766 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1767 .link_encs_assign = link_enc_cfg_link_encs_assign,
1768 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1769 .panel_cntl_create = dcn31_panel_cntl_create,
1770 .validate_bandwidth = dcn35_validate_bandwidth,
1771 .calculate_wm_and_dlg = NULL,
1772 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1773 .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu,
1774 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1775 .release_pipe = dcn20_release_pipe,
1776 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1777 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1778 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1779 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1780 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1781 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1782 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1783 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1784 .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu,
1785 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1786 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1787 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1788 .get_det_buffer_size = dcn31_get_det_buffer_size,
1789 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1790 };
1791
dcn35_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn35_resource_pool * pool)1792 static bool dcn35_resource_construct(
1793 uint8_t num_virtual_links,
1794 struct dc *dc,
1795 struct dcn35_resource_pool *pool)
1796 {
1797 int i;
1798 struct dc_context *ctx = dc->ctx;
1799 struct irq_service_init_data init_data;
1800
1801 #undef REG_STRUCT
1802 #define REG_STRUCT bios_regs
1803 bios_regs_init();
1804
1805 #undef REG_STRUCT
1806 #define REG_STRUCT clk_src_regs
1807 clk_src_regs_init(0, A),
1808 clk_src_regs_init(1, B),
1809 clk_src_regs_init(2, C),
1810 clk_src_regs_init(3, D),
1811 clk_src_regs_init(4, E);
1812
1813 #undef REG_STRUCT
1814 #define REG_STRUCT abm_regs
1815 abm_regs_init(0),
1816 abm_regs_init(1),
1817 abm_regs_init(2),
1818 abm_regs_init(3);
1819
1820 #undef REG_STRUCT
1821 #define REG_STRUCT dccg_regs
1822 dccg_regs_init();
1823
1824 ctx->dc_bios->regs = &bios_regs;
1825
1826 pool->base.res_cap = &res_cap_dcn35;
1827
1828 pool->base.funcs = &dcn35_res_pool_funcs;
1829
1830 /*************************************************
1831 * Resource + asic cap harcoding *
1832 *************************************************/
1833 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1834 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1835 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1836 dc->caps.max_downscale_ratio = 600;
1837 dc->caps.i2c_speed_in_khz = 100;
1838 dc->caps.i2c_speed_in_khz_hdcp = 100;
1839 dc->caps.max_cursor_size = 256;
1840 dc->caps.min_horizontal_blanking_period = 80;
1841 dc->caps.dmdata_alloc_size = 2048;
1842 dc->caps.max_slave_planes = 2;
1843 dc->caps.max_slave_yuv_planes = 2;
1844 dc->caps.max_slave_rgb_planes = 2;
1845 dc->caps.post_blend_color_processing = true;
1846 dc->caps.force_dp_tps4_for_cp2520 = true;
1847 if (dc->config.forceHBR2CP2520)
1848 dc->caps.force_dp_tps4_for_cp2520 = false;
1849 dc->caps.dp_hpo = true;
1850 dc->caps.dp_hdmi21_pcon_support = true;
1851
1852 dc->caps.edp_dsc_support = true;
1853 dc->caps.extended_aux_timeout_support = true;
1854 dc->caps.dmcub_support = true;
1855 dc->caps.is_apu = true;
1856 dc->caps.seamless_odm = true;
1857
1858 dc->caps.zstate_support = true;
1859 dc->caps.ips_support = true;
1860 dc->caps.max_v_total = (1 << 15) - 1;
1861 dc->caps.vtotal_limited_by_fp2 = true;
1862
1863 /* Color pipeline capabilities */
1864 dc->caps.color.dpp.dcn_arch = 1;
1865 dc->caps.color.dpp.input_lut_shared = 0;
1866 dc->caps.color.dpp.icsc = 1;
1867 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1868 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1869 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1870 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1871 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1872 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1873 dc->caps.color.dpp.post_csc = 1;
1874 dc->caps.color.dpp.gamma_corr = 1;
1875 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1876
1877 dc->caps.color.dpp.hw_3d_lut = 1;
1878 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1879 // no OGAM ROM on DCN301
1880 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1881 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1882 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1883 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1884 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1885 dc->caps.color.dpp.ocsc = 0;
1886
1887 dc->caps.color.mpc.gamut_remap = 1;
1888 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1889 dc->caps.color.mpc.ogam_ram = 1;
1890 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1891 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1892 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1893 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1894 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1895 dc->caps.color.mpc.ocsc = 1;
1896
1897 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1898 * to provide some margin.
1899 * It's expected for furture ASIC to have equal or higher value, in order to
1900 * have determinstic power improvement from generate to genration.
1901 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1902 */
1903 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1904
1905 /* Sequential ONO is based on ASIC. */
1906 if (dc->ctx->asic_id.hw_internal_rev > 0x10)
1907 dc->caps.sequential_ono = true;
1908
1909 /* Use pipe context based otg sync logic */
1910 dc->config.use_pipe_ctx_sync_logic = true;
1911
1912 dc->config.disable_hbr_audio_dp2 = true;
1913 /* read VBIOS LTTPR caps */
1914 {
1915 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1916 enum bp_result bp_query_result;
1917 uint8_t is_vbios_lttpr_enable = 0;
1918
1919 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1920 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1921 }
1922
1923 /* interop bit is implicit */
1924 {
1925 dc->caps.vbios_lttpr_aware = true;
1926 }
1927 }
1928
1929 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1930 dc->debug = debug_defaults_drv;
1931 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1932 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1933 // Init the vm_helper
1934 if (dc->vm_helper)
1935 vm_helper_init(dc->vm_helper, 16);
1936
1937 /*************************************************
1938 * Create resources *
1939 *************************************************/
1940
1941 /* Clock Sources for Pixel Clock*/
1942 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
1943 dcn35_clock_source_create(ctx, ctx->dc_bios,
1944 CLOCK_SOURCE_COMBO_PHY_PLL0,
1945 &clk_src_regs[0], false);
1946 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
1947 dcn35_clock_source_create(ctx, ctx->dc_bios,
1948 CLOCK_SOURCE_COMBO_PHY_PLL1,
1949 &clk_src_regs[1], false);
1950 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
1951 dcn35_clock_source_create(ctx, ctx->dc_bios,
1952 CLOCK_SOURCE_COMBO_PHY_PLL2,
1953 &clk_src_regs[2], false);
1954 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
1955 dcn35_clock_source_create(ctx, ctx->dc_bios,
1956 CLOCK_SOURCE_COMBO_PHY_PLL3,
1957 &clk_src_regs[3], false);
1958 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
1959 dcn35_clock_source_create(ctx, ctx->dc_bios,
1960 CLOCK_SOURCE_COMBO_PHY_PLL4,
1961 &clk_src_regs[4], false);
1962
1963 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
1964
1965 /* todo: not reuse phy_pll registers */
1966 pool->base.dp_clock_source =
1967 dcn35_clock_source_create(ctx, ctx->dc_bios,
1968 CLOCK_SOURCE_ID_DP_DTO,
1969 &clk_src_regs[0], true);
1970
1971 for (i = 0; i < pool->base.clk_src_count; i++) {
1972 if (pool->base.clock_sources[i] == NULL) {
1973 dm_error("DC: failed to create clock sources!\n");
1974 BREAK_TO_DEBUGGER();
1975 goto create_fail;
1976 }
1977 }
1978 /*temp till dml2 fully work without dml1*/
1979 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1980
1981 /* TODO: DCCG */
1982 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1983 if (pool->base.dccg == NULL) {
1984 dm_error("DC: failed to create dccg!\n");
1985 BREAK_TO_DEBUGGER();
1986 goto create_fail;
1987 }
1988
1989 #undef REG_STRUCT
1990 #define REG_STRUCT pg_cntl_regs
1991 pg_cntl_dcn35_regs_init();
1992
1993 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1994 if (pool->base.pg_cntl == NULL) {
1995 dm_error("DC: failed to create power gate control!\n");
1996 BREAK_TO_DEBUGGER();
1997 goto create_fail;
1998 }
1999
2000 /* TODO: IRQ */
2001 init_data.ctx = dc->ctx;
2002 pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
2003 if (!pool->base.irqs)
2004 goto create_fail;
2005
2006 /* HUBBUB */
2007 pool->base.hubbub = dcn35_hubbub_create(ctx);
2008 if (pool->base.hubbub == NULL) {
2009 BREAK_TO_DEBUGGER();
2010 dm_error("DC: failed to create hubbub!\n");
2011 goto create_fail;
2012 }
2013
2014 /* HUBPs, DPPs, OPPs and TGs */
2015 for (i = 0; i < pool->base.pipe_count; i++) {
2016 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2017 if (pool->base.hubps[i] == NULL) {
2018 BREAK_TO_DEBUGGER();
2019 dm_error(
2020 "DC: failed to create hubps!\n");
2021 goto create_fail;
2022 }
2023
2024 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2025 if (pool->base.dpps[i] == NULL) {
2026 BREAK_TO_DEBUGGER();
2027 dm_error(
2028 "DC: failed to create dpps!\n");
2029 goto create_fail;
2030 }
2031 }
2032
2033 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2034 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2035 if (pool->base.opps[i] == NULL) {
2036 BREAK_TO_DEBUGGER();
2037 dm_error(
2038 "DC: failed to create output pixel processor!\n");
2039 goto create_fail;
2040 }
2041 }
2042
2043 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2044 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2045 ctx, i);
2046 if (pool->base.timing_generators[i] == NULL) {
2047 BREAK_TO_DEBUGGER();
2048 dm_error("DC: failed to create tg!\n");
2049 goto create_fail;
2050 }
2051 }
2052 pool->base.timing_generator_count = i;
2053
2054 /* PSR */
2055 pool->base.psr = dmub_psr_create(ctx);
2056 if (pool->base.psr == NULL) {
2057 dm_error("DC: failed to create psr obj!\n");
2058 BREAK_TO_DEBUGGER();
2059 goto create_fail;
2060 }
2061
2062 /* Replay */
2063 pool->base.replay = dmub_replay_create(ctx);
2064 if (pool->base.replay == NULL) {
2065 dm_error("DC: failed to create replay obj!\n");
2066 BREAK_TO_DEBUGGER();
2067 goto create_fail;
2068 }
2069
2070 /* ABM */
2071 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2072 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2073 &abm_regs[i],
2074 &abm_shift,
2075 &abm_mask);
2076 if (pool->base.multiple_abms[i] == NULL) {
2077 dm_error("DC: failed to create abm for pipe %d!\n", i);
2078 BREAK_TO_DEBUGGER();
2079 goto create_fail;
2080 }
2081 }
2082
2083 /* MPC and DSC */
2084 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2085 if (pool->base.mpc == NULL) {
2086 BREAK_TO_DEBUGGER();
2087 dm_error("DC: failed to create mpc!\n");
2088 goto create_fail;
2089 }
2090
2091 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2092 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2093 if (pool->base.dscs[i] == NULL) {
2094 BREAK_TO_DEBUGGER();
2095 dm_error("DC: failed to create display stream compressor %d!\n", i);
2096 goto create_fail;
2097 }
2098 }
2099
2100 /* DWB and MMHUBBUB */
2101 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2102 BREAK_TO_DEBUGGER();
2103 dm_error("DC: failed to create dwbc!\n");
2104 goto create_fail;
2105 }
2106
2107 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2108 BREAK_TO_DEBUGGER();
2109 dm_error("DC: failed to create mcif_wb!\n");
2110 goto create_fail;
2111 }
2112
2113 /* AUX and I2C */
2114 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2115 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2116 if (pool->base.engines[i] == NULL) {
2117 BREAK_TO_DEBUGGER();
2118 dm_error(
2119 "DC:failed to create aux engine!!\n");
2120 goto create_fail;
2121 }
2122 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2123 if (pool->base.hw_i2cs[i] == NULL) {
2124 BREAK_TO_DEBUGGER();
2125 dm_error(
2126 "DC:failed to create hw i2c!!\n");
2127 goto create_fail;
2128 }
2129 pool->base.sw_i2cs[i] = NULL;
2130 }
2131
2132 /* DCN3.5 has 6 DPIA */
2133 pool->base.usb4_dpia_count = 4;
2134 if (dc->debug.dpia_debug.bits.disable_dpia)
2135 pool->base.usb4_dpia_count = 0;
2136
2137 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2138 if (!resource_construct(num_virtual_links, dc, &pool->base,
2139 &res_create_funcs))
2140 goto create_fail;
2141
2142 /* HW Sequencer and Plane caps */
2143 dcn35_hw_sequencer_construct(dc);
2144
2145 dc->caps.max_planes = pool->base.pipe_count;
2146
2147 for (i = 0; i < dc->caps.max_planes; ++i)
2148 dc->caps.planes[i] = plane_cap;
2149
2150 dc->cap_funcs = cap_funcs;
2151
2152 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2153
2154 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2155 dc->dml2_options.use_native_pstate_optimization = true;
2156 dc->dml2_options.use_native_soc_bb_construction = true;
2157 dc->dml2_options.minimize_dispclk_using_odm = false;
2158 if (dc->config.EnableMinDispClkODM)
2159 dc->dml2_options.minimize_dispclk_using_odm = true;
2160 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2161
2162 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2163 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2164
2165 dc->dml2_options.max_segments_per_hubp = 24;
2166 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2167 dc->dml2_options.override_det_buffer_size_kbytes = true;
2168
2169 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2170 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2171
2172 return true;
2173
2174 create_fail:
2175
2176 dcn35_resource_destruct(pool);
2177
2178 return false;
2179 }
2180
dcn35_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2181 struct resource_pool *dcn35_create_resource_pool(
2182 const struct dc_init_data *init_data,
2183 struct dc *dc)
2184 {
2185 struct dcn35_resource_pool *pool =
2186 kzalloc(sizeof(struct dcn35_resource_pool), GFP_KERNEL);
2187
2188 if (!pool)
2189 return NULL;
2190
2191 if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
2192 return &pool->base;
2193
2194 BREAK_TO_DEBUGGER();
2195 kfree(pool);
2196 return NULL;
2197 }
2198