1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn31/dcn31_init.h"
9 #include "dcn351/dcn351_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn351_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn31/dcn31_resource.h"
18 #include "dcn32/dcn32_resource.h"
19 #include "dcn35/dcn35_resource.h"
20
21 #include "dcn10/dcn10_ipp.h"
22 #include "dcn30/dcn30_hubbub.h"
23 #include "dcn31/dcn31_hubbub.h"
24 #include "dcn35/dcn35_hubbub.h"
25 #include "dcn32/dcn32_mpc.h"
26 #include "dcn35/dcn35_hubp.h"
27 #include "irq/dcn351/irq_service_dcn351.h"
28 #include "dcn35/dcn35_dpp.h"
29 #include "dcn35/dcn35_optc.h"
30 #include "dcn20/dcn20_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dce110/dce110_hwseq.h"
33 #include "dcn35/dcn35_opp.h"
34 #include "dcn35/dcn35_dsc.h"
35 #include "dcn30/dcn30_vpg.h"
36 #include "dcn30/dcn30_afmt.h"
37
38 #include "dcn31/dcn31_dio_link_encoder.h"
39 #include "dcn35/dcn35_dio_stream_encoder.h"
40 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
41 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
42 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
43 #include "link.h"
44 #include "dcn31/dcn31_apg.h"
45 #include "dcn32/dcn32_dio_link_encoder.h"
46 #include "dcn31/dcn31_vpg.h"
47 #include "dcn31/dcn31_afmt.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "clk_mgr.h"
52 #include "virtual/virtual_stream_encoder.h"
53 #include "dce110/dce110_resource.h"
54 #include "dml/display_mode_vba.h"
55 #include "dcn35/dcn35_dccg.h"
56 #include "dcn35/dcn35_pg_cntl.h"
57 #include "dcn10/dcn10_resource.h"
58 #include "dcn31/dcn31_panel_cntl.h"
59 #include "dcn35/dcn35_hwseq.h"
60 #include "dcn35/dcn35_dio_link_encoder.h"
61 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
62 #include "dml/dcn35/dcn35_fpu.h"
63 #include "dml/dcn351/dcn351_fpu.h"
64 #include "dcn35/dcn35_dwb.h"
65 #include "dcn35/dcn35_mmhubbub.h"
66
67 #include "dcn/dcn_3_5_1_offset.h"
68 #include "dcn/dcn_3_5_1_sh_mask.h"
69 #include "nbio/nbio_7_11_0_offset.h"
70 #include "mmhub/mmhub_3_3_0_offset.h"
71 #include "mmhub/mmhub_3_3_0_sh_mask.h"
72
73 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
74 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
75
76 #include "reg_helper.h"
77 #include "dce/dmub_abm.h"
78 #include "dce/dmub_psr.h"
79 #include "dce/dmub_replay.h"
80 #include "dce/dce_aux.h"
81 #include "dce/dce_i2c.h"
82 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
83 #include "vm_helper.h"
84 #include "dcn20/dcn20_vmid.h"
85
86 #include "dml2/dml2_wrapper.h"
87
88 #include "link_enc_cfg.h"
89 #define DC_LOGGER_INIT(logger)
90
91 enum dcn351_clk_src_array_id {
92 DCN351_CLK_SRC_PLL0,
93 DCN351_CLK_SRC_PLL1,
94 DCN351_CLK_SRC_PLL2,
95 DCN351_CLK_SRC_PLL3,
96 DCN351_CLK_SRC_PLL4,
97 DCN351_CLK_SRC_TOTAL
98 };
99
100 /* begin *********************
101 * macros to expend register list macro defined in HW object header file
102 */
103
104 /* DCN */
105 /* TODO awful hack. fixup dcn20_dwb.h */
106 #undef BASE_INNER
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
108
109 #define BASE(seg) BASE_INNER(seg)
110
111 #define SR(reg_name)\
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
114
115 #define SR_ARR(reg_name, id) \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
117
118 #define SR_ARR_INIT(reg_name, id, value) \
119 REG_STRUCT[id].reg_name = value
120
121 #define SRI(reg_name, block, id)\
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
124
125 #define SRI_ARR(reg_name, block, id)\
126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SR_ARR_I2C(reg_name, id) \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
131
132 #define SRI_ARR_I2C(reg_name, block, id)\
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI2(reg_name, block, id)\
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
142 reg ## reg_name
143
144 #define SRI2_ARR(reg_name, block, id)\
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
147
148 #define SRIR(var_name, reg_name, block, id)\
149 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII(reg_name, block, id)\
153 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII_ARR_2(reg_name, block, id, inst)\
157 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRII_MPC_RMU(reg_name, block, id)\
161 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII_DWB(reg_name, temp_name, block, id)\
165 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## temp_name
167
168 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
169 .field_name = reg_name ## __ ## field_name ## post_fix
170
171 #define DCCG_SRII(reg_name, block, id)\
172 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
174
175 #define VUPDATE_SRII(reg_name, block, id)\
176 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
177 reg ## reg_name ## _ ## block ## id
178
179 /* NBIO */
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
181
182 #define NBIO_BASE(seg) \
183 NBIO_BASE_INNER(seg)
184
185 #define NBIO_SR(reg_name)\
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
187 regBIF_BX2_ ## reg_name
188
189 #define NBIO_SR_ARR(reg_name, id)\
190 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
191 regBIF_BX2_ ## reg_name
192
193 #define bios_regs_init() \
194 ( \
195 NBIO_SR(BIOS_SCRATCH_3),\
196 NBIO_SR(BIOS_SCRATCH_6)\
197 )
198
199 static struct bios_registers bios_regs;
200
201 #define clk_src_regs_init(index, pllid)\
202 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
203
204 static struct dce110_clk_src_regs clk_src_regs[5];
205
206 static const struct dce110_clk_src_shift cs_shift = {
207 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
208 };
209
210 static const struct dce110_clk_src_mask cs_mask = {
211 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
212 };
213
214 #define abm_regs_init(id)\
215 ABM_DCN32_REG_LIST_RI(id)
216
217 static struct dce_abm_registers abm_regs[4];
218
219 static const struct dce_abm_shift abm_shift = {
220 ABM_MASK_SH_LIST_DCN35(__SHIFT)
221 };
222
223 static const struct dce_abm_mask abm_mask = {
224 ABM_MASK_SH_LIST_DCN35(_MASK)
225 };
226
227 #define audio_regs_init(id)\
228 AUD_COMMON_REG_LIST_RI(id)
229
230 static struct dce_audio_registers audio_regs[7];
231
232
233 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
234 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
235 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
236 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
237
238 static const struct dce_audio_shift audio_shift = {
239 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
240 };
241
242 static const struct dce_audio_mask audio_mask = {
243 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
244 };
245
246 #define vpg_regs_init(id)\
247 VPG_DCN31_REG_LIST_RI(id)
248
249 static struct dcn31_vpg_registers vpg_regs[10];
250
251 static const struct dcn31_vpg_shift vpg_shift = {
252 DCN31_VPG_MASK_SH_LIST(__SHIFT)
253 };
254
255 static const struct dcn31_vpg_mask vpg_mask = {
256 DCN31_VPG_MASK_SH_LIST(_MASK)
257 };
258
259 #define afmt_regs_init(id)\
260 AFMT_DCN31_REG_LIST_RI(id)
261
262 static struct dcn31_afmt_registers afmt_regs[6];
263
264 static const struct dcn31_afmt_shift afmt_shift = {
265 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn31_afmt_mask afmt_mask = {
269 DCN31_AFMT_MASK_SH_LIST(_MASK)
270 };
271
272 #define apg_regs_init(id)\
273 APG_DCN31_REG_LIST_RI(id)
274
275 static struct dcn31_apg_registers apg_regs[4];
276
277 static const struct dcn31_apg_shift apg_shift = {
278 DCN31_APG_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dcn31_apg_mask apg_mask = {
282 DCN31_APG_MASK_SH_LIST(_MASK)
283 };
284
285 #define stream_enc_regs_init(id)\
286 SE_DCN35_REG_LIST_RI(id)
287
288 static struct dcn10_stream_enc_registers stream_enc_regs[5];
289
290 static const struct dcn10_stream_encoder_shift se_shift = {
291 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
292 };
293
294 static const struct dcn10_stream_encoder_mask se_mask = {
295 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
296 };
297
298 #define aux_regs_init(id)\
299 DCN2_AUX_REG_LIST_RI(id)
300
301 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
302
303 #define hpd_regs_init(id)\
304 HPD_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
307
308
309 static const struct dce110_aux_registers_shift aux_shift = {
310 DCN_AUX_MASK_SH_LIST(__SHIFT)
311 };
312
313 static const struct dce110_aux_registers_mask aux_mask = {
314 DCN_AUX_MASK_SH_LIST(_MASK)
315 };
316
317 #define link_regs_init(id, phyid)\
318 ( \
319 LE_DCN35_REG_LIST_RI(id), \
320 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
321 )
322
323 static struct dcn10_link_enc_registers link_enc_regs[5];
324
325 static const struct dcn10_link_enc_shift le_shift = {
326 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
327 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
328 };
329
330 static const struct dcn10_link_enc_mask le_mask = {
331 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
332 //DPCS_DCN31_MASK_SH_LIST(_MASK)
333 };
334
335 #define hpo_dp_stream_encoder_reg_init(id)\
336 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
337
338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
339
340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
345 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
346 };
347
348 #define hpo_dp_link_encoder_reg_init(id)\
349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
354
355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
356
357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
358 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
362 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
363 };
364
365 #define dpp_regs_init(id)\
366 DPP_REG_LIST_DCN35_RI(id)
367
368 static struct dcn3_dpp_registers dpp_regs[4];
369
370 static const struct dcn35_dpp_shift tf_shift = {
371 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
372 };
373
374 static const struct dcn35_dpp_mask tf_mask = {
375 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
376 };
377
378 #define opp_regs_init(id)\
379 OPP_REG_LIST_DCN35_RI(id)
380
381 static struct dcn35_opp_registers opp_regs[4];
382
383 static const struct dcn35_opp_shift opp_shift = {
384 OPP_MASK_SH_LIST_DCN35(__SHIFT)
385 };
386
387 static const struct dcn35_opp_mask opp_mask = {
388 OPP_MASK_SH_LIST_DCN35(_MASK)
389 };
390
391 #define aux_engine_regs_init(id)\
392 ( \
393 AUX_COMMON_REG_LIST0_RI(id), \
394 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
395 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
397 )
398
399 static struct dce110_aux_registers aux_engine_regs[5];
400
401 #define dwbc_regs_dcn3_init(id)\
402 DWBC_COMMON_REG_LIST_DCN30_RI(id)
403
404 static struct dcn30_dwbc_registers dwbc35_regs[1];
405
406 static const struct dcn35_dwbc_shift dwbc35_shift = {
407 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
408 };
409
410 static const struct dcn35_dwbc_mask dwbc35_mask = {
411 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
412 };
413
414 #define mcif_wb_regs_dcn3_init(id)\
415 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
416
417 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
418
419 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
420 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
421 };
422
423 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
424 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
425 };
426
427 #define dsc_regsDCN35_init(id)\
428 DSC_REG_LIST_DCN20_RI(id)
429
430 static struct dcn20_dsc_registers dsc_regs[4];
431
432 static const struct dcn35_dsc_shift dsc_shift = {
433 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
434 };
435
436 static const struct dcn35_dsc_mask dsc_mask = {
437 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
438 };
439
440 static struct dcn30_mpc_registers mpc_regs;
441
442 #define dcn_mpc_regs_init() \
443 MPC_REG_LIST_DCN3_2_RI(0),\
444 MPC_REG_LIST_DCN3_2_RI(1),\
445 MPC_REG_LIST_DCN3_2_RI(2),\
446 MPC_REG_LIST_DCN3_2_RI(3),\
447 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
448 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
449 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
450 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
451 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
452
453 static const struct dcn30_mpc_shift mpc_shift = {
454 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
455 };
456
457 static const struct dcn30_mpc_mask mpc_mask = {
458 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
459 };
460
461 #define optc_regs_init(id)\
462 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
463
464 static struct dcn_optc_registers optc_regs[4];
465
466 static const struct dcn_optc_shift optc_shift = {
467 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
468 };
469
470 static const struct dcn_optc_mask optc_mask = {
471 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
472 };
473
474 #define hubp_regs_init(id)\
475 HUBP_REG_LIST_DCN30_RI(id)
476
477 static struct dcn_hubp2_registers hubp_regs[4];
478
479
480 static const struct dcn35_hubp2_shift hubp_shift = {
481 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
482 };
483
484 static const struct dcn35_hubp2_mask hubp_mask = {
485 HUBP_MASK_SH_LIST_DCN35(_MASK)
486 };
487
488 static struct dcn_hubbub_registers hubbub_reg;
489
490 #define hubbub_reg_init()\
491 HUBBUB_REG_LIST_DCN35(0)
492
493 static const struct dcn_hubbub_shift hubbub_shift = {
494 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
495 };
496
497 static const struct dcn_hubbub_mask hubbub_mask = {
498 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
499 };
500
501 static struct dccg_registers dccg_regs;
502
503 #define dccg_regs_init()\
504 DCCG_REG_LIST_DCN35()
505
506 static const struct dccg_shift dccg_shift = {
507 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
508 };
509
510 static const struct dccg_mask dccg_mask = {
511 DCCG_MASK_SH_LIST_DCN35(_MASK)
512 };
513
514 static struct pg_cntl_registers pg_cntl_regs;
515
516 #define pg_cntl_dcn35_regs_init() \
517 PG_CNTL_REG_LIST_DCN35()
518
519 static const struct pg_cntl_shift pg_cntl_shift = {
520 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
521 };
522
523 static const struct pg_cntl_mask pg_cntl_mask = {
524 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
525 };
526
527 #define SRII2(reg_name_pre, reg_name_post, id)\
528 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
529 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
530 reg ## reg_name_pre ## id ## _ ## reg_name_post
531
532 static struct dce_hwseq_registers hwseq_reg;
533
534 #define hwseq_reg_init()\
535 HWSEQ_DCN35_REG_LIST()
536
537 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
538 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
539 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
540 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
541 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
542 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
543 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
544 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
545 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
546 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
547 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
548 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
549 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
550 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
551 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
552 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
553 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
554 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
555 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
556 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
557 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
558 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
559 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
560 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
561 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
562 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
563 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
564 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
565 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
566 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
567 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
568 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
569 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
570 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
571 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
572 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
573 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
574 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
575 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
576 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
577 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
578 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
579 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
580 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
581 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
582 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
583 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
584 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
585 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
586 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
587 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
588 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
589 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
590 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
591 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
592 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
593 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
594 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
595 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
596 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
597 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
598 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
599 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
600 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
601 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
602 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
603 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
613 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
625
626 static const struct dce_hwseq_shift hwseq_shift = {
627 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
628 };
629
630 static const struct dce_hwseq_mask hwseq_mask = {
631 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
632 };
633
634 #define vmid_regs_init(id)\
635 DCN20_VMID_REG_LIST_RI(id)
636
637 static struct dcn_vmid_registers vmid_regs[16];
638
639 static const struct dcn20_vmid_shift vmid_shifts = {
640 DCN20_VMID_MASK_SH_LIST(__SHIFT)
641 };
642
643 static const struct dcn20_vmid_mask vmid_masks = {
644 DCN20_VMID_MASK_SH_LIST(_MASK)
645 };
646
647 static const struct resource_caps res_cap_dcn351 = {
648 .num_timing_generator = 4,
649 .num_opp = 4,
650 .num_video_plane = 4,
651 .num_audio = 5,
652 .num_stream_encoder = 5,
653 .num_dig_link_enc = 5,
654 .num_hpo_dp_stream_encoder = 4,
655 .num_hpo_dp_link_encoder = 2,
656 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
657 .num_dwb = 1,
658 .num_ddc = 5,
659 .num_vmid = 16,
660 .num_mpc_3dlut = 2,
661 .num_dsc = 4,
662 };
663
664 static const struct dc_plane_cap plane_cap = {
665 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
666 .per_pixel_alpha = true,
667
668 .pixel_format_support = {
669 .argb8888 = true,
670 .nv12 = true,
671 .fp16 = true,
672 .p010 = true,
673 .ayuv = false,
674 },
675
676 .max_upscale_factor = {
677 .argb8888 = 16000,
678 .nv12 = 16000,
679 .fp16 = 16000
680 },
681
682 // 6:1 downscaling ratio: 1000/6 = 166.666
683 .max_downscale_factor = {
684 .argb8888 = 250,
685 .nv12 = 167,
686 .fp16 = 167
687 },
688 64,
689 64
690 };
691
692 static const struct dc_debug_options debug_defaults_drv = {
693 .disable_dmcu = true,
694 .force_abm_enable = false,
695 .clock_trace = true,
696 .disable_pplib_clock_request = false,
697 .pipe_split_policy = MPC_SPLIT_AVOID,
698 .force_single_disp_pipe_split = false,
699 .disable_dcc = DCC_ENABLE,
700 .disable_dpp_power_gate = true,
701 .disable_hubp_power_gate = true,
702 .disable_optc_power_gate = true, /*should the same as above two*/
703 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
704 .disable_clock_gate = false,
705 .disable_dsc_power_gate = true,
706 .vsr_support = true,
707 .performance_trace = false,
708 .max_downscale_src_width = 4096,/*upto true 4k*/
709 .disable_pplib_wm_range = false,
710 .scl_reset_length10 = true,
711 .sanity_checks = false,
712 .underflow_assert_delay_us = 0xFFFFFFFF,
713 .dwb_fi_phase = -1, // -1 = disable,
714 .dmub_command_table = true,
715 .pstate_enabled = true,
716 .use_max_lb = true,
717 .enable_mem_low_power = {
718 .bits = {
719 .vga = false,
720 .i2c = true,
721 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
722 .dscl = true,
723 .cm = true,
724 .mpc = true,
725 .optc = true,
726 .vpg = true,
727 .afmt = true,
728 }
729 },
730 .root_clock_optimization = {
731 .bits = {
732 .dpp = true,
733 .dsc = true,/*dscclk and dsc pg*/
734 .hdmistream = true,
735 .hdmichar = true,
736 .dpstream = true,
737 .symclk32_se = true,
738 .symclk32_le = false,
739 .symclk_fe = true,
740 .physymclk = false,
741 .dpiasymclk = true,
742 }
743 },
744 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
745 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
746 .minimum_z8_residency_time = 1,
747 .using_dml2 = true,
748 .support_eDP1_5 = true,
749 .enable_hpo_pg_support = false,
750 .enable_legacy_fast_update = true,
751 .enable_single_display_2to1_odm_policy = true,
752 .disable_idle_power_optimizations = false,
753 .dmcub_emulation = false,
754 .disable_boot_optimizations = false,
755 .disable_unbounded_requesting = false,
756 .disable_mem_low_power = false,
757 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
758 .enable_double_buffered_dsc_pg_support = true,
759 .enable_dp_dig_pixel_rate_div_policy = 1,
760 .disable_z10 = false,
761 .ignore_pg = true,
762 .psp_disabled_wa = true,
763 .ips2_eval_delay_us = 2000,
764 .ips2_entry_delay_us = 800,
765 .disable_dmub_reallow_idle = false,
766 .static_screen_wait_frames = 2,
767 .notify_dpia_hr_bw = true,
768 .min_disp_clk_khz = 50000,
769 };
770
771 static const struct dc_panel_config panel_config_defaults = {
772 .psr = {
773 .disable_psr = false,
774 .disallow_psrsu = false,
775 .disallow_replay = false,
776 },
777 .ilr = {
778 .optimize_edp_link_rate = true,
779 },
780 };
781
dcn35_dpp_destroy(struct dpp ** dpp)782 static void dcn35_dpp_destroy(struct dpp **dpp)
783 {
784 kfree(TO_DCN20_DPP(*dpp));
785 *dpp = NULL;
786 }
787
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)788 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
789 {
790 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
791 bool success = (dpp != NULL);
792
793 if (!success)
794 return NULL;
795
796 #undef REG_STRUCT
797 #define REG_STRUCT dpp_regs
798 dpp_regs_init(0),
799 dpp_regs_init(1),
800 dpp_regs_init(2),
801 dpp_regs_init(3);
802
803 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
804 &tf_mask);
805 if (success) {
806 dpp35_set_fgcg(
807 dpp,
808 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
809 return &dpp->base;
810 }
811
812 BREAK_TO_DEBUGGER();
813 kfree(dpp);
814 return NULL;
815 }
816
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)817 static struct output_pixel_processor *dcn35_opp_create(
818 struct dc_context *ctx, uint32_t inst)
819 {
820 struct dcn20_opp *opp =
821 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
822
823 if (!opp) {
824 BREAK_TO_DEBUGGER();
825 return NULL;
826 }
827
828 #undef REG_STRUCT
829 #define REG_STRUCT opp_regs
830 opp_regs_init(0),
831 opp_regs_init(1),
832 opp_regs_init(2),
833 opp_regs_init(3);
834
835 dcn35_opp_construct(opp, ctx, inst,
836 &opp_regs[inst], &opp_shift, &opp_mask);
837
838 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
839
840 return &opp->base;
841 }
842
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)843 static struct dce_aux *dcn31_aux_engine_create(
844 struct dc_context *ctx,
845 uint32_t inst)
846 {
847 struct aux_engine_dce110 *aux_engine =
848 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
849
850 if (!aux_engine)
851 return NULL;
852
853 #undef REG_STRUCT
854 #define REG_STRUCT aux_engine_regs
855 aux_engine_regs_init(0),
856 aux_engine_regs_init(1),
857 aux_engine_regs_init(2),
858 aux_engine_regs_init(3),
859 aux_engine_regs_init(4);
860
861 dce110_aux_engine_construct(aux_engine, ctx, inst,
862 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
863 &aux_engine_regs[inst],
864 &aux_mask,
865 &aux_shift,
866 ctx->dc->caps.extended_aux_timeout_support);
867
868 return &aux_engine->base;
869 }
870
871 #define i2c_inst_regs_init(id)\
872 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
873
874 static struct dce_i2c_registers i2c_hw_regs[5];
875
876 static const struct dce_i2c_shift i2c_shifts = {
877 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
878 };
879
880 static const struct dce_i2c_mask i2c_masks = {
881 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
882 };
883
884 /* ========================================================== */
885
886 /*
887 * DPIA index | Preferred Encoder | Host Router
888 * 0 | C | 0
889 * 1 | First Available | 0
890 * 2 | D | 1
891 * 3 | First Available | 1
892 */
893 /* ========================================================== */
894 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
895 ENGINE_ID_DIGC,
896 ENGINE_ID_DIGC,
897 ENGINE_ID_DIGD,
898 ENGINE_ID_DIGD
899 };
900
dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)901 static enum engine_id dcn351_get_preferred_eng_id_dpia(unsigned int dpia_index)
902 {
903 return dpia_to_preferred_enc_id_table[dpia_index];
904 }
905
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)906 static struct dce_i2c_hw *dcn31_i2c_hw_create(
907 struct dc_context *ctx,
908 uint32_t inst)
909 {
910 struct dce_i2c_hw *dce_i2c_hw =
911 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
912
913 if (!dce_i2c_hw)
914 return NULL;
915
916 #undef REG_STRUCT
917 #define REG_STRUCT i2c_hw_regs
918 i2c_inst_regs_init(1),
919 i2c_inst_regs_init(2),
920 i2c_inst_regs_init(3),
921 i2c_inst_regs_init(4),
922 i2c_inst_regs_init(5);
923
924 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
925 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
926
927 return dce_i2c_hw;
928 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)929 static struct mpc *dcn35_mpc_create(
930 struct dc_context *ctx,
931 int num_mpcc,
932 int num_rmu)
933 {
934 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
935
936 if (!mpc30)
937 return NULL;
938
939 #undef REG_STRUCT
940 #define REG_STRUCT mpc_regs
941 dcn_mpc_regs_init();
942
943 dcn32_mpc_construct(mpc30, ctx,
944 &mpc_regs,
945 &mpc_shift,
946 &mpc_mask,
947 num_mpcc,
948 num_rmu);
949
950 return &mpc30->base;
951 }
952
dcn35_hubbub_create(struct dc_context * ctx)953 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
954 {
955 int i;
956
957 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
958 GFP_KERNEL);
959
960 if (!hubbub3)
961 return NULL;
962
963 #undef REG_STRUCT
964 #define REG_STRUCT hubbub_reg
965 hubbub_reg_init();
966
967 #undef REG_STRUCT
968 #define REG_STRUCT vmid_regs
969 vmid_regs_init(0),
970 vmid_regs_init(1),
971 vmid_regs_init(2),
972 vmid_regs_init(3),
973 vmid_regs_init(4),
974 vmid_regs_init(5),
975 vmid_regs_init(6),
976 vmid_regs_init(7),
977 vmid_regs_init(8),
978 vmid_regs_init(9),
979 vmid_regs_init(10),
980 vmid_regs_init(11),
981 vmid_regs_init(12),
982 vmid_regs_init(13),
983 vmid_regs_init(14),
984 vmid_regs_init(15);
985
986 hubbub35_construct(hubbub3, ctx,
987 &hubbub_reg,
988 &hubbub_shift,
989 &hubbub_mask,
990 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
991 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
992 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
993
994
995 for (i = 0; i < res_cap_dcn351.num_vmid; i++) {
996 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
997
998 vmid->ctx = ctx;
999
1000 vmid->regs = &vmid_regs[i];
1001 vmid->shifts = &vmid_shifts;
1002 vmid->masks = &vmid_masks;
1003 }
1004
1005 return &hubbub3->base;
1006 }
1007
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1008 static struct timing_generator *dcn35_timing_generator_create(
1009 struct dc_context *ctx,
1010 uint32_t instance)
1011 {
1012 struct optc *tgn10 =
1013 kzalloc(sizeof(struct optc), GFP_KERNEL);
1014
1015 if (!tgn10)
1016 return NULL;
1017
1018 #undef REG_STRUCT
1019 #define REG_STRUCT optc_regs
1020 optc_regs_init(0),
1021 optc_regs_init(1),
1022 optc_regs_init(2),
1023 optc_regs_init(3);
1024
1025 tgn10->base.inst = instance;
1026 tgn10->base.ctx = ctx;
1027
1028 tgn10->tg_regs = &optc_regs[instance];
1029 tgn10->tg_shift = &optc_shift;
1030 tgn10->tg_mask = &optc_mask;
1031
1032 dcn35_timing_generator_init(tgn10);
1033
1034 return &tgn10->base;
1035 }
1036
1037 static const struct encoder_feature_support link_enc_feature = {
1038 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1039 .max_hdmi_pixel_clock = 600000,
1040 .hdmi_ycbcr420_supported = true,
1041 .dp_ycbcr420_supported = true,
1042 .fec_supported = true,
1043 .flags.bits.IS_HBR2_CAPABLE = true,
1044 .flags.bits.IS_HBR3_CAPABLE = true,
1045 .flags.bits.IS_TPS3_CAPABLE = true,
1046 .flags.bits.IS_TPS4_CAPABLE = true
1047 };
1048
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1049 static struct link_encoder *dcn35_link_encoder_create(
1050 struct dc_context *ctx,
1051 const struct encoder_init_data *enc_init_data)
1052 {
1053 struct dcn20_link_encoder *enc20 =
1054 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1055
1056 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1057 return NULL;
1058
1059 #undef REG_STRUCT
1060 #define REG_STRUCT link_enc_aux_regs
1061 aux_regs_init(0),
1062 aux_regs_init(1),
1063 aux_regs_init(2),
1064 aux_regs_init(3),
1065 aux_regs_init(4);
1066
1067 #undef REG_STRUCT
1068 #define REG_STRUCT link_enc_hpd_regs
1069 hpd_regs_init(0),
1070 hpd_regs_init(1),
1071 hpd_regs_init(2),
1072 hpd_regs_init(3),
1073 hpd_regs_init(4);
1074
1075 #undef REG_STRUCT
1076 #define REG_STRUCT link_enc_regs
1077 link_regs_init(0, A),
1078 link_regs_init(1, B),
1079 link_regs_init(2, C),
1080 link_regs_init(3, D),
1081 link_regs_init(4, E);
1082
1083 dcn35_link_encoder_construct(enc20,
1084 enc_init_data,
1085 &link_enc_feature,
1086 &link_enc_regs[enc_init_data->transmitter],
1087 &link_enc_aux_regs[enc_init_data->channel - 1],
1088 &link_enc_hpd_regs[enc_init_data->hpd_source],
1089 &le_shift,
1090 &le_mask);
1091
1092 return &enc20->enc10.base;
1093 }
1094
1095 /* Create a minimal link encoder object not associated with a particular
1096 * physical connector.
1097 * resource_funcs.link_enc_create_minimal
1098 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1099 static struct link_encoder *dcn31_link_enc_create_minimal(
1100 struct dc_context *ctx, enum engine_id eng_id)
1101 {
1102 struct dcn20_link_encoder *enc20;
1103
1104 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1105 return NULL;
1106
1107 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1108 if (!enc20)
1109 return NULL;
1110
1111 dcn31_link_encoder_construct_minimal(
1112 enc20,
1113 ctx,
1114 &link_enc_feature,
1115 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1116 eng_id);
1117
1118 return &enc20->enc10.base;
1119 }
1120
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1121 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1122 {
1123 struct dcn31_panel_cntl *panel_cntl =
1124 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1125
1126 if (!panel_cntl)
1127 return NULL;
1128
1129 dcn31_panel_cntl_construct(panel_cntl, init_data);
1130
1131 return &panel_cntl->base;
1132 }
1133
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1134 static void read_dce_straps(
1135 struct dc_context *ctx,
1136 struct resource_straps *straps)
1137 {
1138 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1139 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1140
1141 }
1142
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1143 static struct audio *dcn31_create_audio(
1144 struct dc_context *ctx, unsigned int inst)
1145 {
1146
1147 #undef REG_STRUCT
1148 #define REG_STRUCT audio_regs
1149 audio_regs_init(0),
1150 audio_regs_init(1),
1151 audio_regs_init(2),
1152 audio_regs_init(3),
1153 audio_regs_init(4);
1154 audio_regs_init(5);
1155 audio_regs_init(6);
1156
1157 return dce_audio_create(ctx, inst,
1158 &audio_regs[inst], &audio_shift, &audio_mask);
1159 }
1160
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1161 static struct vpg *dcn31_vpg_create(
1162 struct dc_context *ctx,
1163 uint32_t inst)
1164 {
1165 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1166
1167 if (!vpg31)
1168 return NULL;
1169
1170 #undef REG_STRUCT
1171 #define REG_STRUCT vpg_regs
1172 vpg_regs_init(0),
1173 vpg_regs_init(1),
1174 vpg_regs_init(2),
1175 vpg_regs_init(3),
1176 vpg_regs_init(4),
1177 vpg_regs_init(5),
1178 vpg_regs_init(6),
1179 vpg_regs_init(7),
1180 vpg_regs_init(8),
1181 vpg_regs_init(9);
1182
1183 vpg31_construct(vpg31, ctx, inst,
1184 &vpg_regs[inst],
1185 &vpg_shift,
1186 &vpg_mask);
1187
1188 return &vpg31->base;
1189 }
1190
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1191 static struct afmt *dcn31_afmt_create(
1192 struct dc_context *ctx,
1193 uint32_t inst)
1194 {
1195 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1196
1197 if (!afmt31)
1198 return NULL;
1199
1200 #undef REG_STRUCT
1201 #define REG_STRUCT afmt_regs
1202 afmt_regs_init(0),
1203 afmt_regs_init(1),
1204 afmt_regs_init(2),
1205 afmt_regs_init(3),
1206 afmt_regs_init(4),
1207 afmt_regs_init(5);
1208
1209 afmt31_construct(afmt31, ctx, inst,
1210 &afmt_regs[inst],
1211 &afmt_shift,
1212 &afmt_mask);
1213
1214 // Light sleep by default, no need to power down here
1215
1216 return &afmt31->base;
1217 }
1218
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1219 static struct apg *dcn31_apg_create(
1220 struct dc_context *ctx,
1221 uint32_t inst)
1222 {
1223 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1224
1225 if (!apg31)
1226 return NULL;
1227
1228 #undef REG_STRUCT
1229 #define REG_STRUCT apg_regs
1230 apg_regs_init(0),
1231 apg_regs_init(1),
1232 apg_regs_init(2),
1233 apg_regs_init(3);
1234
1235 apg31_construct(apg31, ctx, inst,
1236 &apg_regs[inst],
1237 &apg_shift,
1238 &apg_mask);
1239
1240 return &apg31->base;
1241 }
1242
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1243 static struct stream_encoder *dcn35_stream_encoder_create(
1244 enum engine_id eng_id,
1245 struct dc_context *ctx)
1246 {
1247 struct dcn10_stream_encoder *enc1;
1248 struct vpg *vpg;
1249 struct afmt *afmt;
1250 int vpg_inst;
1251 int afmt_inst;
1252
1253 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1254 if (eng_id <= ENGINE_ID_DIGF) {
1255 vpg_inst = eng_id;
1256 afmt_inst = eng_id;
1257 } else
1258 return NULL;
1259
1260 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1261 vpg = dcn31_vpg_create(ctx, vpg_inst);
1262 afmt = dcn31_afmt_create(ctx, afmt_inst);
1263
1264 if (!enc1 || !vpg || !afmt) {
1265 kfree(enc1);
1266 kfree(vpg);
1267 kfree(afmt);
1268 return NULL;
1269 }
1270
1271 #undef REG_STRUCT
1272 #define REG_STRUCT stream_enc_regs
1273 stream_enc_regs_init(0),
1274 stream_enc_regs_init(1),
1275 stream_enc_regs_init(2),
1276 stream_enc_regs_init(3),
1277 stream_enc_regs_init(4);
1278
1279 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1280 eng_id, vpg, afmt,
1281 &stream_enc_regs[eng_id],
1282 &se_shift, &se_mask);
1283
1284 return &enc1->base;
1285 }
1286
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1287 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1288 enum engine_id eng_id,
1289 struct dc_context *ctx)
1290 {
1291 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1292 struct vpg *vpg;
1293 struct apg *apg;
1294 uint32_t hpo_dp_inst;
1295 uint32_t vpg_inst;
1296 uint32_t apg_inst;
1297
1298 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1299 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1300
1301 /* Mapping of VPG register blocks to HPO DP block instance:
1302 * VPG[6] -> HPO_DP[0]
1303 * VPG[7] -> HPO_DP[1]
1304 * VPG[8] -> HPO_DP[2]
1305 * VPG[9] -> HPO_DP[3]
1306 */
1307 vpg_inst = hpo_dp_inst + 6;
1308
1309 /* Mapping of APG register blocks to HPO DP block instance:
1310 * APG[0] -> HPO_DP[0]
1311 * APG[1] -> HPO_DP[1]
1312 * APG[2] -> HPO_DP[2]
1313 * APG[3] -> HPO_DP[3]
1314 */
1315 apg_inst = hpo_dp_inst;
1316
1317 /* allocate HPO stream encoder and create VPG sub-block */
1318 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1319 vpg = dcn31_vpg_create(ctx, vpg_inst);
1320 apg = dcn31_apg_create(ctx, apg_inst);
1321
1322 if (!hpo_dp_enc31 || !vpg || !apg) {
1323 kfree(hpo_dp_enc31);
1324 kfree(vpg);
1325 kfree(apg);
1326 return NULL;
1327 }
1328
1329 #undef REG_STRUCT
1330 #define REG_STRUCT hpo_dp_stream_enc_regs
1331 hpo_dp_stream_encoder_reg_init(0),
1332 hpo_dp_stream_encoder_reg_init(1),
1333 hpo_dp_stream_encoder_reg_init(2),
1334 hpo_dp_stream_encoder_reg_init(3);
1335
1336 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1337 hpo_dp_inst, eng_id, vpg, apg,
1338 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1339 &hpo_dp_se_shift, &hpo_dp_se_mask);
1340
1341 return &hpo_dp_enc31->base;
1342 }
1343
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1344 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1345 uint8_t inst,
1346 struct dc_context *ctx)
1347 {
1348 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1349
1350 /* allocate HPO link encoder */
1351 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1352 if (!hpo_dp_enc31)
1353 return NULL; /* out of memory */
1354
1355 #undef REG_STRUCT
1356 #define REG_STRUCT hpo_dp_link_enc_regs
1357 hpo_dp_link_encoder_reg_init(0),
1358 hpo_dp_link_encoder_reg_init(1);
1359
1360 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1361 &hpo_dp_link_enc_regs[inst],
1362 &hpo_dp_le_shift, &hpo_dp_le_mask);
1363
1364 return &hpo_dp_enc31->base;
1365 }
1366
dcn351_hwseq_create(struct dc_context * ctx)1367 static struct dce_hwseq *dcn351_hwseq_create(
1368 struct dc_context *ctx)
1369 {
1370 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1371
1372 #undef REG_STRUCT
1373 #define REG_STRUCT hwseq_reg
1374 hwseq_reg_init();
1375
1376 if (hws) {
1377 hws->ctx = ctx;
1378 hws->regs = &hwseq_reg;
1379 hws->shifts = &hwseq_shift;
1380 hws->masks = &hwseq_mask;
1381 }
1382 return hws;
1383 }
1384 static const struct resource_create_funcs res_create_funcs = {
1385 .read_dce_straps = read_dce_straps,
1386 .create_audio = dcn31_create_audio,
1387 .create_stream_encoder = dcn35_stream_encoder_create,
1388 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1389 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1390 .create_hwseq = dcn351_hwseq_create,
1391 };
1392
dcn351_resource_destruct(struct dcn351_resource_pool * pool)1393 static void dcn351_resource_destruct(struct dcn351_resource_pool *pool)
1394 {
1395 unsigned int i;
1396
1397 for (i = 0; i < pool->base.stream_enc_count; i++) {
1398 if (pool->base.stream_enc[i] != NULL) {
1399 if (pool->base.stream_enc[i]->vpg != NULL) {
1400 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1401 pool->base.stream_enc[i]->vpg = NULL;
1402 }
1403 if (pool->base.stream_enc[i]->afmt != NULL) {
1404 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1405 pool->base.stream_enc[i]->afmt = NULL;
1406 }
1407 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1408 pool->base.stream_enc[i] = NULL;
1409 }
1410 }
1411
1412 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1413 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1414 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1415 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1416 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1417 }
1418 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1419 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1420 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1421 }
1422 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1423 pool->base.hpo_dp_stream_enc[i] = NULL;
1424 }
1425 }
1426
1427 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1428 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1429 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1430 pool->base.hpo_dp_link_enc[i] = NULL;
1431 }
1432 }
1433
1434 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1435 if (pool->base.dscs[i] != NULL)
1436 dcn20_dsc_destroy(&pool->base.dscs[i]);
1437 }
1438
1439 if (pool->base.mpc != NULL) {
1440 kfree(TO_DCN20_MPC(pool->base.mpc));
1441 pool->base.mpc = NULL;
1442 }
1443 if (pool->base.hubbub != NULL) {
1444 kfree(pool->base.hubbub);
1445 pool->base.hubbub = NULL;
1446 }
1447 for (i = 0; i < pool->base.pipe_count; i++) {
1448 if (pool->base.dpps[i] != NULL)
1449 dcn35_dpp_destroy(&pool->base.dpps[i]);
1450
1451 if (pool->base.ipps[i] != NULL)
1452 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1453
1454 if (pool->base.hubps[i] != NULL) {
1455 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1456 pool->base.hubps[i] = NULL;
1457 }
1458
1459 if (pool->base.irqs != NULL) {
1460 dal_irq_service_destroy(&pool->base.irqs);
1461 }
1462 }
1463
1464 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1465 if (pool->base.engines[i] != NULL)
1466 dce110_engine_destroy(&pool->base.engines[i]);
1467 if (pool->base.hw_i2cs[i] != NULL) {
1468 kfree(pool->base.hw_i2cs[i]);
1469 pool->base.hw_i2cs[i] = NULL;
1470 }
1471 if (pool->base.sw_i2cs[i] != NULL) {
1472 kfree(pool->base.sw_i2cs[i]);
1473 pool->base.sw_i2cs[i] = NULL;
1474 }
1475 }
1476
1477 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1478 if (pool->base.opps[i] != NULL)
1479 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1480 }
1481
1482 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1483 if (pool->base.timing_generators[i] != NULL) {
1484 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1485 pool->base.timing_generators[i] = NULL;
1486 }
1487 }
1488
1489 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1490 if (pool->base.dwbc[i] != NULL) {
1491 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1492 pool->base.dwbc[i] = NULL;
1493 }
1494 if (pool->base.mcif_wb[i] != NULL) {
1495 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1496 pool->base.mcif_wb[i] = NULL;
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.audio_count; i++) {
1501 if (pool->base.audios[i])
1502 dce_aud_destroy(&pool->base.audios[i]);
1503 }
1504
1505 for (i = 0; i < pool->base.clk_src_count; i++) {
1506 if (pool->base.clock_sources[i] != NULL) {
1507 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1508 pool->base.clock_sources[i] = NULL;
1509 }
1510 }
1511
1512 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1513 if (pool->base.mpc_lut[i] != NULL) {
1514 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1515 pool->base.mpc_lut[i] = NULL;
1516 }
1517 if (pool->base.mpc_shaper[i] != NULL) {
1518 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1519 pool->base.mpc_shaper[i] = NULL;
1520 }
1521 }
1522
1523 if (pool->base.dp_clock_source != NULL) {
1524 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1525 pool->base.dp_clock_source = NULL;
1526 }
1527
1528 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1529 if (pool->base.multiple_abms[i] != NULL)
1530 dce_abm_destroy(&pool->base.multiple_abms[i]);
1531 }
1532
1533 if (pool->base.psr != NULL)
1534 dmub_psr_destroy(&pool->base.psr);
1535
1536 if (pool->base.replay != NULL)
1537 dmub_replay_destroy(&pool->base.replay);
1538
1539 if (pool->base.pg_cntl != NULL)
1540 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1541
1542 if (pool->base.dccg != NULL)
1543 dcn_dccg_destroy(&pool->base.dccg);
1544 }
1545
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1546 static struct hubp *dcn35_hubp_create(
1547 struct dc_context *ctx,
1548 uint32_t inst)
1549 {
1550 struct dcn20_hubp *hubp2 =
1551 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1552
1553 if (!hubp2)
1554 return NULL;
1555
1556 #undef REG_STRUCT
1557 #define REG_STRUCT hubp_regs
1558 hubp_regs_init(0),
1559 hubp_regs_init(1),
1560 hubp_regs_init(2),
1561 hubp_regs_init(3);
1562
1563 if (hubp35_construct(hubp2, ctx, inst,
1564 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1565 return &hubp2->base;
1566
1567 BREAK_TO_DEBUGGER();
1568 kfree(hubp2);
1569 return NULL;
1570 }
1571
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1572 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1573 {
1574 dcn35_dwbc_set_fgcg(
1575 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1576 }
1577
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1578 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1579 {
1580 int i;
1581 uint32_t pipe_count = pool->res_cap->num_dwb;
1582
1583 for (i = 0; i < pipe_count; i++) {
1584 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1585 GFP_KERNEL);
1586
1587 if (!dwbc30) {
1588 dm_error("DC: failed to create dwbc30!\n");
1589 return false;
1590 }
1591
1592 #undef REG_STRUCT
1593 #define REG_STRUCT dwbc35_regs
1594 dwbc_regs_dcn3_init(0);
1595
1596 dcn35_dwbc_construct(dwbc30, ctx,
1597 &dwbc35_regs[i],
1598 &dwbc35_shift,
1599 &dwbc35_mask,
1600 i);
1601
1602 pool->dwbc[i] = &dwbc30->base;
1603
1604 dcn35_dwbc_init(dwbc30, ctx);
1605 }
1606 return true;
1607 }
1608
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1609 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1610 struct dc_context *ctx)
1611 {
1612 dcn35_mmhubbub_set_fgcg(
1613 mcif_wb30,
1614 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1615 }
1616
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1617 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1618 {
1619 int i;
1620 uint32_t pipe_count = pool->res_cap->num_dwb;
1621
1622 for (i = 0; i < pipe_count; i++) {
1623 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1624 GFP_KERNEL);
1625
1626 if (!mcif_wb30) {
1627 dm_error("DC: failed to create mcif_wb30!\n");
1628 return false;
1629 }
1630
1631 #undef REG_STRUCT
1632 #define REG_STRUCT mcif_wb35_regs
1633 mcif_wb_regs_dcn3_init(0);
1634
1635 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1636 &mcif_wb35_regs[i],
1637 &mcif_wb35_shift,
1638 &mcif_wb35_mask,
1639 i);
1640
1641 dcn35_mmhubbub_init(mcif_wb30, ctx);
1642
1643 pool->mcif_wb[i] = &mcif_wb30->base;
1644 }
1645 return true;
1646 }
1647
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1648 static struct display_stream_compressor *dcn35_dsc_create(
1649 struct dc_context *ctx, uint32_t inst)
1650 {
1651 struct dcn20_dsc *dsc =
1652 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1653
1654 if (!dsc) {
1655 BREAK_TO_DEBUGGER();
1656 return NULL;
1657 }
1658
1659 #undef REG_STRUCT
1660 #define REG_STRUCT dsc_regs
1661 dsc_regsDCN35_init(0),
1662 dsc_regsDCN35_init(1),
1663 dsc_regsDCN35_init(2),
1664 dsc_regsDCN35_init(3);
1665
1666 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1667 dsc35_set_fgcg(dsc,
1668 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1669 return &dsc->base;
1670 }
1671
dcn351_destroy_resource_pool(struct resource_pool ** pool)1672 static void dcn351_destroy_resource_pool(struct resource_pool **pool)
1673 {
1674 struct dcn351_resource_pool *dcn351_pool = TO_DCN351_RES_POOL(*pool);
1675
1676 dcn351_resource_destruct(dcn351_pool);
1677 kfree(dcn351_pool);
1678 *pool = NULL;
1679 }
1680
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1681 static struct clock_source *dcn35_clock_source_create(
1682 struct dc_context *ctx,
1683 struct dc_bios *bios,
1684 enum clock_source_id id,
1685 const struct dce110_clk_src_regs *regs,
1686 bool dp_clk_src)
1687 {
1688 struct dce110_clk_src *clk_src =
1689 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1690
1691 if (!clk_src)
1692 return NULL;
1693
1694 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1695 regs, &cs_shift, &cs_mask)) {
1696 clk_src->base.dp_clk_src = dp_clk_src;
1697 return &clk_src->base;
1698 }
1699
1700 kfree(clk_src);
1701 BREAK_TO_DEBUGGER();
1702 return NULL;
1703 }
1704
1705 static struct dc_cap_funcs cap_funcs = {
1706 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1707 };
1708
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1709 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1710 {
1711 *panel_config = panel_config_defaults;
1712 }
1713
1714
dcn351_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1715 static bool dcn351_validate_bandwidth(struct dc *dc,
1716 struct dc_state *context,
1717 bool fast_validate)
1718 {
1719 bool out = false;
1720
1721 out = dml2_validate(dc, context,
1722 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1723 fast_validate);
1724
1725 if (fast_validate)
1726 return out;
1727
1728 DC_FP_START();
1729 dcn35_decide_zstate_support(dc, context);
1730 DC_FP_END();
1731
1732 return out;
1733 }
1734
1735 static struct resource_funcs dcn351_res_pool_funcs = {
1736 .destroy = dcn351_destroy_resource_pool,
1737 .link_enc_create = dcn35_link_encoder_create,
1738 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1739 .link_encs_assign = link_enc_cfg_link_encs_assign,
1740 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1741 .panel_cntl_create = dcn31_panel_cntl_create,
1742 .validate_bandwidth = dcn351_validate_bandwidth,
1743 .calculate_wm_and_dlg = NULL,
1744 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1745 .populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu,
1746 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1747 .release_pipe = dcn20_release_pipe,
1748 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1749 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1750 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1751 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1752 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1753 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1754 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1755 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1756 .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu,
1757 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1758 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1759 .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia,
1760 .get_det_buffer_size = dcn31_get_det_buffer_size,
1761 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
1762 };
1763
dcn351_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn351_resource_pool * pool)1764 static bool dcn351_resource_construct(
1765 uint8_t num_virtual_links,
1766 struct dc *dc,
1767 struct dcn351_resource_pool *pool)
1768 {
1769 int i;
1770 struct dc_context *ctx = dc->ctx;
1771 struct irq_service_init_data init_data;
1772
1773 #undef REG_STRUCT
1774 #define REG_STRUCT bios_regs
1775 bios_regs_init();
1776
1777 #undef REG_STRUCT
1778 #define REG_STRUCT clk_src_regs
1779 clk_src_regs_init(0, A),
1780 clk_src_regs_init(1, B),
1781 clk_src_regs_init(2, C),
1782 clk_src_regs_init(3, D),
1783 clk_src_regs_init(4, E);
1784
1785 #undef REG_STRUCT
1786 #define REG_STRUCT abm_regs
1787 abm_regs_init(0),
1788 abm_regs_init(1),
1789 abm_regs_init(2),
1790 abm_regs_init(3);
1791
1792 #undef REG_STRUCT
1793 #define REG_STRUCT dccg_regs
1794 dccg_regs_init();
1795
1796 ctx->dc_bios->regs = &bios_regs;
1797
1798 pool->base.res_cap = &res_cap_dcn351;
1799
1800 pool->base.funcs = &dcn351_res_pool_funcs;
1801
1802 /*************************************************
1803 * Resource + asic cap harcoding *
1804 *************************************************/
1805 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1806 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1807 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1808 dc->caps.max_downscale_ratio = 600;
1809 dc->caps.i2c_speed_in_khz = 100;
1810 dc->caps.i2c_speed_in_khz_hdcp = 100;
1811 dc->caps.max_cursor_size = 256;
1812 dc->caps.min_horizontal_blanking_period = 80;
1813 dc->caps.dmdata_alloc_size = 2048;
1814 dc->caps.max_slave_planes = 2;
1815 dc->caps.max_slave_yuv_planes = 2;
1816 dc->caps.max_slave_rgb_planes = 2;
1817 dc->caps.post_blend_color_processing = true;
1818 dc->caps.force_dp_tps4_for_cp2520 = true;
1819 if (dc->config.forceHBR2CP2520)
1820 dc->caps.force_dp_tps4_for_cp2520 = false;
1821 dc->caps.dp_hpo = true;
1822 dc->caps.dp_hdmi21_pcon_support = true;
1823
1824 dc->caps.edp_dsc_support = true;
1825 dc->caps.extended_aux_timeout_support = true;
1826 dc->caps.dmcub_support = true;
1827 dc->caps.is_apu = true;
1828 dc->caps.seamless_odm = true;
1829
1830 dc->caps.zstate_support = true;
1831 dc->caps.ips_support = true;
1832 dc->caps.max_v_total = (1 << 15) - 1;
1833 dc->caps.vtotal_limited_by_fp2 = true;
1834
1835 /* Color pipeline capabilities */
1836 dc->caps.color.dpp.dcn_arch = 1;
1837 dc->caps.color.dpp.input_lut_shared = 0;
1838 dc->caps.color.dpp.icsc = 1;
1839 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1840 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1841 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1842 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1843 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1844 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1845 dc->caps.color.dpp.post_csc = 1;
1846 dc->caps.color.dpp.gamma_corr = 1;
1847 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1848
1849 dc->caps.color.dpp.hw_3d_lut = 1;
1850 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
1851 // no OGAM ROM on DCN301
1852 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1853 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1854 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1855 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1856 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1857 dc->caps.color.dpp.ocsc = 0;
1858
1859 dc->caps.color.mpc.gamut_remap = 1;
1860 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1861 dc->caps.color.mpc.ogam_ram = 1;
1862 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1863 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1864 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1865 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1866 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1867 dc->caps.color.mpc.ocsc = 1;
1868
1869 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
1870 * to provide some margin.
1871 * It's expected for furture ASIC to have equal or higher value, in order to
1872 * have determinstic power improvement from generate to genration.
1873 * (i.e., we should not expect new ASIC generation with lower vmin rate)
1874 */
1875 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1876
1877 /* Use pipe context based otg sync logic */
1878 dc->config.use_pipe_ctx_sync_logic = true;
1879
1880 /* Use psp mailbox to enable assr */
1881 dc->config.use_assr_psp_message = true;
1882
1883 /* read VBIOS LTTPR caps */
1884 {
1885 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1886 enum bp_result bp_query_result;
1887 uint8_t is_vbios_lttpr_enable = 0;
1888
1889 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1890 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1891 }
1892
1893 /* interop bit is implicit */
1894 {
1895 dc->caps.vbios_lttpr_aware = true;
1896 }
1897 }
1898
1899 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1900 dc->debug = debug_defaults_drv;
1901
1902 /*HW default is to have all the FGCG enabled, SW no need to program them*/
1903 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
1904 // Init the vm_helper
1905 if (dc->vm_helper)
1906 vm_helper_init(dc->vm_helper, 16);
1907
1908 /*************************************************
1909 * Create resources *
1910 *************************************************/
1911
1912 /* Clock Sources for Pixel Clock*/
1913 pool->base.clock_sources[DCN351_CLK_SRC_PLL0] =
1914 dcn35_clock_source_create(ctx, ctx->dc_bios,
1915 CLOCK_SOURCE_COMBO_PHY_PLL0,
1916 &clk_src_regs[0], false);
1917 pool->base.clock_sources[DCN351_CLK_SRC_PLL1] =
1918 dcn35_clock_source_create(ctx, ctx->dc_bios,
1919 CLOCK_SOURCE_COMBO_PHY_PLL1,
1920 &clk_src_regs[1], false);
1921 pool->base.clock_sources[DCN351_CLK_SRC_PLL2] =
1922 dcn35_clock_source_create(ctx, ctx->dc_bios,
1923 CLOCK_SOURCE_COMBO_PHY_PLL2,
1924 &clk_src_regs[2], false);
1925 pool->base.clock_sources[DCN351_CLK_SRC_PLL3] =
1926 dcn35_clock_source_create(ctx, ctx->dc_bios,
1927 CLOCK_SOURCE_COMBO_PHY_PLL3,
1928 &clk_src_regs[3], false);
1929 pool->base.clock_sources[DCN351_CLK_SRC_PLL4] =
1930 dcn35_clock_source_create(ctx, ctx->dc_bios,
1931 CLOCK_SOURCE_COMBO_PHY_PLL4,
1932 &clk_src_regs[4], false);
1933
1934 pool->base.clk_src_count = DCN351_CLK_SRC_TOTAL;
1935
1936 /* todo: not reuse phy_pll registers */
1937 pool->base.dp_clock_source =
1938 dcn35_clock_source_create(ctx, ctx->dc_bios,
1939 CLOCK_SOURCE_ID_DP_DTO,
1940 &clk_src_regs[0], true);
1941
1942 for (i = 0; i < pool->base.clk_src_count; i++) {
1943 if (pool->base.clock_sources[i] == NULL) {
1944 dm_error("DC: failed to create clock sources!\n");
1945 BREAK_TO_DEBUGGER();
1946 goto create_fail;
1947 }
1948 }
1949 /*temp till dml2 fully work without dml1*/
1950 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
1951
1952 /* TODO: DCCG */
1953 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1954 if (pool->base.dccg == NULL) {
1955 dm_error("DC: failed to create dccg!\n");
1956 BREAK_TO_DEBUGGER();
1957 goto create_fail;
1958 }
1959
1960 #undef REG_STRUCT
1961 #define REG_STRUCT pg_cntl_regs
1962 pg_cntl_dcn35_regs_init();
1963
1964 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
1965 if (pool->base.pg_cntl == NULL) {
1966 dm_error("DC: failed to create power gate control!\n");
1967 BREAK_TO_DEBUGGER();
1968 goto create_fail;
1969 }
1970
1971 /* TODO: IRQ */
1972 init_data.ctx = dc->ctx;
1973 pool->base.irqs = dal_irq_service_dcn351_create(&init_data);
1974 if (!pool->base.irqs)
1975 goto create_fail;
1976
1977 /* HUBBUB */
1978 pool->base.hubbub = dcn35_hubbub_create(ctx);
1979 if (pool->base.hubbub == NULL) {
1980 BREAK_TO_DEBUGGER();
1981 dm_error("DC: failed to create hubbub!\n");
1982 goto create_fail;
1983 }
1984
1985 /* HUBPs, DPPs, OPPs and TGs */
1986 for (i = 0; i < pool->base.pipe_count; i++) {
1987 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
1988 if (pool->base.hubps[i] == NULL) {
1989 BREAK_TO_DEBUGGER();
1990 dm_error(
1991 "DC: failed to create hubps!\n");
1992 goto create_fail;
1993 }
1994
1995 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
1996 if (pool->base.dpps[i] == NULL) {
1997 BREAK_TO_DEBUGGER();
1998 dm_error(
1999 "DC: failed to create dpps!\n");
2000 goto create_fail;
2001 }
2002 }
2003
2004 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2005 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2006 if (pool->base.opps[i] == NULL) {
2007 BREAK_TO_DEBUGGER();
2008 dm_error(
2009 "DC: failed to create output pixel processor!\n");
2010 goto create_fail;
2011 }
2012 }
2013
2014 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2015 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2016 ctx, i);
2017 if (pool->base.timing_generators[i] == NULL) {
2018 BREAK_TO_DEBUGGER();
2019 dm_error("DC: failed to create tg!\n");
2020 goto create_fail;
2021 }
2022 }
2023 pool->base.timing_generator_count = i;
2024
2025 /* PSR */
2026 pool->base.psr = dmub_psr_create(ctx);
2027 if (pool->base.psr == NULL) {
2028 dm_error("DC: failed to create psr obj!\n");
2029 BREAK_TO_DEBUGGER();
2030 goto create_fail;
2031 }
2032
2033 /* Replay */
2034 pool->base.replay = dmub_replay_create(ctx);
2035 if (pool->base.replay == NULL) {
2036 dm_error("DC: failed to create replay obj!\n");
2037 BREAK_TO_DEBUGGER();
2038 goto create_fail;
2039 }
2040
2041 /* ABM */
2042 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2043 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2044 &abm_regs[i],
2045 &abm_shift,
2046 &abm_mask);
2047 if (pool->base.multiple_abms[i] == NULL) {
2048 dm_error("DC: failed to create abm for pipe %d!\n", i);
2049 BREAK_TO_DEBUGGER();
2050 goto create_fail;
2051 }
2052 }
2053
2054 /* MPC and DSC */
2055 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2056 if (pool->base.mpc == NULL) {
2057 BREAK_TO_DEBUGGER();
2058 dm_error("DC: failed to create mpc!\n");
2059 goto create_fail;
2060 }
2061
2062 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2063 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2064 if (pool->base.dscs[i] == NULL) {
2065 BREAK_TO_DEBUGGER();
2066 dm_error("DC: failed to create display stream compressor %d!\n", i);
2067 goto create_fail;
2068 }
2069 }
2070
2071 /* DWB and MMHUBBUB */
2072 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2073 BREAK_TO_DEBUGGER();
2074 dm_error("DC: failed to create dwbc!\n");
2075 goto create_fail;
2076 }
2077
2078 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2079 BREAK_TO_DEBUGGER();
2080 dm_error("DC: failed to create mcif_wb!\n");
2081 goto create_fail;
2082 }
2083
2084 /* AUX and I2C */
2085 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2086 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2087 if (pool->base.engines[i] == NULL) {
2088 BREAK_TO_DEBUGGER();
2089 dm_error(
2090 "DC:failed to create aux engine!!\n");
2091 goto create_fail;
2092 }
2093 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2094 if (pool->base.hw_i2cs[i] == NULL) {
2095 BREAK_TO_DEBUGGER();
2096 dm_error(
2097 "DC:failed to create hw i2c!!\n");
2098 goto create_fail;
2099 }
2100 pool->base.sw_i2cs[i] = NULL;
2101 }
2102
2103 /* DCN3.5 has 6 DPIA */
2104 pool->base.usb4_dpia_count = 4;
2105 if (dc->debug.dpia_debug.bits.disable_dpia)
2106 pool->base.usb4_dpia_count = 0;
2107
2108 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2109 if (!resource_construct(num_virtual_links, dc, &pool->base,
2110 &res_create_funcs))
2111 goto create_fail;
2112
2113 /* HW Sequencer and Plane caps */
2114 dcn351_hw_sequencer_construct(dc);
2115
2116 dc->caps.max_planes = pool->base.pipe_count;
2117
2118 for (i = 0; i < dc->caps.max_planes; ++i)
2119 dc->caps.planes[i] = plane_cap;
2120
2121 dc->cap_funcs = cap_funcs;
2122
2123
2124 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2125
2126 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2127 dc->dml2_options.use_native_pstate_optimization = true;
2128 dc->dml2_options.use_native_soc_bb_construction = true;
2129 dc->dml2_options.minimize_dispclk_using_odm = false;
2130 if (dc->config.EnableMinDispClkODM)
2131 dc->dml2_options.minimize_dispclk_using_odm = true;
2132 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2133
2134 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2135 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2136
2137 dc->dml2_options.max_segments_per_hubp = 24;
2138 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2139 dc->dml2_options.override_det_buffer_size_kbytes = true;
2140
2141 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2142 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2143
2144 return true;
2145
2146 create_fail:
2147
2148 dcn351_resource_destruct(pool);
2149
2150 return false;
2151 }
2152
dcn351_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2153 struct resource_pool *dcn351_create_resource_pool(
2154 const struct dc_init_data *init_data,
2155 struct dc *dc)
2156 {
2157 struct dcn351_resource_pool *pool =
2158 kzalloc(sizeof(struct dcn351_resource_pool), GFP_KERNEL);
2159
2160 if (!pool)
2161 return NULL;
2162
2163 if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
2164 return &pool->base;
2165
2166 BREAK_TO_DEBUGGER();
2167 kfree(pool);
2168 return NULL;
2169 }
2170