1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dc_types.h"
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn32/dcn32_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dcn32_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn30/dcn30_hubbub.h"
42 #include "dcn31/dcn31_hubbub.h"
43 #include "dcn32/dcn32_hubbub.h"
44 #include "dcn32/dcn32_mpc.h"
45 #include "dcn32/dcn32_hubp.h"
46 #include "irq/dcn32/irq_service_dcn32.h"
47 #include "dcn32/dcn32_dpp.h"
48 #include "dcn32/dcn32_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn32/dcn32_dio_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
59 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
60 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
61 #include "dcn31/dcn31_apg.h"
62 #include "dcn31/dcn31_dio_link_encoder.h"
63 #include "dcn32/dcn32_dio_link_encoder.h"
64 #include "dce/dce_clock_source.h"
65 #include "dce/dce_audio.h"
66 #include "dce/dce_hwseq.h"
67 #include "clk_mgr.h"
68 #include "dio/virtual/virtual_stream_encoder.h"
69 #include "dio/dcn10/dcn10_dio.h"
70 #include "dml/display_mode_vba.h"
71 #include "dcn32/dcn32_dccg.h"
72 #include "dcn10/dcn10_resource.h"
73 #include "link_service.h"
74 #include "dcn31/dcn31_panel_cntl.h"
75
76 #include "dcn30/dcn30_dwb.h"
77 #include "dcn32/dcn32_mmhubbub.h"
78
79 #include "dcn/dcn_3_2_0_offset.h"
80 #include "dcn/dcn_3_2_0_sh_mask.h"
81 #include "nbio/nbio_4_3_0_offset.h"
82
83 #include "reg_helper.h"
84 #include "dce/dmub_abm.h"
85 #include "dce/dmub_psr.h"
86 #include "dce/dce_aux.h"
87 #include "dce/dce_i2c.h"
88
89 #include "dml/dcn30/display_mode_vba_30.h"
90 #include "vm_helper.h"
91 #include "dcn20/dcn20_vmid.h"
92 #include "dml/dcn32/dcn32_fpu.h"
93
94 #include "dc_state_priv.h"
95 #include "dc_fpu.h"
96
97 #include "dml2_0/dml2_wrapper.h"
98
99 #if !defined(DC_RUN_WITH_PREEMPTION_ENABLED)
100 #define DC_RUN_WITH_PREEMPTION_ENABLED(code) code
101 #endif
102
103 #define DC_LOGGER_INIT(logger)
104
105 enum dcn32_clk_src_array_id {
106 DCN32_CLK_SRC_PLL0,
107 DCN32_CLK_SRC_PLL1,
108 DCN32_CLK_SRC_PLL2,
109 DCN32_CLK_SRC_PLL3,
110 DCN32_CLK_SRC_PLL4,
111 DCN32_CLK_SRC_TOTAL
112 };
113
114 /* begin *********************
115 * macros to expend register list macro defined in HW object header file
116 */
117
118 /* DCN */
119 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
120
121 #define BASE(seg) BASE_INNER(seg)
122
123 #define SR(reg_name)\
124 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
125 reg ## reg_name
126 #define SR_ARR(reg_name, id) \
127 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
128
129 #define SR_ARR_INIT(reg_name, id, value) \
130 REG_STRUCT[id].reg_name = value
131
132 #define SRI(reg_name, block, id)\
133 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI_ARR(reg_name, block, id)\
137 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SR_ARR_I2C(reg_name, id) \
141 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
142
143 #define SRI_ARR_I2C(reg_name, block, id)\
144 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
146
147 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
148 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRI2(reg_name, block, id)\
152 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
153 reg ## reg_name
154 #define SRI2_ARR(reg_name, block, id)\
155 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
156 reg ## reg_name
157
158 #define SRIR(var_name, reg_name, block, id)\
159 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 reg ## block ## id ## _ ## reg_name
161
162 #define SRII(reg_name, block, id)\
163 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 reg ## block ## id ## _ ## reg_name
165
166 #define SRII_ARR_2(reg_name, block, id, inst)\
167 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
168 reg ## block ## id ## _ ## reg_name
169
170 #define SRII_MPC_RMU(reg_name, block, id)\
171 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
172 reg ## block ## id ## _ ## reg_name
173
174 #define SRII_DWB(reg_name, temp_name, block, id)\
175 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## temp_name
177
178 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
179 .field_name = reg_name ## __ ## field_name ## post_fix
180
181 #define DCCG_SRII(reg_name, block, id)\
182 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 reg ## block ## id ## _ ## reg_name
184
185 #define VUPDATE_SRII(reg_name, block, id)\
186 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
187 reg ## reg_name ## _ ## block ## id
188
189 /* NBIO */
190 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
191
192 #define NBIO_BASE(seg) \
193 NBIO_BASE_INNER(seg)
194
195 #define NBIO_SR(reg_name)\
196 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
197 regBIF_BX0_ ## reg_name
198 #define NBIO_SR_ARR(reg_name, id)\
199 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
200 regBIF_BX0_ ## reg_name
201
202 #undef CTX
203 #define CTX ctx
204 #define REG(reg_name) \
205 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
206
207 static struct bios_registers bios_regs;
208
209 #define bios_regs_init() \
210 ( \
211 NBIO_SR(BIOS_SCRATCH_3),\
212 NBIO_SR(BIOS_SCRATCH_6)\
213 )
214
215 #define clk_src_regs_init(index, pllid)\
216 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
217
218 static struct dce110_clk_src_regs clk_src_regs[5];
219
220 static const struct dce110_clk_src_shift cs_shift = {
221 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
222 };
223
224 static const struct dce110_clk_src_mask cs_mask = {
225 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
226 };
227
228 #define abm_regs_init(id)\
229 ABM_DCN32_REG_LIST_RI(id)
230
231 static struct dce_abm_registers abm_regs[4];
232
233 static const struct dce_abm_shift abm_shift = {
234 ABM_MASK_SH_LIST_DCN32(__SHIFT)
235 };
236
237 static const struct dce_abm_mask abm_mask = {
238 ABM_MASK_SH_LIST_DCN32(_MASK)
239 };
240
241 #define audio_regs_init(id)\
242 AUD_COMMON_REG_LIST_RI(id)
243
244 static struct dce_audio_registers audio_regs[5];
245
246 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
247 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
248 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
249 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
250
251 static const struct dce_audio_shift audio_shift = {
252 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
253 };
254
255 static const struct dce_audio_mask audio_mask = {
256 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
257 };
258
259 #define vpg_regs_init(id)\
260 VPG_DCN3_REG_LIST_RI(id)
261
262 static struct dcn30_vpg_registers vpg_regs[10];
263
264 static const struct dcn30_vpg_shift vpg_shift = {
265 DCN3_VPG_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn30_vpg_mask vpg_mask = {
269 DCN3_VPG_MASK_SH_LIST(_MASK)
270 };
271
272 #define afmt_regs_init(id)\
273 AFMT_DCN3_REG_LIST_RI(id)
274
275 static struct dcn30_afmt_registers afmt_regs[6];
276
277 static const struct dcn30_afmt_shift afmt_shift = {
278 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dcn30_afmt_mask afmt_mask = {
282 DCN3_AFMT_MASK_SH_LIST(_MASK)
283 };
284
285 #define apg_regs_init(id)\
286 APG_DCN31_REG_LIST_RI(id)
287
288 static struct dcn31_apg_registers apg_regs[4];
289
290 static const struct dcn31_apg_shift apg_shift = {
291 DCN31_APG_MASK_SH_LIST(__SHIFT)
292 };
293
294 static const struct dcn31_apg_mask apg_mask = {
295 DCN31_APG_MASK_SH_LIST(_MASK)
296 };
297
298 #define stream_enc_regs_init(id)\
299 SE_DCN32_REG_LIST_RI(id)
300
301 static struct dcn10_stream_enc_registers stream_enc_regs[5];
302
303 static const struct dcn10_stream_encoder_shift se_shift = {
304 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
305 };
306
307 static const struct dcn10_stream_encoder_mask se_mask = {
308 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
309 };
310
311
312 #define aux_regs_init(id)\
313 DCN2_AUX_REG_LIST_RI(id)
314
315 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
316
317 #define hpd_regs_init(id)\
318 HPD_REG_LIST_RI(id)
319
320 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
321
322 #define link_regs_init(id, phyid)\
323 ( \
324 LE_DCN31_REG_LIST_RI(id), \
325 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
326 )
327 /*DPCS_DCN31_REG_LIST(id),*/ \
328
329 static struct dcn10_link_enc_registers link_enc_regs[5];
330
331 static const struct dcn10_link_enc_shift le_shift = {
332 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
333 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
334 };
335
336 static const struct dcn10_link_enc_mask le_mask = {
337 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
338 //DPCS_DCN31_MASK_SH_LIST(_MASK)
339 };
340
341 #define hpo_dp_stream_encoder_reg_init(id)\
342 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
343
344 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
345
346 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
347 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
348 };
349
350 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
351 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
352 };
353
354
355 #define hpo_dp_link_encoder_reg_init(id)\
356 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
357 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
358 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
359 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
360 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
361
362 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
363
364 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
365 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
366 };
367
368 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
369 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
370 };
371
372 #define dpp_regs_init(id)\
373 DPP_REG_LIST_DCN30_COMMON_RI(id)
374
375 static struct dcn3_dpp_registers dpp_regs[4];
376
377 static const struct dcn3_dpp_shift tf_shift = {
378 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
379 };
380
381 static const struct dcn3_dpp_mask tf_mask = {
382 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
383 };
384
385
386 #define opp_regs_init(id)\
387 OPP_REG_LIST_DCN30_RI(id)
388
389 static struct dcn20_opp_registers opp_regs[4];
390
391 static const struct dcn20_opp_shift opp_shift = {
392 OPP_MASK_SH_LIST_DCN20(__SHIFT)
393 };
394
395 static const struct dcn20_opp_mask opp_mask = {
396 OPP_MASK_SH_LIST_DCN20(_MASK)
397 };
398
399 #define aux_engine_regs_init(id)\
400 ( \
401 AUX_COMMON_REG_LIST0_RI(id), \
402 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
403 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
404 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
405 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
406 )
407
408 static struct dce110_aux_registers aux_engine_regs[5];
409
410 static const struct dce110_aux_registers_shift aux_shift = {
411 DCN_AUX_MASK_SH_LIST(__SHIFT)
412 };
413
414 static const struct dce110_aux_registers_mask aux_mask = {
415 DCN_AUX_MASK_SH_LIST(_MASK)
416 };
417
418 #define dwbc_regs_dcn3_init(id)\
419 DWBC_COMMON_REG_LIST_DCN30_RI(id)
420
421 static struct dcn30_dwbc_registers dwbc30_regs[1];
422
423 static const struct dcn30_dwbc_shift dwbc30_shift = {
424 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
425 };
426
427 static const struct dcn30_dwbc_mask dwbc30_mask = {
428 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
429 };
430
431 #define mcif_wb_regs_dcn3_init(id)\
432 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
433
434 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
435
436 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
437 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
438 };
439
440 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
441 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
442 };
443
444 #define dsc_regsDCN20_init(id)\
445 DSC_REG_LIST_DCN20_RI(id)
446
447 static struct dcn20_dsc_registers dsc_regs[4];
448
449 static const struct dcn20_dsc_shift dsc_shift = {
450 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
451 };
452
453 static const struct dcn20_dsc_mask dsc_mask = {
454 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
455 };
456
457 static struct dcn30_mpc_registers mpc_regs;
458
459 #define dcn_mpc_regs_init() \
460 MPC_REG_LIST_DCN3_2_RI(0),\
461 MPC_REG_LIST_DCN3_2_RI(1),\
462 MPC_REG_LIST_DCN3_2_RI(2),\
463 MPC_REG_LIST_DCN3_2_RI(3),\
464 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
465 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
466 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
467 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
468 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
469
470 static const struct dcn30_mpc_shift mpc_shift = {
471 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
472 };
473
474 static const struct dcn30_mpc_mask mpc_mask = {
475 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
476 };
477
478 #define optc_regs_init(id)\
479 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
480
481 static struct dcn_optc_registers optc_regs[4];
482
483 static const struct dcn_optc_shift optc_shift = {
484 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
485 };
486
487 static const struct dcn_optc_mask optc_mask = {
488 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
489 };
490
491 #define hubp_regs_init(id)\
492 HUBP_REG_LIST_DCN32_RI(id)
493
494 static struct dcn_hubp2_registers hubp_regs[4];
495
496
497 static const struct dcn_hubp2_shift hubp_shift = {
498 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
499 };
500
501 static const struct dcn_hubp2_mask hubp_mask = {
502 HUBP_MASK_SH_LIST_DCN32(_MASK)
503 };
504
505 static struct dcn_hubbub_registers hubbub_reg;
506 #define hubbub_reg_init()\
507 HUBBUB_REG_LIST_DCN32_RI(0)
508
509 static const struct dcn_hubbub_shift hubbub_shift = {
510 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
511 };
512
513 static const struct dcn_hubbub_mask hubbub_mask = {
514 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
515 };
516
517 static struct dccg_registers dccg_regs;
518
519 #define dccg_regs_init()\
520 DCCG_REG_LIST_DCN32_RI()
521
522 static const struct dccg_shift dccg_shift = {
523 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
524 };
525
526 static const struct dccg_mask dccg_mask = {
527 DCCG_MASK_SH_LIST_DCN32(_MASK)
528 };
529
530
531 #define SRII2(reg_name_pre, reg_name_post, id)\
532 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
533 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
534 reg ## reg_name_pre ## id ## _ ## reg_name_post
535
536
537 #define HWSEQ_DCN32_REG_LIST()\
538 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
539 SR(DIO_MEM_PWR_CTRL), \
540 SR(ODM_MEM_PWR_CTRL3), \
541 SR(MMHUBBUB_MEM_PWR_CNTL), \
542 SR(DCCG_GATE_DISABLE_CNTL), \
543 SR(DCCG_GATE_DISABLE_CNTL2), \
544 SR(DCFCLK_CNTL),\
545 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
546 SRII(PIXEL_RATE_CNTL, OTG, 0), \
547 SRII(PIXEL_RATE_CNTL, OTG, 1),\
548 SRII(PIXEL_RATE_CNTL, OTG, 2),\
549 SRII(PIXEL_RATE_CNTL, OTG, 3),\
550 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
551 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
552 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
553 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
554 SR(MICROSECOND_TIME_BASE_DIV), \
555 SR(MILLISECOND_TIME_BASE_DIV), \
556 SR(DISPCLK_FREQ_CHANGE_CNTL), \
557 SR(RBBMIF_TIMEOUT_DIS), \
558 SR(RBBMIF_TIMEOUT_DIS_2), \
559 SR(DCHUBBUB_CRC_CTRL), \
560 SR(DPP_TOP0_DPP_CRC_CTRL), \
561 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
562 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
563 SR(MPC_CRC_CTRL), \
564 SR(MPC_CRC_RESULT_GB), \
565 SR(MPC_CRC_RESULT_C), \
566 SR(MPC_CRC_RESULT_AR), \
567 SR(DOMAIN0_PG_CONFIG), \
568 SR(DOMAIN1_PG_CONFIG), \
569 SR(DOMAIN2_PG_CONFIG), \
570 SR(DOMAIN3_PG_CONFIG), \
571 SR(DOMAIN16_PG_CONFIG), \
572 SR(DOMAIN17_PG_CONFIG), \
573 SR(DOMAIN18_PG_CONFIG), \
574 SR(DOMAIN19_PG_CONFIG), \
575 SR(DOMAIN0_PG_STATUS), \
576 SR(DOMAIN1_PG_STATUS), \
577 SR(DOMAIN2_PG_STATUS), \
578 SR(DOMAIN3_PG_STATUS), \
579 SR(DOMAIN16_PG_STATUS), \
580 SR(DOMAIN17_PG_STATUS), \
581 SR(DOMAIN18_PG_STATUS), \
582 SR(DOMAIN19_PG_STATUS), \
583 SR(D1VGA_CONTROL), \
584 SR(D2VGA_CONTROL), \
585 SR(D3VGA_CONTROL), \
586 SR(D4VGA_CONTROL), \
587 SR(D5VGA_CONTROL), \
588 SR(D6VGA_CONTROL), \
589 SR(DC_IP_REQUEST_CNTL), \
590 SR(AZALIA_AUDIO_DTO), \
591 SR(AZALIA_CONTROLLER_CLOCK_GATING)
592
593 static struct dce_hwseq_registers hwseq_reg;
594
595 #define hwseq_reg_init()\
596 HWSEQ_DCN32_REG_LIST()
597
598 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
599 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
600 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
601 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
602 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
603 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
604 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
605 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
606 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
607 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
608 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
609 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
610 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
611 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
612 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
613 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
614 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
615 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
616 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
617 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
618 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
619 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
620 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
621 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
622 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
623 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
624 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
625 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
626 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
627 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
628 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
629 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
630 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
631
632 static const struct dce_hwseq_shift hwseq_shift = {
633 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
634 };
635
636 static const struct dce_hwseq_mask hwseq_mask = {
637 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
638 };
639 #define vmid_regs_init(id)\
640 DCN20_VMID_REG_LIST_RI(id)
641
642 static struct dcn_vmid_registers vmid_regs[16];
643
644 static const struct dcn20_vmid_shift vmid_shifts = {
645 DCN20_VMID_MASK_SH_LIST(__SHIFT)
646 };
647
648 static const struct dcn20_vmid_mask vmid_masks = {
649 DCN20_VMID_MASK_SH_LIST(_MASK)
650 };
651
652 static struct dcn_dio_registers dio_regs;
653
654 #define DIO_MASK_SH_LIST(mask_sh)\
655 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
656
657 static const struct dcn_dio_shift dio_shift = {
658 DIO_MASK_SH_LIST(__SHIFT)
659 };
660
661 static const struct dcn_dio_mask dio_mask = {
662 DIO_MASK_SH_LIST(_MASK)
663 };
664
665 static const struct resource_caps res_cap_dcn32 = {
666 .num_timing_generator = 4,
667 .num_opp = 4,
668 .num_video_plane = 4,
669 .num_audio = 5,
670 .num_stream_encoder = 5,
671 .num_hpo_dp_stream_encoder = 4,
672 .num_hpo_dp_link_encoder = 2,
673 .num_pll = 5,
674 .num_dwb = 1,
675 .num_ddc = 5,
676 .num_vmid = 16,
677 .num_mpc_3dlut = 4,
678 .num_dsc = 4,
679 };
680
681 static const struct dc_plane_cap plane_cap = {
682 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
683 .per_pixel_alpha = true,
684
685 .pixel_format_support = {
686 .argb8888 = true,
687 .nv12 = true,
688 .fp16 = true,
689 .p010 = true,
690 .ayuv = false,
691 },
692
693 .max_upscale_factor = {
694 .argb8888 = 16000,
695 .nv12 = 16000,
696 .fp16 = 16000
697 },
698
699 // 6:1 downscaling ratio: 1000/6 = 166.666
700 .max_downscale_factor = {
701 .argb8888 = 167,
702 .nv12 = 167,
703 .fp16 = 167
704 },
705 64,
706 64
707 };
708
709 static const struct dc_debug_options debug_defaults_drv = {
710 .disable_dmcu = true,
711 .force_abm_enable = false,
712 .clock_trace = true,
713 .disable_pplib_clock_request = false,
714 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
715 .force_single_disp_pipe_split = false,
716 .disable_dcc = DCC_ENABLE,
717 .vsr_support = true,
718 .performance_trace = false,
719 .max_downscale_src_width = 7680,/*upto 8K*/
720 .disable_pplib_wm_range = false,
721 .scl_reset_length10 = true,
722 .sanity_checks = false,
723 .underflow_assert_delay_us = 0xFFFFFFFF,
724 .dwb_fi_phase = -1, // -1 = disable,
725 .dmub_command_table = true,
726 .enable_mem_low_power = {
727 .bits = {
728 .vga = false,
729 .i2c = false,
730 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
731 .dscl = false,
732 .cm = false,
733 .mpc = false,
734 .optc = true,
735 }
736 },
737 .use_max_lb = true,
738 .force_disable_subvp = false,
739 .exit_idle_opt_for_cursor_updates = true,
740 .using_dml2 = false,
741 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
742 .enable_single_display_2to1_odm_policy = true,
743
744 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
745 .enable_double_buffered_dsc_pg_support = true,
746 .enable_dp_dig_pixel_rate_div_policy = 1,
747 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
748 .alloc_extra_way_for_cursor = true,
749 .min_prefetch_in_strobe_ns = 60000, // 60us
750 .disable_unbounded_requesting = false,
751 .override_dispclk_programming = true,
752 .disable_fpo_optimizations = false,
753 .fpo_vactive_margin_us = 2000, // 2000us
754 .disable_fpo_vactive = false,
755 .disable_boot_optimizations = false,
756 .disable_subvp_high_refresh = false,
757 .disable_dp_plus_plus_wa = true,
758 .fpo_vactive_min_active_margin_us = 200,
759 .fpo_vactive_max_blank_us = 1000,
760 .disable_stutter_for_wm_program = true
761 };
762
763 static const struct dc_check_config config_defaults = {
764 .enable_legacy_fast_update = false,
765 };
766
dcn32_aux_engine_create(struct dc_context * ctx,uint32_t inst)767 static struct dce_aux *dcn32_aux_engine_create(
768 struct dc_context *ctx,
769 uint32_t inst)
770 {
771 struct aux_engine_dce110 *aux_engine =
772 kzalloc_obj(struct aux_engine_dce110);
773
774 if (!aux_engine)
775 return NULL;
776
777 #undef REG_STRUCT
778 #define REG_STRUCT aux_engine_regs
779 aux_engine_regs_init(0),
780 aux_engine_regs_init(1),
781 aux_engine_regs_init(2),
782 aux_engine_regs_init(3),
783 aux_engine_regs_init(4);
784
785 dce110_aux_engine_construct(aux_engine, ctx, inst,
786 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
787 &aux_engine_regs[inst],
788 &aux_mask,
789 &aux_shift,
790 ctx->dc->caps.extended_aux_timeout_support);
791
792 return &aux_engine->base;
793 }
794 #define i2c_inst_regs_init(id)\
795 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
796
797 static struct dce_i2c_registers i2c_hw_regs[5];
798
799 static const struct dce_i2c_shift i2c_shifts = {
800 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
801 };
802
803 static const struct dce_i2c_mask i2c_masks = {
804 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
805 };
806
dcn32_i2c_hw_create(struct dc_context * ctx,uint32_t inst)807 static struct dce_i2c_hw *dcn32_i2c_hw_create(
808 struct dc_context *ctx,
809 uint32_t inst)
810 {
811 struct dce_i2c_hw *dce_i2c_hw =
812 kzalloc_obj(struct dce_i2c_hw);
813
814 if (!dce_i2c_hw)
815 return NULL;
816
817 #undef REG_STRUCT
818 #define REG_STRUCT i2c_hw_regs
819 i2c_inst_regs_init(1),
820 i2c_inst_regs_init(2),
821 i2c_inst_regs_init(3),
822 i2c_inst_regs_init(4),
823 i2c_inst_regs_init(5);
824
825 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
826 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
827
828 return dce_i2c_hw;
829 }
830
dcn32_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)831 static struct clock_source *dcn32_clock_source_create(
832 struct dc_context *ctx,
833 struct dc_bios *bios,
834 enum clock_source_id id,
835 const struct dce110_clk_src_regs *regs,
836 bool dp_clk_src)
837 {
838 struct dce110_clk_src *clk_src =
839 kzalloc_obj(struct dce110_clk_src);
840
841 if (!clk_src)
842 return NULL;
843
844 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
845 regs, &cs_shift, &cs_mask)) {
846 clk_src->base.dp_clk_src = dp_clk_src;
847 return &clk_src->base;
848 }
849
850 kfree(clk_src);
851 BREAK_TO_DEBUGGER();
852 return NULL;
853 }
854
dcn32_dio_create(struct dc_context * ctx)855 static struct dio *dcn32_dio_create(struct dc_context *ctx)
856 {
857 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
858
859 if (!dio10)
860 return NULL;
861
862 #undef REG_STRUCT
863 #define REG_STRUCT dio_regs
864 DIO_REG_LIST_DCN10();
865
866 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
867
868 return &dio10->base;
869 }
870
dcn32_hubbub_create(struct dc_context * ctx)871 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
872 {
873 int i;
874
875 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
876
877 if (!hubbub2)
878 return NULL;
879
880 #undef REG_STRUCT
881 #define REG_STRUCT hubbub_reg
882 hubbub_reg_init();
883
884 #undef REG_STRUCT
885 #define REG_STRUCT vmid_regs
886 vmid_regs_init(0),
887 vmid_regs_init(1),
888 vmid_regs_init(2),
889 vmid_regs_init(3),
890 vmid_regs_init(4),
891 vmid_regs_init(5),
892 vmid_regs_init(6),
893 vmid_regs_init(7),
894 vmid_regs_init(8),
895 vmid_regs_init(9),
896 vmid_regs_init(10),
897 vmid_regs_init(11),
898 vmid_regs_init(12),
899 vmid_regs_init(13),
900 vmid_regs_init(14),
901 vmid_regs_init(15);
902
903 hubbub32_construct(hubbub2, ctx,
904 &hubbub_reg,
905 &hubbub_shift,
906 &hubbub_mask,
907 ctx->dc->dml.ip.det_buffer_size_kbytes,
908 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
909 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
910
911
912 for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
913 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
914
915 vmid->ctx = ctx;
916
917 vmid->regs = &vmid_regs[i];
918 vmid->shifts = &vmid_shifts;
919 vmid->masks = &vmid_masks;
920 }
921
922 return &hubbub2->base;
923 }
924
dcn32_hubp_create(struct dc_context * ctx,uint32_t inst)925 static struct hubp *dcn32_hubp_create(
926 struct dc_context *ctx,
927 uint32_t inst)
928 {
929 struct dcn20_hubp *hubp2 =
930 kzalloc_obj(struct dcn20_hubp);
931
932 if (!hubp2)
933 return NULL;
934
935 #undef REG_STRUCT
936 #define REG_STRUCT hubp_regs
937 hubp_regs_init(0),
938 hubp_regs_init(1),
939 hubp_regs_init(2),
940 hubp_regs_init(3);
941
942 if (hubp32_construct(hubp2, ctx, inst,
943 &hubp_regs[inst], &hubp_shift, &hubp_mask))
944 return &hubp2->base;
945
946 BREAK_TO_DEBUGGER();
947 kfree(hubp2);
948 return NULL;
949 }
950
dcn32_dpp_destroy(struct dpp ** dpp)951 static void dcn32_dpp_destroy(struct dpp **dpp)
952 {
953 kfree(TO_DCN30_DPP(*dpp));
954 *dpp = NULL;
955 }
956
dcn32_dpp_create(struct dc_context * ctx,uint32_t inst)957 static struct dpp *dcn32_dpp_create(
958 struct dc_context *ctx,
959 uint32_t inst)
960 {
961 struct dcn3_dpp *dpp3 =
962 kzalloc_obj(struct dcn3_dpp);
963
964 if (!dpp3)
965 return NULL;
966
967 #undef REG_STRUCT
968 #define REG_STRUCT dpp_regs
969 dpp_regs_init(0),
970 dpp_regs_init(1),
971 dpp_regs_init(2),
972 dpp_regs_init(3);
973
974 if (dpp32_construct(dpp3, ctx, inst,
975 &dpp_regs[inst], &tf_shift, &tf_mask))
976 return &dpp3->base;
977
978 BREAK_TO_DEBUGGER();
979 kfree(dpp3);
980 return NULL;
981 }
982
dcn32_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)983 static struct mpc *dcn32_mpc_create(
984 struct dc_context *ctx,
985 int num_mpcc,
986 int num_rmu)
987 {
988 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
989
990 if (!mpc30)
991 return NULL;
992
993 #undef REG_STRUCT
994 #define REG_STRUCT mpc_regs
995 dcn_mpc_regs_init();
996
997 dcn32_mpc_construct(mpc30, ctx,
998 &mpc_regs,
999 &mpc_shift,
1000 &mpc_mask,
1001 num_mpcc,
1002 num_rmu);
1003
1004 return &mpc30->base;
1005 }
1006
dcn32_opp_create(struct dc_context * ctx,uint32_t inst)1007 static struct output_pixel_processor *dcn32_opp_create(
1008 struct dc_context *ctx, uint32_t inst)
1009 {
1010 struct dcn20_opp *opp2 =
1011 kzalloc_obj(struct dcn20_opp);
1012
1013 if (!opp2) {
1014 BREAK_TO_DEBUGGER();
1015 return NULL;
1016 }
1017
1018 #undef REG_STRUCT
1019 #define REG_STRUCT opp_regs
1020 opp_regs_init(0),
1021 opp_regs_init(1),
1022 opp_regs_init(2),
1023 opp_regs_init(3);
1024
1025 dcn20_opp_construct(opp2, ctx, inst,
1026 &opp_regs[inst], &opp_shift, &opp_mask);
1027 return &opp2->base;
1028 }
1029
1030
dcn32_timing_generator_create(struct dc_context * ctx,uint32_t instance)1031 static struct timing_generator *dcn32_timing_generator_create(
1032 struct dc_context *ctx,
1033 uint32_t instance)
1034 {
1035 struct optc *tgn10 =
1036 kzalloc_obj(struct optc);
1037
1038 if (!tgn10)
1039 return NULL;
1040
1041 #undef REG_STRUCT
1042 #define REG_STRUCT optc_regs
1043 optc_regs_init(0),
1044 optc_regs_init(1),
1045 optc_regs_init(2),
1046 optc_regs_init(3);
1047
1048 tgn10->base.inst = instance;
1049 tgn10->base.ctx = ctx;
1050
1051 tgn10->tg_regs = &optc_regs[instance];
1052 tgn10->tg_shift = &optc_shift;
1053 tgn10->tg_mask = &optc_mask;
1054
1055 dcn32_timing_generator_init(tgn10);
1056
1057 return &tgn10->base;
1058 }
1059
1060 static const struct encoder_feature_support link_enc_feature = {
1061 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1062 .max_hdmi_pixel_clock = 600000,
1063 .hdmi_ycbcr420_supported = true,
1064 .dp_ycbcr420_supported = true,
1065 .fec_supported = true,
1066 .flags.bits.IS_HBR2_CAPABLE = true,
1067 .flags.bits.IS_HBR3_CAPABLE = true,
1068 .flags.bits.IS_TPS3_CAPABLE = true,
1069 .flags.bits.IS_TPS4_CAPABLE = true
1070 };
1071
dcn32_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1072 static struct link_encoder *dcn32_link_encoder_create(
1073 struct dc_context *ctx,
1074 const struct encoder_init_data *enc_init_data)
1075 {
1076 struct dcn20_link_encoder *enc20 =
1077 kzalloc_obj(struct dcn20_link_encoder);
1078
1079 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1080 return NULL;
1081
1082 #undef REG_STRUCT
1083 #define REG_STRUCT link_enc_aux_regs
1084 aux_regs_init(0),
1085 aux_regs_init(1),
1086 aux_regs_init(2),
1087 aux_regs_init(3),
1088 aux_regs_init(4);
1089
1090 #undef REG_STRUCT
1091 #define REG_STRUCT link_enc_hpd_regs
1092 hpd_regs_init(0),
1093 hpd_regs_init(1),
1094 hpd_regs_init(2),
1095 hpd_regs_init(3),
1096 hpd_regs_init(4);
1097
1098 #undef REG_STRUCT
1099 #define REG_STRUCT link_enc_regs
1100 link_regs_init(0, A),
1101 link_regs_init(1, B),
1102 link_regs_init(2, C),
1103 link_regs_init(3, D),
1104 link_regs_init(4, E);
1105
1106 dcn32_link_encoder_construct(enc20,
1107 enc_init_data,
1108 &link_enc_feature,
1109 &link_enc_regs[enc_init_data->transmitter],
1110 &link_enc_aux_regs[enc_init_data->channel - 1],
1111 &link_enc_hpd_regs[enc_init_data->hpd_source],
1112 &le_shift,
1113 &le_mask);
1114
1115 return &enc20->enc10.base;
1116 }
1117
dcn32_panel_cntl_create(const struct panel_cntl_init_data * init_data)1118 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1119 {
1120 struct dcn31_panel_cntl *panel_cntl =
1121 kzalloc_obj(struct dcn31_panel_cntl);
1122
1123 if (!panel_cntl)
1124 return NULL;
1125
1126 dcn31_panel_cntl_construct(panel_cntl, init_data);
1127
1128 return &panel_cntl->base;
1129 }
1130
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1131 static void read_dce_straps(
1132 struct dc_context *ctx,
1133 struct resource_straps *straps)
1134 {
1135 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1136 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1137
1138 }
1139
dcn32_create_audio(struct dc_context * ctx,unsigned int inst)1140 static struct audio *dcn32_create_audio(
1141 struct dc_context *ctx, unsigned int inst)
1142 {
1143
1144 #undef REG_STRUCT
1145 #define REG_STRUCT audio_regs
1146 audio_regs_init(0),
1147 audio_regs_init(1),
1148 audio_regs_init(2),
1149 audio_regs_init(3),
1150 audio_regs_init(4);
1151
1152 return dce_audio_create(ctx, inst,
1153 &audio_regs[inst], &audio_shift, &audio_mask);
1154 }
1155
dcn32_vpg_create(struct dc_context * ctx,uint32_t inst)1156 static struct vpg *dcn32_vpg_create(
1157 struct dc_context *ctx,
1158 uint32_t inst)
1159 {
1160 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
1161
1162 if (!vpg3)
1163 return NULL;
1164
1165 #undef REG_STRUCT
1166 #define REG_STRUCT vpg_regs
1167 vpg_regs_init(0),
1168 vpg_regs_init(1),
1169 vpg_regs_init(2),
1170 vpg_regs_init(3),
1171 vpg_regs_init(4),
1172 vpg_regs_init(5),
1173 vpg_regs_init(6),
1174 vpg_regs_init(7),
1175 vpg_regs_init(8),
1176 vpg_regs_init(9);
1177
1178 vpg3_construct(vpg3, ctx, inst,
1179 &vpg_regs[inst],
1180 &vpg_shift,
1181 &vpg_mask);
1182
1183 return &vpg3->base;
1184 }
1185
dcn32_afmt_create(struct dc_context * ctx,uint32_t inst)1186 static struct afmt *dcn32_afmt_create(
1187 struct dc_context *ctx,
1188 uint32_t inst)
1189 {
1190 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1191
1192 if (!afmt3)
1193 return NULL;
1194
1195 #undef REG_STRUCT
1196 #define REG_STRUCT afmt_regs
1197 afmt_regs_init(0),
1198 afmt_regs_init(1),
1199 afmt_regs_init(2),
1200 afmt_regs_init(3),
1201 afmt_regs_init(4),
1202 afmt_regs_init(5);
1203
1204 afmt3_construct(afmt3, ctx, inst,
1205 &afmt_regs[inst],
1206 &afmt_shift,
1207 &afmt_mask);
1208
1209 return &afmt3->base;
1210 }
1211
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1212 static struct apg *dcn31_apg_create(
1213 struct dc_context *ctx,
1214 uint32_t inst)
1215 {
1216 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1217
1218 if (!apg31)
1219 return NULL;
1220
1221 #undef REG_STRUCT
1222 #define REG_STRUCT apg_regs
1223 apg_regs_init(0),
1224 apg_regs_init(1),
1225 apg_regs_init(2),
1226 apg_regs_init(3);
1227
1228 apg31_construct(apg31, ctx, inst,
1229 &apg_regs[inst],
1230 &apg_shift,
1231 &apg_mask);
1232
1233 return &apg31->base;
1234 }
1235
dcn32_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1236 static struct stream_encoder *dcn32_stream_encoder_create(
1237 enum engine_id eng_id,
1238 struct dc_context *ctx)
1239 {
1240 struct dcn10_stream_encoder *enc1;
1241 struct vpg *vpg;
1242 struct afmt *afmt;
1243 int vpg_inst;
1244 int afmt_inst;
1245
1246 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1247 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1248 return NULL;
1249
1250 vpg_inst = eng_id;
1251 afmt_inst = eng_id;
1252
1253 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1254 vpg = dcn32_vpg_create(ctx, vpg_inst);
1255 afmt = dcn32_afmt_create(ctx, afmt_inst);
1256
1257 if (!enc1 || !vpg || !afmt) {
1258 kfree(enc1);
1259 kfree(vpg);
1260 kfree(afmt);
1261 return NULL;
1262 }
1263
1264 #undef REG_STRUCT
1265 #define REG_STRUCT stream_enc_regs
1266 stream_enc_regs_init(0),
1267 stream_enc_regs_init(1),
1268 stream_enc_regs_init(2),
1269 stream_enc_regs_init(3),
1270 stream_enc_regs_init(4);
1271
1272 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1273 eng_id, vpg, afmt,
1274 &stream_enc_regs[eng_id],
1275 &se_shift, &se_mask);
1276
1277 return &enc1->base;
1278 }
1279
dcn32_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1280 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1281 enum engine_id eng_id,
1282 struct dc_context *ctx)
1283 {
1284 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1285 struct vpg *vpg;
1286 struct apg *apg;
1287 uint32_t hpo_dp_inst;
1288 uint32_t vpg_inst;
1289 uint32_t apg_inst;
1290
1291 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1292 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1293
1294 /* Mapping of VPG register blocks to HPO DP block instance:
1295 * VPG[6] -> HPO_DP[0]
1296 * VPG[7] -> HPO_DP[1]
1297 * VPG[8] -> HPO_DP[2]
1298 * VPG[9] -> HPO_DP[3]
1299 */
1300 vpg_inst = hpo_dp_inst + 6;
1301
1302 /* Mapping of APG register blocks to HPO DP block instance:
1303 * APG[0] -> HPO_DP[0]
1304 * APG[1] -> HPO_DP[1]
1305 * APG[2] -> HPO_DP[2]
1306 * APG[3] -> HPO_DP[3]
1307 */
1308 apg_inst = hpo_dp_inst;
1309
1310 /* allocate HPO stream encoder and create VPG sub-block */
1311 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1312 vpg = dcn32_vpg_create(ctx, vpg_inst);
1313 apg = dcn31_apg_create(ctx, apg_inst);
1314
1315 if (!hpo_dp_enc31 || !vpg || !apg) {
1316 kfree(hpo_dp_enc31);
1317 kfree(vpg);
1318 kfree(apg);
1319 return NULL;
1320 }
1321
1322 #undef REG_STRUCT
1323 #define REG_STRUCT hpo_dp_stream_enc_regs
1324 hpo_dp_stream_encoder_reg_init(0),
1325 hpo_dp_stream_encoder_reg_init(1),
1326 hpo_dp_stream_encoder_reg_init(2),
1327 hpo_dp_stream_encoder_reg_init(3);
1328
1329 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1330 hpo_dp_inst, eng_id, vpg, apg,
1331 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1332 &hpo_dp_se_shift, &hpo_dp_se_mask);
1333
1334 return &hpo_dp_enc31->base;
1335 }
1336
dcn32_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1337 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1338 uint8_t inst,
1339 struct dc_context *ctx)
1340 {
1341 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1342
1343 /* allocate HPO link encoder */
1344 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1345 if (!hpo_dp_enc31)
1346 return NULL; /* out of memory */
1347
1348 #undef REG_STRUCT
1349 #define REG_STRUCT hpo_dp_link_enc_regs
1350 hpo_dp_link_encoder_reg_init(0),
1351 hpo_dp_link_encoder_reg_init(1);
1352
1353 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1354 &hpo_dp_link_enc_regs[inst],
1355 &hpo_dp_le_shift, &hpo_dp_le_mask);
1356
1357 return &hpo_dp_enc31->base;
1358 }
1359
dcn32_hwseq_create(struct dc_context * ctx)1360 static struct dce_hwseq *dcn32_hwseq_create(
1361 struct dc_context *ctx)
1362 {
1363 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1364
1365 #undef REG_STRUCT
1366 #define REG_STRUCT hwseq_reg
1367 hwseq_reg_init();
1368
1369 if (hws) {
1370 hws->ctx = ctx;
1371 hws->regs = &hwseq_reg;
1372 hws->shifts = &hwseq_shift;
1373 hws->masks = &hwseq_mask;
1374 }
1375 return hws;
1376 }
1377 static const struct resource_create_funcs res_create_funcs = {
1378 .read_dce_straps = read_dce_straps,
1379 .create_audio = dcn32_create_audio,
1380 .create_stream_encoder = dcn32_stream_encoder_create,
1381 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1382 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1383 .create_hwseq = dcn32_hwseq_create,
1384 };
1385
dcn32_resource_destruct(struct dcn32_resource_pool * pool)1386 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1387 {
1388 unsigned int i;
1389
1390 for (i = 0; i < pool->base.stream_enc_count; i++) {
1391 if (pool->base.stream_enc[i] != NULL) {
1392 if (pool->base.stream_enc[i]->vpg != NULL) {
1393 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1394 pool->base.stream_enc[i]->vpg = NULL;
1395 }
1396 if (pool->base.stream_enc[i]->afmt != NULL) {
1397 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1398 pool->base.stream_enc[i]->afmt = NULL;
1399 }
1400 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1401 pool->base.stream_enc[i] = NULL;
1402 }
1403 }
1404
1405 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1406 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1407 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1408 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1409 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1410 }
1411 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1412 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1413 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1414 }
1415 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1416 pool->base.hpo_dp_stream_enc[i] = NULL;
1417 }
1418 }
1419
1420 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1421 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1422 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1423 pool->base.hpo_dp_link_enc[i] = NULL;
1424 }
1425 }
1426
1427 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1428 if (pool->base.dscs[i] != NULL)
1429 dcn20_dsc_destroy(&pool->base.dscs[i]);
1430 }
1431
1432 if (pool->base.mpc != NULL) {
1433 kfree(TO_DCN20_MPC(pool->base.mpc));
1434 pool->base.mpc = NULL;
1435 }
1436 if (pool->base.hubbub != NULL) {
1437 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1438 pool->base.hubbub = NULL;
1439 }
1440 for (i = 0; i < pool->base.pipe_count; i++) {
1441 if (pool->base.dpps[i] != NULL)
1442 dcn32_dpp_destroy(&pool->base.dpps[i]);
1443
1444 if (pool->base.ipps[i] != NULL)
1445 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1446
1447 if (pool->base.hubps[i] != NULL) {
1448 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1449 pool->base.hubps[i] = NULL;
1450 }
1451
1452 if (pool->base.irqs != NULL) {
1453 dal_irq_service_destroy(&pool->base.irqs);
1454 }
1455 }
1456
1457 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1458 if (pool->base.engines[i] != NULL)
1459 dce110_engine_destroy(&pool->base.engines[i]);
1460 if (pool->base.hw_i2cs[i] != NULL) {
1461 kfree(pool->base.hw_i2cs[i]);
1462 pool->base.hw_i2cs[i] = NULL;
1463 }
1464 if (pool->base.sw_i2cs[i] != NULL) {
1465 kfree(pool->base.sw_i2cs[i]);
1466 pool->base.sw_i2cs[i] = NULL;
1467 }
1468 }
1469
1470 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1471 if (pool->base.opps[i] != NULL)
1472 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1473 }
1474
1475 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1476 if (pool->base.timing_generators[i] != NULL) {
1477 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1478 pool->base.timing_generators[i] = NULL;
1479 }
1480 }
1481
1482 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1483 if (pool->base.dwbc[i] != NULL) {
1484 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1485 pool->base.dwbc[i] = NULL;
1486 }
1487 if (pool->base.mcif_wb[i] != NULL) {
1488 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1489 pool->base.mcif_wb[i] = NULL;
1490 }
1491 }
1492
1493 for (i = 0; i < pool->base.audio_count; i++) {
1494 if (pool->base.audios[i])
1495 dce_aud_destroy(&pool->base.audios[i]);
1496 }
1497
1498 for (i = 0; i < pool->base.clk_src_count; i++) {
1499 if (pool->base.clock_sources[i] != NULL) {
1500 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1501 pool->base.clock_sources[i] = NULL;
1502 }
1503 }
1504
1505 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1506 if (pool->base.mpc_lut[i] != NULL) {
1507 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1508 pool->base.mpc_lut[i] = NULL;
1509 }
1510 if (pool->base.mpc_shaper[i] != NULL) {
1511 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1512 pool->base.mpc_shaper[i] = NULL;
1513 }
1514 }
1515
1516 if (pool->base.dp_clock_source != NULL) {
1517 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1518 pool->base.dp_clock_source = NULL;
1519 }
1520
1521 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1522 if (pool->base.multiple_abms[i] != NULL)
1523 dce_abm_destroy(&pool->base.multiple_abms[i]);
1524 }
1525
1526 if (pool->base.psr != NULL)
1527 dmub_psr_destroy(&pool->base.psr);
1528
1529 if (pool->base.dccg != NULL)
1530 dcn_dccg_destroy(&pool->base.dccg);
1531
1532 if (pool->base.dio != NULL) {
1533 kfree(TO_DCN10_DIO(pool->base.dio));
1534 pool->base.dio = NULL;
1535 }
1536
1537 if (pool->base.oem_device != NULL) {
1538 struct dc *dc = pool->base.oem_device->ctx->dc;
1539
1540 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1541 }
1542 }
1543
1544
dcn32_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1545 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1546 {
1547 int i;
1548 uint32_t dwb_count = pool->res_cap->num_dwb;
1549
1550 for (i = 0; i < dwb_count; i++) {
1551 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1552
1553 if (!dwbc30) {
1554 dm_error("DC: failed to create dwbc30!\n");
1555 return false;
1556 }
1557
1558 #undef REG_STRUCT
1559 #define REG_STRUCT dwbc30_regs
1560 dwbc_regs_dcn3_init(0);
1561
1562 dcn30_dwbc_construct(dwbc30, ctx,
1563 &dwbc30_regs[i],
1564 &dwbc30_shift,
1565 &dwbc30_mask,
1566 i);
1567
1568 pool->dwbc[i] = &dwbc30->base;
1569 }
1570 return true;
1571 }
1572
dcn32_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1573 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1574 {
1575 int i;
1576 uint32_t dwb_count = pool->res_cap->num_dwb;
1577
1578 for (i = 0; i < dwb_count; i++) {
1579 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1580
1581 if (!mcif_wb30) {
1582 dm_error("DC: failed to create mcif_wb30!\n");
1583 return false;
1584 }
1585
1586 #undef REG_STRUCT
1587 #define REG_STRUCT mcif_wb30_regs
1588 mcif_wb_regs_dcn3_init(0);
1589
1590 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1591 &mcif_wb30_regs[i],
1592 &mcif_wb30_shift,
1593 &mcif_wb30_mask,
1594 i);
1595
1596 pool->mcif_wb[i] = &mcif_wb30->base;
1597 }
1598 return true;
1599 }
1600
dcn32_dsc_create(struct dc_context * ctx,uint32_t inst)1601 static struct display_stream_compressor *dcn32_dsc_create(
1602 struct dc_context *ctx, uint32_t inst)
1603 {
1604 struct dcn20_dsc *dsc =
1605 kzalloc_obj(struct dcn20_dsc);
1606
1607 if (!dsc) {
1608 BREAK_TO_DEBUGGER();
1609 return NULL;
1610 }
1611
1612 #undef REG_STRUCT
1613 #define REG_STRUCT dsc_regs
1614 dsc_regsDCN20_init(0),
1615 dsc_regsDCN20_init(1),
1616 dsc_regsDCN20_init(2),
1617 dsc_regsDCN20_init(3);
1618
1619 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1620
1621 dsc->max_image_width = 6016;
1622
1623 return &dsc->base;
1624 }
1625
dcn32_destroy_resource_pool(struct resource_pool ** pool)1626 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1627 {
1628 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1629
1630 dcn32_resource_destruct(dcn32_pool);
1631 kfree(dcn32_pool);
1632 *pool = NULL;
1633 }
1634
dcn32_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1635 bool dcn32_acquire_post_bldn_3dlut(
1636 struct resource_context *res_ctx,
1637 const struct resource_pool *pool,
1638 int mpcc_id,
1639 struct dc_3dlut **lut,
1640 struct dc_transfer_func **shaper)
1641 {
1642 bool ret = false;
1643
1644 ASSERT(*lut == NULL && *shaper == NULL);
1645 *lut = NULL;
1646 *shaper = NULL;
1647
1648 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1649 *lut = pool->mpc_lut[mpcc_id];
1650 *shaper = pool->mpc_shaper[mpcc_id];
1651 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1652 ret = true;
1653 }
1654 return ret;
1655 }
1656
dcn32_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1657 bool dcn32_release_post_bldn_3dlut(
1658 struct resource_context *res_ctx,
1659 const struct resource_pool *pool,
1660 struct dc_3dlut **lut,
1661 struct dc_transfer_func **shaper)
1662 {
1663 int i;
1664 bool ret = false;
1665
1666 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1667 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1668 res_ctx->is_mpc_3dlut_acquired[i] = false;
1669 pool->mpc_lut[i]->state.raw = 0;
1670 *lut = NULL;
1671 *shaper = NULL;
1672 ret = true;
1673 break;
1674 }
1675 }
1676 return ret;
1677 }
1678
dcn32_enable_phantom_plane(struct dc * dc,struct dc_state * context,struct dc_stream_state * phantom_stream,unsigned int dc_pipe_idx)1679 static void dcn32_enable_phantom_plane(struct dc *dc,
1680 struct dc_state *context,
1681 struct dc_stream_state *phantom_stream,
1682 unsigned int dc_pipe_idx)
1683 {
1684 struct dc_plane_state *phantom_plane = NULL;
1685 struct dc_plane_state *prev_phantom_plane = NULL;
1686 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1687
1688 while (curr_pipe) {
1689 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1690 phantom_plane = prev_phantom_plane;
1691 else
1692 DC_RUN_WITH_PREEMPTION_ENABLED(phantom_plane =
1693 dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state));
1694
1695 if (!phantom_plane)
1696 continue;
1697
1698 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1699 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1700 sizeof(phantom_plane->scaling_quality));
1701 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1702 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1703 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1704 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1705 sizeof(phantom_plane->plane_size));
1706 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1707 sizeof(phantom_plane->tiling_info));
1708 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1709 phantom_plane->format = curr_pipe->plane_state->format;
1710 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1711 phantom_plane->visible = curr_pipe->plane_state->visible;
1712
1713 /* Shadow pipe has small viewport. */
1714 phantom_plane->clip_rect.y = 0;
1715 phantom_plane->clip_rect.height = phantom_stream->src.height;
1716
1717 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);
1718
1719 curr_pipe = curr_pipe->bottom_pipe;
1720 prev_phantom_plane = phantom_plane;
1721 }
1722 }
1723
dcn32_enable_phantom_stream(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)1724 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1725 struct dc_state *context,
1726 display_e2e_pipe_params_st *pipes,
1727 unsigned int pipe_cnt,
1728 unsigned int dc_pipe_idx)
1729 {
1730 struct dc_stream_state *phantom_stream = NULL;
1731 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1732
1733 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);
1734 if (!phantom_stream)
1735 return phantom_stream;
1736
1737 /* stream has limited viewport and small timing */
1738 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1739 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1740 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1741 DC_FP_START();
1742 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1743 DC_FP_END();
1744
1745 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);
1746 return phantom_stream;
1747 }
1748
1749 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1750 * require a phantom pipe / stream
1751 */
dcn32_add_phantom_pipes(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int index)1752 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1753 display_e2e_pipe_params_st *pipes,
1754 unsigned int pipe_cnt,
1755 unsigned int index)
1756 {
1757 struct dc_stream_state *phantom_stream = NULL;
1758 unsigned int i;
1759
1760 // The index of the DC pipe passed into this function is guarenteed to
1761 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1762 // already have phantom pipe assigned, etc.) by previous checks.
1763 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1764 if (!phantom_stream)
1765 return;
1766
1767 dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1768
1769 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1770 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1771
1772 // Build scaling params for phantom pipes which were newly added.
1773 // We determine which phantom pipes were added by comparing with
1774 // the phantom stream.
1775 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1776 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
1777 pipe->stream->use_dynamic_meta = false;
1778 pipe->plane_state->flip_immediate = false;
1779 if (!resource_build_scaling_params(pipe)) {
1780 // Log / remove phantom pipes since failed to build scaling params
1781 }
1782 }
1783 }
1784 }
1785
dml1_validate(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1786 static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)
1787 {
1788 bool out = false;
1789
1790 BW_VAL_TRACE_SETUP();
1791
1792 int vlevel = 0;
1793 int pipe_cnt = 0;
1794 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1795 dc->res_pool->pipe_count);
1796
1797 /* To handle Freesync properly, setting FreeSync DML parameters
1798 * to its default state for the first stage of validation
1799 */
1800 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1801 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1802
1803 DC_LOGGER_INIT(dc->ctx->logger);
1804
1805 BW_VAL_TRACE_COUNT();
1806
1807 if (!pipes)
1808 goto validate_fail;
1809
1810 DC_FP_START();
1811 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);
1812 DC_FP_END();
1813
1814 if (pipe_cnt == 0)
1815 goto validate_out;
1816
1817 if (!out)
1818 goto validate_fail;
1819
1820 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1821
1822 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1823 BW_VAL_TRACE_SKIP(fast);
1824 goto validate_out;
1825 }
1826
1827 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1828
1829 DC_FP_START();
1830 dcn32_override_min_req_memclk(dc, context);
1831 DC_FP_END();
1832
1833 dcn32_override_min_req_dcfclk(dc, context);
1834
1835 BW_VAL_TRACE_END_WATERMARKS();
1836
1837 goto validate_out;
1838
1839 validate_fail:
1840 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1841 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1842
1843 BW_VAL_TRACE_SKIP(fail);
1844 out = false;
1845
1846 validate_out:
1847 kfree(pipes);
1848
1849 BW_VAL_TRACE_FINISH();
1850
1851 return out;
1852 }
1853
dcn32_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1854 enum dc_status dcn32_validate_bandwidth(struct dc *dc,
1855 struct dc_state *context,
1856 enum dc_validate_mode validate_mode)
1857 {
1858 unsigned int i;
1859 enum dc_status status;
1860 const struct dc_stream_state *stream;
1861
1862 /* reset cursor limitations on subvp */
1863 for (i = 0; i < context->stream_count; i++) {
1864 stream = context->streams[i];
1865
1866 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1867 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1868 }
1869 }
1870
1871 if (dc->debug.using_dml2)
1872 status = dml2_validate(dc, context,
1873 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1874 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1875 else
1876 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1877
1878 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1879 /* check new stream configuration still supports cursor if subvp used */
1880 for (i = 0; i < context->stream_count; i++) {
1881 stream = context->streams[i];
1882
1883 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1884 stream->cursor_position.enable &&
1885 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
1886 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
1887 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1888 status = DC_FAIL_HW_CURSOR_SUPPORT;
1889 }
1890 }
1891 }
1892
1893 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1894 /* attempt to validate again with subvp disabled due to cursor */
1895 if (dc->debug.using_dml2)
1896 status = dml2_validate(dc, context,
1897 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1898 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1899 else
1900 status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1901 }
1902
1903 return status;
1904 }
1905
dcn32_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1906 int dcn32_populate_dml_pipes_from_context(
1907 struct dc *dc, struct dc_state *context,
1908 display_e2e_pipe_params_st *pipes,
1909 enum dc_validate_mode validate_mode)
1910 {
1911 int i, pipe_cnt;
1912 struct resource_context *res_ctx = &context->res_ctx;
1913 struct pipe_ctx *pipe = NULL;
1914 bool subvp_in_use = false;
1915 struct dc_crtc_timing *timing;
1916 int subvp_main_pipe_index = -1;
1917 enum mall_stream_type mall_type;
1918 bool single_display_subvp = false;
1919 struct dc_stream_state *stream = NULL;
1920 int num_subvp_main = 0;
1921 int num_subvp_phantom = 0;
1922 int num_subvp_none = 0;
1923 int odm_slice_count;
1924
1925 dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1926
1927 /* For single display subvp, look for subvp main so if we have phantom
1928 * pipe, we can set odm policy to match main pipe
1929 */
1930 for (i = 0; i < context->stream_count; i++) {
1931 stream = context->streams[i];
1932 mall_type = dc_state_get_stream_subvp_type(context, stream);
1933 if (mall_type == SUBVP_MAIN)
1934 num_subvp_main++;
1935 else if (mall_type == SUBVP_PHANTOM)
1936 num_subvp_phantom++;
1937 else
1938 num_subvp_none++;
1939 }
1940 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0)
1941 single_display_subvp = true;
1942
1943 if (single_display_subvp) {
1944 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1945 pipe = &res_ctx->pipe_ctx[i];
1946 if (!res_ctx->pipe_ctx[i].stream)
1947 continue;
1948
1949 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1950 if (mall_type == SUBVP_MAIN) {
1951 if (resource_is_pipe_type(pipe, OTG_MASTER))
1952 subvp_main_pipe_index = i;
1953 }
1954 pipe_cnt++;
1955 }
1956 }
1957
1958 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1959
1960 if (!res_ctx->pipe_ctx[i].stream)
1961 continue;
1962 pipe = &res_ctx->pipe_ctx[i];
1963 timing = &pipe->stream->timing;
1964
1965 pipes[pipe_cnt].pipe.src.gpuvm = true;
1966 DC_FP_START();
1967 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1968 DC_FP_END();
1969 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1970 if (dc->config.enable_windowed_mpo_odm &&
1971 dc->debug.enable_single_display_2to1_odm_policy) {
1972 /* For single display subvp, if pipe is phantom pipe,
1973 * then copy odm policy from subvp main pipe
1974 */
1975 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1976 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) {
1977 if (subvp_main_pipe_index < 0) {
1978 odm_slice_count = -1;
1979 ASSERT(0);
1980 } else {
1981 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);
1982 }
1983 } else {
1984 odm_slice_count = resource_get_odm_slice_count(pipe);
1985 }
1986 switch (odm_slice_count) {
1987 case 2:
1988 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1989 break;
1990 case 4:
1991 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
1992 break;
1993 default:
1994 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1995 }
1996 } else {
1997 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1998 }
1999
2000 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
2001 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
2002 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
2003
2004 /* Only populate DML input with subvp info for full updates.
2005 * This is just a workaround -- needs a proper fix.
2006 */
2007 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
2008 switch (dc_state_get_pipe_subvp_type(context, pipe)) {
2009 case SUBVP_MAIN:
2010 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
2011 subvp_in_use = true;
2012 break;
2013 case SUBVP_PHANTOM:
2014 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
2015 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
2016 // Disallow unbounded req for SubVP according to DCHUB programming guide
2017 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
2018 break;
2019 case SUBVP_NONE:
2020 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
2021 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
2022 break;
2023 default:
2024 break;
2025 }
2026 }
2027
2028 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
2029 if (pipes[pipe_cnt].dout.dsc_enable) {
2030 switch (timing->display_color_depth) {
2031 case COLOR_DEPTH_888:
2032 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
2033 break;
2034 case COLOR_DEPTH_101010:
2035 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
2036 break;
2037 case COLOR_DEPTH_121212:
2038 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
2039 break;
2040 default:
2041 ASSERT(0);
2042 break;
2043 }
2044 }
2045
2046
2047 pipe_cnt++;
2048 }
2049
2050 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
2051 * the DET available for each pipe). Use the DET override input to maintain our driver
2052 * policy.
2053 */
2054 dcn32_set_det_allocations(dc, context, pipes);
2055
2056 // In general cases we want to keep the dram clock change requirement
2057 // (prefer configs that support MCLK switch). Only override to false
2058 // for SubVP
2059 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
2060 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
2061 else
2062 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
2063
2064 return pipe_cnt;
2065 }
2066
dcn32_calculate_mall_ways_from_bytes(const struct dc * dc,unsigned int total_size_in_mall_bytes)2067 unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)
2068 {
2069 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
2070
2071 if (total_size_in_mall_bytes == 0) {
2072 return 0;
2073 }
2074
2075 if (dc->caps.max_cab_allocation_bytes == 0) {
2076 return 0xffffffff;
2077 }
2078
2079 /* add 2 lines for worst case alignment */
2080 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
2081
2082 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
2083 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
2084 num_ways = cache_lines_used / lines_per_way;
2085 if (cache_lines_used % lines_per_way > 0)
2086 num_ways++;
2087
2088 return num_ways;
2089 }
2090
2091 static struct dc_cap_funcs cap_funcs = {
2092 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
2093 .get_subvp_en = dcn32_subvp_in_use,
2094 };
2095
dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2096 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
2097 display_e2e_pipe_params_st *pipes,
2098 int pipe_cnt,
2099 int vlevel)
2100 {
2101 DC_FP_START();
2102 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
2103 DC_FP_END();
2104 }
2105
dcn32_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2106 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2107 {
2108 DC_FP_START();
2109
2110 dcn32_update_bw_bounding_box_fpu(dc, bw_params);
2111
2112 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
2113 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
2114
2115 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
2116 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
2117
2118 DC_FP_END();
2119 }
2120
dcn32_get_max_hw_cursor_size(const struct dc * dc,struct dc_state * state,const struct dc_stream_state * stream)2121 unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
2122 struct dc_state *state,
2123 const struct dc_stream_state *stream)
2124 {
2125 bool limit_cur_to_buf;
2126
2127 limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) &&
2128 !stream->hw_cursor_req;
2129
2130 return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size;
2131 }
2132
2133 static struct resource_funcs dcn32_res_pool_funcs = {
2134 .destroy = dcn32_destroy_resource_pool,
2135 .link_enc_create = dcn32_link_encoder_create,
2136 .link_enc_create_minimal = NULL,
2137 .panel_cntl_create = dcn32_panel_cntl_create,
2138 .validate_bandwidth = dcn32_validate_bandwidth,
2139 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
2140 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
2141 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
2142 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
2143 .release_pipe = dcn20_release_pipe,
2144 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2145 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2146 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2147 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2148 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2149 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2150 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
2151 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
2152 .update_bw_bounding_box = dcn32_update_bw_bounding_box,
2153 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2154 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2155 .add_phantom_pipes = dcn32_add_phantom_pipes,
2156 .get_default_tiling_info = dcn10_get_default_tiling_info,
2157 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
2158 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
2159 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2160 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
2161 };
2162
read_pipe_fuses(struct dc_context * ctx)2163 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2164 {
2165 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2166 /* DCN32 support max 4 pipes */
2167 value = value & 0xf;
2168 return value;
2169 }
2170
2171
dcn32_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn32_resource_pool * pool)2172 static bool dcn32_resource_construct(
2173 uint8_t num_virtual_links,
2174 struct dc *dc,
2175 struct dcn32_resource_pool *pool)
2176 {
2177 int i, j;
2178 struct dc_context *ctx = dc->ctx;
2179 struct irq_service_init_data init_data;
2180 struct ddc_service_init_data ddc_init_data = {0};
2181 uint32_t pipe_fuses = 0;
2182 uint32_t num_pipes = 4;
2183
2184 #undef REG_STRUCT
2185 #define REG_STRUCT bios_regs
2186 bios_regs_init();
2187
2188 #undef REG_STRUCT
2189 #define REG_STRUCT clk_src_regs
2190 clk_src_regs_init(0, A),
2191 clk_src_regs_init(1, B),
2192 clk_src_regs_init(2, C),
2193 clk_src_regs_init(3, D),
2194 clk_src_regs_init(4, E);
2195
2196 #undef REG_STRUCT
2197 #define REG_STRUCT abm_regs
2198 abm_regs_init(0),
2199 abm_regs_init(1),
2200 abm_regs_init(2),
2201 abm_regs_init(3);
2202
2203 #undef REG_STRUCT
2204 #define REG_STRUCT dccg_regs
2205 dccg_regs_init();
2206
2207 ctx->dc_bios->regs = &bios_regs;
2208
2209 pool->base.res_cap = &res_cap_dcn32;
2210 /* max number of pipes for ASIC before checking for pipe fuses */
2211 num_pipes = pool->base.res_cap->num_timing_generator;
2212 pipe_fuses = read_pipe_fuses(ctx);
2213
2214 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2215 if (pipe_fuses & 1 << i)
2216 num_pipes--;
2217
2218 if (pipe_fuses & 1)
2219 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2220
2221 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2222 ASSERT(0); //Entire DCN is harvested!
2223
2224 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2225 * value will be changed, update max_num_dpp and max_num_otg for dml.
2226 */
2227 dcn3_2_ip.max_num_dpp = num_pipes;
2228 dcn3_2_ip.max_num_otg = num_pipes;
2229
2230 pool->base.funcs = &dcn32_res_pool_funcs;
2231
2232 /*************************************************
2233 * Resource + asic cap harcoding *
2234 *************************************************/
2235 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2236 pool->base.timing_generator_count = num_pipes;
2237 pool->base.pipe_count = num_pipes;
2238 pool->base.mpcc_count = num_pipes;
2239 dc->caps.max_downscale_ratio = 600;
2240 dc->caps.i2c_speed_in_khz = 100;
2241 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2242 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
2243 dc->caps.max_cursor_size = 64;
2244 /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */
2245 dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64
2246 dc->caps.min_horizontal_blanking_period = 80;
2247 dc->caps.dmdata_alloc_size = 2048;
2248 dc->caps.mall_size_per_mem_channel = 4;
2249 /* total size = mall per channel * num channels * 1024 * 1024 */
2250 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2251 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2252
2253 dc->caps.cache_line_size = 64;
2254 dc->caps.cache_num_ways = 16;
2255
2256 /* Calculate the available MALL space */
2257 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
2258 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2259 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2260 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2261
2262 dc->caps.subvp_fw_processing_delay_us = 15;
2263 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2264 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2265 dc->caps.subvp_swath_height_margin_lines = 16;
2266 dc->caps.subvp_pstate_allow_width_us = 20;
2267 dc->caps.subvp_vertical_int_margin_us = 30;
2268 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2269
2270 dc->caps.max_slave_planes = 2;
2271 dc->caps.max_slave_yuv_planes = 2;
2272 dc->caps.max_slave_rgb_planes = 2;
2273 dc->caps.post_blend_color_processing = true;
2274 dc->caps.force_dp_tps4_for_cp2520 = true;
2275 if (dc->config.forceHBR2CP2520)
2276 dc->caps.force_dp_tps4_for_cp2520 = false;
2277 dc->caps.dp_hpo = true;
2278 dc->caps.dp_hdmi21_pcon_support = true;
2279 dc->caps.edp_dsc_support = true;
2280 dc->caps.extended_aux_timeout_support = true;
2281 dc->caps.dmcub_support = true;
2282 dc->caps.seamless_odm = true;
2283 dc->caps.max_v_total = (1 << 15) - 1;
2284 dc->caps.vtotal_limited_by_fp2 = true;
2285
2286 /* Color pipeline capabilities */
2287 dc->caps.color.dpp.dcn_arch = 1;
2288 dc->caps.color.dpp.input_lut_shared = 0;
2289 dc->caps.color.dpp.icsc = 1;
2290 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2291 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2292 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2293 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2294 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2295 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2296 dc->caps.color.dpp.post_csc = 1;
2297 dc->caps.color.dpp.gamma_corr = 1;
2298 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2299
2300 dc->caps.color.dpp.hw_3d_lut = 0;
2301 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2302 // no OGAM ROM on DCN2 and later ASICs
2303 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2304 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2305 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2306 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2307 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2308 dc->caps.color.dpp.ocsc = 0;
2309
2310 dc->caps.color.mpc.gamut_remap = 1;
2311 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2312 dc->caps.color.mpc.ogam_ram = 1;
2313 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2314 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2315 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2316 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2317 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2318 dc->caps.color.mpc.ocsc = 1;
2319 dc->caps.color.mpc.preblend = true;
2320
2321 /* Use pipe context based otg sync logic */
2322 dc->config.use_pipe_ctx_sync_logic = true;
2323
2324 dc->config.dc_mode_clk_limit_support = true;
2325 dc->config.enable_windowed_mpo_odm = true;
2326 dc->config.disable_hbr_audio_dp2 = true;
2327 /* read VBIOS LTTPR caps */
2328 {
2329 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2330 enum bp_result bp_query_result;
2331 uint8_t is_vbios_lttpr_enable = 0;
2332
2333 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2334 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2335 }
2336
2337 /* interop bit is implicit */
2338 {
2339 dc->caps.vbios_lttpr_aware = true;
2340 }
2341 }
2342 dc->check_config = config_defaults;
2343
2344 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2345 dc->debug = debug_defaults_drv;
2346
2347 // Init the vm_helper
2348 if (dc->vm_helper)
2349 vm_helper_init(dc->vm_helper, 16);
2350
2351 /*************************************************
2352 * Create resources *
2353 *************************************************/
2354
2355 /* Clock Sources for Pixel Clock*/
2356 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2357 dcn32_clock_source_create(ctx, ctx->dc_bios,
2358 CLOCK_SOURCE_COMBO_PHY_PLL0,
2359 &clk_src_regs[0], false);
2360 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2361 dcn32_clock_source_create(ctx, ctx->dc_bios,
2362 CLOCK_SOURCE_COMBO_PHY_PLL1,
2363 &clk_src_regs[1], false);
2364 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2365 dcn32_clock_source_create(ctx, ctx->dc_bios,
2366 CLOCK_SOURCE_COMBO_PHY_PLL2,
2367 &clk_src_regs[2], false);
2368 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2369 dcn32_clock_source_create(ctx, ctx->dc_bios,
2370 CLOCK_SOURCE_COMBO_PHY_PLL3,
2371 &clk_src_regs[3], false);
2372 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2373 dcn32_clock_source_create(ctx, ctx->dc_bios,
2374 CLOCK_SOURCE_COMBO_PHY_PLL4,
2375 &clk_src_regs[4], false);
2376
2377 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2378
2379 /* todo: not reuse phy_pll registers */
2380 pool->base.dp_clock_source =
2381 dcn32_clock_source_create(ctx, ctx->dc_bios,
2382 CLOCK_SOURCE_ID_DP_DTO,
2383 &clk_src_regs[0], true);
2384
2385 for (i = 0; i < pool->base.clk_src_count; i++) {
2386 if (pool->base.clock_sources[i] == NULL) {
2387 dm_error("DC: failed to create clock sources!\n");
2388 BREAK_TO_DEBUGGER();
2389 goto create_fail;
2390 }
2391 }
2392
2393 /* DCCG */
2394 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2395 if (pool->base.dccg == NULL) {
2396 dm_error("DC: failed to create dccg!\n");
2397 BREAK_TO_DEBUGGER();
2398 goto create_fail;
2399 }
2400
2401 /* DML */
2402 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2403
2404 /* IRQ Service */
2405 init_data.ctx = dc->ctx;
2406 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2407 if (!pool->base.irqs)
2408 goto create_fail;
2409
2410 /* HUBBUB */
2411 pool->base.hubbub = dcn32_hubbub_create(ctx);
2412 if (pool->base.hubbub == NULL) {
2413 BREAK_TO_DEBUGGER();
2414 dm_error("DC: failed to create hubbub!\n");
2415 goto create_fail;
2416 }
2417
2418 /* DIO */
2419 pool->base.dio = dcn32_dio_create(ctx);
2420 if (pool->base.dio == NULL) {
2421 BREAK_TO_DEBUGGER();
2422 dm_error("DC: failed to create dio!\n");
2423 goto create_fail;
2424 }
2425
2426 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2427 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2428
2429 /* if pipe is disabled, skip instance of HW pipe,
2430 * i.e, skip ASIC register instance
2431 */
2432 if (pipe_fuses & 1 << i)
2433 continue;
2434
2435 /* HUBPs */
2436 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2437 if (pool->base.hubps[j] == NULL) {
2438 BREAK_TO_DEBUGGER();
2439 dm_error(
2440 "DC: failed to create hubps!\n");
2441 goto create_fail;
2442 }
2443
2444 /* DPPs */
2445 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2446 if (pool->base.dpps[j] == NULL) {
2447 BREAK_TO_DEBUGGER();
2448 dm_error(
2449 "DC: failed to create dpps!\n");
2450 goto create_fail;
2451 }
2452
2453 /* OPPs */
2454 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2455 if (pool->base.opps[j] == NULL) {
2456 BREAK_TO_DEBUGGER();
2457 dm_error(
2458 "DC: failed to create output pixel processor!\n");
2459 goto create_fail;
2460 }
2461
2462 /* TGs */
2463 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2464 ctx, i);
2465 if (pool->base.timing_generators[j] == NULL) {
2466 BREAK_TO_DEBUGGER();
2467 dm_error("DC: failed to create tg!\n");
2468 goto create_fail;
2469 }
2470
2471 /* ABMs */
2472 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2473 &abm_regs[i],
2474 &abm_shift,
2475 &abm_mask);
2476 if (pool->base.multiple_abms[j] == NULL) {
2477 dm_error("DC: failed to create abm for pipe %d!\n", i);
2478 BREAK_TO_DEBUGGER();
2479 goto create_fail;
2480 }
2481
2482 /* index for resource pool arrays for next valid pipe */
2483 j++;
2484 }
2485
2486 /* PSR */
2487 pool->base.psr = dmub_psr_create(ctx);
2488 if (pool->base.psr == NULL) {
2489 dm_error("DC: failed to create psr obj!\n");
2490 BREAK_TO_DEBUGGER();
2491 goto create_fail;
2492 }
2493
2494 /* MPCCs */
2495 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2496 if (pool->base.mpc == NULL) {
2497 BREAK_TO_DEBUGGER();
2498 dm_error("DC: failed to create mpc!\n");
2499 goto create_fail;
2500 }
2501
2502 /* DSCs */
2503 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2504 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2505 if (pool->base.dscs[i] == NULL) {
2506 BREAK_TO_DEBUGGER();
2507 dm_error("DC: failed to create display stream compressor %d!\n", i);
2508 goto create_fail;
2509 }
2510 }
2511
2512 /* DWB */
2513 if (!dcn32_dwbc_create(ctx, &pool->base)) {
2514 BREAK_TO_DEBUGGER();
2515 dm_error("DC: failed to create dwbc!\n");
2516 goto create_fail;
2517 }
2518
2519 /* MMHUBBUB */
2520 if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2521 BREAK_TO_DEBUGGER();
2522 dm_error("DC: failed to create mcif_wb!\n");
2523 goto create_fail;
2524 }
2525
2526 /* AUX and I2C */
2527 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2528 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2529 if (pool->base.engines[i] == NULL) {
2530 BREAK_TO_DEBUGGER();
2531 dm_error(
2532 "DC:failed to create aux engine!!\n");
2533 goto create_fail;
2534 }
2535 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2536 if (pool->base.hw_i2cs[i] == NULL) {
2537 BREAK_TO_DEBUGGER();
2538 dm_error(
2539 "DC:failed to create hw i2c!!\n");
2540 goto create_fail;
2541 }
2542 pool->base.sw_i2cs[i] = NULL;
2543 }
2544
2545 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2546 if (!resource_construct(num_virtual_links, dc, &pool->base,
2547 &res_create_funcs))
2548 goto create_fail;
2549
2550 /* HW Sequencer init functions and Plane caps */
2551 dcn32_hw_sequencer_init_functions(dc);
2552
2553 dc->caps.max_planes = pool->base.pipe_count;
2554
2555 for (i = 0; i < dc->caps.max_planes; ++i)
2556 dc->caps.planes[i] = plane_cap;
2557
2558 dc->caps.max_odm_combine_factor = 4;
2559
2560 dc->cap_funcs = cap_funcs;
2561
2562 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2563 ddc_init_data.ctx = dc->ctx;
2564 ddc_init_data.link = NULL;
2565 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2566 ddc_init_data.id.enum_id = 0;
2567 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2568 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2569 } else {
2570 pool->base.oem_device = NULL;
2571 }
2572
2573 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2574 dc->dml2_options.use_native_soc_bb_construction = true;
2575 dc->dml2_options.minimize_dispclk_using_odm = true;
2576
2577 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2578 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2579 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2580 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2581
2582 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2583 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2584 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2585 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2586
2587 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2588 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2589
2590 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2591 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2592 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2593 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2594 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2595 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2596 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2597
2598 dc->dml2_options.max_segments_per_hubp = 18;
2599 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2600 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2601
2602 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
2603 dc->config.sdpif_request_limit_words_per_umc = 16;
2604
2605 /* init DC limited DML2 options */
2606 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2607 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2608
2609 return true;
2610
2611 create_fail:
2612
2613 dcn32_resource_destruct(pool);
2614
2615 return false;
2616 }
2617
dcn32_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2618 struct resource_pool *dcn32_create_resource_pool(
2619 const struct dc_init_data *init_data,
2620 struct dc *dc)
2621 {
2622 struct dcn32_resource_pool *pool =
2623 kzalloc_obj(struct dcn32_resource_pool);
2624
2625 if (!pool)
2626 return NULL;
2627
2628 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
2629 return &pool->base;
2630
2631 BREAK_TO_DEBUGGER();
2632 kfree(pool);
2633 return NULL;
2634 }
2635
2636 /*
2637 * Find the most optimal free pipe from res_ctx, which could be used as a
2638 * secondary dpp pipe for input opp head pipe.
2639 *
2640 * a free pipe - a pipe in input res_ctx not yet used for any streams or
2641 * planes.
2642 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending
2643 * tree. This is typical used for rendering MPO planes or additional offset
2644 * areas in MPCC combine.
2645 *
2646 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe
2647 * -------------------------------------------------------------------------
2648 *
2649 * PROBLEM:
2650 *
2651 * 1. There is a hardware limitation that a secondary DPP pipe cannot be
2652 * transferred from one MPC blending tree to the other in a single frame.
2653 * Otherwise it could cause glitches on the screen.
2654 *
2655 * For instance, we cannot transition from state 1 to state 2 in one frame. This
2656 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to
2657 * PIPE2's MPC blending tree, which is not supported by hardware.
2658 * To support this transition we need to first remove PIPE1 from PIPE0's MPC
2659 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree
2660 * in the next frame. This is not optimal as it will delay the flip for two
2661 * frames.
2662 *
2663 * State 1:
2664 * PIPE0 -- secondary DPP pipe --> (PIPE1)
2665 * PIPE2 -- secondary DPP pipe --> NONE
2666 *
2667 * State 2:
2668 * PIPE0 -- secondary DPP pipe --> NONE
2669 * PIPE2 -- secondary DPP pipe --> (PIPE1)
2670 *
2671 * 2. We want to in general minimize the unnecessary changes in pipe topology.
2672 * If a pipe is already added in current blending tree and there are no changes
2673 * to plane topology, we don't want to swap it with another free pipe
2674 * unnecessarily in every update. Powering up and down a pipe would require a
2675 * full update which delays the flip for 1 frame. If we use the original pipe
2676 * we don't have to toggle its power. So we can flip faster.
2677 */
dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_opp_head)2678 int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2679 const struct resource_context *cur_res_ctx,
2680 struct resource_context *new_res_ctx,
2681 const struct resource_pool *pool,
2682 const struct pipe_ctx *new_opp_head)
2683 {
2684 const struct pipe_ctx *cur_opp_head;
2685 int free_pipe_idx;
2686
2687 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];
2688 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree(
2689 cur_res_ctx, new_res_ctx, cur_opp_head);
2690
2691 /* Up until here if we have not found a free secondary pipe, we will
2692 * need to wait for at least one frame to complete the transition
2693 * sequence.
2694 */
2695 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2696 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2697 cur_res_ctx, new_res_ctx, pool);
2698
2699 /* Up until here if we have not found a free secondary pipe, we will
2700 * need to wait for at least two frames to complete the transition
2701 * sequence. It really doesn't matter which pipe we decide take from
2702 * current enabled pipes. It won't save our frame time when we swap only
2703 * one pipe or more pipes.
2704 */
2705 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2706 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
2707 cur_res_ctx, new_res_ctx, pool);
2708
2709 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2710 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2711
2712 return free_pipe_idx;
2713 }
2714
find_idle_secondary_pipe_check_mpo(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)2715 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2716 struct resource_context *res_ctx,
2717 const struct resource_pool *pool,
2718 const struct pipe_ctx *primary_pipe)
2719 {
2720 int i;
2721 struct pipe_ctx *secondary_pipe = NULL;
2722 struct pipe_ctx *next_odm_mpo_pipe = NULL;
2723 int primary_index, preferred_pipe_idx;
2724 struct pipe_ctx *old_primary_pipe = NULL;
2725
2726 /*
2727 * Modified from find_idle_secondary_pipe
2728 * With windowed MPO and ODM, we want to avoid the case where we want a
2729 * free pipe for the left side but the free pipe is being used on the
2730 * right side.
2731 * Add check on current_state if the primary_pipe is the left side,
2732 * to check the right side ( primary_pipe->next_odm_pipe ) to see if
2733 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2734 * - If so, then don't use this pipe
2735 * EXCEPTION - 3 plane ( 2 MPO plane ) case
2736 * - in this case, the primary pipe has already gotten a free pipe for the
2737 * MPO window in the left
2738 * - when it tries to get a free pipe for the MPO window on the right,
2739 * it will see that it is already assigned to the right side
2740 * ( primary_pipe->next_odm_pipe ). But in this case, we want this
2741 * free pipe, since it will be for the right side. So add an
2742 * additional condition, that skipping the free pipe on the right only
2743 * applies if the primary pipe has no bottom pipe currently assigned
2744 */
2745 if (primary_pipe) {
2746 primary_index = primary_pipe->pipe_idx;
2747 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2748 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2749 && (!primary_pipe->bottom_pipe))
2750 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2751
2752 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2753 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2754 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2755 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2756 secondary_pipe->pipe_idx = preferred_pipe_idx;
2757 }
2758 }
2759
2760 /*
2761 * search backwards for the second pipe to keep pipe
2762 * assignment more consistent
2763 */
2764 if (!secondary_pipe)
2765 for (i = pool->pipe_count - 1; i >= 0; i--) {
2766 if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2767 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2768 secondary_pipe = &res_ctx->pipe_ctx[i];
2769 secondary_pipe->pipe_idx = i;
2770 break;
2771 }
2772 }
2773
2774 return secondary_pipe;
2775 }
2776
dcn32_acquire_idle_pipe_for_head_pipe_in_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream,const struct pipe_ctx * head_pipe)2777 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2778 struct dc_state *state,
2779 const struct resource_pool *pool,
2780 struct dc_stream_state *stream,
2781 const struct pipe_ctx *head_pipe)
2782 {
2783 struct resource_context *res_ctx = &state->res_ctx;
2784 struct pipe_ctx *idle_pipe, *pipe;
2785 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2786 int head_index;
2787
2788 if (!head_pipe) {
2789 ASSERT(0);
2790 return NULL;
2791 }
2792
2793 /*
2794 * Modified from dcn20_acquire_idle_pipe_for_layer
2795 * Check if head_pipe in old_context already has bottom_pipe allocated.
2796 * - If so, check if that pipe is available in the current context.
2797 * -- If so, reuse pipe from old_context
2798 */
2799 head_index = head_pipe->pipe_idx;
2800 pipe = &old_ctx->pipe_ctx[head_index];
2801 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2802 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2803 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
2804 } else {
2805 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2806 if (!idle_pipe)
2807 return NULL;
2808 }
2809
2810 idle_pipe->stream = head_pipe->stream;
2811 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2812 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2813
2814 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2815 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2816 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2817 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2818
2819 return idle_pipe;
2820 }
2821
find_optimal_free_pipe_as_secondary_opp_head(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_otg_master)2822 static int find_optimal_free_pipe_as_secondary_opp_head(
2823 const struct resource_context *cur_res_ctx,
2824 struct resource_context *new_res_ctx,
2825 const struct resource_pool *pool,
2826 const struct pipe_ctx *new_otg_master)
2827 {
2828 const struct pipe_ctx *cur_otg_master;
2829 int free_pipe_idx;
2830
2831 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
2832 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
2833 cur_res_ctx, new_res_ctx, cur_otg_master);
2834
2835 /* Up until here if we have not found a free secondary pipe, we will
2836 * need to wait for at least one frame to complete the transition
2837 * sequence.
2838 */
2839 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2840 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2841 cur_res_ctx, new_res_ctx, pool);
2842
2843 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2844 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2845
2846 return free_pipe_idx;
2847 }
2848
dcn32_acquire_free_pipe_as_secondary_dpp_pipe(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)2849 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
2850 const struct dc_state *cur_ctx,
2851 struct dc_state *new_ctx,
2852 const struct resource_pool *pool,
2853 const struct pipe_ctx *opp_head_pipe)
2854 {
2855
2856 int free_pipe_idx;
2857 struct pipe_ctx *free_pipe;
2858
2859 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
2860 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2861 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2862
2863 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2864 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2865 pool, opp_head_pipe);
2866 if (free_pipe_idx >= 0) {
2867 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2868 free_pipe->pipe_idx = free_pipe_idx;
2869 free_pipe->stream = opp_head_pipe->stream;
2870 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
2871 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
2872
2873 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
2874 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
2875 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
2876 free_pipe->plane_res.mpcc_inst =
2877 pool->dpps[free_pipe->pipe_idx]->inst;
2878 } else {
2879 ASSERT(opp_head_pipe);
2880 free_pipe = NULL;
2881 }
2882
2883 return free_pipe;
2884 }
2885
dcn32_acquire_free_pipe_as_secondary_opp_head(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * otg_master)2886 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
2887 const struct dc_state *cur_ctx,
2888 struct dc_state *new_ctx,
2889 const struct resource_pool *pool,
2890 const struct pipe_ctx *otg_master)
2891 {
2892 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
2893 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2894 pool, otg_master);
2895 struct pipe_ctx *free_pipe;
2896
2897 if (free_pipe_idx >= 0) {
2898 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2899 free_pipe->pipe_idx = free_pipe_idx;
2900 free_pipe->stream = otg_master->stream;
2901 free_pipe->stream_res.tg = otg_master->stream_res.tg;
2902 free_pipe->stream_res.dsc = NULL;
2903 free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
2904 free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
2905 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
2906 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
2907 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
2908 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
2909 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
2910 free_pipe->dsc_padding_params = otg_master->dsc_padding_params;
2911 if (free_pipe->stream->timing.flags.DSC == 1) {
2912 dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
2913 &new_ctx->res_ctx,
2914 &free_pipe->stream_res.dsc,
2915 free_pipe_idx);
2916 ASSERT(free_pipe->stream_res.dsc);
2917 if (free_pipe->stream_res.dsc == NULL) {
2918 memset(free_pipe, 0, sizeof(*free_pipe));
2919 free_pipe = NULL;
2920 }
2921 }
2922 } else {
2923 ASSERT(otg_master);
2924 free_pipe = NULL;
2925 }
2926
2927 return free_pipe;
2928 }
2929
dcn32_calc_num_avail_chans_for_mall(struct dc * dc,int num_chans)2930 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
2931 {
2932 /*
2933 * DCN32 and DCN321 SKUs may have different sizes for MALL
2934 * but we may not be able to access all the MALL space.
2935 * If the num_chans is power of 2, then we can access all
2936 * of the available MALL space. Otherwise, we can only
2937 * access:
2938 *
2939 * max_cab_size_in_bytes = total_cache_size_in_bytes *
2940 * ((2^floor(log2(num_chans)))/num_chans)
2941 *
2942 * Calculating the MALL sizes for all available SKUs, we
2943 * have come up with the follow simplified check.
2944 * - we have max_chans which provides the max MALL size.
2945 * Each chans supports 4MB of MALL so:
2946 *
2947 * total_cache_size_in_bytes = max_chans * 4 MB
2948 *
2949 * - we have avail_chans which shows the number of channels
2950 * we can use if we can't access the entire MALL space.
2951 * It is generally half of max_chans
2952 * - so we use the following checks:
2953 *
2954 * if (num_chans == max_chans), return max_chans
2955 * if (num_chans < max_chans), return avail_chans
2956 *
2957 * - exception is GC_11_0_0 where we can't access max_chans,
2958 * so we define max_avail_chans as the maximum available
2959 * MALL space
2960 *
2961 */
2962 int gc_11_0_0_max_chans = 48;
2963 int gc_11_0_0_max_avail_chans = 32;
2964 int gc_11_0_0_avail_chans = 16;
2965 int gc_11_0_3_max_chans = 16;
2966 int gc_11_0_3_avail_chans = 8;
2967 int gc_11_0_2_max_chans = 8;
2968 int gc_11_0_2_avail_chans = 4;
2969
2970 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {
2971 return (num_chans == gc_11_0_0_max_chans) ?
2972 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;
2973 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {
2974 return (num_chans == gc_11_0_2_max_chans) ?
2975 gc_11_0_2_max_chans : gc_11_0_2_avail_chans;
2976 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {
2977 return (num_chans == gc_11_0_3_max_chans) ?
2978 gc_11_0_3_max_chans : gc_11_0_3_avail_chans;
2979 }
2980 }
2981