1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn32/dcn32_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn32_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn30/dcn30_hubbub.h"
41 #include "dcn31/dcn31_hubbub.h"
42 #include "dcn32/dcn32_hubbub.h"
43 #include "dcn32/dcn32_mpc.h"
44 #include "dcn32/dcn32_hubp.h"
45 #include "irq/dcn32/irq_service_dcn32.h"
46 #include "dcn32/dcn32_dpp.h"
47 #include "dcn32/dcn32_optc.h"
48 #include "dcn20/dcn20_hwseq.h"
49 #include "dcn30/dcn30_hwseq.h"
50 #include "dce110/dce110_hwseq.h"
51 #include "dcn30/dcn30_opp.h"
52 #include "dcn20/dcn20_dsc.h"
53 #include "dcn30/dcn30_vpg.h"
54 #include "dcn30/dcn30_afmt.h"
55 #include "dcn30/dcn30_dio_stream_encoder.h"
56 #include "dcn32/dcn32_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
60 #include "dcn31/dcn31_apg.h"
61 #include "dcn31/dcn31_dio_link_encoder.h"
62 #include "dcn32/dcn32_dio_link_encoder.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dml/display_mode_vba.h"
69 #include "dcn32/dcn32_dccg.h"
70 #include "dcn10/dcn10_resource.h"
71 #include "link.h"
72 #include "dcn31/dcn31_panel_cntl.h"
73
74 #include "dcn30/dcn30_dwb.h"
75 #include "dcn32/dcn32_mmhubbub.h"
76
77 #include "dcn/dcn_3_2_0_offset.h"
78 #include "dcn/dcn_3_2_0_sh_mask.h"
79 #include "nbio/nbio_4_3_0_offset.h"
80
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dml/dcn32/dcn32_fpu.h"
91
92 #include "dc_state_priv.h"
93
94 #include "dml2/dml2_wrapper.h"
95
96 #define DC_LOGGER_INIT(logger)
97
98 enum dcn32_clk_src_array_id {
99 DCN32_CLK_SRC_PLL0,
100 DCN32_CLK_SRC_PLL1,
101 DCN32_CLK_SRC_PLL2,
102 DCN32_CLK_SRC_PLL3,
103 DCN32_CLK_SRC_PLL4,
104 DCN32_CLK_SRC_TOTAL
105 };
106
107 /* begin *********************
108 * macros to expend register list macro defined in HW object header file
109 */
110
111 /* DCN */
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
113
114 #define BASE(seg) BASE_INNER(seg)
115
116 #define SR(reg_name)\
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
121
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name = value
124
125 #define SRI(reg_name, block, id)\
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SRI_ARR(reg_name, block, id)\
130 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 reg ## block ## id ## _ ## reg_name
132
133 #define SR_ARR_I2C(reg_name, id) \
134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
135
136 #define SRI_ARR_I2C(reg_name, block, id)\
137 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
141 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRI2(reg_name, block, id)\
145 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
147 #define SRI2_ARR(reg_name, block, id)\
148 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 reg ## reg_name
150
151 #define SRIR(var_name, reg_name, block, id)\
152 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## reg_name
154
155 #define SRII(reg_name, block, id)\
156 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
158
159 #define SRII_ARR_2(reg_name, block, id, inst)\
160 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## reg_name
162
163 #define SRII_MPC_RMU(reg_name, block, id)\
164 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SRII_DWB(reg_name, temp_name, block, id)\
168 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## temp_name
170
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
172 .field_name = reg_name ## __ ## field_name ## post_fix
173
174 #define DCCG_SRII(reg_name, block, id)\
175 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## reg_name
177
178 #define VUPDATE_SRII(reg_name, block, id)\
179 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
180 reg ## reg_name ## _ ## block ## id
181
182 /* NBIO */
183 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
184
185 #define NBIO_BASE(seg) \
186 NBIO_BASE_INNER(seg)
187
188 #define NBIO_SR(reg_name)\
189 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
190 regBIF_BX0_ ## reg_name
191 #define NBIO_SR_ARR(reg_name, id)\
192 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
193 regBIF_BX0_ ## reg_name
194
195 #undef CTX
196 #define CTX ctx
197 #define REG(reg_name) \
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
199
200 static struct bios_registers bios_regs;
201
202 #define bios_regs_init() \
203 ( \
204 NBIO_SR(BIOS_SCRATCH_3),\
205 NBIO_SR(BIOS_SCRATCH_6)\
206 )
207
208 #define clk_src_regs_init(index, pllid)\
209 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
210
211 static struct dce110_clk_src_regs clk_src_regs[5];
212
213 static const struct dce110_clk_src_shift cs_shift = {
214 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
215 };
216
217 static const struct dce110_clk_src_mask cs_mask = {
218 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
219 };
220
221 #define abm_regs_init(id)\
222 ABM_DCN32_REG_LIST_RI(id)
223
224 static struct dce_abm_registers abm_regs[4];
225
226 static const struct dce_abm_shift abm_shift = {
227 ABM_MASK_SH_LIST_DCN32(__SHIFT)
228 };
229
230 static const struct dce_abm_mask abm_mask = {
231 ABM_MASK_SH_LIST_DCN32(_MASK)
232 };
233
234 #define audio_regs_init(id)\
235 AUD_COMMON_REG_LIST_RI(id)
236
237 static struct dce_audio_registers audio_regs[5];
238
239 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
242 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
243
244 static const struct dce_audio_shift audio_shift = {
245 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
246 };
247
248 static const struct dce_audio_mask audio_mask = {
249 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
250 };
251
252 #define vpg_regs_init(id)\
253 VPG_DCN3_REG_LIST_RI(id)
254
255 static struct dcn30_vpg_registers vpg_regs[10];
256
257 static const struct dcn30_vpg_shift vpg_shift = {
258 DCN3_VPG_MASK_SH_LIST(__SHIFT)
259 };
260
261 static const struct dcn30_vpg_mask vpg_mask = {
262 DCN3_VPG_MASK_SH_LIST(_MASK)
263 };
264
265 #define afmt_regs_init(id)\
266 AFMT_DCN3_REG_LIST_RI(id)
267
268 static struct dcn30_afmt_registers afmt_regs[6];
269
270 static const struct dcn30_afmt_shift afmt_shift = {
271 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
272 };
273
274 static const struct dcn30_afmt_mask afmt_mask = {
275 DCN3_AFMT_MASK_SH_LIST(_MASK)
276 };
277
278 #define apg_regs_init(id)\
279 APG_DCN31_REG_LIST_RI(id)
280
281 static struct dcn31_apg_registers apg_regs[4];
282
283 static const struct dcn31_apg_shift apg_shift = {
284 DCN31_APG_MASK_SH_LIST(__SHIFT)
285 };
286
287 static const struct dcn31_apg_mask apg_mask = {
288 DCN31_APG_MASK_SH_LIST(_MASK)
289 };
290
291 #define stream_enc_regs_init(id)\
292 SE_DCN32_REG_LIST_RI(id)
293
294 static struct dcn10_stream_enc_registers stream_enc_regs[5];
295
296 static const struct dcn10_stream_encoder_shift se_shift = {
297 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
298 };
299
300 static const struct dcn10_stream_encoder_mask se_mask = {
301 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
302 };
303
304
305 #define aux_regs_init(id)\
306 DCN2_AUX_REG_LIST_RI(id)
307
308 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
309
310 #define hpd_regs_init(id)\
311 HPD_REG_LIST_RI(id)
312
313 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
314
315 #define link_regs_init(id, phyid)\
316 ( \
317 LE_DCN31_REG_LIST_RI(id), \
318 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
319 )
320 /*DPCS_DCN31_REG_LIST(id),*/ \
321
322 static struct dcn10_link_enc_registers link_enc_regs[5];
323
324 static const struct dcn10_link_enc_shift le_shift = {
325 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
326 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
327 };
328
329 static const struct dcn10_link_enc_mask le_mask = {
330 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
331 //DPCS_DCN31_MASK_SH_LIST(_MASK)
332 };
333
334 #define hpo_dp_stream_encoder_reg_init(id)\
335 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
336
337 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
338
339 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
344 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
345 };
346
347
348 #define hpo_dp_link_encoder_reg_init(id)\
349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
354
355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
356
357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
362 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
363 };
364
365 #define dpp_regs_init(id)\
366 DPP_REG_LIST_DCN30_COMMON_RI(id)
367
368 static struct dcn3_dpp_registers dpp_regs[4];
369
370 static const struct dcn3_dpp_shift tf_shift = {
371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
372 };
373
374 static const struct dcn3_dpp_mask tf_mask = {
375 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
376 };
377
378
379 #define opp_regs_init(id)\
380 OPP_REG_LIST_DCN30_RI(id)
381
382 static struct dcn20_opp_registers opp_regs[4];
383
384 static const struct dcn20_opp_shift opp_shift = {
385 OPP_MASK_SH_LIST_DCN20(__SHIFT)
386 };
387
388 static const struct dcn20_opp_mask opp_mask = {
389 OPP_MASK_SH_LIST_DCN20(_MASK)
390 };
391
392 #define aux_engine_regs_init(id)\
393 ( \
394 AUX_COMMON_REG_LIST0_RI(id), \
395 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
399 )
400
401 static struct dce110_aux_registers aux_engine_regs[5];
402
403 static const struct dce110_aux_registers_shift aux_shift = {
404 DCN_AUX_MASK_SH_LIST(__SHIFT)
405 };
406
407 static const struct dce110_aux_registers_mask aux_mask = {
408 DCN_AUX_MASK_SH_LIST(_MASK)
409 };
410
411 #define dwbc_regs_dcn3_init(id)\
412 DWBC_COMMON_REG_LIST_DCN30_RI(id)
413
414 static struct dcn30_dwbc_registers dwbc30_regs[1];
415
416 static const struct dcn30_dwbc_shift dwbc30_shift = {
417 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
418 };
419
420 static const struct dcn30_dwbc_mask dwbc30_mask = {
421 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
422 };
423
424 #define mcif_wb_regs_dcn3_init(id)\
425 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
426
427 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
428
429 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
430 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
431 };
432
433 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
434 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
435 };
436
437 #define dsc_regsDCN20_init(id)\
438 DSC_REG_LIST_DCN20_RI(id)
439
440 static struct dcn20_dsc_registers dsc_regs[4];
441
442 static const struct dcn20_dsc_shift dsc_shift = {
443 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
444 };
445
446 static const struct dcn20_dsc_mask dsc_mask = {
447 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
448 };
449
450 static struct dcn30_mpc_registers mpc_regs;
451
452 #define dcn_mpc_regs_init() \
453 MPC_REG_LIST_DCN3_2_RI(0),\
454 MPC_REG_LIST_DCN3_2_RI(1),\
455 MPC_REG_LIST_DCN3_2_RI(2),\
456 MPC_REG_LIST_DCN3_2_RI(3),\
457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
460 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
461 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
462
463 static const struct dcn30_mpc_shift mpc_shift = {
464 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
465 };
466
467 static const struct dcn30_mpc_mask mpc_mask = {
468 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
469 };
470
471 #define optc_regs_init(id)\
472 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
473
474 static struct dcn_optc_registers optc_regs[4];
475
476 static const struct dcn_optc_shift optc_shift = {
477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
478 };
479
480 static const struct dcn_optc_mask optc_mask = {
481 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
482 };
483
484 #define hubp_regs_init(id)\
485 HUBP_REG_LIST_DCN32_RI(id)
486
487 static struct dcn_hubp2_registers hubp_regs[4];
488
489
490 static const struct dcn_hubp2_shift hubp_shift = {
491 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
492 };
493
494 static const struct dcn_hubp2_mask hubp_mask = {
495 HUBP_MASK_SH_LIST_DCN32(_MASK)
496 };
497
498 static struct dcn_hubbub_registers hubbub_reg;
499 #define hubbub_reg_init()\
500 HUBBUB_REG_LIST_DCN32_RI(0)
501
502 static const struct dcn_hubbub_shift hubbub_shift = {
503 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
504 };
505
506 static const struct dcn_hubbub_mask hubbub_mask = {
507 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
508 };
509
510 static struct dccg_registers dccg_regs;
511
512 #define dccg_regs_init()\
513 DCCG_REG_LIST_DCN32_RI()
514
515 static const struct dccg_shift dccg_shift = {
516 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
517 };
518
519 static const struct dccg_mask dccg_mask = {
520 DCCG_MASK_SH_LIST_DCN32(_MASK)
521 };
522
523
524 #define SRII2(reg_name_pre, reg_name_post, id)\
525 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
526 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
527 reg ## reg_name_pre ## id ## _ ## reg_name_post
528
529
530 #define HWSEQ_DCN32_REG_LIST()\
531 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
532 SR(DIO_MEM_PWR_CTRL), \
533 SR(ODM_MEM_PWR_CTRL3), \
534 SR(MMHUBBUB_MEM_PWR_CNTL), \
535 SR(DCCG_GATE_DISABLE_CNTL), \
536 SR(DCCG_GATE_DISABLE_CNTL2), \
537 SR(DCFCLK_CNTL),\
538 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
539 SRII(PIXEL_RATE_CNTL, OTG, 0), \
540 SRII(PIXEL_RATE_CNTL, OTG, 1),\
541 SRII(PIXEL_RATE_CNTL, OTG, 2),\
542 SRII(PIXEL_RATE_CNTL, OTG, 3),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
547 SR(MICROSECOND_TIME_BASE_DIV), \
548 SR(MILLISECOND_TIME_BASE_DIV), \
549 SR(DISPCLK_FREQ_CHANGE_CNTL), \
550 SR(RBBMIF_TIMEOUT_DIS), \
551 SR(RBBMIF_TIMEOUT_DIS_2), \
552 SR(DCHUBBUB_CRC_CTRL), \
553 SR(DPP_TOP0_DPP_CRC_CTRL), \
554 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
555 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
556 SR(MPC_CRC_CTRL), \
557 SR(MPC_CRC_RESULT_GB), \
558 SR(MPC_CRC_RESULT_C), \
559 SR(MPC_CRC_RESULT_AR), \
560 SR(DOMAIN0_PG_CONFIG), \
561 SR(DOMAIN1_PG_CONFIG), \
562 SR(DOMAIN2_PG_CONFIG), \
563 SR(DOMAIN3_PG_CONFIG), \
564 SR(DOMAIN16_PG_CONFIG), \
565 SR(DOMAIN17_PG_CONFIG), \
566 SR(DOMAIN18_PG_CONFIG), \
567 SR(DOMAIN19_PG_CONFIG), \
568 SR(DOMAIN0_PG_STATUS), \
569 SR(DOMAIN1_PG_STATUS), \
570 SR(DOMAIN2_PG_STATUS), \
571 SR(DOMAIN3_PG_STATUS), \
572 SR(DOMAIN16_PG_STATUS), \
573 SR(DOMAIN17_PG_STATUS), \
574 SR(DOMAIN18_PG_STATUS), \
575 SR(DOMAIN19_PG_STATUS), \
576 SR(D1VGA_CONTROL), \
577 SR(D2VGA_CONTROL), \
578 SR(D3VGA_CONTROL), \
579 SR(D4VGA_CONTROL), \
580 SR(D5VGA_CONTROL), \
581 SR(D6VGA_CONTROL), \
582 SR(DC_IP_REQUEST_CNTL), \
583 SR(AZALIA_AUDIO_DTO), \
584 SR(AZALIA_CONTROLLER_CLOCK_GATING)
585
586 static struct dce_hwseq_registers hwseq_reg;
587
588 #define hwseq_reg_init()\
589 HWSEQ_DCN32_REG_LIST()
590
591 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
592 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
593 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
594 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
595 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
596 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
597 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
598 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
599 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
600 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
601 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
602 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
603 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
604 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
605 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
606 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
607 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
608 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
609 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
610 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
615 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
616 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
617 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
618 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
619 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
620 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
621 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
622 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
623 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
624
625 static const struct dce_hwseq_shift hwseq_shift = {
626 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
627 };
628
629 static const struct dce_hwseq_mask hwseq_mask = {
630 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
631 };
632 #define vmid_regs_init(id)\
633 DCN20_VMID_REG_LIST_RI(id)
634
635 static struct dcn_vmid_registers vmid_regs[16];
636
637 static const struct dcn20_vmid_shift vmid_shifts = {
638 DCN20_VMID_MASK_SH_LIST(__SHIFT)
639 };
640
641 static const struct dcn20_vmid_mask vmid_masks = {
642 DCN20_VMID_MASK_SH_LIST(_MASK)
643 };
644
645 static const struct resource_caps res_cap_dcn32 = {
646 .num_timing_generator = 4,
647 .num_opp = 4,
648 .num_video_plane = 4,
649 .num_audio = 5,
650 .num_stream_encoder = 5,
651 .num_hpo_dp_stream_encoder = 4,
652 .num_hpo_dp_link_encoder = 2,
653 .num_pll = 5,
654 .num_dwb = 1,
655 .num_ddc = 5,
656 .num_vmid = 16,
657 .num_mpc_3dlut = 4,
658 .num_dsc = 4,
659 };
660
661 static const struct dc_plane_cap plane_cap = {
662 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
663 .per_pixel_alpha = true,
664
665 .pixel_format_support = {
666 .argb8888 = true,
667 .nv12 = true,
668 .fp16 = true,
669 .p010 = true,
670 .ayuv = false,
671 },
672
673 .max_upscale_factor = {
674 .argb8888 = 16000,
675 .nv12 = 16000,
676 .fp16 = 16000
677 },
678
679 // 6:1 downscaling ratio: 1000/6 = 166.666
680 .max_downscale_factor = {
681 .argb8888 = 167,
682 .nv12 = 167,
683 .fp16 = 167
684 },
685 64,
686 64
687 };
688
689 static const struct dc_debug_options debug_defaults_drv = {
690 .disable_dmcu = true,
691 .force_abm_enable = false,
692 .clock_trace = true,
693 .disable_pplib_clock_request = false,
694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
695 .force_single_disp_pipe_split = false,
696 .disable_dcc = DCC_ENABLE,
697 .vsr_support = true,
698 .performance_trace = false,
699 .max_downscale_src_width = 7680,/*upto 8K*/
700 .disable_pplib_wm_range = false,
701 .scl_reset_length10 = true,
702 .sanity_checks = false,
703 .underflow_assert_delay_us = 0xFFFFFFFF,
704 .dwb_fi_phase = -1, // -1 = disable,
705 .dmub_command_table = true,
706 .enable_mem_low_power = {
707 .bits = {
708 .vga = false,
709 .i2c = false,
710 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
711 .dscl = false,
712 .cm = false,
713 .mpc = false,
714 .optc = true,
715 }
716 },
717 .use_max_lb = true,
718 .force_disable_subvp = false,
719 .exit_idle_opt_for_cursor_updates = true,
720 .using_dml2 = false,
721 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
722 .enable_single_display_2to1_odm_policy = true,
723
724 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
725 .enable_double_buffered_dsc_pg_support = true,
726 .enable_dp_dig_pixel_rate_div_policy = 1,
727 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
728 .alloc_extra_way_for_cursor = true,
729 .min_prefetch_in_strobe_ns = 60000, // 60us
730 .disable_unbounded_requesting = false,
731 .override_dispclk_programming = true,
732 .disable_fpo_optimizations = false,
733 .fpo_vactive_margin_us = 2000, // 2000us
734 .disable_fpo_vactive = false,
735 .disable_boot_optimizations = false,
736 .disable_subvp_high_refresh = false,
737 .disable_dp_plus_plus_wa = true,
738 .fpo_vactive_min_active_margin_us = 200,
739 .fpo_vactive_max_blank_us = 1000,
740 .enable_legacy_fast_update = false,
741 };
742
dcn32_aux_engine_create(struct dc_context * ctx,uint32_t inst)743 static struct dce_aux *dcn32_aux_engine_create(
744 struct dc_context *ctx,
745 uint32_t inst)
746 {
747 struct aux_engine_dce110 *aux_engine =
748 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
749
750 if (!aux_engine)
751 return NULL;
752
753 #undef REG_STRUCT
754 #define REG_STRUCT aux_engine_regs
755 aux_engine_regs_init(0),
756 aux_engine_regs_init(1),
757 aux_engine_regs_init(2),
758 aux_engine_regs_init(3),
759 aux_engine_regs_init(4);
760
761 dce110_aux_engine_construct(aux_engine, ctx, inst,
762 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
763 &aux_engine_regs[inst],
764 &aux_mask,
765 &aux_shift,
766 ctx->dc->caps.extended_aux_timeout_support);
767
768 return &aux_engine->base;
769 }
770 #define i2c_inst_regs_init(id)\
771 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
772
773 static struct dce_i2c_registers i2c_hw_regs[5];
774
775 static const struct dce_i2c_shift i2c_shifts = {
776 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
777 };
778
779 static const struct dce_i2c_mask i2c_masks = {
780 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
781 };
782
dcn32_i2c_hw_create(struct dc_context * ctx,uint32_t inst)783 static struct dce_i2c_hw *dcn32_i2c_hw_create(
784 struct dc_context *ctx,
785 uint32_t inst)
786 {
787 struct dce_i2c_hw *dce_i2c_hw =
788 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
789
790 if (!dce_i2c_hw)
791 return NULL;
792
793 #undef REG_STRUCT
794 #define REG_STRUCT i2c_hw_regs
795 i2c_inst_regs_init(1),
796 i2c_inst_regs_init(2),
797 i2c_inst_regs_init(3),
798 i2c_inst_regs_init(4),
799 i2c_inst_regs_init(5);
800
801 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
802 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
803
804 return dce_i2c_hw;
805 }
806
dcn32_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)807 static struct clock_source *dcn32_clock_source_create(
808 struct dc_context *ctx,
809 struct dc_bios *bios,
810 enum clock_source_id id,
811 const struct dce110_clk_src_regs *regs,
812 bool dp_clk_src)
813 {
814 struct dce110_clk_src *clk_src =
815 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
816
817 if (!clk_src)
818 return NULL;
819
820 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
821 regs, &cs_shift, &cs_mask)) {
822 clk_src->base.dp_clk_src = dp_clk_src;
823 return &clk_src->base;
824 }
825
826 kfree(clk_src);
827 BREAK_TO_DEBUGGER();
828 return NULL;
829 }
830
dcn32_hubbub_create(struct dc_context * ctx)831 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
832 {
833 int i;
834
835 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
836 GFP_KERNEL);
837
838 if (!hubbub2)
839 return NULL;
840
841 #undef REG_STRUCT
842 #define REG_STRUCT hubbub_reg
843 hubbub_reg_init();
844
845 #undef REG_STRUCT
846 #define REG_STRUCT vmid_regs
847 vmid_regs_init(0),
848 vmid_regs_init(1),
849 vmid_regs_init(2),
850 vmid_regs_init(3),
851 vmid_regs_init(4),
852 vmid_regs_init(5),
853 vmid_regs_init(6),
854 vmid_regs_init(7),
855 vmid_regs_init(8),
856 vmid_regs_init(9),
857 vmid_regs_init(10),
858 vmid_regs_init(11),
859 vmid_regs_init(12),
860 vmid_regs_init(13),
861 vmid_regs_init(14),
862 vmid_regs_init(15);
863
864 hubbub32_construct(hubbub2, ctx,
865 &hubbub_reg,
866 &hubbub_shift,
867 &hubbub_mask,
868 ctx->dc->dml.ip.det_buffer_size_kbytes,
869 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
870 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
871
872
873 for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
874 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
875
876 vmid->ctx = ctx;
877
878 vmid->regs = &vmid_regs[i];
879 vmid->shifts = &vmid_shifts;
880 vmid->masks = &vmid_masks;
881 }
882
883 return &hubbub2->base;
884 }
885
dcn32_hubp_create(struct dc_context * ctx,uint32_t inst)886 static struct hubp *dcn32_hubp_create(
887 struct dc_context *ctx,
888 uint32_t inst)
889 {
890 struct dcn20_hubp *hubp2 =
891 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
892
893 if (!hubp2)
894 return NULL;
895
896 #undef REG_STRUCT
897 #define REG_STRUCT hubp_regs
898 hubp_regs_init(0),
899 hubp_regs_init(1),
900 hubp_regs_init(2),
901 hubp_regs_init(3);
902
903 if (hubp32_construct(hubp2, ctx, inst,
904 &hubp_regs[inst], &hubp_shift, &hubp_mask))
905 return &hubp2->base;
906
907 BREAK_TO_DEBUGGER();
908 kfree(hubp2);
909 return NULL;
910 }
911
dcn32_dpp_destroy(struct dpp ** dpp)912 static void dcn32_dpp_destroy(struct dpp **dpp)
913 {
914 kfree(TO_DCN30_DPP(*dpp));
915 *dpp = NULL;
916 }
917
dcn32_dpp_create(struct dc_context * ctx,uint32_t inst)918 static struct dpp *dcn32_dpp_create(
919 struct dc_context *ctx,
920 uint32_t inst)
921 {
922 struct dcn3_dpp *dpp3 =
923 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
924
925 if (!dpp3)
926 return NULL;
927
928 #undef REG_STRUCT
929 #define REG_STRUCT dpp_regs
930 dpp_regs_init(0),
931 dpp_regs_init(1),
932 dpp_regs_init(2),
933 dpp_regs_init(3);
934
935 if (dpp32_construct(dpp3, ctx, inst,
936 &dpp_regs[inst], &tf_shift, &tf_mask))
937 return &dpp3->base;
938
939 BREAK_TO_DEBUGGER();
940 kfree(dpp3);
941 return NULL;
942 }
943
dcn32_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)944 static struct mpc *dcn32_mpc_create(
945 struct dc_context *ctx,
946 int num_mpcc,
947 int num_rmu)
948 {
949 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
950 GFP_KERNEL);
951
952 if (!mpc30)
953 return NULL;
954
955 #undef REG_STRUCT
956 #define REG_STRUCT mpc_regs
957 dcn_mpc_regs_init();
958
959 dcn32_mpc_construct(mpc30, ctx,
960 &mpc_regs,
961 &mpc_shift,
962 &mpc_mask,
963 num_mpcc,
964 num_rmu);
965
966 return &mpc30->base;
967 }
968
dcn32_opp_create(struct dc_context * ctx,uint32_t inst)969 static struct output_pixel_processor *dcn32_opp_create(
970 struct dc_context *ctx, uint32_t inst)
971 {
972 struct dcn20_opp *opp2 =
973 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
974
975 if (!opp2) {
976 BREAK_TO_DEBUGGER();
977 return NULL;
978 }
979
980 #undef REG_STRUCT
981 #define REG_STRUCT opp_regs
982 opp_regs_init(0),
983 opp_regs_init(1),
984 opp_regs_init(2),
985 opp_regs_init(3);
986
987 dcn20_opp_construct(opp2, ctx, inst,
988 &opp_regs[inst], &opp_shift, &opp_mask);
989 return &opp2->base;
990 }
991
992
dcn32_timing_generator_create(struct dc_context * ctx,uint32_t instance)993 static struct timing_generator *dcn32_timing_generator_create(
994 struct dc_context *ctx,
995 uint32_t instance)
996 {
997 struct optc *tgn10 =
998 kzalloc(sizeof(struct optc), GFP_KERNEL);
999
1000 if (!tgn10)
1001 return NULL;
1002
1003 #undef REG_STRUCT
1004 #define REG_STRUCT optc_regs
1005 optc_regs_init(0),
1006 optc_regs_init(1),
1007 optc_regs_init(2),
1008 optc_regs_init(3);
1009
1010 tgn10->base.inst = instance;
1011 tgn10->base.ctx = ctx;
1012
1013 tgn10->tg_regs = &optc_regs[instance];
1014 tgn10->tg_shift = &optc_shift;
1015 tgn10->tg_mask = &optc_mask;
1016
1017 dcn32_timing_generator_init(tgn10);
1018
1019 return &tgn10->base;
1020 }
1021
1022 static const struct encoder_feature_support link_enc_feature = {
1023 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1024 .max_hdmi_pixel_clock = 600000,
1025 .hdmi_ycbcr420_supported = true,
1026 .dp_ycbcr420_supported = true,
1027 .fec_supported = true,
1028 .flags.bits.IS_HBR2_CAPABLE = true,
1029 .flags.bits.IS_HBR3_CAPABLE = true,
1030 .flags.bits.IS_TPS3_CAPABLE = true,
1031 .flags.bits.IS_TPS4_CAPABLE = true
1032 };
1033
dcn32_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1034 static struct link_encoder *dcn32_link_encoder_create(
1035 struct dc_context *ctx,
1036 const struct encoder_init_data *enc_init_data)
1037 {
1038 struct dcn20_link_encoder *enc20 =
1039 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1040
1041 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1042 return NULL;
1043
1044 #undef REG_STRUCT
1045 #define REG_STRUCT link_enc_aux_regs
1046 aux_regs_init(0),
1047 aux_regs_init(1),
1048 aux_regs_init(2),
1049 aux_regs_init(3),
1050 aux_regs_init(4);
1051
1052 #undef REG_STRUCT
1053 #define REG_STRUCT link_enc_hpd_regs
1054 hpd_regs_init(0),
1055 hpd_regs_init(1),
1056 hpd_regs_init(2),
1057 hpd_regs_init(3),
1058 hpd_regs_init(4);
1059
1060 #undef REG_STRUCT
1061 #define REG_STRUCT link_enc_regs
1062 link_regs_init(0, A),
1063 link_regs_init(1, B),
1064 link_regs_init(2, C),
1065 link_regs_init(3, D),
1066 link_regs_init(4, E);
1067
1068 dcn32_link_encoder_construct(enc20,
1069 enc_init_data,
1070 &link_enc_feature,
1071 &link_enc_regs[enc_init_data->transmitter],
1072 &link_enc_aux_regs[enc_init_data->channel - 1],
1073 &link_enc_hpd_regs[enc_init_data->hpd_source],
1074 &le_shift,
1075 &le_mask);
1076
1077 return &enc20->enc10.base;
1078 }
1079
dcn32_panel_cntl_create(const struct panel_cntl_init_data * init_data)1080 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1081 {
1082 struct dcn31_panel_cntl *panel_cntl =
1083 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1084
1085 if (!panel_cntl)
1086 return NULL;
1087
1088 dcn31_panel_cntl_construct(panel_cntl, init_data);
1089
1090 return &panel_cntl->base;
1091 }
1092
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1093 static void read_dce_straps(
1094 struct dc_context *ctx,
1095 struct resource_straps *straps)
1096 {
1097 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1098 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1099
1100 }
1101
dcn32_create_audio(struct dc_context * ctx,unsigned int inst)1102 static struct audio *dcn32_create_audio(
1103 struct dc_context *ctx, unsigned int inst)
1104 {
1105
1106 #undef REG_STRUCT
1107 #define REG_STRUCT audio_regs
1108 audio_regs_init(0),
1109 audio_regs_init(1),
1110 audio_regs_init(2),
1111 audio_regs_init(3),
1112 audio_regs_init(4);
1113
1114 return dce_audio_create(ctx, inst,
1115 &audio_regs[inst], &audio_shift, &audio_mask);
1116 }
1117
dcn32_vpg_create(struct dc_context * ctx,uint32_t inst)1118 static struct vpg *dcn32_vpg_create(
1119 struct dc_context *ctx,
1120 uint32_t inst)
1121 {
1122 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1123
1124 if (!vpg3)
1125 return NULL;
1126
1127 #undef REG_STRUCT
1128 #define REG_STRUCT vpg_regs
1129 vpg_regs_init(0),
1130 vpg_regs_init(1),
1131 vpg_regs_init(2),
1132 vpg_regs_init(3),
1133 vpg_regs_init(4),
1134 vpg_regs_init(5),
1135 vpg_regs_init(6),
1136 vpg_regs_init(7),
1137 vpg_regs_init(8),
1138 vpg_regs_init(9);
1139
1140 vpg3_construct(vpg3, ctx, inst,
1141 &vpg_regs[inst],
1142 &vpg_shift,
1143 &vpg_mask);
1144
1145 return &vpg3->base;
1146 }
1147
dcn32_afmt_create(struct dc_context * ctx,uint32_t inst)1148 static struct afmt *dcn32_afmt_create(
1149 struct dc_context *ctx,
1150 uint32_t inst)
1151 {
1152 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1153
1154 if (!afmt3)
1155 return NULL;
1156
1157 #undef REG_STRUCT
1158 #define REG_STRUCT afmt_regs
1159 afmt_regs_init(0),
1160 afmt_regs_init(1),
1161 afmt_regs_init(2),
1162 afmt_regs_init(3),
1163 afmt_regs_init(4),
1164 afmt_regs_init(5);
1165
1166 afmt3_construct(afmt3, ctx, inst,
1167 &afmt_regs[inst],
1168 &afmt_shift,
1169 &afmt_mask);
1170
1171 return &afmt3->base;
1172 }
1173
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1174 static struct apg *dcn31_apg_create(
1175 struct dc_context *ctx,
1176 uint32_t inst)
1177 {
1178 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1179
1180 if (!apg31)
1181 return NULL;
1182
1183 #undef REG_STRUCT
1184 #define REG_STRUCT apg_regs
1185 apg_regs_init(0),
1186 apg_regs_init(1),
1187 apg_regs_init(2),
1188 apg_regs_init(3);
1189
1190 apg31_construct(apg31, ctx, inst,
1191 &apg_regs[inst],
1192 &apg_shift,
1193 &apg_mask);
1194
1195 return &apg31->base;
1196 }
1197
dcn32_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1198 static struct stream_encoder *dcn32_stream_encoder_create(
1199 enum engine_id eng_id,
1200 struct dc_context *ctx)
1201 {
1202 struct dcn10_stream_encoder *enc1;
1203 struct vpg *vpg;
1204 struct afmt *afmt;
1205 int vpg_inst;
1206 int afmt_inst;
1207
1208 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1209 if (eng_id <= ENGINE_ID_DIGF) {
1210 vpg_inst = eng_id;
1211 afmt_inst = eng_id;
1212 } else
1213 return NULL;
1214
1215 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1216 vpg = dcn32_vpg_create(ctx, vpg_inst);
1217 afmt = dcn32_afmt_create(ctx, afmt_inst);
1218
1219 if (!enc1 || !vpg || !afmt) {
1220 kfree(enc1);
1221 kfree(vpg);
1222 kfree(afmt);
1223 return NULL;
1224 }
1225
1226 #undef REG_STRUCT
1227 #define REG_STRUCT stream_enc_regs
1228 stream_enc_regs_init(0),
1229 stream_enc_regs_init(1),
1230 stream_enc_regs_init(2),
1231 stream_enc_regs_init(3),
1232 stream_enc_regs_init(4);
1233
1234 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1235 eng_id, vpg, afmt,
1236 &stream_enc_regs[eng_id],
1237 &se_shift, &se_mask);
1238
1239 return &enc1->base;
1240 }
1241
dcn32_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1242 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1243 enum engine_id eng_id,
1244 struct dc_context *ctx)
1245 {
1246 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1247 struct vpg *vpg;
1248 struct apg *apg;
1249 uint32_t hpo_dp_inst;
1250 uint32_t vpg_inst;
1251 uint32_t apg_inst;
1252
1253 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1254 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1255
1256 /* Mapping of VPG register blocks to HPO DP block instance:
1257 * VPG[6] -> HPO_DP[0]
1258 * VPG[7] -> HPO_DP[1]
1259 * VPG[8] -> HPO_DP[2]
1260 * VPG[9] -> HPO_DP[3]
1261 */
1262 vpg_inst = hpo_dp_inst + 6;
1263
1264 /* Mapping of APG register blocks to HPO DP block instance:
1265 * APG[0] -> HPO_DP[0]
1266 * APG[1] -> HPO_DP[1]
1267 * APG[2] -> HPO_DP[2]
1268 * APG[3] -> HPO_DP[3]
1269 */
1270 apg_inst = hpo_dp_inst;
1271
1272 /* allocate HPO stream encoder and create VPG sub-block */
1273 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1274 vpg = dcn32_vpg_create(ctx, vpg_inst);
1275 apg = dcn31_apg_create(ctx, apg_inst);
1276
1277 if (!hpo_dp_enc31 || !vpg || !apg) {
1278 kfree(hpo_dp_enc31);
1279 kfree(vpg);
1280 kfree(apg);
1281 return NULL;
1282 }
1283
1284 #undef REG_STRUCT
1285 #define REG_STRUCT hpo_dp_stream_enc_regs
1286 hpo_dp_stream_encoder_reg_init(0),
1287 hpo_dp_stream_encoder_reg_init(1),
1288 hpo_dp_stream_encoder_reg_init(2),
1289 hpo_dp_stream_encoder_reg_init(3);
1290
1291 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1292 hpo_dp_inst, eng_id, vpg, apg,
1293 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1294 &hpo_dp_se_shift, &hpo_dp_se_mask);
1295
1296 return &hpo_dp_enc31->base;
1297 }
1298
dcn32_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1299 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1300 uint8_t inst,
1301 struct dc_context *ctx)
1302 {
1303 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1304
1305 /* allocate HPO link encoder */
1306 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1307 if (!hpo_dp_enc31)
1308 return NULL; /* out of memory */
1309
1310 #undef REG_STRUCT
1311 #define REG_STRUCT hpo_dp_link_enc_regs
1312 hpo_dp_link_encoder_reg_init(0),
1313 hpo_dp_link_encoder_reg_init(1);
1314
1315 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1316 &hpo_dp_link_enc_regs[inst],
1317 &hpo_dp_le_shift, &hpo_dp_le_mask);
1318
1319 return &hpo_dp_enc31->base;
1320 }
1321
dcn32_hwseq_create(struct dc_context * ctx)1322 static struct dce_hwseq *dcn32_hwseq_create(
1323 struct dc_context *ctx)
1324 {
1325 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1326
1327 #undef REG_STRUCT
1328 #define REG_STRUCT hwseq_reg
1329 hwseq_reg_init();
1330
1331 if (hws) {
1332 hws->ctx = ctx;
1333 hws->regs = &hwseq_reg;
1334 hws->shifts = &hwseq_shift;
1335 hws->masks = &hwseq_mask;
1336 }
1337 return hws;
1338 }
1339 static const struct resource_create_funcs res_create_funcs = {
1340 .read_dce_straps = read_dce_straps,
1341 .create_audio = dcn32_create_audio,
1342 .create_stream_encoder = dcn32_stream_encoder_create,
1343 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1344 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1345 .create_hwseq = dcn32_hwseq_create,
1346 };
1347
dcn32_resource_destruct(struct dcn32_resource_pool * pool)1348 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1349 {
1350 unsigned int i;
1351
1352 for (i = 0; i < pool->base.stream_enc_count; i++) {
1353 if (pool->base.stream_enc[i] != NULL) {
1354 if (pool->base.stream_enc[i]->vpg != NULL) {
1355 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1356 pool->base.stream_enc[i]->vpg = NULL;
1357 }
1358 if (pool->base.stream_enc[i]->afmt != NULL) {
1359 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1360 pool->base.stream_enc[i]->afmt = NULL;
1361 }
1362 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1363 pool->base.stream_enc[i] = NULL;
1364 }
1365 }
1366
1367 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1368 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1369 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1370 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1371 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1372 }
1373 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1374 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1375 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1376 }
1377 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1378 pool->base.hpo_dp_stream_enc[i] = NULL;
1379 }
1380 }
1381
1382 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1383 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1384 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1385 pool->base.hpo_dp_link_enc[i] = NULL;
1386 }
1387 }
1388
1389 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1390 if (pool->base.dscs[i] != NULL)
1391 dcn20_dsc_destroy(&pool->base.dscs[i]);
1392 }
1393
1394 if (pool->base.mpc != NULL) {
1395 kfree(TO_DCN20_MPC(pool->base.mpc));
1396 pool->base.mpc = NULL;
1397 }
1398 if (pool->base.hubbub != NULL) {
1399 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1400 pool->base.hubbub = NULL;
1401 }
1402 for (i = 0; i < pool->base.pipe_count; i++) {
1403 if (pool->base.dpps[i] != NULL)
1404 dcn32_dpp_destroy(&pool->base.dpps[i]);
1405
1406 if (pool->base.ipps[i] != NULL)
1407 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1408
1409 if (pool->base.hubps[i] != NULL) {
1410 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1411 pool->base.hubps[i] = NULL;
1412 }
1413
1414 if (pool->base.irqs != NULL) {
1415 dal_irq_service_destroy(&pool->base.irqs);
1416 }
1417 }
1418
1419 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1420 if (pool->base.engines[i] != NULL)
1421 dce110_engine_destroy(&pool->base.engines[i]);
1422 if (pool->base.hw_i2cs[i] != NULL) {
1423 kfree(pool->base.hw_i2cs[i]);
1424 pool->base.hw_i2cs[i] = NULL;
1425 }
1426 if (pool->base.sw_i2cs[i] != NULL) {
1427 kfree(pool->base.sw_i2cs[i]);
1428 pool->base.sw_i2cs[i] = NULL;
1429 }
1430 }
1431
1432 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1433 if (pool->base.opps[i] != NULL)
1434 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1435 }
1436
1437 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1438 if (pool->base.timing_generators[i] != NULL) {
1439 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1440 pool->base.timing_generators[i] = NULL;
1441 }
1442 }
1443
1444 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1445 if (pool->base.dwbc[i] != NULL) {
1446 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1447 pool->base.dwbc[i] = NULL;
1448 }
1449 if (pool->base.mcif_wb[i] != NULL) {
1450 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1451 pool->base.mcif_wb[i] = NULL;
1452 }
1453 }
1454
1455 for (i = 0; i < pool->base.audio_count; i++) {
1456 if (pool->base.audios[i])
1457 dce_aud_destroy(&pool->base.audios[i]);
1458 }
1459
1460 for (i = 0; i < pool->base.clk_src_count; i++) {
1461 if (pool->base.clock_sources[i] != NULL) {
1462 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1463 pool->base.clock_sources[i] = NULL;
1464 }
1465 }
1466
1467 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1468 if (pool->base.mpc_lut[i] != NULL) {
1469 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1470 pool->base.mpc_lut[i] = NULL;
1471 }
1472 if (pool->base.mpc_shaper[i] != NULL) {
1473 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1474 pool->base.mpc_shaper[i] = NULL;
1475 }
1476 }
1477
1478 if (pool->base.dp_clock_source != NULL) {
1479 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1480 pool->base.dp_clock_source = NULL;
1481 }
1482
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1484 if (pool->base.multiple_abms[i] != NULL)
1485 dce_abm_destroy(&pool->base.multiple_abms[i]);
1486 }
1487
1488 if (pool->base.psr != NULL)
1489 dmub_psr_destroy(&pool->base.psr);
1490
1491 if (pool->base.dccg != NULL)
1492 dcn_dccg_destroy(&pool->base.dccg);
1493
1494 if (pool->base.oem_device != NULL) {
1495 struct dc *dc = pool->base.oem_device->ctx->dc;
1496
1497 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1498 }
1499 }
1500
1501
dcn32_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1502 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1503 {
1504 int i;
1505 uint32_t dwb_count = pool->res_cap->num_dwb;
1506
1507 for (i = 0; i < dwb_count; i++) {
1508 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1509 GFP_KERNEL);
1510
1511 if (!dwbc30) {
1512 dm_error("DC: failed to create dwbc30!\n");
1513 return false;
1514 }
1515
1516 #undef REG_STRUCT
1517 #define REG_STRUCT dwbc30_regs
1518 dwbc_regs_dcn3_init(0);
1519
1520 dcn30_dwbc_construct(dwbc30, ctx,
1521 &dwbc30_regs[i],
1522 &dwbc30_shift,
1523 &dwbc30_mask,
1524 i);
1525
1526 pool->dwbc[i] = &dwbc30->base;
1527 }
1528 return true;
1529 }
1530
dcn32_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1531 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1532 {
1533 int i;
1534 uint32_t dwb_count = pool->res_cap->num_dwb;
1535
1536 for (i = 0; i < dwb_count; i++) {
1537 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1538 GFP_KERNEL);
1539
1540 if (!mcif_wb30) {
1541 dm_error("DC: failed to create mcif_wb30!\n");
1542 return false;
1543 }
1544
1545 #undef REG_STRUCT
1546 #define REG_STRUCT mcif_wb30_regs
1547 mcif_wb_regs_dcn3_init(0);
1548
1549 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1550 &mcif_wb30_regs[i],
1551 &mcif_wb30_shift,
1552 &mcif_wb30_mask,
1553 i);
1554
1555 pool->mcif_wb[i] = &mcif_wb30->base;
1556 }
1557 return true;
1558 }
1559
dcn32_dsc_create(struct dc_context * ctx,uint32_t inst)1560 static struct display_stream_compressor *dcn32_dsc_create(
1561 struct dc_context *ctx, uint32_t inst)
1562 {
1563 struct dcn20_dsc *dsc =
1564 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1565
1566 if (!dsc) {
1567 BREAK_TO_DEBUGGER();
1568 return NULL;
1569 }
1570
1571 #undef REG_STRUCT
1572 #define REG_STRUCT dsc_regs
1573 dsc_regsDCN20_init(0),
1574 dsc_regsDCN20_init(1),
1575 dsc_regsDCN20_init(2),
1576 dsc_regsDCN20_init(3);
1577
1578 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1579
1580 dsc->max_image_width = 6016;
1581
1582 return &dsc->base;
1583 }
1584
dcn32_destroy_resource_pool(struct resource_pool ** pool)1585 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1586 {
1587 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1588
1589 dcn32_resource_destruct(dcn32_pool);
1590 kfree(dcn32_pool);
1591 *pool = NULL;
1592 }
1593
dcn32_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1594 bool dcn32_acquire_post_bldn_3dlut(
1595 struct resource_context *res_ctx,
1596 const struct resource_pool *pool,
1597 int mpcc_id,
1598 struct dc_3dlut **lut,
1599 struct dc_transfer_func **shaper)
1600 {
1601 bool ret = false;
1602
1603 ASSERT(*lut == NULL && *shaper == NULL);
1604 *lut = NULL;
1605 *shaper = NULL;
1606
1607 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1608 *lut = pool->mpc_lut[mpcc_id];
1609 *shaper = pool->mpc_shaper[mpcc_id];
1610 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1611 ret = true;
1612 }
1613 return ret;
1614 }
1615
dcn32_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1616 bool dcn32_release_post_bldn_3dlut(
1617 struct resource_context *res_ctx,
1618 const struct resource_pool *pool,
1619 struct dc_3dlut **lut,
1620 struct dc_transfer_func **shaper)
1621 {
1622 int i;
1623 bool ret = false;
1624
1625 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1626 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1627 res_ctx->is_mpc_3dlut_acquired[i] = false;
1628 pool->mpc_lut[i]->state.raw = 0;
1629 *lut = NULL;
1630 *shaper = NULL;
1631 ret = true;
1632 break;
1633 }
1634 }
1635 return ret;
1636 }
1637
dcn32_enable_phantom_plane(struct dc * dc,struct dc_state * context,struct dc_stream_state * phantom_stream,unsigned int dc_pipe_idx)1638 static void dcn32_enable_phantom_plane(struct dc *dc,
1639 struct dc_state *context,
1640 struct dc_stream_state *phantom_stream,
1641 unsigned int dc_pipe_idx)
1642 {
1643 struct dc_plane_state *phantom_plane = NULL;
1644 struct dc_plane_state *prev_phantom_plane = NULL;
1645 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1646
1647 while (curr_pipe) {
1648 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1649 phantom_plane = prev_phantom_plane;
1650 else
1651 phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);
1652
1653 if (!phantom_plane)
1654 continue;
1655
1656 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1657 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1658 sizeof(phantom_plane->scaling_quality));
1659 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1660 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1661 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1662 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1663 sizeof(phantom_plane->plane_size));
1664 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1665 sizeof(phantom_plane->tiling_info));
1666 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1667 phantom_plane->format = curr_pipe->plane_state->format;
1668 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1669 phantom_plane->visible = curr_pipe->plane_state->visible;
1670
1671 /* Shadow pipe has small viewport. */
1672 phantom_plane->clip_rect.y = 0;
1673 phantom_plane->clip_rect.height = phantom_stream->src.height;
1674
1675 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);
1676
1677 curr_pipe = curr_pipe->bottom_pipe;
1678 prev_phantom_plane = phantom_plane;
1679 }
1680 }
1681
dcn32_enable_phantom_stream(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)1682 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1683 struct dc_state *context,
1684 display_e2e_pipe_params_st *pipes,
1685 unsigned int pipe_cnt,
1686 unsigned int dc_pipe_idx)
1687 {
1688 struct dc_stream_state *phantom_stream = NULL;
1689 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1690
1691 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);
1692 if (!phantom_stream)
1693 return phantom_stream;
1694
1695 /* stream has limited viewport and small timing */
1696 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1697 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1698 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1699 DC_FP_START();
1700 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1701 DC_FP_END();
1702
1703 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);
1704 return phantom_stream;
1705 }
1706
1707 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1708 * require a phantom pipe / stream
1709 */
dcn32_add_phantom_pipes(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int index)1710 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1711 display_e2e_pipe_params_st *pipes,
1712 unsigned int pipe_cnt,
1713 unsigned int index)
1714 {
1715 struct dc_stream_state *phantom_stream = NULL;
1716 unsigned int i;
1717
1718 // The index of the DC pipe passed into this function is guarenteed to
1719 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1720 // already have phantom pipe assigned, etc.) by previous checks.
1721 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1722 if (!phantom_stream)
1723 return;
1724
1725 dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1726
1727 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1728 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1729
1730 // Build scaling params for phantom pipes which were newly added.
1731 // We determine which phantom pipes were added by comparing with
1732 // the phantom stream.
1733 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1734 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
1735 pipe->stream->use_dynamic_meta = false;
1736 pipe->plane_state->flip_immediate = false;
1737 if (!resource_build_scaling_params(pipe)) {
1738 // Log / remove phantom pipes since failed to build scaling params
1739 }
1740 }
1741 }
1742 }
1743
dml1_validate(struct dc * dc,struct dc_state * context,bool fast_validate)1744 static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)
1745 {
1746 bool out = false;
1747
1748 BW_VAL_TRACE_SETUP();
1749
1750 int vlevel = 0;
1751 int pipe_cnt = 0;
1752 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1753
1754 /* To handle Freesync properly, setting FreeSync DML parameters
1755 * to its default state for the first stage of validation
1756 */
1757 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1758 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1759
1760 DC_LOGGER_INIT(dc->ctx->logger);
1761
1762 BW_VAL_TRACE_COUNT();
1763
1764 if (!pipes)
1765 goto validate_fail;
1766
1767 DC_FP_START();
1768 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1769 DC_FP_END();
1770
1771 if (pipe_cnt == 0)
1772 goto validate_out;
1773
1774 if (!out)
1775 goto validate_fail;
1776
1777 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1778
1779 if (fast_validate) {
1780 BW_VAL_TRACE_SKIP(fast);
1781 goto validate_out;
1782 }
1783
1784 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1785
1786 dcn32_override_min_req_memclk(dc, context);
1787 dcn32_override_min_req_dcfclk(dc, context);
1788
1789 BW_VAL_TRACE_END_WATERMARKS();
1790
1791 goto validate_out;
1792
1793 validate_fail:
1794 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1795 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1796
1797 BW_VAL_TRACE_SKIP(fail);
1798 out = false;
1799
1800 validate_out:
1801 kfree(pipes);
1802
1803 BW_VAL_TRACE_FINISH();
1804
1805 return out;
1806 }
1807
dcn32_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1808 bool dcn32_validate_bandwidth(struct dc *dc,
1809 struct dc_state *context,
1810 bool fast_validate)
1811 {
1812 bool out = false;
1813
1814 if (dc->debug.using_dml2)
1815 out = dml2_validate(dc, context,
1816 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1817 fast_validate);
1818 else
1819 out = dml1_validate(dc, context, fast_validate);
1820 return out;
1821 }
1822
dcn32_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1823 int dcn32_populate_dml_pipes_from_context(
1824 struct dc *dc, struct dc_state *context,
1825 display_e2e_pipe_params_st *pipes,
1826 bool fast_validate)
1827 {
1828 int i, pipe_cnt;
1829 struct resource_context *res_ctx = &context->res_ctx;
1830 struct pipe_ctx *pipe = NULL;
1831 bool subvp_in_use = false;
1832 struct dc_crtc_timing *timing;
1833 int subvp_main_pipe_index = -1;
1834 enum mall_stream_type mall_type;
1835 bool single_display_subvp = false;
1836 struct dc_stream_state *stream = NULL;
1837 int num_subvp_main = 0;
1838 int num_subvp_phantom = 0;
1839 int num_subvp_none = 0;
1840 int odm_slice_count;
1841
1842 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1843
1844 /* For single display subvp, look for subvp main so if we have phantom
1845 * pipe, we can set odm policy to match main pipe
1846 */
1847 for (i = 0; i < context->stream_count; i++) {
1848 stream = context->streams[i];
1849 mall_type = dc_state_get_stream_subvp_type(context, stream);
1850 if (mall_type == SUBVP_MAIN)
1851 num_subvp_main++;
1852 else if (mall_type == SUBVP_PHANTOM)
1853 num_subvp_phantom++;
1854 else
1855 num_subvp_none++;
1856 }
1857 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0)
1858 single_display_subvp = true;
1859
1860 if (single_display_subvp) {
1861 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1862 pipe = &res_ctx->pipe_ctx[i];
1863 if (!res_ctx->pipe_ctx[i].stream)
1864 continue;
1865
1866 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1867 if (mall_type == SUBVP_MAIN) {
1868 if (resource_is_pipe_type(pipe, OTG_MASTER))
1869 subvp_main_pipe_index = i;
1870 }
1871 pipe_cnt++;
1872 }
1873 }
1874
1875 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1876
1877 if (!res_ctx->pipe_ctx[i].stream)
1878 continue;
1879 pipe = &res_ctx->pipe_ctx[i];
1880 timing = &pipe->stream->timing;
1881
1882 pipes[pipe_cnt].pipe.src.gpuvm = true;
1883 DC_FP_START();
1884 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1885 DC_FP_END();
1886 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1887 if (dc->config.enable_windowed_mpo_odm &&
1888 dc->debug.enable_single_display_2to1_odm_policy) {
1889 /* For single display subvp, if pipe is phantom pipe,
1890 * then copy odm policy from subvp main pipe
1891 */
1892 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1893 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) {
1894 if (subvp_main_pipe_index < 0) {
1895 odm_slice_count = -1;
1896 ASSERT(0);
1897 } else {
1898 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);
1899 }
1900 } else {
1901 odm_slice_count = resource_get_odm_slice_count(pipe);
1902 }
1903 switch (odm_slice_count) {
1904 case 2:
1905 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1906 break;
1907 case 4:
1908 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
1909 break;
1910 default:
1911 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1912 }
1913 } else {
1914 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1915 }
1916
1917 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
1918 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1919 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
1920
1921 /* Only populate DML input with subvp info for full updates.
1922 * This is just a workaround -- needs a proper fix.
1923 */
1924 if (!fast_validate) {
1925 switch (dc_state_get_pipe_subvp_type(context, pipe)) {
1926 case SUBVP_MAIN:
1927 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
1928 subvp_in_use = true;
1929 break;
1930 case SUBVP_PHANTOM:
1931 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
1932 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1933 // Disallow unbounded req for SubVP according to DCHUB programming guide
1934 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1935 break;
1936 case SUBVP_NONE:
1937 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
1938 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1939 break;
1940 default:
1941 break;
1942 }
1943 }
1944
1945 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1946 if (pipes[pipe_cnt].dout.dsc_enable) {
1947 switch (timing->display_color_depth) {
1948 case COLOR_DEPTH_888:
1949 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1950 break;
1951 case COLOR_DEPTH_101010:
1952 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1953 break;
1954 case COLOR_DEPTH_121212:
1955 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1956 break;
1957 default:
1958 ASSERT(0);
1959 break;
1960 }
1961 }
1962
1963
1964 pipe_cnt++;
1965 }
1966
1967 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
1968 * the DET available for each pipe). Use the DET override input to maintain our driver
1969 * policy.
1970 */
1971 dcn32_set_det_allocations(dc, context, pipes);
1972
1973 // In general cases we want to keep the dram clock change requirement
1974 // (prefer configs that support MCLK switch). Only override to false
1975 // for SubVP
1976 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
1977 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
1978 else
1979 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1980
1981 return pipe_cnt;
1982 }
1983
dcn32_calculate_mall_ways_from_bytes(const struct dc * dc,unsigned int total_size_in_mall_bytes)1984 unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)
1985 {
1986 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
1987
1988 if (total_size_in_mall_bytes == 0) {
1989 return 0;
1990 }
1991
1992 if (dc->caps.max_cab_allocation_bytes == 0) {
1993 return 0xffffffff;
1994 }
1995
1996 /* add 2 lines for worst case alignment */
1997 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
1998
1999 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
2000 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
2001 num_ways = cache_lines_used / lines_per_way;
2002 if (cache_lines_used % lines_per_way > 0)
2003 num_ways++;
2004
2005 return num_ways;
2006 }
2007
2008 static struct dc_cap_funcs cap_funcs = {
2009 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
2010 .get_subvp_en = dcn32_subvp_in_use,
2011 };
2012
dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2013 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
2014 display_e2e_pipe_params_st *pipes,
2015 int pipe_cnt,
2016 int vlevel)
2017 {
2018 DC_FP_START();
2019 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
2020 DC_FP_END();
2021 }
2022
dcn32_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2023 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2024 {
2025 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
2026
2027 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
2028
2029 DC_FP_START();
2030
2031 dcn32_update_bw_bounding_box_fpu(dc, bw_params);
2032
2033 dml2_opt->use_clock_dc_limits = false;
2034 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
2035 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
2036
2037 dml2_opt->use_clock_dc_limits = true;
2038 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
2039 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
2040
2041 DC_FP_END();
2042 }
2043
2044 static struct resource_funcs dcn32_res_pool_funcs = {
2045 .destroy = dcn32_destroy_resource_pool,
2046 .link_enc_create = dcn32_link_encoder_create,
2047 .link_enc_create_minimal = NULL,
2048 .panel_cntl_create = dcn32_panel_cntl_create,
2049 .validate_bandwidth = dcn32_validate_bandwidth,
2050 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
2051 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
2052 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
2053 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
2054 .release_pipe = dcn20_release_pipe,
2055 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2056 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2057 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2058 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2059 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2060 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2061 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
2062 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
2063 .update_bw_bounding_box = dcn32_update_bw_bounding_box,
2064 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2065 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2066 .add_phantom_pipes = dcn32_add_phantom_pipes,
2067 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
2068 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
2069 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
2070 };
2071
read_pipe_fuses(struct dc_context * ctx)2072 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2073 {
2074 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2075 /* DCN32 support max 4 pipes */
2076 value = value & 0xf;
2077 return value;
2078 }
2079
2080
dcn32_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn32_resource_pool * pool)2081 static bool dcn32_resource_construct(
2082 uint8_t num_virtual_links,
2083 struct dc *dc,
2084 struct dcn32_resource_pool *pool)
2085 {
2086 int i, j;
2087 struct dc_context *ctx = dc->ctx;
2088 struct irq_service_init_data init_data;
2089 struct ddc_service_init_data ddc_init_data = {0};
2090 uint32_t pipe_fuses = 0;
2091 uint32_t num_pipes = 4;
2092
2093 #undef REG_STRUCT
2094 #define REG_STRUCT bios_regs
2095 bios_regs_init();
2096
2097 #undef REG_STRUCT
2098 #define REG_STRUCT clk_src_regs
2099 clk_src_regs_init(0, A),
2100 clk_src_regs_init(1, B),
2101 clk_src_regs_init(2, C),
2102 clk_src_regs_init(3, D),
2103 clk_src_regs_init(4, E);
2104
2105 #undef REG_STRUCT
2106 #define REG_STRUCT abm_regs
2107 abm_regs_init(0),
2108 abm_regs_init(1),
2109 abm_regs_init(2),
2110 abm_regs_init(3);
2111
2112 #undef REG_STRUCT
2113 #define REG_STRUCT dccg_regs
2114 dccg_regs_init();
2115
2116 DC_FP_START();
2117
2118 ctx->dc_bios->regs = &bios_regs;
2119
2120 pool->base.res_cap = &res_cap_dcn32;
2121 /* max number of pipes for ASIC before checking for pipe fuses */
2122 num_pipes = pool->base.res_cap->num_timing_generator;
2123 pipe_fuses = read_pipe_fuses(ctx);
2124
2125 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2126 if (pipe_fuses & 1 << i)
2127 num_pipes--;
2128
2129 if (pipe_fuses & 1)
2130 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2131
2132 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2133 ASSERT(0); //Entire DCN is harvested!
2134
2135 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2136 * value will be changed, update max_num_dpp and max_num_otg for dml.
2137 */
2138 dcn3_2_ip.max_num_dpp = num_pipes;
2139 dcn3_2_ip.max_num_otg = num_pipes;
2140
2141 pool->base.funcs = &dcn32_res_pool_funcs;
2142
2143 /*************************************************
2144 * Resource + asic cap harcoding *
2145 *************************************************/
2146 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2147 pool->base.timing_generator_count = num_pipes;
2148 pool->base.pipe_count = num_pipes;
2149 pool->base.mpcc_count = num_pipes;
2150 dc->caps.max_downscale_ratio = 600;
2151 dc->caps.i2c_speed_in_khz = 100;
2152 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2153 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
2154 dc->caps.max_cursor_size = 64;
2155 dc->caps.min_horizontal_blanking_period = 80;
2156 dc->caps.dmdata_alloc_size = 2048;
2157 dc->caps.mall_size_per_mem_channel = 4;
2158 /* total size = mall per channel * num channels * 1024 * 1024 */
2159 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2160 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2161
2162 dc->caps.cache_line_size = 64;
2163 dc->caps.cache_num_ways = 16;
2164
2165 /* Calculate the available MALL space */
2166 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
2167 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2168 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2169 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2170
2171 dc->caps.subvp_fw_processing_delay_us = 15;
2172 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2173 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2174 dc->caps.subvp_swath_height_margin_lines = 16;
2175 dc->caps.subvp_pstate_allow_width_us = 20;
2176 dc->caps.subvp_vertical_int_margin_us = 30;
2177 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2178
2179 dc->caps.max_slave_planes = 2;
2180 dc->caps.max_slave_yuv_planes = 2;
2181 dc->caps.max_slave_rgb_planes = 2;
2182 dc->caps.post_blend_color_processing = true;
2183 dc->caps.force_dp_tps4_for_cp2520 = true;
2184 if (dc->config.forceHBR2CP2520)
2185 dc->caps.force_dp_tps4_for_cp2520 = false;
2186 dc->caps.dp_hpo = true;
2187 dc->caps.dp_hdmi21_pcon_support = true;
2188 dc->caps.edp_dsc_support = true;
2189 dc->caps.extended_aux_timeout_support = true;
2190 dc->caps.dmcub_support = true;
2191 dc->caps.seamless_odm = true;
2192 dc->caps.max_v_total = (1 << 15) - 1;
2193 dc->caps.vtotal_limited_by_fp2 = true;
2194
2195 /* Color pipeline capabilities */
2196 dc->caps.color.dpp.dcn_arch = 1;
2197 dc->caps.color.dpp.input_lut_shared = 0;
2198 dc->caps.color.dpp.icsc = 1;
2199 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2200 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2201 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2202 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2203 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2204 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2205 dc->caps.color.dpp.post_csc = 1;
2206 dc->caps.color.dpp.gamma_corr = 1;
2207 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2208
2209 dc->caps.color.dpp.hw_3d_lut = 1;
2210 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2211 // no OGAM ROM on DCN2 and later ASICs
2212 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2213 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2214 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2215 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2216 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2217 dc->caps.color.dpp.ocsc = 0;
2218
2219 dc->caps.color.mpc.gamut_remap = 1;
2220 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2221 dc->caps.color.mpc.ogam_ram = 1;
2222 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2223 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2224 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2225 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2226 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2227 dc->caps.color.mpc.ocsc = 1;
2228
2229 /* Use pipe context based otg sync logic */
2230 dc->config.use_pipe_ctx_sync_logic = true;
2231
2232 dc->config.dc_mode_clk_limit_support = true;
2233 dc->config.enable_windowed_mpo_odm = true;
2234 dc->config.disable_hbr_audio_dp2 = true;
2235 /* read VBIOS LTTPR caps */
2236 {
2237 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2238 enum bp_result bp_query_result;
2239 uint8_t is_vbios_lttpr_enable = 0;
2240
2241 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2242 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2243 }
2244
2245 /* interop bit is implicit */
2246 {
2247 dc->caps.vbios_lttpr_aware = true;
2248 }
2249 }
2250
2251 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2252 dc->debug = debug_defaults_drv;
2253
2254 // Init the vm_helper
2255 if (dc->vm_helper)
2256 vm_helper_init(dc->vm_helper, 16);
2257
2258 /*************************************************
2259 * Create resources *
2260 *************************************************/
2261
2262 /* Clock Sources for Pixel Clock*/
2263 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2264 dcn32_clock_source_create(ctx, ctx->dc_bios,
2265 CLOCK_SOURCE_COMBO_PHY_PLL0,
2266 &clk_src_regs[0], false);
2267 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2268 dcn32_clock_source_create(ctx, ctx->dc_bios,
2269 CLOCK_SOURCE_COMBO_PHY_PLL1,
2270 &clk_src_regs[1], false);
2271 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2272 dcn32_clock_source_create(ctx, ctx->dc_bios,
2273 CLOCK_SOURCE_COMBO_PHY_PLL2,
2274 &clk_src_regs[2], false);
2275 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2276 dcn32_clock_source_create(ctx, ctx->dc_bios,
2277 CLOCK_SOURCE_COMBO_PHY_PLL3,
2278 &clk_src_regs[3], false);
2279 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2280 dcn32_clock_source_create(ctx, ctx->dc_bios,
2281 CLOCK_SOURCE_COMBO_PHY_PLL4,
2282 &clk_src_regs[4], false);
2283
2284 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2285
2286 /* todo: not reuse phy_pll registers */
2287 pool->base.dp_clock_source =
2288 dcn32_clock_source_create(ctx, ctx->dc_bios,
2289 CLOCK_SOURCE_ID_DP_DTO,
2290 &clk_src_regs[0], true);
2291
2292 for (i = 0; i < pool->base.clk_src_count; i++) {
2293 if (pool->base.clock_sources[i] == NULL) {
2294 dm_error("DC: failed to create clock sources!\n");
2295 BREAK_TO_DEBUGGER();
2296 goto create_fail;
2297 }
2298 }
2299
2300 /* DCCG */
2301 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2302 if (pool->base.dccg == NULL) {
2303 dm_error("DC: failed to create dccg!\n");
2304 BREAK_TO_DEBUGGER();
2305 goto create_fail;
2306 }
2307
2308 /* DML */
2309 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2310
2311 /* IRQ Service */
2312 init_data.ctx = dc->ctx;
2313 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2314 if (!pool->base.irqs)
2315 goto create_fail;
2316
2317 /* HUBBUB */
2318 pool->base.hubbub = dcn32_hubbub_create(ctx);
2319 if (pool->base.hubbub == NULL) {
2320 BREAK_TO_DEBUGGER();
2321 dm_error("DC: failed to create hubbub!\n");
2322 goto create_fail;
2323 }
2324
2325 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2326 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2327
2328 /* if pipe is disabled, skip instance of HW pipe,
2329 * i.e, skip ASIC register instance
2330 */
2331 if (pipe_fuses & 1 << i)
2332 continue;
2333
2334 /* HUBPs */
2335 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2336 if (pool->base.hubps[j] == NULL) {
2337 BREAK_TO_DEBUGGER();
2338 dm_error(
2339 "DC: failed to create hubps!\n");
2340 goto create_fail;
2341 }
2342
2343 /* DPPs */
2344 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2345 if (pool->base.dpps[j] == NULL) {
2346 BREAK_TO_DEBUGGER();
2347 dm_error(
2348 "DC: failed to create dpps!\n");
2349 goto create_fail;
2350 }
2351
2352 /* OPPs */
2353 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2354 if (pool->base.opps[j] == NULL) {
2355 BREAK_TO_DEBUGGER();
2356 dm_error(
2357 "DC: failed to create output pixel processor!\n");
2358 goto create_fail;
2359 }
2360
2361 /* TGs */
2362 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2363 ctx, i);
2364 if (pool->base.timing_generators[j] == NULL) {
2365 BREAK_TO_DEBUGGER();
2366 dm_error("DC: failed to create tg!\n");
2367 goto create_fail;
2368 }
2369
2370 /* ABMs */
2371 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2372 &abm_regs[i],
2373 &abm_shift,
2374 &abm_mask);
2375 if (pool->base.multiple_abms[j] == NULL) {
2376 dm_error("DC: failed to create abm for pipe %d!\n", i);
2377 BREAK_TO_DEBUGGER();
2378 goto create_fail;
2379 }
2380
2381 /* index for resource pool arrays for next valid pipe */
2382 j++;
2383 }
2384
2385 /* PSR */
2386 pool->base.psr = dmub_psr_create(ctx);
2387 if (pool->base.psr == NULL) {
2388 dm_error("DC: failed to create psr obj!\n");
2389 BREAK_TO_DEBUGGER();
2390 goto create_fail;
2391 }
2392
2393 /* MPCCs */
2394 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2395 if (pool->base.mpc == NULL) {
2396 BREAK_TO_DEBUGGER();
2397 dm_error("DC: failed to create mpc!\n");
2398 goto create_fail;
2399 }
2400
2401 /* DSCs */
2402 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2403 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2404 if (pool->base.dscs[i] == NULL) {
2405 BREAK_TO_DEBUGGER();
2406 dm_error("DC: failed to create display stream compressor %d!\n", i);
2407 goto create_fail;
2408 }
2409 }
2410
2411 /* DWB */
2412 if (!dcn32_dwbc_create(ctx, &pool->base)) {
2413 BREAK_TO_DEBUGGER();
2414 dm_error("DC: failed to create dwbc!\n");
2415 goto create_fail;
2416 }
2417
2418 /* MMHUBBUB */
2419 if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2420 BREAK_TO_DEBUGGER();
2421 dm_error("DC: failed to create mcif_wb!\n");
2422 goto create_fail;
2423 }
2424
2425 /* AUX and I2C */
2426 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2427 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2428 if (pool->base.engines[i] == NULL) {
2429 BREAK_TO_DEBUGGER();
2430 dm_error(
2431 "DC:failed to create aux engine!!\n");
2432 goto create_fail;
2433 }
2434 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2435 if (pool->base.hw_i2cs[i] == NULL) {
2436 BREAK_TO_DEBUGGER();
2437 dm_error(
2438 "DC:failed to create hw i2c!!\n");
2439 goto create_fail;
2440 }
2441 pool->base.sw_i2cs[i] = NULL;
2442 }
2443
2444 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2445 if (!resource_construct(num_virtual_links, dc, &pool->base,
2446 &res_create_funcs))
2447 goto create_fail;
2448
2449 /* HW Sequencer init functions and Plane caps */
2450 dcn32_hw_sequencer_init_functions(dc);
2451
2452 dc->caps.max_planes = pool->base.pipe_count;
2453
2454 for (i = 0; i < dc->caps.max_planes; ++i)
2455 dc->caps.planes[i] = plane_cap;
2456
2457 dc->cap_funcs = cap_funcs;
2458
2459 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2460 ddc_init_data.ctx = dc->ctx;
2461 ddc_init_data.link = NULL;
2462 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2463 ddc_init_data.id.enum_id = 0;
2464 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2465 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2466 } else {
2467 pool->base.oem_device = NULL;
2468 }
2469
2470 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2471 dc->dml2_options.use_native_pstate_optimization = false;
2472 dc->dml2_options.use_native_soc_bb_construction = true;
2473 dc->dml2_options.minimize_dispclk_using_odm = true;
2474
2475 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2476 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2477 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2478 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2479
2480 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2481 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2482 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2483 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2484
2485 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2486 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2487
2488 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2489 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2490 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2491 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2492 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2493 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2494 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2495
2496 dc->dml2_options.max_segments_per_hubp = 18;
2497 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2498 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2499
2500 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
2501 dc->config.sdpif_request_limit_words_per_umc = 16;
2502
2503 DC_FP_END();
2504
2505 return true;
2506
2507 create_fail:
2508
2509 DC_FP_END();
2510
2511 dcn32_resource_destruct(pool);
2512
2513 return false;
2514 }
2515
dcn32_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2516 struct resource_pool *dcn32_create_resource_pool(
2517 const struct dc_init_data *init_data,
2518 struct dc *dc)
2519 {
2520 struct dcn32_resource_pool *pool =
2521 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
2522
2523 if (!pool)
2524 return NULL;
2525
2526 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
2527 return &pool->base;
2528
2529 BREAK_TO_DEBUGGER();
2530 kfree(pool);
2531 return NULL;
2532 }
2533
2534 /*
2535 * Find the most optimal free pipe from res_ctx, which could be used as a
2536 * secondary dpp pipe for input opp head pipe.
2537 *
2538 * a free pipe - a pipe in input res_ctx not yet used for any streams or
2539 * planes.
2540 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending
2541 * tree. This is typical used for rendering MPO planes or additional offset
2542 * areas in MPCC combine.
2543 *
2544 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe
2545 * -------------------------------------------------------------------------
2546 *
2547 * PROBLEM:
2548 *
2549 * 1. There is a hardware limitation that a secondary DPP pipe cannot be
2550 * transferred from one MPC blending tree to the other in a single frame.
2551 * Otherwise it could cause glitches on the screen.
2552 *
2553 * For instance, we cannot transition from state 1 to state 2 in one frame. This
2554 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to
2555 * PIPE2's MPC blending tree, which is not supported by hardware.
2556 * To support this transition we need to first remove PIPE1 from PIPE0's MPC
2557 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree
2558 * in the next frame. This is not optimal as it will delay the flip for two
2559 * frames.
2560 *
2561 * State 1:
2562 * PIPE0 -- secondary DPP pipe --> (PIPE1)
2563 * PIPE2 -- secondary DPP pipe --> NONE
2564 *
2565 * State 2:
2566 * PIPE0 -- secondary DPP pipe --> NONE
2567 * PIPE2 -- secondary DPP pipe --> (PIPE1)
2568 *
2569 * 2. We want to in general minimize the unnecessary changes in pipe topology.
2570 * If a pipe is already added in current blending tree and there are no changes
2571 * to plane topology, we don't want to swap it with another free pipe
2572 * unnecessarily in every update. Powering up and down a pipe would require a
2573 * full update which delays the flip for 1 frame. If we use the original pipe
2574 * we don't have to toggle its power. So we can flip faster.
2575 */
dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_opp_head)2576 int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2577 const struct resource_context *cur_res_ctx,
2578 struct resource_context *new_res_ctx,
2579 const struct resource_pool *pool,
2580 const struct pipe_ctx *new_opp_head)
2581 {
2582 const struct pipe_ctx *cur_opp_head;
2583 int free_pipe_idx;
2584
2585 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];
2586 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree(
2587 cur_res_ctx, new_res_ctx, cur_opp_head);
2588
2589 /* Up until here if we have not found a free secondary pipe, we will
2590 * need to wait for at least one frame to complete the transition
2591 * sequence.
2592 */
2593 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2594 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2595 cur_res_ctx, new_res_ctx, pool);
2596
2597 /* Up until here if we have not found a free secondary pipe, we will
2598 * need to wait for at least two frames to complete the transition
2599 * sequence. It really doesn't matter which pipe we decide take from
2600 * current enabled pipes. It won't save our frame time when we swap only
2601 * one pipe or more pipes.
2602 */
2603 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2604 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
2605 cur_res_ctx, new_res_ctx, pool);
2606
2607 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2608 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2609
2610 return free_pipe_idx;
2611 }
2612
find_idle_secondary_pipe_check_mpo(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)2613 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2614 struct resource_context *res_ctx,
2615 const struct resource_pool *pool,
2616 const struct pipe_ctx *primary_pipe)
2617 {
2618 int i;
2619 struct pipe_ctx *secondary_pipe = NULL;
2620 struct pipe_ctx *next_odm_mpo_pipe = NULL;
2621 int primary_index, preferred_pipe_idx;
2622 struct pipe_ctx *old_primary_pipe = NULL;
2623
2624 /*
2625 * Modified from find_idle_secondary_pipe
2626 * With windowed MPO and ODM, we want to avoid the case where we want a
2627 * free pipe for the left side but the free pipe is being used on the
2628 * right side.
2629 * Add check on current_state if the primary_pipe is the left side,
2630 * to check the right side ( primary_pipe->next_odm_pipe ) to see if
2631 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2632 * - If so, then don't use this pipe
2633 * EXCEPTION - 3 plane ( 2 MPO plane ) case
2634 * - in this case, the primary pipe has already gotten a free pipe for the
2635 * MPO window in the left
2636 * - when it tries to get a free pipe for the MPO window on the right,
2637 * it will see that it is already assigned to the right side
2638 * ( primary_pipe->next_odm_pipe ). But in this case, we want this
2639 * free pipe, since it will be for the right side. So add an
2640 * additional condition, that skipping the free pipe on the right only
2641 * applies if the primary pipe has no bottom pipe currently assigned
2642 */
2643 if (primary_pipe) {
2644 primary_index = primary_pipe->pipe_idx;
2645 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2646 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2647 && (!primary_pipe->bottom_pipe))
2648 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2649
2650 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2651 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2652 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2653 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2654 secondary_pipe->pipe_idx = preferred_pipe_idx;
2655 }
2656 }
2657
2658 /*
2659 * search backwards for the second pipe to keep pipe
2660 * assignment more consistent
2661 */
2662 if (!secondary_pipe)
2663 for (i = pool->pipe_count - 1; i >= 0; i--) {
2664 if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2665 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2666 secondary_pipe = &res_ctx->pipe_ctx[i];
2667 secondary_pipe->pipe_idx = i;
2668 break;
2669 }
2670 }
2671
2672 return secondary_pipe;
2673 }
2674
dcn32_acquire_idle_pipe_for_head_pipe_in_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream,const struct pipe_ctx * head_pipe)2675 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2676 struct dc_state *state,
2677 const struct resource_pool *pool,
2678 struct dc_stream_state *stream,
2679 const struct pipe_ctx *head_pipe)
2680 {
2681 struct resource_context *res_ctx = &state->res_ctx;
2682 struct pipe_ctx *idle_pipe, *pipe;
2683 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2684 int head_index;
2685
2686 if (!head_pipe) {
2687 ASSERT(0);
2688 return NULL;
2689 }
2690
2691 /*
2692 * Modified from dcn20_acquire_idle_pipe_for_layer
2693 * Check if head_pipe in old_context already has bottom_pipe allocated.
2694 * - If so, check if that pipe is available in the current context.
2695 * -- If so, reuse pipe from old_context
2696 */
2697 head_index = head_pipe->pipe_idx;
2698 pipe = &old_ctx->pipe_ctx[head_index];
2699 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2700 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2701 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
2702 } else {
2703 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2704 if (!idle_pipe)
2705 return NULL;
2706 }
2707
2708 idle_pipe->stream = head_pipe->stream;
2709 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2710 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2711
2712 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2713 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2714 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2715 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2716
2717 return idle_pipe;
2718 }
2719
find_optimal_free_pipe_as_secondary_opp_head(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_otg_master)2720 static int find_optimal_free_pipe_as_secondary_opp_head(
2721 const struct resource_context *cur_res_ctx,
2722 struct resource_context *new_res_ctx,
2723 const struct resource_pool *pool,
2724 const struct pipe_ctx *new_otg_master)
2725 {
2726 const struct pipe_ctx *cur_otg_master;
2727 int free_pipe_idx;
2728
2729 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
2730 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
2731 cur_res_ctx, new_res_ctx, cur_otg_master);
2732
2733 /* Up until here if we have not found a free secondary pipe, we will
2734 * need to wait for at least one frame to complete the transition
2735 * sequence.
2736 */
2737 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2738 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2739 cur_res_ctx, new_res_ctx, pool);
2740
2741 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2742 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2743
2744 return free_pipe_idx;
2745 }
2746
dcn32_acquire_free_pipe_as_secondary_dpp_pipe(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)2747 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
2748 const struct dc_state *cur_ctx,
2749 struct dc_state *new_ctx,
2750 const struct resource_pool *pool,
2751 const struct pipe_ctx *opp_head_pipe)
2752 {
2753
2754 int free_pipe_idx;
2755 struct pipe_ctx *free_pipe;
2756
2757 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
2758 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2759 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2760
2761 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2762 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2763 pool, opp_head_pipe);
2764 if (free_pipe_idx >= 0) {
2765 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2766 free_pipe->pipe_idx = free_pipe_idx;
2767 free_pipe->stream = opp_head_pipe->stream;
2768 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
2769 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
2770
2771 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
2772 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
2773 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
2774 free_pipe->plane_res.mpcc_inst =
2775 pool->dpps[free_pipe->pipe_idx]->inst;
2776 } else {
2777 ASSERT(opp_head_pipe);
2778 free_pipe = NULL;
2779 }
2780
2781 return free_pipe;
2782 }
2783
dcn32_acquire_free_pipe_as_secondary_opp_head(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * otg_master)2784 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
2785 const struct dc_state *cur_ctx,
2786 struct dc_state *new_ctx,
2787 const struct resource_pool *pool,
2788 const struct pipe_ctx *otg_master)
2789 {
2790 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
2791 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2792 pool, otg_master);
2793 struct pipe_ctx *free_pipe;
2794
2795 if (free_pipe_idx >= 0) {
2796 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2797 free_pipe->pipe_idx = free_pipe_idx;
2798 free_pipe->stream = otg_master->stream;
2799 free_pipe->stream_res.tg = otg_master->stream_res.tg;
2800 free_pipe->stream_res.dsc = NULL;
2801 free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
2802 free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
2803 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
2804 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
2805 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
2806 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
2807 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
2808 free_pipe->hblank_borrow = otg_master->hblank_borrow;
2809 if (free_pipe->stream->timing.flags.DSC == 1) {
2810 dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
2811 &new_ctx->res_ctx,
2812 &free_pipe->stream_res.dsc,
2813 free_pipe_idx);
2814 ASSERT(free_pipe->stream_res.dsc);
2815 if (free_pipe->stream_res.dsc == NULL) {
2816 memset(free_pipe, 0, sizeof(*free_pipe));
2817 free_pipe = NULL;
2818 }
2819 }
2820 } else {
2821 ASSERT(otg_master);
2822 free_pipe = NULL;
2823 }
2824
2825 return free_pipe;
2826 }
2827
dcn32_calc_num_avail_chans_for_mall(struct dc * dc,int num_chans)2828 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
2829 {
2830 /*
2831 * DCN32 and DCN321 SKUs may have different sizes for MALL
2832 * but we may not be able to access all the MALL space.
2833 * If the num_chans is power of 2, then we can access all
2834 * of the available MALL space. Otherwise, we can only
2835 * access:
2836 *
2837 * max_cab_size_in_bytes = total_cache_size_in_bytes *
2838 * ((2^floor(log2(num_chans)))/num_chans)
2839 *
2840 * Calculating the MALL sizes for all available SKUs, we
2841 * have come up with the follow simplified check.
2842 * - we have max_chans which provides the max MALL size.
2843 * Each chans supports 4MB of MALL so:
2844 *
2845 * total_cache_size_in_bytes = max_chans * 4 MB
2846 *
2847 * - we have avail_chans which shows the number of channels
2848 * we can use if we can't access the entire MALL space.
2849 * It is generally half of max_chans
2850 * - so we use the following checks:
2851 *
2852 * if (num_chans == max_chans), return max_chans
2853 * if (num_chans < max_chans), return avail_chans
2854 *
2855 * - exception is GC_11_0_0 where we can't access max_chans,
2856 * so we define max_avail_chans as the maximum available
2857 * MALL space
2858 *
2859 */
2860 int gc_11_0_0_max_chans = 48;
2861 int gc_11_0_0_max_avail_chans = 32;
2862 int gc_11_0_0_avail_chans = 16;
2863 int gc_11_0_3_max_chans = 16;
2864 int gc_11_0_3_avail_chans = 8;
2865 int gc_11_0_2_max_chans = 8;
2866 int gc_11_0_2_avail_chans = 4;
2867
2868 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {
2869 return (num_chans == gc_11_0_0_max_chans) ?
2870 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;
2871 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {
2872 return (num_chans == gc_11_0_2_max_chans) ?
2873 gc_11_0_2_max_chans : gc_11_0_2_avail_chans;
2874 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {
2875 return (num_chans == gc_11_0_3_max_chans) ?
2876 gc_11_0_3_max_chans : gc_11_0_3_avail_chans;
2877 }
2878 }
2879