1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn32/dcn32_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn32/dcn32_resource.h"
35 #include "dcn321_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39
40 #include "dml/dcn321/dcn321_fpu.h"
41
42 #include "dcn10/dcn10_ipp.h"
43 #include "dcn30/dcn30_hubbub.h"
44 #include "dcn31/dcn31_hubbub.h"
45 #include "dcn32/dcn32_hubbub.h"
46 #include "dcn32/dcn32_mpc.h"
47 #include "dcn32/dcn32_hubp.h"
48 #include "irq/dcn32/irq_service_dcn32.h"
49 #include "dcn32/dcn32_dpp.h"
50 #include "dcn32/dcn32_optc.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_hwseq.h"
53 #include "dce110/dce110_hwseq.h"
54 #include "dcn30/dcn30_opp.h"
55 #include "dcn20/dcn20_dsc.h"
56 #include "dcn30/dcn30_vpg.h"
57 #include "dcn30/dcn30_afmt.h"
58 #include "dcn30/dcn30_dio_stream_encoder.h"
59 #include "dcn32/dcn32_dio_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
63 #include "dcn31/dcn31_apg.h"
64 #include "dcn31/dcn31_dio_link_encoder.h"
65 #include "dcn32/dcn32_dio_link_encoder.h"
66 #include "dcn321/dcn321_dio_link_encoder.h"
67 #include "dce/dce_clock_source.h"
68 #include "dce/dce_audio.h"
69 #include "dce/dce_hwseq.h"
70 #include "clk_mgr.h"
71 #include "dio/virtual/virtual_stream_encoder.h"
72 #include "dio/dcn10/dcn10_dio.h"
73 #include "dml/display_mode_vba.h"
74 #include "dcn32/dcn32_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "link_service.h"
77 #include "dcn31/dcn31_panel_cntl.h"
78
79 #include "dcn30/dcn30_dwb.h"
80 #include "dcn32/dcn32_mmhubbub.h"
81
82 #include "dcn/dcn_3_2_1_offset.h"
83 #include "dcn/dcn_3_2_1_sh_mask.h"
84 #include "nbio/nbio_4_3_0_offset.h"
85
86 #include "reg_helper.h"
87 #include "dce/dmub_abm.h"
88 #include "dce/dmub_psr.h"
89 #include "dce/dce_aux.h"
90 #include "dce/dce_i2c.h"
91
92 #include "dml/dcn30/display_mode_vba_30.h"
93 #include "vm_helper.h"
94 #include "dcn20/dcn20_vmid.h"
95
96 #include "dc_state_priv.h"
97
98 #define DC_LOGGER_INIT(logger)
99
100 enum dcn321_clk_src_array_id {
101 DCN321_CLK_SRC_PLL0,
102 DCN321_CLK_SRC_PLL1,
103 DCN321_CLK_SRC_PLL2,
104 DCN321_CLK_SRC_PLL3,
105 DCN321_CLK_SRC_PLL4,
106 DCN321_CLK_SRC_TOTAL
107 };
108
109 /* begin *********************
110 * macros to expend register list macro defined in HW object header file
111 */
112
113 /* DCN */
114 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
115
116 #define BASE(seg) BASE_INNER(seg)
117
118 #define SR(reg_name)\
119 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
120 reg ## reg_name
121 #define SR_ARR(reg_name, id)\
122 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
123 reg ## reg_name
124 #define SR_ARR_INIT(reg_name, id, value)\
125 REG_STRUCT[id].reg_name = value
126
127 #define SRI(reg_name, block, id)\
128 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
129 reg ## block ## id ## _ ## reg_name
130
131 #define SRI_ARR(reg_name, block, id)\
132 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 reg ## block ## id ## _ ## reg_name
134
135 #define SR_ARR_I2C(reg_name, id) \
136 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
137
138 #define SRI_ARR_I2C(reg_name, block, id)\
139 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
140 reg ## block ## id ## _ ## reg_name
141
142 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
143 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
144 reg ## block ## id ## _ ## reg_name
145
146 #define SRI2(reg_name, block, id)\
147 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
148 reg ## reg_name
149 #define SRI2_ARR(reg_name, block, id)\
150 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
151 reg ## reg_name
152
153 #define SRIR(var_name, reg_name, block, id)\
154 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## reg_name
156
157 #define SRII(reg_name, block, id)\
158 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 reg ## block ## id ## _ ## reg_name
160
161 #define SRII_ARR_2(reg_name, block, id, inst)\
162 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 reg ## block ## id ## _ ## reg_name
164
165 #define SRII_MPC_RMU(reg_name, block, id)\
166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
168
169 #define SRII_DWB(reg_name, temp_name, block, id)\
170 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## temp_name
172
173 #define DCCG_SRII(reg_name, block, id)\
174 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## reg_name
176
177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
178 .field_name = reg_name ## __ ## field_name ## post_fix
179
180 #define VUPDATE_SRII(reg_name, block, id)\
181 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
182 reg ## reg_name ## _ ## block ## id
183
184 /* NBIO */
185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
186
187 #define NBIO_BASE(seg) \
188 NBIO_BASE_INNER(seg)
189
190 #define NBIO_SR(reg_name)\
191 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
192 regBIF_BX0_ ## reg_name
193 #define NBIO_SR_ARR(reg_name, id)\
194 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
195 regBIF_BX0_ ## reg_name
196
197 #define CTX ctx
198 #define REG(reg_name) \
199 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
200
201 static struct bios_registers bios_regs;
202
203 #define bios_regs_init() \
204 ( \
205 NBIO_SR(BIOS_SCRATCH_3),\
206 NBIO_SR(BIOS_SCRATCH_6)\
207 )
208
209 #define clk_src_regs_init(index, pllid)\
210 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
211
212 static struct dce110_clk_src_regs clk_src_regs[5];
213
214 static const struct dce110_clk_src_shift cs_shift = {
215 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
216 };
217
218 static const struct dce110_clk_src_mask cs_mask = {
219 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
220 };
221
222 #define abm_regs_init(id)\
223 ABM_DCN32_REG_LIST_RI(id)
224
225 static struct dce_abm_registers abm_regs[4];
226
227 static const struct dce_abm_shift abm_shift = {
228 ABM_MASK_SH_LIST_DCN32(__SHIFT)
229 };
230
231 static const struct dce_abm_mask abm_mask = {
232 ABM_MASK_SH_LIST_DCN32(_MASK)
233 };
234
235 #define audio_regs_init(id)\
236 AUD_COMMON_REG_LIST_RI(id)
237
238 static struct dce_audio_registers audio_regs[5];
239
240 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
242 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
243 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
244
245 static const struct dce_audio_shift audio_shift = {
246 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
247 };
248
249 static const struct dce_audio_mask audio_mask = {
250 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
251 };
252
253 #define vpg_regs_init(id)\
254 VPG_DCN3_REG_LIST_RI(id)
255
256 static struct dcn30_vpg_registers vpg_regs[10];
257
258 static const struct dcn30_vpg_shift vpg_shift = {
259 DCN3_VPG_MASK_SH_LIST(__SHIFT)
260 };
261
262 static const struct dcn30_vpg_mask vpg_mask = {
263 DCN3_VPG_MASK_SH_LIST(_MASK)
264 };
265
266 #define afmt_regs_init(id)\
267 AFMT_DCN3_REG_LIST_RI(id)
268
269 static struct dcn30_afmt_registers afmt_regs[6];
270
271 static const struct dcn30_afmt_shift afmt_shift = {
272 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
273 };
274
275 static const struct dcn30_afmt_mask afmt_mask = {
276 DCN3_AFMT_MASK_SH_LIST(_MASK)
277 };
278
279 #define apg_regs_init(id)\
280 APG_DCN31_REG_LIST_RI(id)
281
282 static struct dcn31_apg_registers apg_regs[4];
283
284 static const struct dcn31_apg_shift apg_shift = {
285 DCN31_APG_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dcn31_apg_mask apg_mask = {
289 DCN31_APG_MASK_SH_LIST(_MASK)
290 };
291
292 #define stream_enc_regs_init(id)\
293 SE_DCN32_REG_LIST_RI(id)
294
295 static struct dcn10_stream_enc_registers stream_enc_regs[5];
296
297 static const struct dcn10_stream_encoder_shift se_shift = {
298 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
299 };
300
301 static const struct dcn10_stream_encoder_mask se_mask = {
302 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
303 };
304
305
306 #define aux_regs_init(id)\
307 DCN2_AUX_REG_LIST_RI(id)
308
309 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
310
311 #define hpd_regs_init(id)\
312 HPD_REG_LIST_RI(id)
313
314 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
315
316 #define link_regs_init(id, phyid)\
317 ( \
318 LE_DCN31_REG_LIST_RI(id), \
319 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
320 )
321 /*DPCS_DCN31_REG_LIST(id),*/ \
322
323 static struct dcn10_link_enc_registers link_enc_regs[5];
324
325 static const struct dcn10_link_enc_shift le_shift = {
326 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
327 // DPCS_DCN31_MASK_SH_LIST(__SHIFT)
328 };
329
330 static const struct dcn10_link_enc_mask le_mask = {
331 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
332 // DPCS_DCN31_MASK_SH_LIST(_MASK)
333 };
334
335 #define hpo_dp_stream_encoder_reg_init(id)\
336 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
337
338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
339
340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
345 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
346 };
347
348
349 #define hpo_dp_link_encoder_reg_init(id)\
350 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
351 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
354 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
355
356 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
357
358 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
360 };
361
362 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
363 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
364 };
365
366 #define dpp_regs_init(id)\
367 DPP_REG_LIST_DCN30_COMMON_RI(id)
368
369 static struct dcn3_dpp_registers dpp_regs[4];
370
371 static const struct dcn3_dpp_shift tf_shift = {
372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
373 };
374
375 static const struct dcn3_dpp_mask tf_mask = {
376 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
377 };
378
379
380 #define opp_regs_init(id)\
381 OPP_REG_LIST_DCN30_RI(id)
382
383 static struct dcn20_opp_registers opp_regs[4];
384
385 static const struct dcn20_opp_shift opp_shift = {
386 OPP_MASK_SH_LIST_DCN20(__SHIFT)
387 };
388
389 static const struct dcn20_opp_mask opp_mask = {
390 OPP_MASK_SH_LIST_DCN20(_MASK)
391 };
392
393 #define aux_engine_regs_init(id) \
394 ( \
395 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
399 )
400
401 static struct dce110_aux_registers aux_engine_regs[5];
402
403 static const struct dce110_aux_registers_shift aux_shift = {
404 DCN_AUX_MASK_SH_LIST(__SHIFT)
405 };
406
407 static const struct dce110_aux_registers_mask aux_mask = {
408 DCN_AUX_MASK_SH_LIST(_MASK)
409 };
410
411 #define dwbc_regs_dcn3_init(id)\
412 DWBC_COMMON_REG_LIST_DCN30_RI(id)
413
414 static struct dcn30_dwbc_registers dwbc30_regs[1];
415
416 static const struct dcn30_dwbc_shift dwbc30_shift = {
417 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
418 };
419
420 static const struct dcn30_dwbc_mask dwbc30_mask = {
421 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
422 };
423
424 #define mcif_wb_regs_dcn3_init(id)\
425 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
426
427 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
428
429 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
430 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
431 };
432
433 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
434 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
435 };
436
437 #define dsc_regsDCN20_init(id)\
438 DSC_REG_LIST_DCN20_RI(id)
439
440 static struct dcn20_dsc_registers dsc_regs[4];
441
442 static const struct dcn20_dsc_shift dsc_shift = {
443 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
444 };
445
446 static const struct dcn20_dsc_mask dsc_mask = {
447 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
448 };
449
450 static struct dcn30_mpc_registers mpc_regs;
451 #define dcn_mpc_regs_init()\
452 MPC_REG_LIST_DCN3_2_RI(0),\
453 MPC_REG_LIST_DCN3_2_RI(1),\
454 MPC_REG_LIST_DCN3_2_RI(2),\
455 MPC_REG_LIST_DCN3_2_RI(3),\
456 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
460 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
461
462 static const struct dcn30_mpc_shift mpc_shift = {
463 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
464 };
465
466 static const struct dcn30_mpc_mask mpc_mask = {
467 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
468 };
469
470 #define optc_regs_init(id)\
471 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
472
473 static struct dcn_optc_registers optc_regs[4];
474
475 static const struct dcn_optc_shift optc_shift = {
476 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
477 };
478
479 static const struct dcn_optc_mask optc_mask = {
480 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
481 };
482
483 #define hubp_regs_init(id) \
484 HUBP_REG_LIST_DCN32_RI(id)
485
486 static struct dcn_hubp2_registers hubp_regs[4];
487
488 static const struct dcn_hubp2_shift hubp_shift = {
489 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
490 };
491
492 static const struct dcn_hubp2_mask hubp_mask = {
493 HUBP_MASK_SH_LIST_DCN32(_MASK)
494 };
495
496 static struct dcn_hubbub_registers hubbub_reg;
497 #define hubbub_reg_init()\
498 HUBBUB_REG_LIST_DCN32_RI(0)
499
500 static const struct dcn_hubbub_shift hubbub_shift = {
501 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
502 };
503
504 static const struct dcn_hubbub_mask hubbub_mask = {
505 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
506 };
507
508 static struct dccg_registers dccg_regs;
509
510 #define dccg_regs_init()\
511 DCCG_REG_LIST_DCN32_RI()
512
513 static const struct dccg_shift dccg_shift = {
514 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
515 };
516
517 static const struct dccg_mask dccg_mask = {
518 DCCG_MASK_SH_LIST_DCN32(_MASK)
519 };
520
521
522 #define SRII2(reg_name_pre, reg_name_post, id)\
523 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
524 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
525 reg ## reg_name_pre ## id ## _ ## reg_name_post
526
527
528 #define HWSEQ_DCN32_REG_LIST()\
529 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
530 SR(DIO_MEM_PWR_CTRL), \
531 SR(ODM_MEM_PWR_CTRL3), \
532 SR(MMHUBBUB_MEM_PWR_CNTL), \
533 SR(DCCG_GATE_DISABLE_CNTL), \
534 SR(DCCG_GATE_DISABLE_CNTL2), \
535 SR(DCFCLK_CNTL),\
536 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
537 SRII(PIXEL_RATE_CNTL, OTG, 0), \
538 SRII(PIXEL_RATE_CNTL, OTG, 1),\
539 SRII(PIXEL_RATE_CNTL, OTG, 2),\
540 SRII(PIXEL_RATE_CNTL, OTG, 3),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
545 SR(MICROSECOND_TIME_BASE_DIV), \
546 SR(MILLISECOND_TIME_BASE_DIV), \
547 SR(DISPCLK_FREQ_CHANGE_CNTL), \
548 SR(RBBMIF_TIMEOUT_DIS), \
549 SR(RBBMIF_TIMEOUT_DIS_2), \
550 SR(DCHUBBUB_CRC_CTRL), \
551 SR(DPP_TOP0_DPP_CRC_CTRL), \
552 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
553 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
554 SR(MPC_CRC_CTRL), \
555 SR(MPC_CRC_RESULT_GB), \
556 SR(MPC_CRC_RESULT_C), \
557 SR(MPC_CRC_RESULT_AR), \
558 SR(DOMAIN0_PG_CONFIG), \
559 SR(DOMAIN1_PG_CONFIG), \
560 SR(DOMAIN2_PG_CONFIG), \
561 SR(DOMAIN3_PG_CONFIG), \
562 SR(DOMAIN16_PG_CONFIG), \
563 SR(DOMAIN17_PG_CONFIG), \
564 SR(DOMAIN18_PG_CONFIG), \
565 SR(DOMAIN19_PG_CONFIG), \
566 SR(DOMAIN0_PG_STATUS), \
567 SR(DOMAIN1_PG_STATUS), \
568 SR(DOMAIN2_PG_STATUS), \
569 SR(DOMAIN3_PG_STATUS), \
570 SR(DOMAIN16_PG_STATUS), \
571 SR(DOMAIN17_PG_STATUS), \
572 SR(DOMAIN18_PG_STATUS), \
573 SR(DOMAIN19_PG_STATUS), \
574 SR(D1VGA_CONTROL), \
575 SR(D2VGA_CONTROL), \
576 SR(D3VGA_CONTROL), \
577 SR(D4VGA_CONTROL), \
578 SR(D5VGA_CONTROL), \
579 SR(D6VGA_CONTROL), \
580 SR(DC_IP_REQUEST_CNTL), \
581 SR(AZALIA_AUDIO_DTO), \
582 SR(AZALIA_CONTROLLER_CLOCK_GATING)
583
584 static struct dce_hwseq_registers hwseq_reg;
585
586 #define hwseq_reg_init()\
587 HWSEQ_DCN32_REG_LIST()
588
589 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
590 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
591 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
592 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
593 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
594 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
595 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
596 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
597 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
598 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
599 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
600 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
601 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
602 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
603 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
604 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
605 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
606 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
607 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
608 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
615 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
616 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
617 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
618 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
619 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
620 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
621 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
622
623 static const struct dce_hwseq_shift hwseq_shift = {
624 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
625 };
626
627 static const struct dce_hwseq_mask hwseq_mask = {
628 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
629 };
630 #define vmid_regs_init(id)\
631 DCN20_VMID_REG_LIST_RI(id)
632
633 static struct dcn_vmid_registers vmid_regs[16];
634
635 static const struct dcn20_vmid_shift vmid_shifts = {
636 DCN20_VMID_MASK_SH_LIST(__SHIFT)
637 };
638
639 static const struct dcn20_vmid_mask vmid_masks = {
640 DCN20_VMID_MASK_SH_LIST(_MASK)
641 };
642
643 static struct dcn_dio_registers dio_regs;
644
645 #define DIO_MASK_SH_LIST(mask_sh)\
646 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
647
648 static const struct dcn_dio_shift dio_shift = {
649 DIO_MASK_SH_LIST(__SHIFT)
650 };
651
652 static const struct dcn_dio_mask dio_mask = {
653 DIO_MASK_SH_LIST(_MASK)
654 };
655
656 static const struct resource_caps res_cap_dcn321 = {
657 .num_timing_generator = 4,
658 .num_opp = 4,
659 .num_video_plane = 4,
660 .num_audio = 5,
661 .num_stream_encoder = 5,
662 .num_hpo_dp_stream_encoder = 4,
663 .num_hpo_dp_link_encoder = 2,
664 .num_pll = 5,
665 .num_dwb = 1,
666 .num_ddc = 5,
667 .num_vmid = 16,
668 .num_mpc_3dlut = 4,
669 .num_dsc = 4,
670 };
671
672 static const struct dc_plane_cap plane_cap = {
673 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
674 .per_pixel_alpha = true,
675
676 .pixel_format_support = {
677 .argb8888 = true,
678 .nv12 = true,
679 .fp16 = true,
680 .p010 = true,
681 .ayuv = false,
682 },
683
684 .max_upscale_factor = {
685 .argb8888 = 16000,
686 .nv12 = 16000,
687 .fp16 = 16000
688 },
689
690 // 6:1 downscaling ratio: 1000/6 = 166.666
691 .max_downscale_factor = {
692 .argb8888 = 167,
693 .nv12 = 167,
694 .fp16 = 167
695 },
696 64,
697 64
698 };
699
700 static const struct dc_debug_options debug_defaults_drv = {
701 .disable_dmcu = true,
702 .force_abm_enable = false,
703 .clock_trace = true,
704 .disable_pplib_clock_request = false,
705 .pipe_split_policy = MPC_SPLIT_AVOID,
706 .force_single_disp_pipe_split = false,
707 .disable_dcc = DCC_ENABLE,
708 .vsr_support = true,
709 .performance_trace = false,
710 .max_downscale_src_width = 7680,/*upto 8K*/
711 .disable_pplib_wm_range = false,
712 .scl_reset_length10 = true,
713 .sanity_checks = false,
714 .underflow_assert_delay_us = 0xFFFFFFFF,
715 .dwb_fi_phase = -1, // -1 = disable,
716 .dmub_command_table = true,
717 .enable_mem_low_power = {
718 .bits = {
719 .vga = false,
720 .i2c = false,
721 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
722 .dscl = false,
723 .cm = false,
724 .mpc = false,
725 .optc = true,
726 }
727 },
728 .use_max_lb = true,
729 .force_disable_subvp = false,
730 .exit_idle_opt_for_cursor_updates = true,
731 .enable_single_display_2to1_odm_policy = true,
732
733 /*must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
734 .enable_double_buffered_dsc_pg_support = true,
735 .enable_dp_dig_pixel_rate_div_policy = 1,
736 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
737 .alloc_extra_way_for_cursor = true,
738 .min_prefetch_in_strobe_ns = 60000, // 60us
739 .disable_unbounded_requesting = false,
740 .override_dispclk_programming = true,
741 .disable_fpo_optimizations = false,
742 .fpo_vactive_margin_us = 2000, // 2000us
743 .disable_fpo_vactive = false,
744 .disable_boot_optimizations = false,
745 .disable_subvp_high_refresh = false,
746 .fpo_vactive_min_active_margin_us = 200,
747 .fpo_vactive_max_blank_us = 1000,
748 .disable_dc_mode_overwrite = true,
749 .using_dml2 = false,
750 };
751
752 static const struct dc_check_config config_defaults = {
753 .enable_legacy_fast_update = false,
754 };
755
dcn321_aux_engine_create(struct dc_context * ctx,uint32_t inst)756 static struct dce_aux *dcn321_aux_engine_create(
757 struct dc_context *ctx,
758 uint32_t inst)
759 {
760 struct aux_engine_dce110 *aux_engine =
761 kzalloc_obj(struct aux_engine_dce110);
762
763 if (!aux_engine)
764 return NULL;
765
766 #undef REG_STRUCT
767 #define REG_STRUCT aux_engine_regs
768 aux_engine_regs_init(0),
769 aux_engine_regs_init(1),
770 aux_engine_regs_init(2),
771 aux_engine_regs_init(3),
772 aux_engine_regs_init(4);
773
774 dce110_aux_engine_construct(aux_engine, ctx, inst,
775 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
776 &aux_engine_regs[inst],
777 &aux_mask,
778 &aux_shift,
779 ctx->dc->caps.extended_aux_timeout_support);
780
781 return &aux_engine->base;
782 }
783 #define i2c_inst_regs_init(id)\
784 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
785
786 static struct dce_i2c_registers i2c_hw_regs[5];
787
788 static const struct dce_i2c_shift i2c_shifts = {
789 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
790 };
791
792 static const struct dce_i2c_mask i2c_masks = {
793 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
794 };
795
dcn321_i2c_hw_create(struct dc_context * ctx,uint32_t inst)796 static struct dce_i2c_hw *dcn321_i2c_hw_create(
797 struct dc_context *ctx,
798 uint32_t inst)
799 {
800 struct dce_i2c_hw *dce_i2c_hw =
801 kzalloc_obj(struct dce_i2c_hw);
802
803 if (!dce_i2c_hw)
804 return NULL;
805
806 #undef REG_STRUCT
807 #define REG_STRUCT i2c_hw_regs
808 i2c_inst_regs_init(1),
809 i2c_inst_regs_init(2),
810 i2c_inst_regs_init(3),
811 i2c_inst_regs_init(4),
812 i2c_inst_regs_init(5);
813
814 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
815 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
816
817 return dce_i2c_hw;
818 }
819
dcn321_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)820 static struct clock_source *dcn321_clock_source_create(
821 struct dc_context *ctx,
822 struct dc_bios *bios,
823 enum clock_source_id id,
824 const struct dce110_clk_src_regs *regs,
825 bool dp_clk_src)
826 {
827 struct dce110_clk_src *clk_src =
828 kzalloc_obj(struct dce110_clk_src);
829
830 if (!clk_src)
831 return NULL;
832
833 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
834 regs, &cs_shift, &cs_mask)) {
835 clk_src->base.dp_clk_src = dp_clk_src;
836 return &clk_src->base;
837 }
838
839 kfree(clk_src);
840 BREAK_TO_DEBUGGER();
841 return NULL;
842 }
843
dcn321_dio_create(struct dc_context * ctx)844 static struct dio *dcn321_dio_create(struct dc_context *ctx)
845 {
846 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
847
848 if (!dio10)
849 return NULL;
850
851 #undef REG_STRUCT
852 #define REG_STRUCT dio_regs
853 DIO_REG_LIST_DCN10();
854
855 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
856
857 return &dio10->base;
858 }
859
dcn321_hubbub_create(struct dc_context * ctx)860 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
861 {
862 int i;
863
864 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
865
866 if (!hubbub2)
867 return NULL;
868
869 #undef REG_STRUCT
870 #define REG_STRUCT hubbub_reg
871 hubbub_reg_init();
872
873 #undef REG_STRUCT
874 #define REG_STRUCT vmid_regs
875 vmid_regs_init(0),
876 vmid_regs_init(1),
877 vmid_regs_init(2),
878 vmid_regs_init(3),
879 vmid_regs_init(4),
880 vmid_regs_init(5),
881 vmid_regs_init(6),
882 vmid_regs_init(7),
883 vmid_regs_init(8),
884 vmid_regs_init(9),
885 vmid_regs_init(10),
886 vmid_regs_init(11),
887 vmid_regs_init(12),
888 vmid_regs_init(13),
889 vmid_regs_init(14),
890 vmid_regs_init(15);
891
892 hubbub32_construct(hubbub2, ctx,
893 &hubbub_reg,
894 &hubbub_shift,
895 &hubbub_mask,
896 ctx->dc->dml.ip.det_buffer_size_kbytes,
897 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
898 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
899
900
901 for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
902 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
903
904 vmid->ctx = ctx;
905
906 vmid->regs = &vmid_regs[i];
907 vmid->shifts = &vmid_shifts;
908 vmid->masks = &vmid_masks;
909 }
910
911 return &hubbub2->base;
912 }
913
dcn321_hubp_create(struct dc_context * ctx,uint32_t inst)914 static struct hubp *dcn321_hubp_create(
915 struct dc_context *ctx,
916 uint32_t inst)
917 {
918 struct dcn20_hubp *hubp2 =
919 kzalloc_obj(struct dcn20_hubp);
920
921 if (!hubp2)
922 return NULL;
923
924 #undef REG_STRUCT
925 #define REG_STRUCT hubp_regs
926 hubp_regs_init(0),
927 hubp_regs_init(1),
928 hubp_regs_init(2),
929 hubp_regs_init(3);
930
931 if (hubp32_construct(hubp2, ctx, inst,
932 &hubp_regs[inst], &hubp_shift, &hubp_mask))
933 return &hubp2->base;
934
935 BREAK_TO_DEBUGGER();
936 kfree(hubp2);
937 return NULL;
938 }
939
dcn321_dpp_destroy(struct dpp ** dpp)940 static void dcn321_dpp_destroy(struct dpp **dpp)
941 {
942 kfree(TO_DCN30_DPP(*dpp));
943 *dpp = NULL;
944 }
945
dcn321_dpp_create(struct dc_context * ctx,uint32_t inst)946 static struct dpp *dcn321_dpp_create(
947 struct dc_context *ctx,
948 uint32_t inst)
949 {
950 struct dcn3_dpp *dpp3 =
951 kzalloc_obj(struct dcn3_dpp);
952
953 if (!dpp3)
954 return NULL;
955
956 #undef REG_STRUCT
957 #define REG_STRUCT dpp_regs
958 dpp_regs_init(0),
959 dpp_regs_init(1),
960 dpp_regs_init(2),
961 dpp_regs_init(3);
962
963 if (dpp32_construct(dpp3, ctx, inst,
964 &dpp_regs[inst], &tf_shift, &tf_mask))
965 return &dpp3->base;
966
967 BREAK_TO_DEBUGGER();
968 kfree(dpp3);
969 return NULL;
970 }
971
dcn321_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)972 static struct mpc *dcn321_mpc_create(
973 struct dc_context *ctx,
974 int num_mpcc,
975 int num_rmu)
976 {
977 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
978
979 if (!mpc30)
980 return NULL;
981
982 #undef REG_STRUCT
983 #define REG_STRUCT mpc_regs
984 dcn_mpc_regs_init();
985
986 dcn32_mpc_construct(mpc30, ctx,
987 &mpc_regs,
988 &mpc_shift,
989 &mpc_mask,
990 num_mpcc,
991 num_rmu);
992
993 return &mpc30->base;
994 }
995
dcn321_opp_create(struct dc_context * ctx,uint32_t inst)996 static struct output_pixel_processor *dcn321_opp_create(
997 struct dc_context *ctx, uint32_t inst)
998 {
999 struct dcn20_opp *opp2 =
1000 kzalloc_obj(struct dcn20_opp);
1001
1002 if (!opp2) {
1003 BREAK_TO_DEBUGGER();
1004 return NULL;
1005 }
1006
1007 #undef REG_STRUCT
1008 #define REG_STRUCT opp_regs
1009 opp_regs_init(0),
1010 opp_regs_init(1),
1011 opp_regs_init(2),
1012 opp_regs_init(3);
1013
1014 dcn20_opp_construct(opp2, ctx, inst,
1015 &opp_regs[inst], &opp_shift, &opp_mask);
1016 return &opp2->base;
1017 }
1018
1019
dcn321_timing_generator_create(struct dc_context * ctx,uint32_t instance)1020 static struct timing_generator *dcn321_timing_generator_create(
1021 struct dc_context *ctx,
1022 uint32_t instance)
1023 {
1024 struct optc *tgn10 =
1025 kzalloc_obj(struct optc);
1026
1027 if (!tgn10)
1028 return NULL;
1029
1030 #undef REG_STRUCT
1031 #define REG_STRUCT optc_regs
1032 optc_regs_init(0),
1033 optc_regs_init(1),
1034 optc_regs_init(2),
1035 optc_regs_init(3);
1036
1037 tgn10->base.inst = instance;
1038 tgn10->base.ctx = ctx;
1039
1040 tgn10->tg_regs = &optc_regs[instance];
1041 tgn10->tg_shift = &optc_shift;
1042 tgn10->tg_mask = &optc_mask;
1043
1044 dcn32_timing_generator_init(tgn10);
1045
1046 return &tgn10->base;
1047 }
1048
1049 static const struct encoder_feature_support link_enc_feature = {
1050 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1051 .max_hdmi_pixel_clock = 600000,
1052 .hdmi_ycbcr420_supported = true,
1053 .dp_ycbcr420_supported = true,
1054 .fec_supported = true,
1055 .flags.bits.IS_HBR2_CAPABLE = true,
1056 .flags.bits.IS_HBR3_CAPABLE = true,
1057 .flags.bits.IS_TPS3_CAPABLE = true,
1058 .flags.bits.IS_TPS4_CAPABLE = true
1059 };
1060
dcn321_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1061 static struct link_encoder *dcn321_link_encoder_create(
1062 struct dc_context *ctx,
1063 const struct encoder_init_data *enc_init_data)
1064 {
1065 struct dcn20_link_encoder *enc20 =
1066 kzalloc_obj(struct dcn20_link_encoder);
1067
1068 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1069 return NULL;
1070
1071 #undef REG_STRUCT
1072 #define REG_STRUCT link_enc_aux_regs
1073 aux_regs_init(0),
1074 aux_regs_init(1),
1075 aux_regs_init(2),
1076 aux_regs_init(3),
1077 aux_regs_init(4);
1078
1079 #undef REG_STRUCT
1080 #define REG_STRUCT link_enc_hpd_regs
1081 hpd_regs_init(0),
1082 hpd_regs_init(1),
1083 hpd_regs_init(2),
1084 hpd_regs_init(3),
1085 hpd_regs_init(4);
1086
1087 #undef REG_STRUCT
1088 #define REG_STRUCT link_enc_regs
1089 link_regs_init(0, A),
1090 link_regs_init(1, B),
1091 link_regs_init(2, C),
1092 link_regs_init(3, D),
1093 link_regs_init(4, E);
1094
1095 dcn321_link_encoder_construct(enc20,
1096 enc_init_data,
1097 &link_enc_feature,
1098 &link_enc_regs[enc_init_data->transmitter],
1099 &link_enc_aux_regs[enc_init_data->channel - 1],
1100 &link_enc_hpd_regs[enc_init_data->hpd_source],
1101 &le_shift,
1102 &le_mask);
1103
1104 return &enc20->enc10.base;
1105 }
1106
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1107 static void read_dce_straps(
1108 struct dc_context *ctx,
1109 struct resource_straps *straps)
1110 {
1111 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1112 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1113
1114 }
1115
dcn321_create_audio(struct dc_context * ctx,unsigned int inst)1116 static struct audio *dcn321_create_audio(
1117 struct dc_context *ctx, unsigned int inst)
1118 {
1119
1120 #undef REG_STRUCT
1121 #define REG_STRUCT audio_regs
1122 audio_regs_init(0),
1123 audio_regs_init(1),
1124 audio_regs_init(2),
1125 audio_regs_init(3),
1126 audio_regs_init(4);
1127
1128 return dce_audio_create(ctx, inst,
1129 &audio_regs[inst], &audio_shift, &audio_mask);
1130 }
1131
dcn321_vpg_create(struct dc_context * ctx,uint32_t inst)1132 static struct vpg *dcn321_vpg_create(
1133 struct dc_context *ctx,
1134 uint32_t inst)
1135 {
1136 struct dcn30_vpg *vpg3 = kzalloc_obj(struct dcn30_vpg);
1137
1138 if (!vpg3)
1139 return NULL;
1140
1141 #undef REG_STRUCT
1142 #define REG_STRUCT vpg_regs
1143 vpg_regs_init(0),
1144 vpg_regs_init(1),
1145 vpg_regs_init(2),
1146 vpg_regs_init(3),
1147 vpg_regs_init(4),
1148 vpg_regs_init(5),
1149 vpg_regs_init(6),
1150 vpg_regs_init(7),
1151 vpg_regs_init(8),
1152 vpg_regs_init(9);
1153
1154 vpg3_construct(vpg3, ctx, inst,
1155 &vpg_regs[inst],
1156 &vpg_shift,
1157 &vpg_mask);
1158
1159 return &vpg3->base;
1160 }
1161
dcn321_afmt_create(struct dc_context * ctx,uint32_t inst)1162 static struct afmt *dcn321_afmt_create(
1163 struct dc_context *ctx,
1164 uint32_t inst)
1165 {
1166 struct dcn30_afmt *afmt3 = kzalloc_obj(struct dcn30_afmt);
1167
1168 if (!afmt3)
1169 return NULL;
1170
1171 #undef REG_STRUCT
1172 #define REG_STRUCT afmt_regs
1173 afmt_regs_init(0),
1174 afmt_regs_init(1),
1175 afmt_regs_init(2),
1176 afmt_regs_init(3),
1177 afmt_regs_init(4),
1178 afmt_regs_init(5);
1179
1180 afmt3_construct(afmt3, ctx, inst,
1181 &afmt_regs[inst],
1182 &afmt_shift,
1183 &afmt_mask);
1184
1185 return &afmt3->base;
1186 }
1187
dcn321_apg_create(struct dc_context * ctx,uint32_t inst)1188 static struct apg *dcn321_apg_create(
1189 struct dc_context *ctx,
1190 uint32_t inst)
1191 {
1192 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1193
1194 if (!apg31)
1195 return NULL;
1196
1197 #undef REG_STRUCT
1198 #define REG_STRUCT apg_regs
1199 apg_regs_init(0),
1200 apg_regs_init(1),
1201 apg_regs_init(2),
1202 apg_regs_init(3);
1203
1204 apg31_construct(apg31, ctx, inst,
1205 &apg_regs[inst],
1206 &apg_shift,
1207 &apg_mask);
1208
1209 return &apg31->base;
1210 }
1211
dcn321_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1212 static struct stream_encoder *dcn321_stream_encoder_create(
1213 enum engine_id eng_id,
1214 struct dc_context *ctx)
1215 {
1216 struct dcn10_stream_encoder *enc1;
1217 struct vpg *vpg;
1218 struct afmt *afmt;
1219 int vpg_inst;
1220 int afmt_inst;
1221
1222 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1223 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1224 return NULL;
1225
1226 vpg_inst = eng_id;
1227 afmt_inst = eng_id;
1228
1229 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1230 vpg = dcn321_vpg_create(ctx, vpg_inst);
1231 afmt = dcn321_afmt_create(ctx, afmt_inst);
1232
1233 if (!enc1 || !vpg || !afmt) {
1234 kfree(enc1);
1235 kfree(vpg);
1236 kfree(afmt);
1237 return NULL;
1238 }
1239
1240 #undef REG_STRUCT
1241 #define REG_STRUCT stream_enc_regs
1242 stream_enc_regs_init(0),
1243 stream_enc_regs_init(1),
1244 stream_enc_regs_init(2),
1245 stream_enc_regs_init(3),
1246 stream_enc_regs_init(4);
1247
1248 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1249 eng_id, vpg, afmt,
1250 &stream_enc_regs[eng_id],
1251 &se_shift, &se_mask);
1252
1253 return &enc1->base;
1254 }
1255
dcn321_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1256 static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1257 enum engine_id eng_id,
1258 struct dc_context *ctx)
1259 {
1260 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1261 struct vpg *vpg;
1262 struct apg *apg;
1263 uint32_t hpo_dp_inst;
1264 uint32_t vpg_inst;
1265 uint32_t apg_inst;
1266
1267 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1268 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1269
1270 /* Mapping of VPG register blocks to HPO DP block instance:
1271 * VPG[6] -> HPO_DP[0]
1272 * VPG[7] -> HPO_DP[1]
1273 * VPG[8] -> HPO_DP[2]
1274 * VPG[9] -> HPO_DP[3]
1275 */
1276 vpg_inst = hpo_dp_inst + 6;
1277
1278 /* Mapping of APG register blocks to HPO DP block instance:
1279 * APG[0] -> HPO_DP[0]
1280 * APG[1] -> HPO_DP[1]
1281 * APG[2] -> HPO_DP[2]
1282 * APG[3] -> HPO_DP[3]
1283 */
1284 apg_inst = hpo_dp_inst;
1285
1286 /* allocate HPO stream encoder and create VPG sub-block */
1287 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1288 vpg = dcn321_vpg_create(ctx, vpg_inst);
1289 apg = dcn321_apg_create(ctx, apg_inst);
1290
1291 if (!hpo_dp_enc31 || !vpg || !apg) {
1292 kfree(hpo_dp_enc31);
1293 kfree(vpg);
1294 kfree(apg);
1295 return NULL;
1296 }
1297
1298 #undef REG_STRUCT
1299 #define REG_STRUCT hpo_dp_stream_enc_regs
1300 hpo_dp_stream_encoder_reg_init(0),
1301 hpo_dp_stream_encoder_reg_init(1),
1302 hpo_dp_stream_encoder_reg_init(2),
1303 hpo_dp_stream_encoder_reg_init(3);
1304
1305 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1306 hpo_dp_inst, eng_id, vpg, apg,
1307 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1308 &hpo_dp_se_shift, &hpo_dp_se_mask);
1309
1310 return &hpo_dp_enc31->base;
1311 }
1312
dcn321_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1313 static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1314 uint8_t inst,
1315 struct dc_context *ctx)
1316 {
1317 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1318
1319 /* allocate HPO link encoder */
1320 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1321 if (!hpo_dp_enc31)
1322 return NULL; /* out of memory */
1323
1324 #undef REG_STRUCT
1325 #define REG_STRUCT hpo_dp_link_enc_regs
1326 hpo_dp_link_encoder_reg_init(0),
1327 hpo_dp_link_encoder_reg_init(1);
1328
1329 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1330 &hpo_dp_link_enc_regs[inst],
1331 &hpo_dp_le_shift, &hpo_dp_le_mask);
1332
1333 return &hpo_dp_enc31->base;
1334 }
1335
dcn321_hwseq_create(struct dc_context * ctx)1336 static struct dce_hwseq *dcn321_hwseq_create(
1337 struct dc_context *ctx)
1338 {
1339 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1340
1341 #undef REG_STRUCT
1342 #define REG_STRUCT hwseq_reg
1343 hwseq_reg_init();
1344
1345 if (hws) {
1346 hws->ctx = ctx;
1347 hws->regs = &hwseq_reg;
1348 hws->shifts = &hwseq_shift;
1349 hws->masks = &hwseq_mask;
1350 }
1351 return hws;
1352 }
1353 static const struct resource_create_funcs res_create_funcs = {
1354 .read_dce_straps = read_dce_straps,
1355 .create_audio = dcn321_create_audio,
1356 .create_stream_encoder = dcn321_stream_encoder_create,
1357 .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1358 .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1359 .create_hwseq = dcn321_hwseq_create,
1360 };
1361
dcn321_resource_destruct(struct dcn321_resource_pool * pool)1362 static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1363 {
1364 unsigned int i;
1365
1366 for (i = 0; i < pool->base.stream_enc_count; i++) {
1367 if (pool->base.stream_enc[i] != NULL) {
1368 if (pool->base.stream_enc[i]->vpg != NULL) {
1369 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1370 pool->base.stream_enc[i]->vpg = NULL;
1371 }
1372 if (pool->base.stream_enc[i]->afmt != NULL) {
1373 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1374 pool->base.stream_enc[i]->afmt = NULL;
1375 }
1376 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1377 pool->base.stream_enc[i] = NULL;
1378 }
1379 }
1380
1381 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1382 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1383 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1384 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1385 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1386 }
1387 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1388 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1389 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1390 }
1391 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1392 pool->base.hpo_dp_stream_enc[i] = NULL;
1393 }
1394 }
1395
1396 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1397 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1398 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1399 pool->base.hpo_dp_link_enc[i] = NULL;
1400 }
1401 }
1402
1403 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1404 if (pool->base.dscs[i] != NULL)
1405 dcn20_dsc_destroy(&pool->base.dscs[i]);
1406 }
1407
1408 if (pool->base.mpc != NULL) {
1409 kfree(TO_DCN20_MPC(pool->base.mpc));
1410 pool->base.mpc = NULL;
1411 }
1412 if (pool->base.hubbub != NULL) {
1413 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1414 pool->base.hubbub = NULL;
1415 }
1416 for (i = 0; i < pool->base.pipe_count; i++) {
1417 if (pool->base.dpps[i] != NULL)
1418 dcn321_dpp_destroy(&pool->base.dpps[i]);
1419
1420 if (pool->base.ipps[i] != NULL)
1421 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1422
1423 if (pool->base.hubps[i] != NULL) {
1424 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1425 pool->base.hubps[i] = NULL;
1426 }
1427
1428 if (pool->base.irqs != NULL)
1429 dal_irq_service_destroy(&pool->base.irqs);
1430 }
1431
1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1433 if (pool->base.engines[i] != NULL)
1434 dce110_engine_destroy(&pool->base.engines[i]);
1435 if (pool->base.hw_i2cs[i] != NULL) {
1436 kfree(pool->base.hw_i2cs[i]);
1437 pool->base.hw_i2cs[i] = NULL;
1438 }
1439 if (pool->base.sw_i2cs[i] != NULL) {
1440 kfree(pool->base.sw_i2cs[i]);
1441 pool->base.sw_i2cs[i] = NULL;
1442 }
1443 }
1444
1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1446 if (pool->base.opps[i] != NULL)
1447 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1448 }
1449
1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1451 if (pool->base.timing_generators[i] != NULL) {
1452 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1453 pool->base.timing_generators[i] = NULL;
1454 }
1455 }
1456
1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1458 if (pool->base.dwbc[i] != NULL) {
1459 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1460 pool->base.dwbc[i] = NULL;
1461 }
1462 if (pool->base.mcif_wb[i] != NULL) {
1463 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1464 pool->base.mcif_wb[i] = NULL;
1465 }
1466 }
1467
1468 for (i = 0; i < pool->base.audio_count; i++) {
1469 if (pool->base.audios[i])
1470 dce_aud_destroy(&pool->base.audios[i]);
1471 }
1472
1473 for (i = 0; i < pool->base.clk_src_count; i++) {
1474 if (pool->base.clock_sources[i] != NULL) {
1475 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1476 pool->base.clock_sources[i] = NULL;
1477 }
1478 }
1479
1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1481 if (pool->base.mpc_lut[i] != NULL) {
1482 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1483 pool->base.mpc_lut[i] = NULL;
1484 }
1485 if (pool->base.mpc_shaper[i] != NULL) {
1486 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1487 pool->base.mpc_shaper[i] = NULL;
1488 }
1489 }
1490
1491 if (pool->base.dp_clock_source != NULL) {
1492 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1493 pool->base.dp_clock_source = NULL;
1494 }
1495
1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1497 if (pool->base.multiple_abms[i] != NULL)
1498 dce_abm_destroy(&pool->base.multiple_abms[i]);
1499 }
1500
1501 if (pool->base.psr != NULL)
1502 dmub_psr_destroy(&pool->base.psr);
1503
1504 if (pool->base.dccg != NULL)
1505 dcn_dccg_destroy(&pool->base.dccg);
1506
1507 if (pool->base.dio != NULL) {
1508 kfree(TO_DCN10_DIO(pool->base.dio));
1509 pool->base.dio = NULL;
1510 }
1511
1512 if (pool->base.oem_device != NULL) {
1513 struct dc *dc = pool->base.oem_device->ctx->dc;
1514
1515 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1516 }
1517 }
1518
1519
dcn321_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1520 static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1521 {
1522 int i;
1523 uint32_t dwb_count = pool->res_cap->num_dwb;
1524
1525 for (i = 0; i < dwb_count; i++) {
1526 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1527
1528 if (!dwbc30) {
1529 dm_error("DC: failed to create dwbc30!\n");
1530 return false;
1531 }
1532
1533 #undef REG_STRUCT
1534 #define REG_STRUCT dwbc30_regs
1535 dwbc_regs_dcn3_init(0);
1536
1537 dcn30_dwbc_construct(dwbc30, ctx,
1538 &dwbc30_regs[i],
1539 &dwbc30_shift,
1540 &dwbc30_mask,
1541 i);
1542
1543 pool->dwbc[i] = &dwbc30->base;
1544 }
1545 return true;
1546 }
1547
dcn321_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1548 static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1549 {
1550 int i;
1551 uint32_t dwb_count = pool->res_cap->num_dwb;
1552
1553 for (i = 0; i < dwb_count; i++) {
1554 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1555
1556 if (!mcif_wb30) {
1557 dm_error("DC: failed to create mcif_wb30!\n");
1558 return false;
1559 }
1560
1561 #undef REG_STRUCT
1562 #define REG_STRUCT mcif_wb30_regs
1563 mcif_wb_regs_dcn3_init(0);
1564
1565 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1566 &mcif_wb30_regs[i],
1567 &mcif_wb30_shift,
1568 &mcif_wb30_mask,
1569 i);
1570
1571 pool->mcif_wb[i] = &mcif_wb30->base;
1572 }
1573 return true;
1574 }
1575
dcn321_dsc_create(struct dc_context * ctx,uint32_t inst)1576 static struct display_stream_compressor *dcn321_dsc_create(
1577 struct dc_context *ctx, uint32_t inst)
1578 {
1579 struct dcn20_dsc *dsc =
1580 kzalloc_obj(struct dcn20_dsc);
1581
1582 if (!dsc) {
1583 BREAK_TO_DEBUGGER();
1584 return NULL;
1585 }
1586
1587 #undef REG_STRUCT
1588 #define REG_STRUCT dsc_regs
1589 dsc_regsDCN20_init(0),
1590 dsc_regsDCN20_init(1),
1591 dsc_regsDCN20_init(2),
1592 dsc_regsDCN20_init(3);
1593
1594 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1595
1596 dsc->max_image_width = 6016;
1597
1598 return &dsc->base;
1599 }
1600
dcn321_destroy_resource_pool(struct resource_pool ** pool)1601 static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1602 {
1603 struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1604
1605 dcn321_resource_destruct(dcn321_pool);
1606 kfree(dcn321_pool);
1607 *pool = NULL;
1608 }
1609
1610 static struct dc_cap_funcs cap_funcs = {
1611 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1612 .get_subvp_en = dcn32_subvp_in_use,
1613 };
1614
dcn321_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1615 static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1616 {
1617 DC_FP_START();
1618
1619 dcn321_update_bw_bounding_box_fpu(dc, bw_params);
1620
1621 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1622 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1623
1624 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1625 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1626
1627 DC_FP_END();
1628 }
1629
1630 static struct resource_funcs dcn321_res_pool_funcs = {
1631 .destroy = dcn321_destroy_resource_pool,
1632 .link_enc_create = dcn321_link_encoder_create,
1633 .link_enc_create_minimal = NULL,
1634 .panel_cntl_create = dcn32_panel_cntl_create,
1635 .validate_bandwidth = dcn32_validate_bandwidth,
1636 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1637 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1638 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1639 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1640 .release_pipe = dcn20_release_pipe,
1641 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1642 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1643 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1644 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1645 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1646 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1647 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1648 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1649 .update_bw_bounding_box = dcn321_update_bw_bounding_box,
1650 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1651 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1652 .add_phantom_pipes = dcn32_add_phantom_pipes,
1653 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1654 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1655 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1656 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
1657 .get_default_tiling_info = dcn10_get_default_tiling_info,
1658 };
1659
read_pipe_fuses(struct dc_context * ctx)1660 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1661 {
1662 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1663 /* DCN321 support max 4 pipes */
1664 value = value & 0xf;
1665 return value;
1666 }
1667
1668
dcn321_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn321_resource_pool * pool)1669 static bool dcn321_resource_construct(
1670 uint8_t num_virtual_links,
1671 struct dc *dc,
1672 struct dcn321_resource_pool *pool)
1673 {
1674 int i, j;
1675 struct dc_context *ctx = dc->ctx;
1676 struct irq_service_init_data init_data;
1677 struct ddc_service_init_data ddc_init_data = {0};
1678 uint32_t pipe_fuses = 0;
1679 uint32_t num_pipes = 4;
1680
1681 #undef REG_STRUCT
1682 #define REG_STRUCT bios_regs
1683 bios_regs_init();
1684
1685 #undef REG_STRUCT
1686 #define REG_STRUCT clk_src_regs
1687 clk_src_regs_init(0, A),
1688 clk_src_regs_init(1, B),
1689 clk_src_regs_init(2, C),
1690 clk_src_regs_init(3, D),
1691 clk_src_regs_init(4, E);
1692
1693 #undef REG_STRUCT
1694 #define REG_STRUCT abm_regs
1695 abm_regs_init(0),
1696 abm_regs_init(1),
1697 abm_regs_init(2),
1698 abm_regs_init(3);
1699
1700 #undef REG_STRUCT
1701 #define REG_STRUCT dccg_regs
1702 dccg_regs_init();
1703
1704
1705 ctx->dc_bios->regs = &bios_regs;
1706
1707 pool->base.res_cap = &res_cap_dcn321;
1708 /* max number of pipes for ASIC before checking for pipe fuses */
1709 num_pipes = pool->base.res_cap->num_timing_generator;
1710 pipe_fuses = read_pipe_fuses(ctx);
1711
1712 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1713 if (pipe_fuses & 1 << i)
1714 num_pipes--;
1715
1716 if (pipe_fuses & 1)
1717 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1718
1719 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1720 ASSERT(0); //Entire DCN is harvested!
1721
1722 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1723 * value will be changed, update max_num_dpp and max_num_otg for dml.
1724 */
1725 dcn3_21_ip.max_num_dpp = num_pipes;
1726 dcn3_21_ip.max_num_otg = num_pipes;
1727
1728 pool->base.funcs = &dcn321_res_pool_funcs;
1729
1730 /*************************************************
1731 * Resource + asic cap harcoding *
1732 *************************************************/
1733 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1734 pool->base.timing_generator_count = num_pipes;
1735 pool->base.pipe_count = num_pipes;
1736 pool->base.mpcc_count = num_pipes;
1737 dc->caps.max_downscale_ratio = 600;
1738 dc->caps.i2c_speed_in_khz = 100;
1739 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1740 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1741 dc->caps.max_cursor_size = 64;
1742 dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)
1743 dc->caps.min_horizontal_blanking_period = 80;
1744 dc->caps.dmdata_alloc_size = 2048;
1745 dc->caps.mall_size_per_mem_channel = 4;
1746 /* total size = mall per channel * num channels * 1024 * 1024 */
1747 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1748
1749 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1750 dc->caps.cache_line_size = 64;
1751 dc->caps.cache_num_ways = 16;
1752
1753 /* Calculate the available MALL space */
1754 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
1755 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1756 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1757 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1758
1759 dc->caps.subvp_fw_processing_delay_us = 15;
1760 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1761 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1762 dc->caps.subvp_swath_height_margin_lines = 16;
1763 dc->caps.subvp_pstate_allow_width_us = 20;
1764 dc->caps.subvp_vertical_int_margin_us = 30;
1765 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1766 dc->caps.max_slave_planes = 2;
1767 dc->caps.max_slave_yuv_planes = 2;
1768 dc->caps.max_slave_rgb_planes = 2;
1769 dc->caps.post_blend_color_processing = true;
1770 dc->caps.force_dp_tps4_for_cp2520 = true;
1771 dc->caps.dp_hpo = true;
1772 dc->caps.dp_hdmi21_pcon_support = true;
1773 dc->caps.edp_dsc_support = true;
1774 dc->caps.extended_aux_timeout_support = true;
1775 dc->caps.dmcub_support = true;
1776 dc->caps.max_v_total = (1 << 15) - 1;
1777 dc->caps.vtotal_limited_by_fp2 = true;
1778
1779 /* Color pipeline capabilities */
1780 dc->caps.color.dpp.dcn_arch = 1;
1781 dc->caps.color.dpp.input_lut_shared = 0;
1782 dc->caps.color.dpp.icsc = 1;
1783 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1784 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1785 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1786 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1787 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1788 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1789 dc->caps.color.dpp.post_csc = 1;
1790 dc->caps.color.dpp.gamma_corr = 1;
1791 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1792
1793 dc->caps.color.dpp.hw_3d_lut = 0;
1794 dc->caps.color.dpp.ogam_ram = 0;
1795 // no OGAM ROM on DCN2 and later ASICs
1796 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1797 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1798 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1799 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1800 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1801 dc->caps.color.dpp.ocsc = 0;
1802
1803 dc->caps.color.mpc.gamut_remap = 1;
1804 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1805 dc->caps.color.mpc.ogam_ram = 1;
1806 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1807 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1808 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1809 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1810 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1811 dc->caps.color.mpc.ocsc = 1;
1812 dc->caps.color.mpc.preblend = true;
1813
1814 /* Use pipe context based otg sync logic */
1815 dc->config.use_pipe_ctx_sync_logic = true;
1816
1817 dc->config.dc_mode_clk_limit_support = true;
1818 dc->config.enable_windowed_mpo_odm = true;
1819 dc->config.disable_hbr_audio_dp2 = true;
1820 /* read VBIOS LTTPR caps */
1821 {
1822 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1823 enum bp_result bp_query_result;
1824 uint8_t is_vbios_lttpr_enable = 0;
1825
1826 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1827 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1828 }
1829
1830 /* interop bit is implicit */
1831 {
1832 dc->caps.vbios_lttpr_aware = true;
1833 }
1834 }
1835 dc->check_config = config_defaults;
1836
1837 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1838 dc->debug = debug_defaults_drv;
1839
1840 // Init the vm_helper
1841 if (dc->vm_helper)
1842 vm_helper_init(dc->vm_helper, 16);
1843
1844 /*************************************************
1845 * Create resources *
1846 *************************************************/
1847
1848 /* Clock Sources for Pixel Clock*/
1849 pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
1850 dcn321_clock_source_create(ctx, ctx->dc_bios,
1851 CLOCK_SOURCE_COMBO_PHY_PLL0,
1852 &clk_src_regs[0], false);
1853 pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
1854 dcn321_clock_source_create(ctx, ctx->dc_bios,
1855 CLOCK_SOURCE_COMBO_PHY_PLL1,
1856 &clk_src_regs[1], false);
1857 pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
1858 dcn321_clock_source_create(ctx, ctx->dc_bios,
1859 CLOCK_SOURCE_COMBO_PHY_PLL2,
1860 &clk_src_regs[2], false);
1861 pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
1862 dcn321_clock_source_create(ctx, ctx->dc_bios,
1863 CLOCK_SOURCE_COMBO_PHY_PLL3,
1864 &clk_src_regs[3], false);
1865 pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
1866 dcn321_clock_source_create(ctx, ctx->dc_bios,
1867 CLOCK_SOURCE_COMBO_PHY_PLL4,
1868 &clk_src_regs[4], false);
1869
1870 pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
1871
1872 /* todo: not reuse phy_pll registers */
1873 pool->base.dp_clock_source =
1874 dcn321_clock_source_create(ctx, ctx->dc_bios,
1875 CLOCK_SOURCE_ID_DP_DTO,
1876 &clk_src_regs[0], true);
1877
1878 for (i = 0; i < pool->base.clk_src_count; i++) {
1879 if (pool->base.clock_sources[i] == NULL) {
1880 dm_error("DC: failed to create clock sources!\n");
1881 BREAK_TO_DEBUGGER();
1882 goto create_fail;
1883 }
1884 }
1885
1886 /* DCCG */
1887 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1888 if (pool->base.dccg == NULL) {
1889 dm_error("DC: failed to create dccg!\n");
1890 BREAK_TO_DEBUGGER();
1891 goto create_fail;
1892 }
1893
1894 /* DML */
1895 dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1896
1897 /* IRQ Service */
1898 init_data.ctx = dc->ctx;
1899 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
1900 if (!pool->base.irqs)
1901 goto create_fail;
1902
1903 /* HUBBUB */
1904 pool->base.hubbub = dcn321_hubbub_create(ctx);
1905 if (pool->base.hubbub == NULL) {
1906 BREAK_TO_DEBUGGER();
1907 dm_error("DC: failed to create hubbub!\n");
1908 goto create_fail;
1909 }
1910
1911 /* DIO */
1912 pool->base.dio = dcn321_dio_create(ctx);
1913 if (pool->base.dio == NULL) {
1914 BREAK_TO_DEBUGGER();
1915 dm_error("DC: failed to create dio!\n");
1916 goto create_fail;
1917 }
1918
1919 /* HUBPs, DPPs, OPPs, TGs, ABMs */
1920 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1921
1922 /* if pipe is disabled, skip instance of HW pipe,
1923 * i.e, skip ASIC register instance
1924 */
1925 if (pipe_fuses & 1 << i)
1926 continue;
1927
1928 pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
1929 if (pool->base.hubps[j] == NULL) {
1930 BREAK_TO_DEBUGGER();
1931 dm_error(
1932 "DC: failed to create hubps!\n");
1933 goto create_fail;
1934 }
1935
1936 pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
1937 if (pool->base.dpps[j] == NULL) {
1938 BREAK_TO_DEBUGGER();
1939 dm_error(
1940 "DC: failed to create dpps!\n");
1941 goto create_fail;
1942 }
1943
1944 pool->base.opps[j] = dcn321_opp_create(ctx, i);
1945 if (pool->base.opps[j] == NULL) {
1946 BREAK_TO_DEBUGGER();
1947 dm_error(
1948 "DC: failed to create output pixel processor!\n");
1949 goto create_fail;
1950 }
1951
1952 pool->base.timing_generators[j] = dcn321_timing_generator_create(
1953 ctx, i);
1954 if (pool->base.timing_generators[j] == NULL) {
1955 BREAK_TO_DEBUGGER();
1956 dm_error("DC: failed to create tg!\n");
1957 goto create_fail;
1958 }
1959
1960 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
1961 &abm_regs[i],
1962 &abm_shift,
1963 &abm_mask);
1964 if (pool->base.multiple_abms[j] == NULL) {
1965 dm_error("DC: failed to create abm for pipe %d!\n", i);
1966 BREAK_TO_DEBUGGER();
1967 goto create_fail;
1968 }
1969
1970 /* index for resource pool arrays for next valid pipe */
1971 j++;
1972 }
1973
1974 /* PSR */
1975 pool->base.psr = dmub_psr_create(ctx);
1976 if (pool->base.psr == NULL) {
1977 dm_error("DC: failed to create psr obj!\n");
1978 BREAK_TO_DEBUGGER();
1979 goto create_fail;
1980 }
1981
1982 /* MPCCs */
1983 pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
1984 if (pool->base.mpc == NULL) {
1985 BREAK_TO_DEBUGGER();
1986 dm_error("DC: failed to create mpc!\n");
1987 goto create_fail;
1988 }
1989
1990 /* DSCs */
1991 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1992 pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
1993 if (pool->base.dscs[i] == NULL) {
1994 BREAK_TO_DEBUGGER();
1995 dm_error("DC: failed to create display stream compressor %d!\n", i);
1996 goto create_fail;
1997 }
1998 }
1999
2000 /* DWB */
2001 if (!dcn321_dwbc_create(ctx, &pool->base)) {
2002 BREAK_TO_DEBUGGER();
2003 dm_error("DC: failed to create dwbc!\n");
2004 goto create_fail;
2005 }
2006
2007 /* MMHUBBUB */
2008 if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
2009 BREAK_TO_DEBUGGER();
2010 dm_error("DC: failed to create mcif_wb!\n");
2011 goto create_fail;
2012 }
2013
2014 /* AUX and I2C */
2015 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2016 pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
2017 if (pool->base.engines[i] == NULL) {
2018 BREAK_TO_DEBUGGER();
2019 dm_error(
2020 "DC:failed to create aux engine!!\n");
2021 goto create_fail;
2022 }
2023 pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
2024 if (pool->base.hw_i2cs[i] == NULL) {
2025 BREAK_TO_DEBUGGER();
2026 dm_error(
2027 "DC:failed to create hw i2c!!\n");
2028 goto create_fail;
2029 }
2030 pool->base.sw_i2cs[i] = NULL;
2031 }
2032
2033 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2034 if (!resource_construct(num_virtual_links, dc, &pool->base,
2035 &res_create_funcs))
2036 goto create_fail;
2037
2038 /* HW Sequencer init functions and Plane caps */
2039 dcn32_hw_sequencer_init_functions(dc);
2040
2041 dc->caps.max_planes = pool->base.pipe_count;
2042
2043 for (i = 0; i < dc->caps.max_planes; ++i)
2044 dc->caps.planes[i] = plane_cap;
2045
2046 dc->caps.max_odm_combine_factor = 4;
2047
2048 dc->cap_funcs = cap_funcs;
2049
2050 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2051 ddc_init_data.ctx = dc->ctx;
2052 ddc_init_data.link = NULL;
2053 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2054 ddc_init_data.id.enum_id = 0;
2055 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2056 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2057 } else {
2058 pool->base.oem_device = NULL;
2059 }
2060
2061 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2062 dc->dml2_options.use_native_soc_bb_construction = true;
2063 dc->dml2_options.minimize_dispclk_using_odm = true;
2064
2065 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2066 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2067 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2068 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2069
2070 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2071 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2072 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2073 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2074
2075 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2076 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2077
2078 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2079 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2080 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2081 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2082 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2083 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2084 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2085
2086 dc->dml2_options.max_segments_per_hubp = 18;
2087 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2088
2089 /* init DC limited DML2 options */
2090 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2091 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2092
2093 return true;
2094
2095 create_fail:
2096
2097 dcn321_resource_destruct(pool);
2098
2099 return false;
2100 }
2101
dcn321_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2102 struct resource_pool *dcn321_create_resource_pool(
2103 const struct dc_init_data *init_data,
2104 struct dc *dc)
2105 {
2106 struct dcn321_resource_pool *pool =
2107 kzalloc_obj(struct dcn321_resource_pool);
2108
2109 if (!pool)
2110 return NULL;
2111
2112 if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
2113 return &pool->base;
2114
2115 BREAK_TO_DEBUGGER();
2116 kfree(pool);
2117 return NULL;
2118 }
2119