1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn31/dcn31_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn31_resource.h" 35 36 #include "dcn20/dcn20_resource.h" 37 #include "dcn30/dcn30_resource.h" 38 39 #include "dml/dcn30/dcn30_fpu.h" 40 41 #include "dcn10/dcn10_ipp.h" 42 #include "dcn30/dcn30_hubbub.h" 43 #include "dcn31/dcn31_hubbub.h" 44 #include "dcn30/dcn30_mpc.h" 45 #include "dcn31/dcn31_hubp.h" 46 #include "irq/dcn31/irq_service_dcn31.h" 47 #include "dcn30/dcn30_dpp.h" 48 #include "dcn31/dcn31_optc.h" 49 #include "dcn20/dcn20_hwseq.h" 50 #include "dcn30/dcn30_hwseq.h" 51 #include "dce110/dce110_hwseq.h" 52 #include "dcn30/dcn30_opp.h" 53 #include "dcn20/dcn20_dsc.h" 54 #include "dcn30/dcn30_vpg.h" 55 #include "dcn30/dcn30_afmt.h" 56 #include "dcn30/dcn30_dio_stream_encoder.h" 57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 58 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 59 #include "dcn31/dcn31_apg.h" 60 #include "dcn31/dcn31_dio_link_encoder.h" 61 #include "dcn31/dcn31_vpg.h" 62 #include "dcn31/dcn31_afmt.h" 63 #include "dce/dce_clock_source.h" 64 #include "dce/dce_audio.h" 65 #include "dce/dce_hwseq.h" 66 #include "clk_mgr.h" 67 #include "virtual/virtual_stream_encoder.h" 68 #include "dce110/dce110_resource.h" 69 #include "dml/display_mode_vba.h" 70 #include "dml/dcn31/dcn31_fpu.h" 71 #include "dcn31/dcn31_dccg.h" 72 #include "dcn10/dcn10_resource.h" 73 #include "dcn31/dcn31_panel_cntl.h" 74 75 #include "dcn30/dcn30_dwb.h" 76 #include "dcn30/dcn30_mmhubbub.h" 77 78 #include "yellow_carp_offset.h" 79 #include "dcn/dcn_3_1_2_offset.h" 80 #include "dcn/dcn_3_1_2_sh_mask.h" 81 #include "nbio/nbio_7_2_0_offset.h" 82 #include "dpcs/dpcs_4_2_0_offset.h" 83 #include "dpcs/dpcs_4_2_0_sh_mask.h" 84 #include "mmhub/mmhub_2_3_0_offset.h" 85 #include "mmhub/mmhub_2_3_0_sh_mask.h" 86 87 88 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6 89 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 90 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L 92 93 #include "reg_helper.h" 94 #include "dce/dmub_abm.h" 95 #include "dce/dmub_psr.h" 96 #include "dce/dce_aux.h" 97 #include "dce/dce_i2c.h" 98 #include "dce/dmub_replay.h" 99 100 #include "dml/dcn30/display_mode_vba_30.h" 101 #include "vm_helper.h" 102 #include "dcn20/dcn20_vmid.h" 103 104 #include "link_enc_cfg.h" 105 106 #define DC_LOGGER \ 107 dc->ctx->logger 108 #define DC_LOGGER_INIT(logger) 109 110 enum dcn31_clk_src_array_id { 111 DCN31_CLK_SRC_PLL0, 112 DCN31_CLK_SRC_PLL1, 113 DCN31_CLK_SRC_PLL2, 114 DCN31_CLK_SRC_PLL3, 115 DCN31_CLK_SRC_PLL4, 116 DCN30_CLK_SRC_TOTAL 117 }; 118 119 /* begin ********************* 120 * macros to expend register list macro defined in HW object header file 121 */ 122 123 /* DCN */ 124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 125 126 #define BASE(seg) BASE_INNER(seg) 127 128 #define SR(reg_name)\ 129 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 130 reg ## reg_name 131 132 #define SRI(reg_name, block, id)\ 133 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 reg ## block ## id ## _ ## reg_name 135 136 #define SRI2(reg_name, block, id)\ 137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 138 reg ## reg_name 139 140 #define SRIR(var_name, reg_name, block, id)\ 141 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 142 reg ## block ## id ## _ ## reg_name 143 144 #define SRII(reg_name, block, id)\ 145 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 146 reg ## block ## id ## _ ## reg_name 147 148 #define SRII_MPC_RMU(reg_name, block, id)\ 149 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 150 reg ## block ## id ## _ ## reg_name 151 152 #define SRII_DWB(reg_name, temp_name, block, id)\ 153 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 154 reg ## block ## id ## _ ## temp_name 155 156 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 157 .field_name = reg_name ## __ ## field_name ## post_fix 158 159 #define DCCG_SRII(reg_name, block, id)\ 160 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 161 reg ## block ## id ## _ ## reg_name 162 163 #define VUPDATE_SRII(reg_name, block, id)\ 164 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 165 reg ## reg_name ## _ ## block ## id 166 167 /* NBIO */ 168 #define NBIO_BASE_INNER(seg) \ 169 NBIO_BASE__INST0_SEG ## seg 170 171 #define NBIO_BASE(seg) \ 172 NBIO_BASE_INNER(seg) 173 174 #define NBIO_SR(reg_name)\ 175 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 176 regBIF_BX1_ ## reg_name 177 178 /* MMHUB */ 179 #define MMHUB_BASE_INNER(seg) \ 180 MMHUB_BASE__INST0_SEG ## seg 181 182 #define MMHUB_BASE(seg) \ 183 MMHUB_BASE_INNER(seg) 184 185 #define MMHUB_SR(reg_name)\ 186 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 187 mm ## reg_name 188 189 /* CLOCK */ 190 #define CLK_BASE_INNER(seg) \ 191 CLK_BASE__INST0_SEG ## seg 192 193 #define CLK_BASE(seg) \ 194 CLK_BASE_INNER(seg) 195 196 #define CLK_SRI(reg_name, block, inst)\ 197 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 198 reg ## block ## _ ## inst ## _ ## reg_name 199 200 201 static const struct bios_registers bios_regs = { 202 NBIO_SR(BIOS_SCRATCH_3), 203 NBIO_SR(BIOS_SCRATCH_6) 204 }; 205 206 #define clk_src_regs(index, pllid)\ 207 [index] = {\ 208 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\ 209 } 210 211 static const struct dce110_clk_src_regs clk_src_regs[] = { 212 clk_src_regs(0, A), 213 clk_src_regs(1, B), 214 clk_src_regs(2, C), 215 clk_src_regs(3, D), 216 clk_src_regs(4, E) 217 }; 218 /*pll_id being rempped in dmub, in driver it is logical instance*/ 219 static const struct dce110_clk_src_regs clk_src_regs_b0[] = { 220 clk_src_regs(0, A), 221 clk_src_regs(1, B), 222 clk_src_regs(2, F), 223 clk_src_regs(3, G), 224 clk_src_regs(4, E) 225 }; 226 227 static const struct dce110_clk_src_shift cs_shift = { 228 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 229 }; 230 231 static const struct dce110_clk_src_mask cs_mask = { 232 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 233 }; 234 235 #define abm_regs(id)\ 236 [id] = {\ 237 ABM_DCN302_REG_LIST(id)\ 238 } 239 240 static const struct dce_abm_registers abm_regs[] = { 241 abm_regs(0), 242 abm_regs(1), 243 abm_regs(2), 244 abm_regs(3), 245 }; 246 247 static const struct dce_abm_shift abm_shift = { 248 ABM_MASK_SH_LIST_DCN30(__SHIFT) 249 }; 250 251 static const struct dce_abm_mask abm_mask = { 252 ABM_MASK_SH_LIST_DCN30(_MASK) 253 }; 254 255 #define audio_regs(id)\ 256 [id] = {\ 257 AUD_COMMON_REG_LIST(id)\ 258 } 259 260 static const struct dce_audio_registers audio_regs[] = { 261 audio_regs(0), 262 audio_regs(1), 263 audio_regs(2), 264 audio_regs(3), 265 audio_regs(4), 266 audio_regs(5), 267 audio_regs(6) 268 }; 269 270 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 271 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 273 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 274 275 static const struct dce_audio_shift audio_shift = { 276 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 277 }; 278 279 static const struct dce_audio_mask audio_mask = { 280 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 281 }; 282 283 #define vpg_regs(id)\ 284 [id] = {\ 285 VPG_DCN31_REG_LIST(id)\ 286 } 287 288 static const struct dcn31_vpg_registers vpg_regs[] = { 289 vpg_regs(0), 290 vpg_regs(1), 291 vpg_regs(2), 292 vpg_regs(3), 293 vpg_regs(4), 294 vpg_regs(5), 295 vpg_regs(6), 296 vpg_regs(7), 297 vpg_regs(8), 298 vpg_regs(9), 299 }; 300 301 static const struct dcn31_vpg_shift vpg_shift = { 302 DCN31_VPG_MASK_SH_LIST(__SHIFT) 303 }; 304 305 static const struct dcn31_vpg_mask vpg_mask = { 306 DCN31_VPG_MASK_SH_LIST(_MASK) 307 }; 308 309 #define afmt_regs(id)\ 310 [id] = {\ 311 AFMT_DCN31_REG_LIST(id)\ 312 } 313 314 static const struct dcn31_afmt_registers afmt_regs[] = { 315 afmt_regs(0), 316 afmt_regs(1), 317 afmt_regs(2), 318 afmt_regs(3), 319 afmt_regs(4), 320 afmt_regs(5) 321 }; 322 323 static const struct dcn31_afmt_shift afmt_shift = { 324 DCN31_AFMT_MASK_SH_LIST(__SHIFT) 325 }; 326 327 static const struct dcn31_afmt_mask afmt_mask = { 328 DCN31_AFMT_MASK_SH_LIST(_MASK) 329 }; 330 331 #define apg_regs(id)\ 332 [id] = {\ 333 APG_DCN31_REG_LIST(id)\ 334 } 335 336 static const struct dcn31_apg_registers apg_regs[] = { 337 apg_regs(0), 338 apg_regs(1), 339 apg_regs(2), 340 apg_regs(3) 341 }; 342 343 static const struct dcn31_apg_shift apg_shift = { 344 DCN31_APG_MASK_SH_LIST(__SHIFT) 345 }; 346 347 static const struct dcn31_apg_mask apg_mask = { 348 DCN31_APG_MASK_SH_LIST(_MASK) 349 }; 350 351 #define stream_enc_regs(id)\ 352 [id] = {\ 353 SE_DCN3_REG_LIST(id)\ 354 } 355 356 /* Some encoders won't be initialized here - but they're logical, not physical. */ 357 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = { 358 stream_enc_regs(0), 359 stream_enc_regs(1), 360 stream_enc_regs(2), 361 stream_enc_regs(3), 362 stream_enc_regs(4) 363 }; 364 365 static const struct dcn10_stream_encoder_shift se_shift = { 366 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 367 }; 368 369 static const struct dcn10_stream_encoder_mask se_mask = { 370 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 371 }; 372 373 374 #define aux_regs(id)\ 375 [id] = {\ 376 DCN2_AUX_REG_LIST(id)\ 377 } 378 379 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 380 aux_regs(0), 381 aux_regs(1), 382 aux_regs(2), 383 aux_regs(3), 384 aux_regs(4) 385 }; 386 387 #define hpd_regs(id)\ 388 [id] = {\ 389 HPD_REG_LIST(id)\ 390 } 391 392 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 393 hpd_regs(0), 394 hpd_regs(1), 395 hpd_regs(2), 396 hpd_regs(3), 397 hpd_regs(4) 398 }; 399 400 #define link_regs(id, phyid)\ 401 [id] = {\ 402 LE_DCN31_REG_LIST(id), \ 403 UNIPHY_DCN2_REG_LIST(phyid), \ 404 DPCS_DCN31_REG_LIST(id), \ 405 } 406 407 static const struct dce110_aux_registers_shift aux_shift = { 408 DCN_AUX_MASK_SH_LIST(__SHIFT) 409 }; 410 411 static const struct dce110_aux_registers_mask aux_mask = { 412 DCN_AUX_MASK_SH_LIST(_MASK) 413 }; 414 415 static const struct dcn10_link_enc_registers link_enc_regs[] = { 416 link_regs(0, A), 417 link_regs(1, B), 418 link_regs(2, C), 419 link_regs(3, D), 420 link_regs(4, E) 421 }; 422 423 static const struct dcn10_link_enc_shift le_shift = { 424 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \ 425 DPCS_DCN31_MASK_SH_LIST(__SHIFT) 426 }; 427 428 static const struct dcn10_link_enc_mask le_mask = { 429 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 430 DPCS_DCN31_MASK_SH_LIST(_MASK) 431 }; 432 433 #define hpo_dp_stream_encoder_reg_list(id)\ 434 [id] = {\ 435 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\ 436 } 437 438 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { 439 hpo_dp_stream_encoder_reg_list(0), 440 hpo_dp_stream_encoder_reg_list(1), 441 hpo_dp_stream_encoder_reg_list(2), 442 hpo_dp_stream_encoder_reg_list(3), 443 }; 444 445 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 446 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 447 }; 448 449 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 450 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 451 }; 452 453 #define hpo_dp_link_encoder_reg_list(id)\ 454 [id] = {\ 455 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\ 456 DCN3_1_RDPCSTX_REG_LIST(0),\ 457 DCN3_1_RDPCSTX_REG_LIST(1),\ 458 DCN3_1_RDPCSTX_REG_LIST(2),\ 459 DCN3_1_RDPCSTX_REG_LIST(3),\ 460 DCN3_1_RDPCSTX_REG_LIST(4)\ 461 } 462 463 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { 464 hpo_dp_link_encoder_reg_list(0), 465 hpo_dp_link_encoder_reg_list(1), 466 }; 467 468 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 469 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 470 }; 471 472 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 473 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 474 }; 475 476 #define dpp_regs(id)\ 477 [id] = {\ 478 DPP_REG_LIST_DCN30(id),\ 479 } 480 481 static const struct dcn3_dpp_registers dpp_regs[] = { 482 dpp_regs(0), 483 dpp_regs(1), 484 dpp_regs(2), 485 dpp_regs(3) 486 }; 487 488 static const struct dcn3_dpp_shift tf_shift = { 489 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 490 }; 491 492 static const struct dcn3_dpp_mask tf_mask = { 493 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 494 }; 495 496 #define opp_regs(id)\ 497 [id] = {\ 498 OPP_REG_LIST_DCN30(id),\ 499 } 500 501 static const struct dcn20_opp_registers opp_regs[] = { 502 opp_regs(0), 503 opp_regs(1), 504 opp_regs(2), 505 opp_regs(3) 506 }; 507 508 static const struct dcn20_opp_shift opp_shift = { 509 OPP_MASK_SH_LIST_DCN20(__SHIFT) 510 }; 511 512 static const struct dcn20_opp_mask opp_mask = { 513 OPP_MASK_SH_LIST_DCN20(_MASK) 514 }; 515 516 #define aux_engine_regs(id)\ 517 [id] = {\ 518 AUX_COMMON_REG_LIST0(id), \ 519 .AUXN_IMPCAL = 0, \ 520 .AUXP_IMPCAL = 0, \ 521 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 522 } 523 524 static const struct dce110_aux_registers aux_engine_regs[] = { 525 aux_engine_regs(0), 526 aux_engine_regs(1), 527 aux_engine_regs(2), 528 aux_engine_regs(3), 529 aux_engine_regs(4) 530 }; 531 532 #define dwbc_regs_dcn3(id)\ 533 [id] = {\ 534 DWBC_COMMON_REG_LIST_DCN30(id),\ 535 } 536 537 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 538 dwbc_regs_dcn3(0), 539 }; 540 541 static const struct dcn30_dwbc_shift dwbc30_shift = { 542 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 543 }; 544 545 static const struct dcn30_dwbc_mask dwbc30_mask = { 546 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 547 }; 548 549 #define mcif_wb_regs_dcn3(id)\ 550 [id] = {\ 551 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 552 } 553 554 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 555 mcif_wb_regs_dcn3(0) 556 }; 557 558 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 559 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 560 }; 561 562 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 563 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 564 }; 565 566 #define dsc_regsDCN20(id)\ 567 [id] = {\ 568 DSC_REG_LIST_DCN20(id)\ 569 } 570 571 static const struct dcn20_dsc_registers dsc_regs[] = { 572 dsc_regsDCN20(0), 573 dsc_regsDCN20(1), 574 dsc_regsDCN20(2) 575 }; 576 577 static const struct dcn20_dsc_shift dsc_shift = { 578 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 579 }; 580 581 static const struct dcn20_dsc_mask dsc_mask = { 582 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 583 }; 584 585 static const struct dcn30_mpc_registers mpc_regs = { 586 MPC_REG_LIST_DCN3_0(0), 587 MPC_REG_LIST_DCN3_0(1), 588 MPC_REG_LIST_DCN3_0(2), 589 MPC_REG_LIST_DCN3_0(3), 590 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 591 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 593 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 594 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 595 MPC_RMU_REG_LIST_DCN3AG(0), 596 MPC_RMU_REG_LIST_DCN3AG(1), 597 //MPC_RMU_REG_LIST_DCN3AG(2), 598 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 599 }; 600 601 static const struct dcn30_mpc_shift mpc_shift = { 602 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 603 }; 604 605 static const struct dcn30_mpc_mask mpc_mask = { 606 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 607 }; 608 609 #define optc_regs(id)\ 610 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)} 611 612 static const struct dcn_optc_registers optc_regs[] = { 613 optc_regs(0), 614 optc_regs(1), 615 optc_regs(2), 616 optc_regs(3) 617 }; 618 619 static const struct dcn_optc_shift optc_shift = { 620 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT) 621 }; 622 623 static const struct dcn_optc_mask optc_mask = { 624 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK) 625 }; 626 627 #define hubp_regs(id)\ 628 [id] = {\ 629 HUBP_REG_LIST_DCN30(id)\ 630 } 631 632 static const struct dcn_hubp2_registers hubp_regs[] = { 633 hubp_regs(0), 634 hubp_regs(1), 635 hubp_regs(2), 636 hubp_regs(3) 637 }; 638 639 640 static const struct dcn_hubp2_shift hubp_shift = { 641 HUBP_MASK_SH_LIST_DCN31(__SHIFT) 642 }; 643 644 static const struct dcn_hubp2_mask hubp_mask = { 645 HUBP_MASK_SH_LIST_DCN31(_MASK) 646 }; 647 static const struct dcn_hubbub_registers hubbub_reg = { 648 HUBBUB_REG_LIST_DCN31(0) 649 }; 650 651 static const struct dcn_hubbub_shift hubbub_shift = { 652 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT) 653 }; 654 655 static const struct dcn_hubbub_mask hubbub_mask = { 656 HUBBUB_MASK_SH_LIST_DCN31(_MASK) 657 }; 658 659 static const struct dccg_registers dccg_regs = { 660 DCCG_REG_LIST_DCN31() 661 }; 662 663 static const struct dccg_shift dccg_shift = { 664 DCCG_MASK_SH_LIST_DCN31(__SHIFT) 665 }; 666 667 static const struct dccg_mask dccg_mask = { 668 DCCG_MASK_SH_LIST_DCN31(_MASK) 669 }; 670 671 672 #define SRII2(reg_name_pre, reg_name_post, id)\ 673 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 674 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 675 reg ## reg_name_pre ## id ## _ ## reg_name_post 676 677 678 #define HWSEQ_DCN31_REG_LIST()\ 679 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 680 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 681 SR(DIO_MEM_PWR_CTRL), \ 682 SR(ODM_MEM_PWR_CTRL3), \ 683 SR(DMU_MEM_PWR_CNTL), \ 684 SR(MMHUBBUB_MEM_PWR_CNTL), \ 685 SR(DCCG_GATE_DISABLE_CNTL), \ 686 SR(DCCG_GATE_DISABLE_CNTL2), \ 687 SR(DCFCLK_CNTL),\ 688 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 689 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 690 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 691 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 692 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\ 694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\ 695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\ 696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ 697 SR(MICROSECOND_TIME_BASE_DIV), \ 698 SR(MILLISECOND_TIME_BASE_DIV), \ 699 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 700 SR(RBBMIF_TIMEOUT_DIS), \ 701 SR(RBBMIF_TIMEOUT_DIS_2), \ 702 SR(DCHUBBUB_CRC_CTRL), \ 703 SR(DPP_TOP0_DPP_CRC_CTRL), \ 704 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 705 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 706 SR(MPC_CRC_CTRL), \ 707 SR(MPC_CRC_RESULT_GB), \ 708 SR(MPC_CRC_RESULT_C), \ 709 SR(MPC_CRC_RESULT_AR), \ 710 SR(DOMAIN0_PG_CONFIG), \ 711 SR(DOMAIN1_PG_CONFIG), \ 712 SR(DOMAIN2_PG_CONFIG), \ 713 SR(DOMAIN3_PG_CONFIG), \ 714 SR(DOMAIN16_PG_CONFIG), \ 715 SR(DOMAIN17_PG_CONFIG), \ 716 SR(DOMAIN18_PG_CONFIG), \ 717 SR(DOMAIN0_PG_STATUS), \ 718 SR(DOMAIN1_PG_STATUS), \ 719 SR(DOMAIN2_PG_STATUS), \ 720 SR(DOMAIN3_PG_STATUS), \ 721 SR(DOMAIN16_PG_STATUS), \ 722 SR(DOMAIN17_PG_STATUS), \ 723 SR(DOMAIN18_PG_STATUS), \ 724 SR(D1VGA_CONTROL), \ 725 SR(D2VGA_CONTROL), \ 726 SR(D3VGA_CONTROL), \ 727 SR(D4VGA_CONTROL), \ 728 SR(D5VGA_CONTROL), \ 729 SR(D6VGA_CONTROL), \ 730 SR(DC_IP_REQUEST_CNTL), \ 731 SR(AZALIA_AUDIO_DTO), \ 732 SR(AZALIA_CONTROLLER_CLOCK_GATING), \ 733 SR(HPO_TOP_HW_CONTROL) 734 735 static const struct dce_hwseq_registers hwseq_reg = { 736 HWSEQ_DCN31_REG_LIST() 737 }; 738 739 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\ 740 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 741 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 742 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ 743 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 744 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 745 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 746 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 747 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 748 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 749 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 750 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 751 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 752 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 753 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 754 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 755 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ 756 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ 757 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 758 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 759 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 760 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 761 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 762 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 763 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ 764 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 765 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 766 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 767 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \ 768 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 769 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 770 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \ 771 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ 772 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh) 773 774 static const struct dce_hwseq_shift hwseq_shift = { 775 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT) 776 }; 777 778 static const struct dce_hwseq_mask hwseq_mask = { 779 HWSEQ_DCN31_MASK_SH_LIST(_MASK) 780 }; 781 #define vmid_regs(id)\ 782 [id] = {\ 783 DCN20_VMID_REG_LIST(id)\ 784 } 785 786 static const struct dcn_vmid_registers vmid_regs[] = { 787 vmid_regs(0), 788 vmid_regs(1), 789 vmid_regs(2), 790 vmid_regs(3), 791 vmid_regs(4), 792 vmid_regs(5), 793 vmid_regs(6), 794 vmid_regs(7), 795 vmid_regs(8), 796 vmid_regs(9), 797 vmid_regs(10), 798 vmid_regs(11), 799 vmid_regs(12), 800 vmid_regs(13), 801 vmid_regs(14), 802 vmid_regs(15) 803 }; 804 805 static const struct dcn20_vmid_shift vmid_shifts = { 806 DCN20_VMID_MASK_SH_LIST(__SHIFT) 807 }; 808 809 static const struct dcn20_vmid_mask vmid_masks = { 810 DCN20_VMID_MASK_SH_LIST(_MASK) 811 }; 812 813 static const struct resource_caps res_cap_dcn31 = { 814 .num_timing_generator = 4, 815 .num_opp = 4, 816 .num_video_plane = 4, 817 .num_audio = 5, 818 .num_stream_encoder = 5, 819 .num_dig_link_enc = 5, 820 .num_hpo_dp_stream_encoder = 4, 821 .num_hpo_dp_link_encoder = 2, 822 .num_pll = 5, 823 .num_dwb = 1, 824 .num_ddc = 5, 825 .num_vmid = 16, 826 .num_mpc_3dlut = 2, 827 .num_dsc = 3, 828 }; 829 830 static const struct dc_plane_cap plane_cap = { 831 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 832 .per_pixel_alpha = true, 833 834 .pixel_format_support = { 835 .argb8888 = true, 836 .nv12 = true, 837 .fp16 = true, 838 .p010 = true, 839 .ayuv = false, 840 }, 841 842 .max_upscale_factor = { 843 .argb8888 = 16000, 844 .nv12 = 16000, 845 .fp16 = 16000 846 }, 847 848 // 6:1 downscaling ratio: 1000/6 = 166.666 849 .max_downscale_factor = { 850 .argb8888 = 167, 851 .nv12 = 167, 852 .fp16 = 167 853 }, 854 64, 855 64 856 }; 857 858 static const struct dc_debug_options debug_defaults_drv = { 859 .disable_dmcu = true, 860 .force_abm_enable = false, 861 .clock_trace = true, 862 .disable_pplib_clock_request = false, 863 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 864 .force_single_disp_pipe_split = false, 865 .disable_dcc = DCC_ENABLE, 866 .vsr_support = true, 867 .performance_trace = false, 868 .max_downscale_src_width = 4096,/*upto true 4K*/ 869 .disable_pplib_wm_range = false, 870 .scl_reset_length10 = true, 871 .sanity_checks = false, 872 .underflow_assert_delay_us = 0xFFFFFFFF, 873 .dwb_fi_phase = -1, // -1 = disable, 874 .dmub_command_table = true, 875 .pstate_enabled = true, 876 .use_max_lb = true, 877 .enable_mem_low_power = { 878 .bits = { 879 .vga = true, 880 .i2c = true, 881 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 882 .dscl = true, 883 .cm = true, 884 .mpc = true, 885 .optc = true, 886 .vpg = true, 887 .afmt = true, 888 } 889 }, 890 .disable_z10 = true, 891 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ 892 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, 893 .using_dml2 = false, 894 }; 895 896 static const struct dc_check_config config_defaults = { 897 .enable_legacy_fast_update = true, 898 }; 899 900 static const struct dc_panel_config panel_config_defaults = { 901 .psr = { 902 .disable_psr = false, 903 .disallow_psrsu = false, 904 .disallow_replay = false, 905 }, 906 .ilr = { 907 .optimize_edp_link_rate = true, 908 }, 909 }; 910 911 static void dcn31_dpp_destroy(struct dpp **dpp) 912 { 913 kfree(TO_DCN20_DPP(*dpp)); 914 *dpp = NULL; 915 } 916 917 static struct dpp *dcn31_dpp_create( 918 struct dc_context *ctx, 919 uint32_t inst) 920 { 921 struct dcn3_dpp *dpp = 922 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 923 924 if (!dpp) 925 return NULL; 926 927 if (dpp3_construct(dpp, ctx, inst, 928 &dpp_regs[inst], &tf_shift, &tf_mask)) 929 return &dpp->base; 930 931 BREAK_TO_DEBUGGER(); 932 kfree(dpp); 933 return NULL; 934 } 935 936 static struct output_pixel_processor *dcn31_opp_create( 937 struct dc_context *ctx, uint32_t inst) 938 { 939 struct dcn20_opp *opp = 940 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 941 942 if (!opp) { 943 BREAK_TO_DEBUGGER(); 944 return NULL; 945 } 946 947 dcn20_opp_construct(opp, ctx, inst, 948 &opp_regs[inst], &opp_shift, &opp_mask); 949 return &opp->base; 950 } 951 952 static struct dce_aux *dcn31_aux_engine_create( 953 struct dc_context *ctx, 954 uint32_t inst) 955 { 956 struct aux_engine_dce110 *aux_engine = 957 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 958 959 if (!aux_engine) 960 return NULL; 961 962 dce110_aux_engine_construct(aux_engine, ctx, inst, 963 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 964 &aux_engine_regs[inst], 965 &aux_mask, 966 &aux_shift, 967 ctx->dc->caps.extended_aux_timeout_support); 968 969 return &aux_engine->base; 970 } 971 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 972 973 static const struct dce_i2c_registers i2c_hw_regs[] = { 974 i2c_inst_regs(1), 975 i2c_inst_regs(2), 976 i2c_inst_regs(3), 977 i2c_inst_regs(4), 978 i2c_inst_regs(5), 979 }; 980 981 static const struct dce_i2c_shift i2c_shifts = { 982 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 983 }; 984 985 static const struct dce_i2c_mask i2c_masks = { 986 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 987 }; 988 989 static struct dce_i2c_hw *dcn31_i2c_hw_create( 990 struct dc_context *ctx, 991 uint32_t inst) 992 { 993 struct dce_i2c_hw *dce_i2c_hw = 994 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 995 996 if (!dce_i2c_hw) 997 return NULL; 998 999 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1000 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1001 1002 return dce_i2c_hw; 1003 } 1004 static struct mpc *dcn31_mpc_create( 1005 struct dc_context *ctx, 1006 int num_mpcc, 1007 int num_rmu) 1008 { 1009 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 1010 GFP_KERNEL); 1011 1012 if (!mpc30) 1013 return NULL; 1014 1015 dcn30_mpc_construct(mpc30, ctx, 1016 &mpc_regs, 1017 &mpc_shift, 1018 &mpc_mask, 1019 num_mpcc, 1020 num_rmu); 1021 1022 return &mpc30->base; 1023 } 1024 1025 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) 1026 { 1027 int i; 1028 1029 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1030 GFP_KERNEL); 1031 1032 if (!hubbub3) 1033 return NULL; 1034 1035 hubbub31_construct(hubbub3, ctx, 1036 &hubbub_reg, 1037 &hubbub_shift, 1038 &hubbub_mask, 1039 dcn3_1_ip.det_buffer_size_kbytes, 1040 dcn3_1_ip.pixel_chunk_size_kbytes, 1041 dcn3_1_ip.config_return_buffer_size_in_kbytes); 1042 1043 1044 for (i = 0; i < res_cap_dcn31.num_vmid; i++) { 1045 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1046 1047 vmid->ctx = ctx; 1048 1049 vmid->regs = &vmid_regs[i]; 1050 vmid->shifts = &vmid_shifts; 1051 vmid->masks = &vmid_masks; 1052 } 1053 1054 return &hubbub3->base; 1055 } 1056 1057 static struct timing_generator *dcn31_timing_generator_create( 1058 struct dc_context *ctx, 1059 uint32_t instance) 1060 { 1061 struct optc *tgn10 = 1062 kzalloc(sizeof(struct optc), GFP_KERNEL); 1063 1064 if (!tgn10) 1065 return NULL; 1066 1067 tgn10->base.inst = instance; 1068 tgn10->base.ctx = ctx; 1069 1070 tgn10->tg_regs = &optc_regs[instance]; 1071 tgn10->tg_shift = &optc_shift; 1072 tgn10->tg_mask = &optc_mask; 1073 1074 dcn31_timing_generator_init(tgn10); 1075 1076 return &tgn10->base; 1077 } 1078 1079 static const struct encoder_feature_support link_enc_feature = { 1080 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1081 .max_hdmi_pixel_clock = 600000, 1082 .hdmi_ycbcr420_supported = true, 1083 .dp_ycbcr420_supported = true, 1084 .fec_supported = true, 1085 .flags.bits.IS_HBR2_CAPABLE = true, 1086 .flags.bits.IS_HBR3_CAPABLE = true, 1087 .flags.bits.IS_TPS3_CAPABLE = true, 1088 .flags.bits.IS_TPS4_CAPABLE = true 1089 }; 1090 1091 static struct link_encoder *dcn31_link_encoder_create( 1092 struct dc_context *ctx, 1093 const struct encoder_init_data *enc_init_data) 1094 { 1095 struct dcn20_link_encoder *enc20 = 1096 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1097 1098 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 1099 return NULL; 1100 1101 dcn31_link_encoder_construct(enc20, 1102 enc_init_data, 1103 &link_enc_feature, 1104 &link_enc_regs[enc_init_data->transmitter], 1105 &link_enc_aux_regs[enc_init_data->channel - 1], 1106 &link_enc_hpd_regs[enc_init_data->hpd_source], 1107 &le_shift, 1108 &le_mask); 1109 1110 return &enc20->enc10.base; 1111 } 1112 1113 /* Create a minimal link encoder object not associated with a particular 1114 * physical connector. 1115 * resource_funcs.link_enc_create_minimal 1116 */ 1117 static struct link_encoder *dcn31_link_enc_create_minimal( 1118 struct dc_context *ctx, enum engine_id eng_id) 1119 { 1120 struct dcn20_link_encoder *enc20; 1121 1122 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) 1123 return NULL; 1124 1125 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1126 if (!enc20) 1127 return NULL; 1128 1129 dcn31_link_encoder_construct_minimal( 1130 enc20, 1131 ctx, 1132 &link_enc_feature, 1133 &link_enc_regs[eng_id - ENGINE_ID_DIGA], 1134 eng_id); 1135 1136 return &enc20->enc10.base; 1137 } 1138 1139 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1140 { 1141 struct dcn31_panel_cntl *panel_cntl = 1142 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL); 1143 1144 if (!panel_cntl) 1145 return NULL; 1146 1147 dcn31_panel_cntl_construct(panel_cntl, init_data); 1148 1149 return &panel_cntl->base; 1150 } 1151 1152 static void read_dce_straps( 1153 struct dc_context *ctx, 1154 struct resource_straps *straps) 1155 { 1156 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1157 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1158 1159 } 1160 1161 static struct audio *dcn31_create_audio( 1162 struct dc_context *ctx, unsigned int inst) 1163 { 1164 return dce_audio_create(ctx, inst, 1165 &audio_regs[inst], &audio_shift, &audio_mask); 1166 } 1167 1168 static struct vpg *dcn31_vpg_create( 1169 struct dc_context *ctx, 1170 uint32_t inst) 1171 { 1172 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); 1173 1174 if (!vpg31) 1175 return NULL; 1176 1177 vpg31_construct(vpg31, ctx, inst, 1178 &vpg_regs[inst], 1179 &vpg_shift, 1180 &vpg_mask); 1181 1182 return &vpg31->base; 1183 } 1184 1185 static struct afmt *dcn31_afmt_create( 1186 struct dc_context *ctx, 1187 uint32_t inst) 1188 { 1189 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL); 1190 1191 if (!afmt31) 1192 return NULL; 1193 1194 afmt31_construct(afmt31, ctx, inst, 1195 &afmt_regs[inst], 1196 &afmt_shift, 1197 &afmt_mask); 1198 1199 // Light sleep by default, no need to power down here 1200 1201 return &afmt31->base; 1202 } 1203 1204 static struct apg *dcn31_apg_create( 1205 struct dc_context *ctx, 1206 uint32_t inst) 1207 { 1208 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); 1209 1210 if (!apg31) 1211 return NULL; 1212 1213 apg31_construct(apg31, ctx, inst, 1214 &apg_regs[inst], 1215 &apg_shift, 1216 &apg_mask); 1217 1218 return &apg31->base; 1219 } 1220 1221 static struct stream_encoder *dcn31_stream_encoder_create( 1222 enum engine_id eng_id, 1223 struct dc_context *ctx) 1224 { 1225 struct dcn10_stream_encoder *enc1; 1226 struct vpg *vpg; 1227 struct afmt *afmt; 1228 int vpg_inst; 1229 int afmt_inst; 1230 1231 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1232 if (eng_id <= ENGINE_ID_DIGF) { 1233 vpg_inst = eng_id; 1234 afmt_inst = eng_id; 1235 } else 1236 return NULL; 1237 1238 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1239 vpg = dcn31_vpg_create(ctx, vpg_inst); 1240 afmt = dcn31_afmt_create(ctx, afmt_inst); 1241 1242 if (!enc1 || !vpg || !afmt) { 1243 kfree(enc1); 1244 kfree(vpg); 1245 kfree(afmt); 1246 return NULL; 1247 } 1248 1249 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1250 eng_id, vpg, afmt, 1251 &stream_enc_regs[eng_id], 1252 &se_shift, &se_mask); 1253 1254 return &enc1->base; 1255 } 1256 1257 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( 1258 enum engine_id eng_id, 1259 struct dc_context *ctx) 1260 { 1261 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; 1262 struct vpg *vpg; 1263 struct apg *apg; 1264 uint32_t hpo_dp_inst; 1265 uint32_t vpg_inst; 1266 uint32_t apg_inst; 1267 1268 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1269 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1270 1271 /* Mapping of VPG register blocks to HPO DP block instance: 1272 * VPG[6] -> HPO_DP[0] 1273 * VPG[7] -> HPO_DP[1] 1274 * VPG[8] -> HPO_DP[2] 1275 * VPG[9] -> HPO_DP[3] 1276 */ 1277 vpg_inst = hpo_dp_inst + 6; 1278 1279 /* Mapping of APG register blocks to HPO DP block instance: 1280 * APG[0] -> HPO_DP[0] 1281 * APG[1] -> HPO_DP[1] 1282 * APG[2] -> HPO_DP[2] 1283 * APG[3] -> HPO_DP[3] 1284 */ 1285 apg_inst = hpo_dp_inst; 1286 1287 /* allocate HPO stream encoder and create VPG sub-block */ 1288 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); 1289 vpg = dcn31_vpg_create(ctx, vpg_inst); 1290 apg = dcn31_apg_create(ctx, apg_inst); 1291 1292 if (!hpo_dp_enc31 || !vpg || !apg) { 1293 kfree(hpo_dp_enc31); 1294 kfree(vpg); 1295 kfree(apg); 1296 return NULL; 1297 } 1298 1299 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, 1300 hpo_dp_inst, eng_id, vpg, apg, 1301 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1302 &hpo_dp_se_shift, &hpo_dp_se_mask); 1303 1304 return &hpo_dp_enc31->base; 1305 } 1306 1307 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( 1308 uint8_t inst, 1309 struct dc_context *ctx) 1310 { 1311 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; 1312 1313 /* allocate HPO link encoder */ 1314 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); 1315 if (!hpo_dp_enc31) 1316 return NULL; /* out of memory */ 1317 1318 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, 1319 &hpo_dp_link_enc_regs[inst], 1320 &hpo_dp_le_shift, &hpo_dp_le_mask); 1321 1322 return &hpo_dp_enc31->base; 1323 } 1324 1325 static struct dce_hwseq *dcn31_hwseq_create( 1326 struct dc_context *ctx) 1327 { 1328 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1329 1330 if (hws) { 1331 hws->ctx = ctx; 1332 hws->regs = &hwseq_reg; 1333 hws->shifts = &hwseq_shift; 1334 hws->masks = &hwseq_mask; 1335 } 1336 return hws; 1337 } 1338 static const struct resource_create_funcs res_create_funcs = { 1339 .read_dce_straps = read_dce_straps, 1340 .create_audio = dcn31_create_audio, 1341 .create_stream_encoder = dcn31_stream_encoder_create, 1342 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, 1343 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, 1344 .create_hwseq = dcn31_hwseq_create, 1345 }; 1346 1347 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 1348 { 1349 unsigned int i; 1350 1351 for (i = 0; i < pool->base.stream_enc_count; i++) { 1352 if (pool->base.stream_enc[i] != NULL) { 1353 if (pool->base.stream_enc[i]->vpg != NULL) { 1354 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1355 pool->base.stream_enc[i]->vpg = NULL; 1356 } 1357 if (pool->base.stream_enc[i]->afmt != NULL) { 1358 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1359 pool->base.stream_enc[i]->afmt = NULL; 1360 } 1361 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1362 pool->base.stream_enc[i] = NULL; 1363 } 1364 } 1365 1366 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1367 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1368 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1369 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1370 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1371 } 1372 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1373 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1374 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1375 } 1376 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1377 pool->base.hpo_dp_stream_enc[i] = NULL; 1378 } 1379 } 1380 1381 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1382 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1383 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1384 pool->base.hpo_dp_link_enc[i] = NULL; 1385 } 1386 } 1387 1388 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1389 if (pool->base.dscs[i] != NULL) 1390 dcn20_dsc_destroy(&pool->base.dscs[i]); 1391 } 1392 1393 if (pool->base.mpc != NULL) { 1394 kfree(TO_DCN20_MPC(pool->base.mpc)); 1395 pool->base.mpc = NULL; 1396 } 1397 if (pool->base.hubbub != NULL) { 1398 kfree(pool->base.hubbub); 1399 pool->base.hubbub = NULL; 1400 } 1401 for (i = 0; i < pool->base.pipe_count; i++) { 1402 if (pool->base.dpps[i] != NULL) 1403 dcn31_dpp_destroy(&pool->base.dpps[i]); 1404 1405 if (pool->base.ipps[i] != NULL) 1406 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1407 1408 if (pool->base.hubps[i] != NULL) { 1409 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1410 pool->base.hubps[i] = NULL; 1411 } 1412 1413 if (pool->base.irqs != NULL) { 1414 dal_irq_service_destroy(&pool->base.irqs); 1415 } 1416 } 1417 1418 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1419 if (pool->base.engines[i] != NULL) 1420 dce110_engine_destroy(&pool->base.engines[i]); 1421 if (pool->base.hw_i2cs[i] != NULL) { 1422 kfree(pool->base.hw_i2cs[i]); 1423 pool->base.hw_i2cs[i] = NULL; 1424 } 1425 if (pool->base.sw_i2cs[i] != NULL) { 1426 kfree(pool->base.sw_i2cs[i]); 1427 pool->base.sw_i2cs[i] = NULL; 1428 } 1429 } 1430 1431 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1432 if (pool->base.opps[i] != NULL) 1433 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1434 } 1435 1436 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1437 if (pool->base.timing_generators[i] != NULL) { 1438 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1439 pool->base.timing_generators[i] = NULL; 1440 } 1441 } 1442 1443 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1444 if (pool->base.dwbc[i] != NULL) { 1445 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1446 pool->base.dwbc[i] = NULL; 1447 } 1448 if (pool->base.mcif_wb[i] != NULL) { 1449 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1450 pool->base.mcif_wb[i] = NULL; 1451 } 1452 } 1453 1454 for (i = 0; i < pool->base.audio_count; i++) { 1455 if (pool->base.audios[i]) 1456 dce_aud_destroy(&pool->base.audios[i]); 1457 } 1458 1459 for (i = 0; i < pool->base.clk_src_count; i++) { 1460 if (pool->base.clock_sources[i] != NULL) { 1461 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1462 pool->base.clock_sources[i] = NULL; 1463 } 1464 } 1465 1466 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1467 if (pool->base.mpc_lut[i] != NULL) { 1468 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1469 pool->base.mpc_lut[i] = NULL; 1470 } 1471 if (pool->base.mpc_shaper[i] != NULL) { 1472 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1473 pool->base.mpc_shaper[i] = NULL; 1474 } 1475 } 1476 1477 if (pool->base.dp_clock_source != NULL) { 1478 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1479 pool->base.dp_clock_source = NULL; 1480 } 1481 1482 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1483 if (pool->base.multiple_abms[i] != NULL) 1484 dce_abm_destroy(&pool->base.multiple_abms[i]); 1485 } 1486 1487 if (pool->base.psr != NULL) 1488 dmub_psr_destroy(&pool->base.psr); 1489 1490 if (pool->base.replay != NULL) 1491 dmub_replay_destroy(&pool->base.replay); 1492 1493 if (pool->base.dccg != NULL) 1494 dcn_dccg_destroy(&pool->base.dccg); 1495 } 1496 1497 static struct hubp *dcn31_hubp_create( 1498 struct dc_context *ctx, 1499 uint32_t inst) 1500 { 1501 struct dcn20_hubp *hubp2 = 1502 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1503 1504 if (!hubp2) 1505 return NULL; 1506 1507 if (hubp31_construct(hubp2, ctx, inst, 1508 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1509 return &hubp2->base; 1510 1511 BREAK_TO_DEBUGGER(); 1512 kfree(hubp2); 1513 return NULL; 1514 } 1515 1516 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1517 { 1518 int i; 1519 uint32_t pipe_count = pool->res_cap->num_dwb; 1520 1521 for (i = 0; i < pipe_count; i++) { 1522 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1523 GFP_KERNEL); 1524 1525 if (!dwbc30) { 1526 dm_error("DC: failed to create dwbc30!\n"); 1527 return false; 1528 } 1529 1530 dcn30_dwbc_construct(dwbc30, ctx, 1531 &dwbc30_regs[i], 1532 &dwbc30_shift, 1533 &dwbc30_mask, 1534 i); 1535 1536 pool->dwbc[i] = &dwbc30->base; 1537 } 1538 return true; 1539 } 1540 1541 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1542 { 1543 int i; 1544 uint32_t pipe_count = pool->res_cap->num_dwb; 1545 1546 for (i = 0; i < pipe_count; i++) { 1547 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1548 GFP_KERNEL); 1549 1550 if (!mcif_wb30) { 1551 dm_error("DC: failed to create mcif_wb30!\n"); 1552 return false; 1553 } 1554 1555 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1556 &mcif_wb30_regs[i], 1557 &mcif_wb30_shift, 1558 &mcif_wb30_mask, 1559 i); 1560 1561 pool->mcif_wb[i] = &mcif_wb30->base; 1562 } 1563 return true; 1564 } 1565 1566 static struct display_stream_compressor *dcn31_dsc_create( 1567 struct dc_context *ctx, uint32_t inst) 1568 { 1569 struct dcn20_dsc *dsc = 1570 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1571 1572 if (!dsc) { 1573 BREAK_TO_DEBUGGER(); 1574 return NULL; 1575 } 1576 1577 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1578 return &dsc->base; 1579 } 1580 1581 static void dcn31_destroy_resource_pool(struct resource_pool **pool) 1582 { 1583 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool); 1584 1585 dcn31_resource_destruct(dcn31_pool); 1586 kfree(dcn31_pool); 1587 *pool = NULL; 1588 } 1589 1590 static struct clock_source *dcn31_clock_source_create( 1591 struct dc_context *ctx, 1592 struct dc_bios *bios, 1593 enum clock_source_id id, 1594 const struct dce110_clk_src_regs *regs, 1595 bool dp_clk_src) 1596 { 1597 struct dce110_clk_src *clk_src = 1598 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1599 1600 if (!clk_src) 1601 return NULL; 1602 1603 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1604 regs, &cs_shift, &cs_mask)) { 1605 clk_src->base.dp_clk_src = dp_clk_src; 1606 return &clk_src->base; 1607 } 1608 1609 kfree(clk_src); 1610 BREAK_TO_DEBUGGER(); 1611 return NULL; 1612 } 1613 1614 static bool is_dual_plane(enum surface_pixel_format format) 1615 { 1616 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; 1617 } 1618 1619 int dcn31x_populate_dml_pipes_from_context(struct dc *dc, 1620 struct dc_state *context, 1621 display_e2e_pipe_params_st *pipes, 1622 enum dc_validate_mode validate_mode) 1623 { 1624 uint32_t pipe_cnt; 1625 int i; 1626 1627 dc_assert_fp_enabled(); 1628 1629 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); 1630 1631 for (i = 0; i < pipe_cnt; i++) { 1632 pipes[i].pipe.src.gpuvm = 1; 1633 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) { 1634 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; 1635 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled; 1636 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE) 1637 pipes[i].pipe.src.hostvm = false; 1638 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE) 1639 pipes[i].pipe.src.hostvm = true; 1640 } 1641 return pipe_cnt; 1642 } 1643 1644 int dcn31_populate_dml_pipes_from_context( 1645 struct dc *dc, struct dc_state *context, 1646 display_e2e_pipe_params_st *pipes, 1647 enum dc_validate_mode validate_mode) 1648 { 1649 int i, pipe_cnt; 1650 struct resource_context *res_ctx = &context->res_ctx; 1651 struct pipe_ctx *pipe = 0; 1652 bool upscaled = false; 1653 1654 DC_FP_START(); 1655 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); 1656 DC_FP_END(); 1657 1658 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1659 struct dc_crtc_timing *timing; 1660 1661 if (!res_ctx->pipe_ctx[i].stream) 1662 continue; 1663 pipe = &res_ctx->pipe_ctx[i]; 1664 timing = &pipe->stream->timing; 1665 if (pipe->plane_state && 1666 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || 1667 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) 1668 upscaled = true; 1669 1670 /* 1671 * Immediate flip can be set dynamically after enabling the plane. 1672 * We need to require support for immediate flip or underflow can be 1673 * intermittently experienced depending on peak b/w requirements. 1674 */ 1675 pipes[pipe_cnt].pipe.src.immediate_flip = true; 1676 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; 1677 pipes[pipe_cnt].pipe.src.gpuvm = true; 1678 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; 1679 pipes[pipe_cnt].pipe.src.dcc_rate = 3; 1680 pipes[pipe_cnt].dout.dsc_input_bpc = 0; 1681 DC_FP_START(); 1682 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); 1683 DC_FP_END(); 1684 1685 1686 if (pipes[pipe_cnt].dout.dsc_enable) { 1687 switch (timing->display_color_depth) { 1688 case COLOR_DEPTH_888: 1689 pipes[pipe_cnt].dout.dsc_input_bpc = 8; 1690 break; 1691 case COLOR_DEPTH_101010: 1692 pipes[pipe_cnt].dout.dsc_input_bpc = 10; 1693 break; 1694 case COLOR_DEPTH_121212: 1695 pipes[pipe_cnt].dout.dsc_input_bpc = 12; 1696 break; 1697 default: 1698 ASSERT(0); 1699 break; 1700 } 1701 } 1702 1703 pipe_cnt++; 1704 } 1705 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; 1706 dc->config.enable_4to1MPC = false; 1707 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) { 1708 if (is_dual_plane(pipe->plane_state->format) 1709 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { 1710 dc->config.enable_4to1MPC = true; 1711 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { 1712 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ 1713 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1714 pipes[0].pipe.src.unbounded_req_mode = true; 1715 } 1716 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count 1717 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { 1718 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; 1719 } else if (context->stream_count >= 3 && upscaled) { 1720 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; 1721 } 1722 1723 return pipe_cnt; 1724 } 1725 1726 unsigned int dcn31_get_det_buffer_size( 1727 const struct dc_state *context) 1728 { 1729 return context->bw_ctx.dml.ip.det_buffer_size_kbytes; 1730 } 1731 1732 void dcn31_calculate_wm_and_dlg( 1733 struct dc *dc, struct dc_state *context, 1734 display_e2e_pipe_params_st *pipes, 1735 int pipe_cnt, 1736 int vlevel) 1737 { 1738 DC_FP_START(); 1739 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1740 DC_FP_END(); 1741 } 1742 1743 void 1744 dcn31_populate_dml_writeback_from_context(struct dc *dc, 1745 struct resource_context *res_ctx, 1746 display_e2e_pipe_params_st *pipes) 1747 { 1748 DC_FP_START(); 1749 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes); 1750 DC_FP_END(); 1751 } 1752 1753 void 1754 dcn31_set_mcif_arb_params(struct dc *dc, 1755 struct dc_state *context, 1756 display_e2e_pipe_params_st *pipes, 1757 int pipe_cnt) 1758 { 1759 DC_FP_START(); 1760 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt); 1761 DC_FP_END(); 1762 } 1763 1764 enum dc_status dcn31_validate_bandwidth(struct dc *dc, 1765 struct dc_state *context, 1766 enum dc_validate_mode validate_mode) 1767 { 1768 bool out = false; 1769 1770 BW_VAL_TRACE_SETUP(); 1771 1772 int vlevel = 0; 1773 int pipe_cnt = 0; 1774 display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count, 1775 sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 1776 DC_LOGGER_INIT(dc->ctx->logger); 1777 1778 BW_VAL_TRACE_COUNT(); 1779 1780 if (!pipes) 1781 goto validate_fail; 1782 1783 DC_FP_START(); 1784 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true); 1785 DC_FP_END(); 1786 1787 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg 1788 if (pipe_cnt == 0) 1789 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING; 1790 1791 if (!out) 1792 goto validate_fail; 1793 1794 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 1795 1796 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) { 1797 BW_VAL_TRACE_SKIP(fast); 1798 goto validate_out; 1799 } 1800 if (dc->res_pool->funcs->calculate_wm_and_dlg) 1801 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 1802 1803 BW_VAL_TRACE_END_WATERMARKS(); 1804 1805 goto validate_out; 1806 1807 validate_fail: 1808 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 1809 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 1810 1811 BW_VAL_TRACE_SKIP(fail); 1812 out = false; 1813 1814 validate_out: 1815 kfree(pipes); 1816 1817 BW_VAL_TRACE_FINISH(); 1818 1819 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1820 } 1821 1822 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config) 1823 { 1824 *panel_config = panel_config_defaults; 1825 } 1826 1827 static struct dc_cap_funcs cap_funcs = { 1828 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1829 }; 1830 1831 static struct resource_funcs dcn31_res_pool_funcs = { 1832 .destroy = dcn31_destroy_resource_pool, 1833 .link_enc_create = dcn31_link_encoder_create, 1834 .link_enc_create_minimal = dcn31_link_enc_create_minimal, 1835 .link_encs_assign = link_enc_cfg_link_encs_assign, 1836 .link_enc_unassign = link_enc_cfg_link_enc_unassign, 1837 .panel_cntl_create = dcn31_panel_cntl_create, 1838 .validate_bandwidth = dcn31_validate_bandwidth, 1839 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, 1840 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, 1841 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context, 1842 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1843 .release_pipe = dcn20_release_pipe, 1844 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1845 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1846 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1847 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, 1848 .set_mcif_arb_params = dcn31_set_mcif_arb_params, 1849 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1850 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1851 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1852 .update_bw_bounding_box = dcn31_update_bw_bounding_box, 1853 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1854 .get_panel_config_defaults = dcn31_get_panel_config_defaults, 1855 .get_det_buffer_size = dcn31_get_det_buffer_size, 1856 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, 1857 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, 1858 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params 1859 }; 1860 1861 static struct clock_source *dcn30_clock_source_create( 1862 struct dc_context *ctx, 1863 struct dc_bios *bios, 1864 enum clock_source_id id, 1865 const struct dce110_clk_src_regs *regs, 1866 bool dp_clk_src) 1867 { 1868 struct dce110_clk_src *clk_src = 1869 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1870 1871 if (!clk_src) 1872 return NULL; 1873 1874 if (dcn31_clk_src_construct(clk_src, ctx, bios, id, 1875 regs, &cs_shift, &cs_mask)) { 1876 clk_src->base.dp_clk_src = dp_clk_src; 1877 return &clk_src->base; 1878 } 1879 1880 kfree(clk_src); 1881 BREAK_TO_DEBUGGER(); 1882 return NULL; 1883 } 1884 1885 static bool dcn31_resource_construct( 1886 uint8_t num_virtual_links, 1887 struct dc *dc, 1888 struct dcn31_resource_pool *pool) 1889 { 1890 int i; 1891 struct dc_context *ctx = dc->ctx; 1892 struct irq_service_init_data init_data; 1893 1894 ctx->dc_bios->regs = &bios_regs; 1895 1896 pool->base.res_cap = &res_cap_dcn31; 1897 1898 pool->base.funcs = &dcn31_res_pool_funcs; 1899 1900 /************************************************* 1901 * Resource + asic cap harcoding * 1902 *************************************************/ 1903 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1904 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1905 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1906 dc->caps.max_downscale_ratio = 600; 1907 dc->caps.i2c_speed_in_khz = 100; 1908 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/ 1909 dc->caps.max_cursor_size = 256; 1910 dc->caps.min_horizontal_blanking_period = 80; 1911 dc->caps.dmdata_alloc_size = 2048; 1912 1913 dc->caps.max_slave_planes = 2; 1914 dc->caps.max_slave_yuv_planes = 2; 1915 dc->caps.max_slave_rgb_planes = 2; 1916 dc->caps.post_blend_color_processing = true; 1917 dc->caps.force_dp_tps4_for_cp2520 = true; 1918 if (dc->config.forceHBR2CP2520) 1919 dc->caps.force_dp_tps4_for_cp2520 = false; 1920 dc->caps.dp_hpo = true; 1921 dc->caps.dp_hdmi21_pcon_support = true; 1922 dc->caps.edp_dsc_support = true; 1923 dc->caps.extended_aux_timeout_support = true; 1924 dc->caps.dmcub_support = true; 1925 dc->caps.is_apu = true; 1926 dc->caps.zstate_support = true; 1927 1928 /* Color pipeline capabilities */ 1929 dc->caps.color.dpp.dcn_arch = 1; 1930 dc->caps.color.dpp.input_lut_shared = 0; 1931 dc->caps.color.dpp.icsc = 1; 1932 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1933 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1934 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1935 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1936 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1937 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1938 dc->caps.color.dpp.post_csc = 1; 1939 dc->caps.color.dpp.gamma_corr = 1; 1940 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1941 1942 dc->caps.color.dpp.hw_3d_lut = 1; 1943 dc->caps.color.dpp.ogam_ram = 1; 1944 // no OGAM ROM on DCN301 1945 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1946 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1947 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1948 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1949 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1950 dc->caps.color.dpp.ocsc = 0; 1951 1952 dc->caps.color.mpc.gamut_remap = 1; 1953 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1954 dc->caps.color.mpc.ogam_ram = 1; 1955 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1956 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1957 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1958 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1959 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1960 dc->caps.color.mpc.ocsc = 1; 1961 1962 dc->caps.num_of_host_routers = 2; 1963 dc->caps.num_of_dpias_per_host_router = 2; 1964 1965 /* Use pipe context based otg sync logic */ 1966 dc->config.use_pipe_ctx_sync_logic = true; 1967 dc->config.disable_hbr_audio_dp2 = true; 1968 1969 /* read VBIOS LTTPR caps */ 1970 { 1971 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1972 enum bp_result bp_query_result; 1973 uint8_t is_vbios_lttpr_enable = 0; 1974 1975 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1976 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1977 } 1978 1979 /* interop bit is implicit */ 1980 { 1981 dc->caps.vbios_lttpr_aware = true; 1982 } 1983 } 1984 dc->check_config = config_defaults; 1985 1986 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1987 dc->debug = debug_defaults_drv; 1988 1989 // Init the vm_helper 1990 if (dc->vm_helper) 1991 vm_helper_init(dc->vm_helper, 16); 1992 1993 /************************************************* 1994 * Create resources * 1995 *************************************************/ 1996 1997 /* Clock Sources for Pixel Clock*/ 1998 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = 1999 dcn30_clock_source_create(ctx, ctx->dc_bios, 2000 CLOCK_SOURCE_COMBO_PHY_PLL0, 2001 &clk_src_regs[0], false); 2002 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = 2003 dcn30_clock_source_create(ctx, ctx->dc_bios, 2004 CLOCK_SOURCE_COMBO_PHY_PLL1, 2005 &clk_src_regs[1], false); 2006 /*move phypllx_pixclk_resync to dmub next*/ 2007 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 2008 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2009 dcn30_clock_source_create(ctx, ctx->dc_bios, 2010 CLOCK_SOURCE_COMBO_PHY_PLL2, 2011 &clk_src_regs_b0[2], false); 2012 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2013 dcn30_clock_source_create(ctx, ctx->dc_bios, 2014 CLOCK_SOURCE_COMBO_PHY_PLL3, 2015 &clk_src_regs_b0[3], false); 2016 } else { 2017 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = 2018 dcn30_clock_source_create(ctx, ctx->dc_bios, 2019 CLOCK_SOURCE_COMBO_PHY_PLL2, 2020 &clk_src_regs[2], false); 2021 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = 2022 dcn30_clock_source_create(ctx, ctx->dc_bios, 2023 CLOCK_SOURCE_COMBO_PHY_PLL3, 2024 &clk_src_regs[3], false); 2025 } 2026 2027 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = 2028 dcn30_clock_source_create(ctx, ctx->dc_bios, 2029 CLOCK_SOURCE_COMBO_PHY_PLL4, 2030 &clk_src_regs[4], false); 2031 2032 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2033 2034 /* todo: not reuse phy_pll registers */ 2035 pool->base.dp_clock_source = 2036 dcn31_clock_source_create(ctx, ctx->dc_bios, 2037 CLOCK_SOURCE_ID_DP_DTO, 2038 &clk_src_regs[0], true); 2039 2040 for (i = 0; i < pool->base.clk_src_count; i++) { 2041 if (pool->base.clock_sources[i] == NULL) { 2042 dm_error("DC: failed to create clock sources!\n"); 2043 BREAK_TO_DEBUGGER(); 2044 goto create_fail; 2045 } 2046 } 2047 2048 /* TODO: DCCG */ 2049 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2050 if (pool->base.dccg == NULL) { 2051 dm_error("DC: failed to create dccg!\n"); 2052 BREAK_TO_DEBUGGER(); 2053 goto create_fail; 2054 } 2055 2056 /* TODO: IRQ */ 2057 init_data.ctx = dc->ctx; 2058 pool->base.irqs = dal_irq_service_dcn31_create(&init_data); 2059 if (!pool->base.irqs) 2060 goto create_fail; 2061 2062 /* HUBBUB */ 2063 pool->base.hubbub = dcn31_hubbub_create(ctx); 2064 if (pool->base.hubbub == NULL) { 2065 BREAK_TO_DEBUGGER(); 2066 dm_error("DC: failed to create hubbub!\n"); 2067 goto create_fail; 2068 } 2069 2070 /* HUBPs, DPPs, OPPs and TGs */ 2071 for (i = 0; i < pool->base.pipe_count; i++) { 2072 pool->base.hubps[i] = dcn31_hubp_create(ctx, i); 2073 if (pool->base.hubps[i] == NULL) { 2074 BREAK_TO_DEBUGGER(); 2075 dm_error( 2076 "DC: failed to create hubps!\n"); 2077 goto create_fail; 2078 } 2079 2080 pool->base.dpps[i] = dcn31_dpp_create(ctx, i); 2081 if (pool->base.dpps[i] == NULL) { 2082 BREAK_TO_DEBUGGER(); 2083 dm_error( 2084 "DC: failed to create dpps!\n"); 2085 goto create_fail; 2086 } 2087 } 2088 2089 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2090 pool->base.opps[i] = dcn31_opp_create(ctx, i); 2091 if (pool->base.opps[i] == NULL) { 2092 BREAK_TO_DEBUGGER(); 2093 dm_error( 2094 "DC: failed to create output pixel processor!\n"); 2095 goto create_fail; 2096 } 2097 } 2098 2099 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2100 pool->base.timing_generators[i] = dcn31_timing_generator_create( 2101 ctx, i); 2102 if (pool->base.timing_generators[i] == NULL) { 2103 BREAK_TO_DEBUGGER(); 2104 dm_error("DC: failed to create tg!\n"); 2105 goto create_fail; 2106 } 2107 } 2108 pool->base.timing_generator_count = i; 2109 2110 /* PSR */ 2111 pool->base.psr = dmub_psr_create(ctx); 2112 if (pool->base.psr == NULL) { 2113 dm_error("DC: failed to create psr obj!\n"); 2114 BREAK_TO_DEBUGGER(); 2115 goto create_fail; 2116 } 2117 2118 /* Replay */ 2119 pool->base.replay = dmub_replay_create(ctx); 2120 if (pool->base.replay == NULL) { 2121 dm_error("DC: failed to create replay obj!\n"); 2122 BREAK_TO_DEBUGGER(); 2123 goto create_fail; 2124 } 2125 2126 /* ABM */ 2127 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2128 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2129 &abm_regs[i], 2130 &abm_shift, 2131 &abm_mask); 2132 if (pool->base.multiple_abms[i] == NULL) { 2133 dm_error("DC: failed to create abm for pipe %d!\n", i); 2134 BREAK_TO_DEBUGGER(); 2135 goto create_fail; 2136 } 2137 } 2138 2139 /* MPC and DSC */ 2140 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2141 if (pool->base.mpc == NULL) { 2142 BREAK_TO_DEBUGGER(); 2143 dm_error("DC: failed to create mpc!\n"); 2144 goto create_fail; 2145 } 2146 2147 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2148 pool->base.dscs[i] = dcn31_dsc_create(ctx, i); 2149 if (pool->base.dscs[i] == NULL) { 2150 BREAK_TO_DEBUGGER(); 2151 dm_error("DC: failed to create display stream compressor %d!\n", i); 2152 goto create_fail; 2153 } 2154 } 2155 2156 /* DWB and MMHUBBUB */ 2157 if (!dcn31_dwbc_create(ctx, &pool->base)) { 2158 BREAK_TO_DEBUGGER(); 2159 dm_error("DC: failed to create dwbc!\n"); 2160 goto create_fail; 2161 } 2162 2163 if (!dcn31_mmhubbub_create(ctx, &pool->base)) { 2164 BREAK_TO_DEBUGGER(); 2165 dm_error("DC: failed to create mcif_wb!\n"); 2166 goto create_fail; 2167 } 2168 2169 /* AUX and I2C */ 2170 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2171 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); 2172 if (pool->base.engines[i] == NULL) { 2173 BREAK_TO_DEBUGGER(); 2174 dm_error( 2175 "DC:failed to create aux engine!!\n"); 2176 goto create_fail; 2177 } 2178 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); 2179 if (pool->base.hw_i2cs[i] == NULL) { 2180 BREAK_TO_DEBUGGER(); 2181 dm_error( 2182 "DC:failed to create hw i2c!!\n"); 2183 goto create_fail; 2184 } 2185 pool->base.sw_i2cs[i] = NULL; 2186 } 2187 2188 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && 2189 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 && 2190 !dc->debug.dpia_debug.bits.disable_dpia) { 2191 /* YELLOW CARP B0 has 4 DPIA's */ 2192 pool->base.usb4_dpia_count = 4; 2193 } 2194 2195 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1) 2196 pool->base.usb4_dpia_count = 4; 2197 2198 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2199 if (!resource_construct(num_virtual_links, dc, &pool->base, 2200 &res_create_funcs)) 2201 goto create_fail; 2202 2203 /* HW Sequencer and Plane caps */ 2204 dcn31_hw_sequencer_construct(dc); 2205 2206 dc->caps.max_planes = pool->base.pipe_count; 2207 2208 for (i = 0; i < dc->caps.max_planes; ++i) 2209 dc->caps.planes[i] = plane_cap; 2210 2211 dc->caps.max_odm_combine_factor = 4; 2212 2213 dc->cap_funcs = cap_funcs; 2214 2215 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp; 2216 2217 return true; 2218 2219 create_fail: 2220 dcn31_resource_destruct(pool); 2221 2222 return false; 2223 } 2224 2225 struct resource_pool *dcn31_create_resource_pool( 2226 const struct dc_init_data *init_data, 2227 struct dc *dc) 2228 { 2229 struct dcn31_resource_pool *pool = 2230 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL); 2231 2232 if (!pool) 2233 return NULL; 2234 2235 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool)) 2236 return &pool->base; 2237 2238 BREAK_TO_DEBUGGER(); 2239 kfree(pool); 2240 return NULL; 2241 } 2242 2243 enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, 2244 struct dc_link_settings *link_setting, 2245 uint8_t pipe_count, 2246 struct pipe_ctx *pipes, 2247 struct audio_output *audio_output) 2248 { 2249 struct dc_state *state = link->dc->current_state; 2250 int i; 2251 2252 #if defined(CONFIG_DRM_AMD_DC_FP) 2253 for (i = 0; i < state->stream_count; i++) 2254 if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) 2255 link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]); 2256 2257 for (i = 0; i < pipe_count; i++) { 2258 link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); 2259 2260 // Setup audio 2261 if (pipes[i].stream_res.audio != NULL) 2262 build_audio_output(state, &pipes[i], &audio_output[i]); 2263 } 2264 #else 2265 /* This DCN requires rate divider updates and audio reprogramming to allow DP1<-->DP2 link rate switching, 2266 * but the above will not compile on architectures without an FPU. 2267 */ 2268 DC_LOG_WARNING("%s: DP1<-->DP2 link retraining will not work on this DCN on non-FPU platforms", __func__); 2269 ASSERT(0); 2270 #endif 2271 2272 return DC_OK; 2273 } 2274