1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dml/dcn30/dcn30_fpu.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn31/dcn31_apg.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn31/dcn31_vpg.h"
62 #include "dcn31/dcn31_afmt.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "dio/dcn10/dcn10_dio.h"
68 #include "dio/virtual/virtual_stream_encoder.h"
69 #include "dce110/dce110_resource.h"
70 #include "dml/display_mode_vba.h"
71 #include "dml/dcn31/dcn31_fpu.h"
72 #include "dcn31/dcn31_dccg.h"
73 #include "dcn10/dcn10_resource.h"
74 #include "dcn31/dcn31_panel_cntl.h"
75
76 #include "dcn30/dcn30_dwb.h"
77 #include "dcn30/dcn30_mmhubbub.h"
78
79 #include "yellow_carp_offset.h"
80 #include "dcn/dcn_3_1_2_offset.h"
81 #include "dcn/dcn_3_1_2_sh_mask.h"
82 #include "nbio/nbio_7_2_0_offset.h"
83 #include "dpcs/dpcs_4_2_0_offset.h"
84 #include "dpcs/dpcs_4_2_0_sh_mask.h"
85 #include "mmhub/mmhub_2_3_0_offset.h"
86 #include "mmhub/mmhub_2_3_0_sh_mask.h"
87
88
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99 #include "dce/dmub_replay.h"
100
101 #include "dml/dcn30/display_mode_vba_30.h"
102 #include "vm_helper.h"
103 #include "dcn20/dcn20_vmid.h"
104
105 #include "link_enc_cfg.h"
106
107 #define DC_LOGGER \
108 dc->ctx->logger
109 #define DC_LOGGER_INIT(logger)
110
111 enum dcn31_clk_src_array_id {
112 DCN31_CLK_SRC_PLL0,
113 DCN31_CLK_SRC_PLL1,
114 DCN31_CLK_SRC_PLL2,
115 DCN31_CLK_SRC_PLL3,
116 DCN31_CLK_SRC_PLL4,
117 DCN30_CLK_SRC_TOTAL
118 };
119
120 /* begin *********************
121 * macros to expend register list macro defined in HW object header file
122 */
123
124 /* DCN */
125 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
126
127 #define BASE(seg) BASE_INNER(seg)
128
129 #define SR(reg_name)\
130 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
131 reg ## reg_name
132
133 #define SRI(reg_name, block, id)\
134 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
136
137 #define SRI2(reg_name, block, id)\
138 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
139 reg ## reg_name
140
141 #define SRIR(var_name, reg_name, block, id)\
142 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRII(reg_name, block, id)\
146 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SRII_MPC_RMU(reg_name, block, id)\
150 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SRII_DWB(reg_name, temp_name, block, id)\
154 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## temp_name
156
157 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
158 .field_name = reg_name ## __ ## field_name ## post_fix
159
160 #define DCCG_SRII(reg_name, block, id)\
161 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define VUPDATE_SRII(reg_name, block, id)\
165 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
166 reg ## reg_name ## _ ## block ## id
167
168 /* NBIO */
169 #define NBIO_BASE_INNER(seg) \
170 NBIO_BASE__INST0_SEG ## seg
171
172 #define NBIO_BASE(seg) \
173 NBIO_BASE_INNER(seg)
174
175 #define NBIO_SR(reg_name)\
176 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
177 regBIF_BX1_ ## reg_name
178
179 /* MMHUB */
180 #define MMHUB_BASE_INNER(seg) \
181 MMHUB_BASE__INST0_SEG ## seg
182
183 #define MMHUB_BASE(seg) \
184 MMHUB_BASE_INNER(seg)
185
186 #define MMHUB_SR(reg_name)\
187 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
188 mm ## reg_name
189
190 /* CLOCK */
191 #define CLK_BASE_INNER(seg) \
192 CLK_BASE__INST0_SEG ## seg
193
194 #define CLK_BASE(seg) \
195 CLK_BASE_INNER(seg)
196
197 #define CLK_SRI(reg_name, block, inst)\
198 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
199 reg ## block ## _ ## inst ## _ ## reg_name
200
201
202 static const struct bios_registers bios_regs = {
203 NBIO_SR(BIOS_SCRATCH_3),
204 NBIO_SR(BIOS_SCRATCH_6)
205 };
206
207 #define clk_src_regs(index, pllid)\
208 [index] = {\
209 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
210 }
211
212 static const struct dce110_clk_src_regs clk_src_regs[] = {
213 clk_src_regs(0, A),
214 clk_src_regs(1, B),
215 clk_src_regs(2, C),
216 clk_src_regs(3, D),
217 clk_src_regs(4, E)
218 };
219 /*pll_id being rempped in dmub, in driver it is logical instance*/
220 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
221 clk_src_regs(0, A),
222 clk_src_regs(1, B),
223 clk_src_regs(2, F),
224 clk_src_regs(3, G),
225 clk_src_regs(4, E)
226 };
227
228 static const struct dce110_clk_src_shift cs_shift = {
229 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
230 };
231
232 static const struct dce110_clk_src_mask cs_mask = {
233 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
234 };
235
236 #define abm_regs(id)\
237 [id] = {\
238 ABM_DCN302_REG_LIST(id)\
239 }
240
241 static const struct dce_abm_registers abm_regs[] = {
242 abm_regs(0),
243 abm_regs(1),
244 abm_regs(2),
245 abm_regs(3),
246 };
247
248 static const struct dce_abm_shift abm_shift = {
249 ABM_MASK_SH_LIST_DCN30(__SHIFT)
250 };
251
252 static const struct dce_abm_mask abm_mask = {
253 ABM_MASK_SH_LIST_DCN30(_MASK)
254 };
255
256 #define audio_regs(id)\
257 [id] = {\
258 AUD_COMMON_REG_LIST(id)\
259 }
260
261 static const struct dce_audio_registers audio_regs[] = {
262 audio_regs(0),
263 audio_regs(1),
264 audio_regs(2),
265 audio_regs(3),
266 audio_regs(4),
267 audio_regs(5),
268 audio_regs(6)
269 };
270
271 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
274 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
275
276 static const struct dce_audio_shift audio_shift = {
277 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_audio_mask audio_mask = {
281 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
282 };
283
284 #define vpg_regs(id)\
285 [id] = {\
286 VPG_DCN31_REG_LIST(id)\
287 }
288
289 static const struct dcn31_vpg_registers vpg_regs[] = {
290 vpg_regs(0),
291 vpg_regs(1),
292 vpg_regs(2),
293 vpg_regs(3),
294 vpg_regs(4),
295 vpg_regs(5),
296 vpg_regs(6),
297 vpg_regs(7),
298 vpg_regs(8),
299 vpg_regs(9),
300 };
301
302 static const struct dcn31_vpg_shift vpg_shift = {
303 DCN31_VPG_MASK_SH_LIST(__SHIFT)
304 };
305
306 static const struct dcn31_vpg_mask vpg_mask = {
307 DCN31_VPG_MASK_SH_LIST(_MASK)
308 };
309
310 #define afmt_regs(id)\
311 [id] = {\
312 AFMT_DCN31_REG_LIST(id)\
313 }
314
315 static const struct dcn31_afmt_registers afmt_regs[] = {
316 afmt_regs(0),
317 afmt_regs(1),
318 afmt_regs(2),
319 afmt_regs(3),
320 afmt_regs(4),
321 afmt_regs(5)
322 };
323
324 static const struct dcn31_afmt_shift afmt_shift = {
325 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
326 };
327
328 static const struct dcn31_afmt_mask afmt_mask = {
329 DCN31_AFMT_MASK_SH_LIST(_MASK)
330 };
331
332 #define apg_regs(id)\
333 [id] = {\
334 APG_DCN31_REG_LIST(id)\
335 }
336
337 static const struct dcn31_apg_registers apg_regs[] = {
338 apg_regs(0),
339 apg_regs(1),
340 apg_regs(2),
341 apg_regs(3)
342 };
343
344 static const struct dcn31_apg_shift apg_shift = {
345 DCN31_APG_MASK_SH_LIST(__SHIFT)
346 };
347
348 static const struct dcn31_apg_mask apg_mask = {
349 DCN31_APG_MASK_SH_LIST(_MASK)
350 };
351
352 #define stream_enc_regs(id)\
353 [id] = {\
354 SE_DCN3_REG_LIST(id)\
355 }
356
357 /* Some encoders won't be initialized here - but they're logical, not physical. */
358 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
359 stream_enc_regs(0),
360 stream_enc_regs(1),
361 stream_enc_regs(2),
362 stream_enc_regs(3),
363 stream_enc_regs(4)
364 };
365
366 static const struct dcn10_stream_encoder_shift se_shift = {
367 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
368 };
369
370 static const struct dcn10_stream_encoder_mask se_mask = {
371 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
372 };
373
374
375 #define aux_regs(id)\
376 [id] = {\
377 DCN2_AUX_REG_LIST(id)\
378 }
379
380 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
381 aux_regs(0),
382 aux_regs(1),
383 aux_regs(2),
384 aux_regs(3),
385 aux_regs(4)
386 };
387
388 #define hpd_regs(id)\
389 [id] = {\
390 HPD_REG_LIST(id)\
391 }
392
393 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
394 hpd_regs(0),
395 hpd_regs(1),
396 hpd_regs(2),
397 hpd_regs(3),
398 hpd_regs(4)
399 };
400
401 #define link_regs(id, phyid)\
402 [id] = {\
403 LE_DCN31_REG_LIST(id), \
404 UNIPHY_DCN2_REG_LIST(phyid), \
405 DPCS_DCN31_REG_LIST(id), \
406 }
407
408 static const struct dce110_aux_registers_shift aux_shift = {
409 DCN_AUX_MASK_SH_LIST(__SHIFT)
410 };
411
412 static const struct dce110_aux_registers_mask aux_mask = {
413 DCN_AUX_MASK_SH_LIST(_MASK)
414 };
415
416 static const struct dcn10_link_enc_registers link_enc_regs[] = {
417 link_regs(0, A),
418 link_regs(1, B),
419 link_regs(2, C),
420 link_regs(3, D),
421 link_regs(4, E)
422 };
423
424 static const struct dcn10_link_enc_shift le_shift = {
425 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
426 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
427 };
428
429 static const struct dcn10_link_enc_mask le_mask = {
430 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
431 DPCS_DCN31_MASK_SH_LIST(_MASK)
432 };
433
434 #define hpo_dp_stream_encoder_reg_list(id)\
435 [id] = {\
436 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
437 }
438
439 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
440 hpo_dp_stream_encoder_reg_list(0),
441 hpo_dp_stream_encoder_reg_list(1),
442 hpo_dp_stream_encoder_reg_list(2),
443 hpo_dp_stream_encoder_reg_list(3),
444 };
445
446 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
447 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
448 };
449
450 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
451 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
452 };
453
454 #define hpo_dp_link_encoder_reg_list(id)\
455 [id] = {\
456 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
457 DCN3_1_RDPCSTX_REG_LIST(0),\
458 DCN3_1_RDPCSTX_REG_LIST(1),\
459 DCN3_1_RDPCSTX_REG_LIST(2),\
460 DCN3_1_RDPCSTX_REG_LIST(3),\
461 DCN3_1_RDPCSTX_REG_LIST(4)\
462 }
463
464 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
465 hpo_dp_link_encoder_reg_list(0),
466 hpo_dp_link_encoder_reg_list(1),
467 };
468
469 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
470 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
471 };
472
473 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
474 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
475 };
476
477 #define dpp_regs(id)\
478 [id] = {\
479 DPP_REG_LIST_DCN30(id),\
480 }
481
482 static const struct dcn3_dpp_registers dpp_regs[] = {
483 dpp_regs(0),
484 dpp_regs(1),
485 dpp_regs(2),
486 dpp_regs(3)
487 };
488
489 static const struct dcn3_dpp_shift tf_shift = {
490 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
491 };
492
493 static const struct dcn3_dpp_mask tf_mask = {
494 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
495 };
496
497 #define opp_regs(id)\
498 [id] = {\
499 OPP_REG_LIST_DCN30(id),\
500 }
501
502 static const struct dcn20_opp_registers opp_regs[] = {
503 opp_regs(0),
504 opp_regs(1),
505 opp_regs(2),
506 opp_regs(3)
507 };
508
509 static const struct dcn20_opp_shift opp_shift = {
510 OPP_MASK_SH_LIST_DCN20(__SHIFT)
511 };
512
513 static const struct dcn20_opp_mask opp_mask = {
514 OPP_MASK_SH_LIST_DCN20(_MASK)
515 };
516
517 #define aux_engine_regs(id)\
518 [id] = {\
519 AUX_COMMON_REG_LIST0(id), \
520 .AUXN_IMPCAL = 0, \
521 .AUXP_IMPCAL = 0, \
522 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
523 }
524
525 static const struct dce110_aux_registers aux_engine_regs[] = {
526 aux_engine_regs(0),
527 aux_engine_regs(1),
528 aux_engine_regs(2),
529 aux_engine_regs(3),
530 aux_engine_regs(4)
531 };
532
533 #define dwbc_regs_dcn3(id)\
534 [id] = {\
535 DWBC_COMMON_REG_LIST_DCN30(id),\
536 }
537
538 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
539 dwbc_regs_dcn3(0),
540 };
541
542 static const struct dcn30_dwbc_shift dwbc30_shift = {
543 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
544 };
545
546 static const struct dcn30_dwbc_mask dwbc30_mask = {
547 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
548 };
549
550 #define mcif_wb_regs_dcn3(id)\
551 [id] = {\
552 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
553 }
554
555 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
556 mcif_wb_regs_dcn3(0)
557 };
558
559 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
560 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
561 };
562
563 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
564 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
565 };
566
567 #define dsc_regsDCN20(id)\
568 [id] = {\
569 DSC_REG_LIST_DCN20(id)\
570 }
571
572 static const struct dcn20_dsc_registers dsc_regs[] = {
573 dsc_regsDCN20(0),
574 dsc_regsDCN20(1),
575 dsc_regsDCN20(2)
576 };
577
578 static const struct dcn20_dsc_shift dsc_shift = {
579 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
580 };
581
582 static const struct dcn20_dsc_mask dsc_mask = {
583 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
584 };
585
586 static const struct dcn30_mpc_registers mpc_regs = {
587 MPC_REG_LIST_DCN3_0(0),
588 MPC_REG_LIST_DCN3_0(1),
589 MPC_REG_LIST_DCN3_0(2),
590 MPC_REG_LIST_DCN3_0(3),
591 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
592 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
593 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
594 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
595 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
596 MPC_RMU_REG_LIST_DCN3AG(0),
597 MPC_RMU_REG_LIST_DCN3AG(1),
598 //MPC_RMU_REG_LIST_DCN3AG(2),
599 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
600 };
601
602 static const struct dcn30_mpc_shift mpc_shift = {
603 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
604 };
605
606 static const struct dcn30_mpc_mask mpc_mask = {
607 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
608 };
609
610 #define optc_regs(id)\
611 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
612
613 static const struct dcn_optc_registers optc_regs[] = {
614 optc_regs(0),
615 optc_regs(1),
616 optc_regs(2),
617 optc_regs(3)
618 };
619
620 static const struct dcn_optc_shift optc_shift = {
621 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
622 };
623
624 static const struct dcn_optc_mask optc_mask = {
625 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
626 };
627
628 #define hubp_regs(id)\
629 [id] = {\
630 HUBP_REG_LIST_DCN30(id)\
631 }
632
633 static const struct dcn_hubp2_registers hubp_regs[] = {
634 hubp_regs(0),
635 hubp_regs(1),
636 hubp_regs(2),
637 hubp_regs(3)
638 };
639
640
641 static const struct dcn_hubp2_shift hubp_shift = {
642 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
643 };
644
645 static const struct dcn_hubp2_mask hubp_mask = {
646 HUBP_MASK_SH_LIST_DCN31(_MASK)
647 };
648 static const struct dcn_hubbub_registers hubbub_reg = {
649 HUBBUB_REG_LIST_DCN31(0)
650 };
651
652 static const struct dcn_hubbub_shift hubbub_shift = {
653 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
654 };
655
656 static const struct dcn_hubbub_mask hubbub_mask = {
657 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
658 };
659
660 static const struct dccg_registers dccg_regs = {
661 DCCG_REG_LIST_DCN31()
662 };
663
664 static const struct dccg_shift dccg_shift = {
665 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
666 };
667
668 static const struct dccg_mask dccg_mask = {
669 DCCG_MASK_SH_LIST_DCN31(_MASK)
670 };
671
672
673 #define SRII2(reg_name_pre, reg_name_post, id)\
674 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
675 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
676 reg ## reg_name_pre ## id ## _ ## reg_name_post
677
678
679 #define HWSEQ_DCN31_REG_LIST()\
680 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
681 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
682 SR(DIO_MEM_PWR_CTRL), \
683 SR(ODM_MEM_PWR_CTRL3), \
684 SR(DMU_MEM_PWR_CNTL), \
685 SR(MMHUBBUB_MEM_PWR_CNTL), \
686 SR(DCCG_GATE_DISABLE_CNTL), \
687 SR(DCCG_GATE_DISABLE_CNTL2), \
688 SR(DCFCLK_CNTL),\
689 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
690 SRII(PIXEL_RATE_CNTL, OTG, 0), \
691 SRII(PIXEL_RATE_CNTL, OTG, 1),\
692 SRII(PIXEL_RATE_CNTL, OTG, 2),\
693 SRII(PIXEL_RATE_CNTL, OTG, 3),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
697 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
698 SR(MICROSECOND_TIME_BASE_DIV), \
699 SR(MILLISECOND_TIME_BASE_DIV), \
700 SR(DISPCLK_FREQ_CHANGE_CNTL), \
701 SR(RBBMIF_TIMEOUT_DIS), \
702 SR(RBBMIF_TIMEOUT_DIS_2), \
703 SR(DCHUBBUB_CRC_CTRL), \
704 SR(DPP_TOP0_DPP_CRC_CTRL), \
705 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
706 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
707 SR(MPC_CRC_CTRL), \
708 SR(MPC_CRC_RESULT_GB), \
709 SR(MPC_CRC_RESULT_C), \
710 SR(MPC_CRC_RESULT_AR), \
711 SR(DOMAIN0_PG_CONFIG), \
712 SR(DOMAIN1_PG_CONFIG), \
713 SR(DOMAIN2_PG_CONFIG), \
714 SR(DOMAIN3_PG_CONFIG), \
715 SR(DOMAIN16_PG_CONFIG), \
716 SR(DOMAIN17_PG_CONFIG), \
717 SR(DOMAIN18_PG_CONFIG), \
718 SR(DOMAIN0_PG_STATUS), \
719 SR(DOMAIN1_PG_STATUS), \
720 SR(DOMAIN2_PG_STATUS), \
721 SR(DOMAIN3_PG_STATUS), \
722 SR(DOMAIN16_PG_STATUS), \
723 SR(DOMAIN17_PG_STATUS), \
724 SR(DOMAIN18_PG_STATUS), \
725 SR(D1VGA_CONTROL), \
726 SR(D2VGA_CONTROL), \
727 SR(D3VGA_CONTROL), \
728 SR(D4VGA_CONTROL), \
729 SR(D5VGA_CONTROL), \
730 SR(D6VGA_CONTROL), \
731 SR(DC_IP_REQUEST_CNTL), \
732 SR(AZALIA_AUDIO_DTO), \
733 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
734 SR(HPO_TOP_HW_CONTROL)
735
736 static const struct dce_hwseq_registers hwseq_reg = {
737 HWSEQ_DCN31_REG_LIST()
738 };
739
740 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
741 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
742 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
743 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
744 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
746 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
747 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
748 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
749 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
750 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
757 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
758 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
759 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
760 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
761 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
762 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
763 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
764 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
765 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
766 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
767 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
768 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
769 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
770 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
771 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
772 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
773 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
774
775 static const struct dce_hwseq_shift hwseq_shift = {
776 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
777 };
778
779 static const struct dce_hwseq_mask hwseq_mask = {
780 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
781 };
782 #define vmid_regs(id)\
783 [id] = {\
784 DCN20_VMID_REG_LIST(id)\
785 }
786
787 static const struct dcn_vmid_registers vmid_regs[] = {
788 vmid_regs(0),
789 vmid_regs(1),
790 vmid_regs(2),
791 vmid_regs(3),
792 vmid_regs(4),
793 vmid_regs(5),
794 vmid_regs(6),
795 vmid_regs(7),
796 vmid_regs(8),
797 vmid_regs(9),
798 vmid_regs(10),
799 vmid_regs(11),
800 vmid_regs(12),
801 vmid_regs(13),
802 vmid_regs(14),
803 vmid_regs(15)
804 };
805
806 static const struct dcn20_vmid_shift vmid_shifts = {
807 DCN20_VMID_MASK_SH_LIST(__SHIFT)
808 };
809
810 static const struct dcn20_vmid_mask vmid_masks = {
811 DCN20_VMID_MASK_SH_LIST(_MASK)
812 };
813
814 static const struct dcn_dio_registers dio_regs = {
815 DIO_REG_LIST_DCN10()
816 };
817
818 #define DIO_MASK_SH_LIST(mask_sh)\
819 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
820
821 static const struct dcn_dio_shift dio_shift = {
822 DIO_MASK_SH_LIST(__SHIFT)
823 };
824
825 static const struct dcn_dio_mask dio_mask = {
826 DIO_MASK_SH_LIST(_MASK)
827 };
828
829 static const struct resource_caps res_cap_dcn31 = {
830 .num_timing_generator = 4,
831 .num_opp = 4,
832 .num_video_plane = 4,
833 .num_audio = 5,
834 .num_stream_encoder = 5,
835 .num_dig_link_enc = 5,
836 .num_hpo_dp_stream_encoder = 4,
837 .num_hpo_dp_link_encoder = 2,
838 .num_pll = 5,
839 .num_dwb = 1,
840 .num_ddc = 5,
841 .num_vmid = 16,
842 .num_mpc_3dlut = 2,
843 .num_dsc = 3,
844 };
845
846 static const struct dc_plane_cap plane_cap = {
847 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
848 .per_pixel_alpha = true,
849
850 .pixel_format_support = {
851 .argb8888 = true,
852 .nv12 = true,
853 .fp16 = true,
854 .p010 = true,
855 .ayuv = false,
856 },
857
858 .max_upscale_factor = {
859 .argb8888 = 16000,
860 .nv12 = 16000,
861 .fp16 = 16000
862 },
863
864 // 6:1 downscaling ratio: 1000/6 = 166.666
865 .max_downscale_factor = {
866 .argb8888 = 167,
867 .nv12 = 167,
868 .fp16 = 167
869 },
870 64,
871 64
872 };
873
874 static const struct dc_debug_options debug_defaults_drv = {
875 .disable_dmcu = true,
876 .force_abm_enable = false,
877 .clock_trace = true,
878 .disable_pplib_clock_request = false,
879 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
880 .force_single_disp_pipe_split = false,
881 .disable_dcc = DCC_ENABLE,
882 .vsr_support = true,
883 .performance_trace = false,
884 .max_downscale_src_width = 4096,/*upto true 4K*/
885 .disable_pplib_wm_range = false,
886 .scl_reset_length10 = true,
887 .sanity_checks = false,
888 .underflow_assert_delay_us = 0xFFFFFFFF,
889 .dwb_fi_phase = -1, // -1 = disable,
890 .dmub_command_table = true,
891 .pstate_enabled = true,
892 .use_max_lb = true,
893 .enable_mem_low_power = {
894 .bits = {
895 .vga = true,
896 .i2c = true,
897 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
898 .dscl = true,
899 .cm = true,
900 .mpc = true,
901 .optc = true,
902 .vpg = true,
903 .afmt = true,
904 }
905 },
906 .disable_z10 = true,
907 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
908 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
909 .using_dml2 = false,
910 };
911
912 static const struct dc_check_config config_defaults = {
913 .enable_legacy_fast_update = true,
914 };
915
916 static const struct dc_panel_config panel_config_defaults = {
917 .psr = {
918 .disable_psr = false,
919 .disallow_psrsu = false,
920 .disallow_replay = false,
921 },
922 .ilr = {
923 .optimize_edp_link_rate = true,
924 },
925 };
926
dcn31_dpp_destroy(struct dpp ** dpp)927 static void dcn31_dpp_destroy(struct dpp **dpp)
928 {
929 kfree(TO_DCN20_DPP(*dpp));
930 *dpp = NULL;
931 }
932
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)933 static struct dpp *dcn31_dpp_create(
934 struct dc_context *ctx,
935 uint32_t inst)
936 {
937 struct dcn3_dpp *dpp =
938 kzalloc_obj(struct dcn3_dpp);
939
940 if (!dpp)
941 return NULL;
942
943 if (dpp3_construct(dpp, ctx, inst,
944 &dpp_regs[inst], &tf_shift, &tf_mask))
945 return &dpp->base;
946
947 BREAK_TO_DEBUGGER();
948 kfree(dpp);
949 return NULL;
950 }
951
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)952 static struct output_pixel_processor *dcn31_opp_create(
953 struct dc_context *ctx, uint32_t inst)
954 {
955 struct dcn20_opp *opp =
956 kzalloc_obj(struct dcn20_opp);
957
958 if (!opp) {
959 BREAK_TO_DEBUGGER();
960 return NULL;
961 }
962
963 dcn20_opp_construct(opp, ctx, inst,
964 &opp_regs[inst], &opp_shift, &opp_mask);
965 return &opp->base;
966 }
967
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)968 static struct dce_aux *dcn31_aux_engine_create(
969 struct dc_context *ctx,
970 uint32_t inst)
971 {
972 struct aux_engine_dce110 *aux_engine =
973 kzalloc_obj(struct aux_engine_dce110);
974
975 if (!aux_engine)
976 return NULL;
977
978 dce110_aux_engine_construct(aux_engine, ctx, inst,
979 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
980 &aux_engine_regs[inst],
981 &aux_mask,
982 &aux_shift,
983 ctx->dc->caps.extended_aux_timeout_support);
984
985 return &aux_engine->base;
986 }
987 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
988
989 static const struct dce_i2c_registers i2c_hw_regs[] = {
990 i2c_inst_regs(1),
991 i2c_inst_regs(2),
992 i2c_inst_regs(3),
993 i2c_inst_regs(4),
994 i2c_inst_regs(5),
995 };
996
997 static const struct dce_i2c_shift i2c_shifts = {
998 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
999 };
1000
1001 static const struct dce_i2c_mask i2c_masks = {
1002 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1003 };
1004
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1005 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1006 struct dc_context *ctx,
1007 uint32_t inst)
1008 {
1009 struct dce_i2c_hw *dce_i2c_hw =
1010 kzalloc_obj(struct dce_i2c_hw);
1011
1012 if (!dce_i2c_hw)
1013 return NULL;
1014
1015 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1016 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1017
1018 return dce_i2c_hw;
1019 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1020 static struct mpc *dcn31_mpc_create(
1021 struct dc_context *ctx,
1022 int num_mpcc,
1023 int num_rmu)
1024 {
1025 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1026
1027 if (!mpc30)
1028 return NULL;
1029
1030 dcn30_mpc_construct(mpc30, ctx,
1031 &mpc_regs,
1032 &mpc_shift,
1033 &mpc_mask,
1034 num_mpcc,
1035 num_rmu);
1036
1037 return &mpc30->base;
1038 }
1039
dcn31_dio_create(struct dc_context * ctx)1040 static struct dio *dcn31_dio_create(struct dc_context *ctx)
1041 {
1042 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1043
1044 if (!dio10)
1045 return NULL;
1046
1047 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1048
1049 return &dio10->base;
1050 }
1051
dcn31_hubbub_create(struct dc_context * ctx)1052 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1053 {
1054 int i;
1055
1056 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1057
1058 if (!hubbub3)
1059 return NULL;
1060
1061 hubbub31_construct(hubbub3, ctx,
1062 &hubbub_reg,
1063 &hubbub_shift,
1064 &hubbub_mask,
1065 dcn3_1_ip.det_buffer_size_kbytes,
1066 dcn3_1_ip.pixel_chunk_size_kbytes,
1067 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1068
1069
1070 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1071 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1072
1073 vmid->ctx = ctx;
1074
1075 vmid->regs = &vmid_regs[i];
1076 vmid->shifts = &vmid_shifts;
1077 vmid->masks = &vmid_masks;
1078 }
1079
1080 return &hubbub3->base;
1081 }
1082
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1083 static struct timing_generator *dcn31_timing_generator_create(
1084 struct dc_context *ctx,
1085 uint32_t instance)
1086 {
1087 struct optc *tgn10 =
1088 kzalloc_obj(struct optc);
1089
1090 if (!tgn10)
1091 return NULL;
1092
1093 tgn10->base.inst = instance;
1094 tgn10->base.ctx = ctx;
1095
1096 tgn10->tg_regs = &optc_regs[instance];
1097 tgn10->tg_shift = &optc_shift;
1098 tgn10->tg_mask = &optc_mask;
1099
1100 dcn31_timing_generator_init(tgn10);
1101
1102 return &tgn10->base;
1103 }
1104
1105 static const struct encoder_feature_support link_enc_feature = {
1106 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1107 .max_hdmi_pixel_clock = 600000,
1108 .hdmi_ycbcr420_supported = true,
1109 .dp_ycbcr420_supported = true,
1110 .fec_supported = true,
1111 .flags.bits.IS_HBR2_CAPABLE = true,
1112 .flags.bits.IS_HBR3_CAPABLE = true,
1113 .flags.bits.IS_TPS3_CAPABLE = true,
1114 .flags.bits.IS_TPS4_CAPABLE = true
1115 };
1116
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1117 static struct link_encoder *dcn31_link_encoder_create(
1118 struct dc_context *ctx,
1119 const struct encoder_init_data *enc_init_data)
1120 {
1121 (void)ctx;
1122 struct dcn20_link_encoder *enc20 =
1123 kzalloc_obj(struct dcn20_link_encoder);
1124
1125 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1126 return NULL;
1127
1128 dcn31_link_encoder_construct(enc20,
1129 enc_init_data,
1130 &link_enc_feature,
1131 &link_enc_regs[enc_init_data->transmitter],
1132 &link_enc_aux_regs[enc_init_data->channel - 1],
1133 &link_enc_hpd_regs[enc_init_data->hpd_source],
1134 &le_shift,
1135 &le_mask);
1136
1137 return &enc20->enc10.base;
1138 }
1139
1140 /* Create a minimal link encoder object not associated with a particular
1141 * physical connector.
1142 * resource_funcs.link_enc_create_minimal
1143 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1144 static struct link_encoder *dcn31_link_enc_create_minimal(
1145 struct dc_context *ctx, enum engine_id eng_id)
1146 {
1147 struct dcn20_link_encoder *enc20;
1148
1149 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1150 return NULL;
1151
1152 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1153 if (!enc20)
1154 return NULL;
1155
1156 dcn31_link_encoder_construct_minimal(
1157 enc20,
1158 ctx,
1159 &link_enc_feature,
1160 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1161 eng_id);
1162
1163 return &enc20->enc10.base;
1164 }
1165
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1166 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1167 {
1168 struct dcn31_panel_cntl *panel_cntl =
1169 kzalloc_obj(struct dcn31_panel_cntl);
1170
1171 if (!panel_cntl)
1172 return NULL;
1173
1174 dcn31_panel_cntl_construct(panel_cntl, init_data);
1175
1176 return &panel_cntl->base;
1177 }
1178
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1179 static void read_dce_straps(
1180 struct dc_context *ctx,
1181 struct resource_straps *straps)
1182 {
1183 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1184 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1185
1186 }
1187
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1188 static struct audio *dcn31_create_audio(
1189 struct dc_context *ctx, unsigned int inst)
1190 {
1191 return dce_audio_create(ctx, inst,
1192 &audio_regs[inst], &audio_shift, &audio_mask);
1193 }
1194
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1195 static struct vpg *dcn31_vpg_create(
1196 struct dc_context *ctx,
1197 uint32_t inst)
1198 {
1199 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1200
1201 if (!vpg31)
1202 return NULL;
1203
1204 vpg31_construct(vpg31, ctx, inst,
1205 &vpg_regs[inst],
1206 &vpg_shift,
1207 &vpg_mask);
1208
1209 return &vpg31->base;
1210 }
1211
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1212 static struct afmt *dcn31_afmt_create(
1213 struct dc_context *ctx,
1214 uint32_t inst)
1215 {
1216 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1217
1218 if (!afmt31)
1219 return NULL;
1220
1221 afmt31_construct(afmt31, ctx, inst,
1222 &afmt_regs[inst],
1223 &afmt_shift,
1224 &afmt_mask);
1225
1226 // Light sleep by default, no need to power down here
1227
1228 return &afmt31->base;
1229 }
1230
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1231 static struct apg *dcn31_apg_create(
1232 struct dc_context *ctx,
1233 uint32_t inst)
1234 {
1235 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1236
1237 if (!apg31)
1238 return NULL;
1239
1240 apg31_construct(apg31, ctx, inst,
1241 &apg_regs[inst],
1242 &apg_shift,
1243 &apg_mask);
1244
1245 return &apg31->base;
1246 }
1247
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1248 static struct stream_encoder *dcn31_stream_encoder_create(
1249 enum engine_id eng_id,
1250 struct dc_context *ctx)
1251 {
1252 struct dcn10_stream_encoder *enc1;
1253 struct vpg *vpg;
1254 struct afmt *afmt;
1255 int vpg_inst;
1256 int afmt_inst;
1257
1258 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1259 if (eng_id <= ENGINE_ID_DIGF) {
1260 vpg_inst = eng_id;
1261 afmt_inst = eng_id;
1262 } else
1263 return NULL;
1264
1265 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1266 vpg = dcn31_vpg_create(ctx, vpg_inst);
1267 afmt = dcn31_afmt_create(ctx, afmt_inst);
1268
1269 if (!enc1 || !vpg || !afmt) {
1270 kfree(enc1);
1271 kfree(vpg);
1272 kfree(afmt);
1273 return NULL;
1274 }
1275
1276 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1277 eng_id, vpg, afmt,
1278 &stream_enc_regs[eng_id],
1279 &se_shift, &se_mask);
1280
1281 return &enc1->base;
1282 }
1283
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1284 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1285 enum engine_id eng_id,
1286 struct dc_context *ctx)
1287 {
1288 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1289 struct vpg *vpg;
1290 struct apg *apg;
1291 uint32_t hpo_dp_inst;
1292 uint32_t vpg_inst;
1293 uint32_t apg_inst;
1294
1295 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1296 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1297
1298 /* Mapping of VPG register blocks to HPO DP block instance:
1299 * VPG[6] -> HPO_DP[0]
1300 * VPG[7] -> HPO_DP[1]
1301 * VPG[8] -> HPO_DP[2]
1302 * VPG[9] -> HPO_DP[3]
1303 */
1304 vpg_inst = hpo_dp_inst + 6;
1305
1306 /* Mapping of APG register blocks to HPO DP block instance:
1307 * APG[0] -> HPO_DP[0]
1308 * APG[1] -> HPO_DP[1]
1309 * APG[2] -> HPO_DP[2]
1310 * APG[3] -> HPO_DP[3]
1311 */
1312 apg_inst = hpo_dp_inst;
1313
1314 /* allocate HPO stream encoder and create VPG sub-block */
1315 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1316 vpg = dcn31_vpg_create(ctx, vpg_inst);
1317 apg = dcn31_apg_create(ctx, apg_inst);
1318
1319 if (!hpo_dp_enc31 || !vpg || !apg) {
1320 kfree(hpo_dp_enc31);
1321 kfree(vpg);
1322 kfree(apg);
1323 return NULL;
1324 }
1325
1326 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1327 hpo_dp_inst, eng_id, vpg, apg,
1328 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1329 &hpo_dp_se_shift, &hpo_dp_se_mask);
1330
1331 return &hpo_dp_enc31->base;
1332 }
1333
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1334 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1335 uint8_t inst,
1336 struct dc_context *ctx)
1337 {
1338 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1339
1340 /* allocate HPO link encoder */
1341 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1342 if (!hpo_dp_enc31)
1343 return NULL; /* out of memory */
1344
1345 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1346 &hpo_dp_link_enc_regs[inst],
1347 &hpo_dp_le_shift, &hpo_dp_le_mask);
1348
1349 return &hpo_dp_enc31->base;
1350 }
1351
dcn31_hwseq_create(struct dc_context * ctx)1352 static struct dce_hwseq *dcn31_hwseq_create(
1353 struct dc_context *ctx)
1354 {
1355 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1356
1357 if (hws) {
1358 hws->ctx = ctx;
1359 hws->regs = &hwseq_reg;
1360 hws->shifts = &hwseq_shift;
1361 hws->masks = &hwseq_mask;
1362 }
1363 return hws;
1364 }
1365 static const struct resource_create_funcs res_create_funcs = {
1366 .read_dce_straps = read_dce_straps,
1367 .create_audio = dcn31_create_audio,
1368 .create_stream_encoder = dcn31_stream_encoder_create,
1369 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1370 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1371 .create_hwseq = dcn31_hwseq_create,
1372 };
1373
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1374 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1375 {
1376 unsigned int i;
1377
1378 for (i = 0; i < pool->base.stream_enc_count; i++) {
1379 if (pool->base.stream_enc[i] != NULL) {
1380 if (pool->base.stream_enc[i]->vpg != NULL) {
1381 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1382 pool->base.stream_enc[i]->vpg = NULL;
1383 }
1384 if (pool->base.stream_enc[i]->afmt != NULL) {
1385 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1386 pool->base.stream_enc[i]->afmt = NULL;
1387 }
1388 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1389 pool->base.stream_enc[i] = NULL;
1390 }
1391 }
1392
1393 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1394 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1395 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1396 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1397 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1398 }
1399 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1400 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1401 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1402 }
1403 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1404 pool->base.hpo_dp_stream_enc[i] = NULL;
1405 }
1406 }
1407
1408 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1409 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1410 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1411 pool->base.hpo_dp_link_enc[i] = NULL;
1412 }
1413 }
1414
1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1416 if (pool->base.dscs[i] != NULL)
1417 dcn20_dsc_destroy(&pool->base.dscs[i]);
1418 }
1419
1420 if (pool->base.mpc != NULL) {
1421 kfree(TO_DCN20_MPC(pool->base.mpc));
1422 pool->base.mpc = NULL;
1423 }
1424 if (pool->base.hubbub != NULL) {
1425 kfree(pool->base.hubbub);
1426 pool->base.hubbub = NULL;
1427 }
1428 if (pool->base.dio != NULL) {
1429 kfree(TO_DCN10_DIO(pool->base.dio));
1430 pool->base.dio = NULL;
1431 }
1432 for (i = 0; i < pool->base.pipe_count; i++) {
1433 if (pool->base.dpps[i] != NULL)
1434 dcn31_dpp_destroy(&pool->base.dpps[i]);
1435
1436 if (pool->base.ipps[i] != NULL)
1437 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1438
1439 if (pool->base.hubps[i] != NULL) {
1440 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1441 pool->base.hubps[i] = NULL;
1442 }
1443
1444 if (pool->base.irqs != NULL) {
1445 dal_irq_service_destroy(&pool->base.irqs);
1446 }
1447 }
1448
1449 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1450 if (pool->base.engines[i] != NULL)
1451 dce110_engine_destroy(&pool->base.engines[i]);
1452 if (pool->base.hw_i2cs[i] != NULL) {
1453 kfree(pool->base.hw_i2cs[i]);
1454 pool->base.hw_i2cs[i] = NULL;
1455 }
1456 if (pool->base.sw_i2cs[i] != NULL) {
1457 kfree(pool->base.sw_i2cs[i]);
1458 pool->base.sw_i2cs[i] = NULL;
1459 }
1460 }
1461
1462 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1463 if (pool->base.opps[i] != NULL)
1464 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1465 }
1466
1467 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1468 if (pool->base.timing_generators[i] != NULL) {
1469 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1470 pool->base.timing_generators[i] = NULL;
1471 }
1472 }
1473
1474 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1475 if (pool->base.dwbc[i] != NULL) {
1476 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1477 pool->base.dwbc[i] = NULL;
1478 }
1479 if (pool->base.mcif_wb[i] != NULL) {
1480 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1481 pool->base.mcif_wb[i] = NULL;
1482 }
1483 }
1484
1485 for (i = 0; i < pool->base.audio_count; i++) {
1486 if (pool->base.audios[i])
1487 dce_aud_destroy(&pool->base.audios[i]);
1488 }
1489
1490 for (i = 0; i < pool->base.clk_src_count; i++) {
1491 if (pool->base.clock_sources[i] != NULL) {
1492 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1493 pool->base.clock_sources[i] = NULL;
1494 }
1495 }
1496
1497 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1498 if (pool->base.mpc_lut[i] != NULL) {
1499 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1500 pool->base.mpc_lut[i] = NULL;
1501 }
1502 if (pool->base.mpc_shaper[i] != NULL) {
1503 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1504 pool->base.mpc_shaper[i] = NULL;
1505 }
1506 }
1507
1508 if (pool->base.dp_clock_source != NULL) {
1509 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1510 pool->base.dp_clock_source = NULL;
1511 }
1512
1513 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1514 if (pool->base.multiple_abms[i] != NULL)
1515 dce_abm_destroy(&pool->base.multiple_abms[i]);
1516 }
1517
1518 if (pool->base.psr != NULL)
1519 dmub_psr_destroy(&pool->base.psr);
1520
1521 if (pool->base.replay != NULL)
1522 dmub_replay_destroy(&pool->base.replay);
1523
1524 if (pool->base.dccg != NULL)
1525 dcn_dccg_destroy(&pool->base.dccg);
1526 }
1527
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1528 static struct hubp *dcn31_hubp_create(
1529 struct dc_context *ctx,
1530 uint32_t inst)
1531 {
1532 struct dcn20_hubp *hubp2 =
1533 kzalloc_obj(struct dcn20_hubp);
1534
1535 if (!hubp2)
1536 return NULL;
1537
1538 if (hubp31_construct(hubp2, ctx, inst,
1539 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1540 return &hubp2->base;
1541
1542 BREAK_TO_DEBUGGER();
1543 kfree(hubp2);
1544 return NULL;
1545 }
1546
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1547 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1548 {
1549 int i;
1550 uint32_t pipe_count = pool->res_cap->num_dwb;
1551
1552 for (i = 0; i < pipe_count; i++) {
1553 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1554
1555 if (!dwbc30) {
1556 dm_error("DC: failed to create dwbc30!\n");
1557 return false;
1558 }
1559
1560 dcn30_dwbc_construct(dwbc30, ctx,
1561 &dwbc30_regs[i],
1562 &dwbc30_shift,
1563 &dwbc30_mask,
1564 i);
1565
1566 pool->dwbc[i] = &dwbc30->base;
1567 }
1568 return true;
1569 }
1570
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1571 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1572 {
1573 int i;
1574 uint32_t pipe_count = pool->res_cap->num_dwb;
1575
1576 for (i = 0; i < pipe_count; i++) {
1577 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1578
1579 if (!mcif_wb30) {
1580 dm_error("DC: failed to create mcif_wb30!\n");
1581 return false;
1582 }
1583
1584 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1585 &mcif_wb30_regs[i],
1586 &mcif_wb30_shift,
1587 &mcif_wb30_mask,
1588 i);
1589
1590 pool->mcif_wb[i] = &mcif_wb30->base;
1591 }
1592 return true;
1593 }
1594
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1595 static struct display_stream_compressor *dcn31_dsc_create(
1596 struct dc_context *ctx, uint32_t inst)
1597 {
1598 struct dcn20_dsc *dsc =
1599 kzalloc_obj(struct dcn20_dsc);
1600
1601 if (!dsc) {
1602 BREAK_TO_DEBUGGER();
1603 return NULL;
1604 }
1605
1606 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1607 return &dsc->base;
1608 }
1609
dcn31_destroy_resource_pool(struct resource_pool ** pool)1610 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1611 {
1612 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1613
1614 dcn31_resource_destruct(dcn31_pool);
1615 kfree(dcn31_pool);
1616 *pool = NULL;
1617 }
1618
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1619 static struct clock_source *dcn31_clock_source_create(
1620 struct dc_context *ctx,
1621 struct dc_bios *bios,
1622 enum clock_source_id id,
1623 const struct dce110_clk_src_regs *regs,
1624 bool dp_clk_src)
1625 {
1626 struct dce110_clk_src *clk_src =
1627 kzalloc_obj(struct dce110_clk_src);
1628
1629 if (!clk_src)
1630 return NULL;
1631
1632 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1633 regs, &cs_shift, &cs_mask)) {
1634 clk_src->base.dp_clk_src = dp_clk_src;
1635 return &clk_src->base;
1636 }
1637
1638 kfree(clk_src);
1639 BREAK_TO_DEBUGGER();
1640 return NULL;
1641 }
1642
is_dual_plane(enum surface_pixel_format format)1643 static bool is_dual_plane(enum surface_pixel_format format)
1644 {
1645 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1646 }
1647
dcn31x_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1648 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1649 struct dc_state *context,
1650 display_e2e_pipe_params_st *pipes,
1651 enum dc_validate_mode validate_mode)
1652 {
1653 uint32_t pipe_cnt;
1654 int i;
1655
1656 dc_assert_fp_enabled();
1657
1658 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1659
1660 for (i = 0; i < pipe_cnt; i++) {
1661 pipes[i].pipe.src.gpuvm = 1;
1662 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1663 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1664 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1665 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1666 pipes[i].pipe.src.hostvm = false;
1667 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1668 pipes[i].pipe.src.hostvm = true;
1669 }
1670 return pipe_cnt;
1671 }
1672
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1673 int dcn31_populate_dml_pipes_from_context(
1674 struct dc *dc, struct dc_state *context,
1675 display_e2e_pipe_params_st *pipes,
1676 enum dc_validate_mode validate_mode)
1677 {
1678 int i, pipe_cnt;
1679 struct resource_context *res_ctx = &context->res_ctx;
1680 struct pipe_ctx *pipe = 0;
1681 bool upscaled = false;
1682
1683 DC_FP_START();
1684 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1685 DC_FP_END();
1686
1687 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1688 struct dc_crtc_timing *timing;
1689
1690 if (!res_ctx->pipe_ctx[i].stream)
1691 continue;
1692 pipe = &res_ctx->pipe_ctx[i];
1693 timing = &pipe->stream->timing;
1694 if (pipe->plane_state &&
1695 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1696 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1697 upscaled = true;
1698
1699 /*
1700 * Immediate flip can be set dynamically after enabling the plane.
1701 * We need to require support for immediate flip or underflow can be
1702 * intermittently experienced depending on peak b/w requirements.
1703 */
1704 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1705 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1706 pipes[pipe_cnt].pipe.src.gpuvm = true;
1707 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1708 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1709 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1710 DC_FP_START();
1711 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1712 DC_FP_END();
1713
1714
1715 if (pipes[pipe_cnt].dout.dsc_enable) {
1716 switch (timing->display_color_depth) {
1717 case COLOR_DEPTH_888:
1718 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1719 break;
1720 case COLOR_DEPTH_101010:
1721 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1722 break;
1723 case COLOR_DEPTH_121212:
1724 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1725 break;
1726 default:
1727 ASSERT(0);
1728 break;
1729 }
1730 }
1731
1732 pipe_cnt++;
1733 }
1734 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1735
1736 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1737 if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1738 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1739 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1740 pipes[0].pipe.src.unbounded_req_mode = true;
1741 }
1742 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1743 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1744 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1745 } else if (context->stream_count >= 3 && upscaled) {
1746 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1747 }
1748
1749 return pipe_cnt;
1750 }
1751
dcn31_get_det_buffer_size(const struct dc_state * context)1752 unsigned int dcn31_get_det_buffer_size(
1753 const struct dc_state *context)
1754 {
1755 return context->bw_ctx.dml.ip.det_buffer_size_kbytes;
1756 }
1757
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1758 void dcn31_calculate_wm_and_dlg(
1759 struct dc *dc, struct dc_state *context,
1760 display_e2e_pipe_params_st *pipes,
1761 int pipe_cnt,
1762 int vlevel)
1763 {
1764 DC_FP_START();
1765 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1766 DC_FP_END();
1767 }
1768
1769 void
dcn31_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1770 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1771 struct resource_context *res_ctx,
1772 display_e2e_pipe_params_st *pipes)
1773 {
1774 DC_FP_START();
1775 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1776 DC_FP_END();
1777 }
1778
1779 void
dcn31_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1780 dcn31_set_mcif_arb_params(struct dc *dc,
1781 struct dc_state *context,
1782 display_e2e_pipe_params_st *pipes,
1783 int pipe_cnt)
1784 {
1785 DC_FP_START();
1786 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1787 DC_FP_END();
1788 }
1789
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1790 enum dc_status dcn31_validate_bandwidth(struct dc *dc,
1791 struct dc_state *context,
1792 enum dc_validate_mode validate_mode)
1793 {
1794 bool out = false;
1795
1796 BW_VAL_TRACE_SETUP();
1797
1798 int vlevel = 0;
1799 int pipe_cnt = 0;
1800 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1801 dc->res_pool->pipe_count);
1802 DC_LOGGER_INIT(dc->ctx->logger);
1803
1804 BW_VAL_TRACE_COUNT();
1805
1806 if (!pipes)
1807 goto validate_fail;
1808
1809 DC_FP_START();
1810 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);
1811 DC_FP_END();
1812
1813 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1814 if (pipe_cnt == 0)
1815 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1816
1817 if (!out)
1818 goto validate_fail;
1819
1820 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1821
1822 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1823 BW_VAL_TRACE_SKIP(fast);
1824 goto validate_out;
1825 }
1826 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1827 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1828
1829 BW_VAL_TRACE_END_WATERMARKS();
1830
1831 goto validate_out;
1832
1833 validate_fail:
1834 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1835 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1836
1837 BW_VAL_TRACE_SKIP(fail);
1838 out = false;
1839
1840 validate_out:
1841 kfree(pipes);
1842
1843 BW_VAL_TRACE_FINISH();
1844
1845 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1846 }
1847
dcn31_get_panel_config_defaults(struct dc_panel_config * panel_config)1848 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1849 {
1850 *panel_config = panel_config_defaults;
1851 }
1852
1853 static struct dc_cap_funcs cap_funcs = {
1854 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1855 };
1856
dcn31_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1857 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1858 {
1859 DC_FP_START();
1860 dcn31_update_bw_bounding_box_fpu(dc, bw_params);
1861 DC_FP_END();
1862 }
1863
1864 static struct resource_funcs dcn31_res_pool_funcs = {
1865 .destroy = dcn31_destroy_resource_pool,
1866 .link_enc_create = dcn31_link_encoder_create,
1867 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1868 .link_encs_assign = link_enc_cfg_link_encs_assign,
1869 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1870 .panel_cntl_create = dcn31_panel_cntl_create,
1871 .validate_bandwidth = dcn31_validate_bandwidth,
1872 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1873 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1874 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1875 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1876 .release_pipe = dcn20_release_pipe,
1877 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1878 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1879 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1880 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1881 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1882 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1883 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1884 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1885 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1886 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1887 .get_panel_config_defaults = dcn31_get_panel_config_defaults,
1888 .get_det_buffer_size = dcn31_get_det_buffer_size,
1889 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1890 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1891 .get_default_tiling_info = dcn10_get_default_tiling_info,
1892 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
1893 };
1894
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1895 static struct clock_source *dcn30_clock_source_create(
1896 struct dc_context *ctx,
1897 struct dc_bios *bios,
1898 enum clock_source_id id,
1899 const struct dce110_clk_src_regs *regs,
1900 bool dp_clk_src)
1901 {
1902 struct dce110_clk_src *clk_src =
1903 kzalloc_obj(struct dce110_clk_src);
1904
1905 if (!clk_src)
1906 return NULL;
1907
1908 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1909 regs, &cs_shift, &cs_mask)) {
1910 clk_src->base.dp_clk_src = dp_clk_src;
1911 return &clk_src->base;
1912 }
1913
1914 kfree(clk_src);
1915 BREAK_TO_DEBUGGER();
1916 return NULL;
1917 }
1918
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)1919 static bool dcn31_resource_construct(
1920 uint8_t num_virtual_links,
1921 struct dc *dc,
1922 struct dcn31_resource_pool *pool)
1923 {
1924 int i;
1925 struct dc_context *ctx = dc->ctx;
1926 struct irq_service_init_data init_data;
1927
1928 ctx->dc_bios->regs = &bios_regs;
1929
1930 pool->base.res_cap = &res_cap_dcn31;
1931
1932 pool->base.funcs = &dcn31_res_pool_funcs;
1933
1934 /*************************************************
1935 * Resource + asic cap harcoding *
1936 *************************************************/
1937 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1938 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1939 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1940 dc->caps.max_downscale_ratio = 600;
1941 dc->caps.i2c_speed_in_khz = 100;
1942 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1943 dc->caps.max_cursor_size = 256;
1944 dc->caps.min_horizontal_blanking_period = 80;
1945 dc->caps.dmdata_alloc_size = 2048;
1946
1947 dc->caps.max_slave_planes = 2;
1948 dc->caps.max_slave_yuv_planes = 2;
1949 dc->caps.max_slave_rgb_planes = 2;
1950 dc->caps.post_blend_color_processing = true;
1951 dc->caps.force_dp_tps4_for_cp2520 = true;
1952 if (dc->config.forceHBR2CP2520)
1953 dc->caps.force_dp_tps4_for_cp2520 = false;
1954 dc->caps.dp_hpo = true;
1955 dc->caps.dp_hdmi21_pcon_support = true;
1956 dc->caps.edp_dsc_support = true;
1957 dc->caps.extended_aux_timeout_support = true;
1958 dc->caps.dmcub_support = true;
1959 dc->caps.is_apu = true;
1960 dc->caps.zstate_support = true;
1961
1962 /* Enable 4to1MPC by default */
1963 dc->config.allow_4to1MPC = true;
1964
1965 /* Color pipeline capabilities */
1966 dc->caps.color.dpp.dcn_arch = 1;
1967 dc->caps.color.dpp.input_lut_shared = 0;
1968 dc->caps.color.dpp.icsc = 1;
1969 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1970 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1971 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1972 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1973 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1974 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1975 dc->caps.color.dpp.post_csc = 1;
1976 dc->caps.color.dpp.gamma_corr = 1;
1977 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1978
1979 dc->caps.color.dpp.hw_3d_lut = 1;
1980 dc->caps.color.dpp.ogam_ram = 1;
1981 // no OGAM ROM on DCN301
1982 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1983 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1984 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1985 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1986 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1987 dc->caps.color.dpp.ocsc = 0;
1988
1989 dc->caps.color.mpc.gamut_remap = 1;
1990 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1991 dc->caps.color.mpc.ogam_ram = 1;
1992 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1993 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1994 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1995 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1996 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1997 dc->caps.color.mpc.ocsc = 1;
1998
1999 dc->caps.num_of_host_routers = 2;
2000 dc->caps.num_of_dpias_per_host_router = 2;
2001
2002 /* Use pipe context based otg sync logic */
2003 dc->config.use_pipe_ctx_sync_logic = true;
2004 dc->config.disable_hbr_audio_dp2 = true;
2005
2006 dc->config.no_native422_support = true;
2007
2008 /* read VBIOS LTTPR caps */
2009 {
2010 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2011 enum bp_result bp_query_result;
2012 uint8_t is_vbios_lttpr_enable = 0;
2013
2014 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2015 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2016 }
2017
2018 /* interop bit is implicit */
2019 {
2020 dc->caps.vbios_lttpr_aware = true;
2021 }
2022 }
2023 dc->check_config = config_defaults;
2024
2025 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2026 dc->debug = debug_defaults_drv;
2027
2028 // Init the vm_helper
2029 if (dc->vm_helper)
2030 vm_helper_init(dc->vm_helper, 16);
2031
2032 /*************************************************
2033 * Create resources *
2034 *************************************************/
2035
2036 /* Clock Sources for Pixel Clock*/
2037 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2038 dcn30_clock_source_create(ctx, ctx->dc_bios,
2039 CLOCK_SOURCE_COMBO_PHY_PLL0,
2040 &clk_src_regs[0], false);
2041 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2042 dcn30_clock_source_create(ctx, ctx->dc_bios,
2043 CLOCK_SOURCE_COMBO_PHY_PLL1,
2044 &clk_src_regs[1], false);
2045 /*move phypllx_pixclk_resync to dmub next*/
2046 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
2047 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2048 dcn30_clock_source_create(ctx, ctx->dc_bios,
2049 CLOCK_SOURCE_COMBO_PHY_PLL2,
2050 &clk_src_regs_b0[2], false);
2051 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2052 dcn30_clock_source_create(ctx, ctx->dc_bios,
2053 CLOCK_SOURCE_COMBO_PHY_PLL3,
2054 &clk_src_regs_b0[3], false);
2055 } else {
2056 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2057 dcn30_clock_source_create(ctx, ctx->dc_bios,
2058 CLOCK_SOURCE_COMBO_PHY_PLL2,
2059 &clk_src_regs[2], false);
2060 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2061 dcn30_clock_source_create(ctx, ctx->dc_bios,
2062 CLOCK_SOURCE_COMBO_PHY_PLL3,
2063 &clk_src_regs[3], false);
2064 }
2065
2066 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2067 dcn30_clock_source_create(ctx, ctx->dc_bios,
2068 CLOCK_SOURCE_COMBO_PHY_PLL4,
2069 &clk_src_regs[4], false);
2070
2071 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2072
2073 /* todo: not reuse phy_pll registers */
2074 pool->base.dp_clock_source =
2075 dcn31_clock_source_create(ctx, ctx->dc_bios,
2076 CLOCK_SOURCE_ID_DP_DTO,
2077 &clk_src_regs[0], true);
2078
2079 for (i = 0; i < pool->base.clk_src_count; i++) {
2080 if (pool->base.clock_sources[i] == NULL) {
2081 dm_error("DC: failed to create clock sources!\n");
2082 BREAK_TO_DEBUGGER();
2083 goto create_fail;
2084 }
2085 }
2086
2087 /* TODO: DCCG */
2088 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2089 if (pool->base.dccg == NULL) {
2090 dm_error("DC: failed to create dccg!\n");
2091 BREAK_TO_DEBUGGER();
2092 goto create_fail;
2093 }
2094
2095 /* TODO: IRQ */
2096 init_data.ctx = dc->ctx;
2097 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2098 if (!pool->base.irqs)
2099 goto create_fail;
2100
2101 /* HUBBUB */
2102 pool->base.hubbub = dcn31_hubbub_create(ctx);
2103 if (pool->base.hubbub == NULL) {
2104 BREAK_TO_DEBUGGER();
2105 dm_error("DC: failed to create hubbub!\n");
2106 goto create_fail;
2107 }
2108
2109 /* DIO */
2110 pool->base.dio = dcn31_dio_create(ctx);
2111 if (pool->base.dio == NULL) {
2112 BREAK_TO_DEBUGGER();
2113 dm_error("DC: failed to create dio!\n");
2114 goto create_fail;
2115 }
2116
2117 /* HUBPs, DPPs, OPPs and TGs */
2118 for (i = 0; i < pool->base.pipe_count; i++) {
2119 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2120 if (pool->base.hubps[i] == NULL) {
2121 BREAK_TO_DEBUGGER();
2122 dm_error(
2123 "DC: failed to create hubps!\n");
2124 goto create_fail;
2125 }
2126
2127 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2128 if (pool->base.dpps[i] == NULL) {
2129 BREAK_TO_DEBUGGER();
2130 dm_error(
2131 "DC: failed to create dpps!\n");
2132 goto create_fail;
2133 }
2134 }
2135
2136 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2137 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2138 if (pool->base.opps[i] == NULL) {
2139 BREAK_TO_DEBUGGER();
2140 dm_error(
2141 "DC: failed to create output pixel processor!\n");
2142 goto create_fail;
2143 }
2144 }
2145
2146 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2147 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2148 ctx, i);
2149 if (pool->base.timing_generators[i] == NULL) {
2150 BREAK_TO_DEBUGGER();
2151 dm_error("DC: failed to create tg!\n");
2152 goto create_fail;
2153 }
2154 }
2155 pool->base.timing_generator_count = i;
2156
2157 /* PSR */
2158 pool->base.psr = dmub_psr_create(ctx);
2159 if (pool->base.psr == NULL) {
2160 dm_error("DC: failed to create psr obj!\n");
2161 BREAK_TO_DEBUGGER();
2162 goto create_fail;
2163 }
2164
2165 /* Replay */
2166 pool->base.replay = dmub_replay_create(ctx);
2167 if (pool->base.replay == NULL) {
2168 dm_error("DC: failed to create replay obj!\n");
2169 BREAK_TO_DEBUGGER();
2170 goto create_fail;
2171 }
2172
2173 /* ABM */
2174 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2175 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2176 &abm_regs[i],
2177 &abm_shift,
2178 &abm_mask);
2179 if (pool->base.multiple_abms[i] == NULL) {
2180 dm_error("DC: failed to create abm for pipe %d!\n", i);
2181 BREAK_TO_DEBUGGER();
2182 goto create_fail;
2183 }
2184 }
2185
2186 /* MPC and DSC */
2187 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2188 if (pool->base.mpc == NULL) {
2189 BREAK_TO_DEBUGGER();
2190 dm_error("DC: failed to create mpc!\n");
2191 goto create_fail;
2192 }
2193
2194 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2195 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2196 if (pool->base.dscs[i] == NULL) {
2197 BREAK_TO_DEBUGGER();
2198 dm_error("DC: failed to create display stream compressor %d!\n", i);
2199 goto create_fail;
2200 }
2201 }
2202
2203 /* DWB and MMHUBBUB */
2204 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2205 BREAK_TO_DEBUGGER();
2206 dm_error("DC: failed to create dwbc!\n");
2207 goto create_fail;
2208 }
2209
2210 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2211 BREAK_TO_DEBUGGER();
2212 dm_error("DC: failed to create mcif_wb!\n");
2213 goto create_fail;
2214 }
2215
2216 /* AUX and I2C */
2217 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2218 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2219 if (pool->base.engines[i] == NULL) {
2220 BREAK_TO_DEBUGGER();
2221 dm_error(
2222 "DC:failed to create aux engine!!\n");
2223 goto create_fail;
2224 }
2225 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2226 if (pool->base.hw_i2cs[i] == NULL) {
2227 BREAK_TO_DEBUGGER();
2228 dm_error(
2229 "DC:failed to create hw i2c!!\n");
2230 goto create_fail;
2231 }
2232 pool->base.sw_i2cs[i] = NULL;
2233 }
2234
2235 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2236 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2237 !dc->debug.dpia_debug.bits.disable_dpia) {
2238 /* YELLOW CARP B0 has 4 DPIA's */
2239 pool->base.usb4_dpia_count = 4;
2240 }
2241
2242 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2243 pool->base.usb4_dpia_count = 4;
2244
2245 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2246 if (!resource_construct(num_virtual_links, dc, &pool->base,
2247 &res_create_funcs))
2248 goto create_fail;
2249
2250 /* HW Sequencer and Plane caps */
2251 dcn31_hw_sequencer_construct(dc);
2252
2253 dc->caps.max_planes = pool->base.pipe_count;
2254
2255 for (i = 0; i < dc->caps.max_planes; ++i)
2256 dc->caps.planes[i] = plane_cap;
2257
2258 dc->caps.max_odm_combine_factor = 4;
2259
2260 dc->cap_funcs = cap_funcs;
2261
2262 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2263
2264 return true;
2265
2266 create_fail:
2267 dcn31_resource_destruct(pool);
2268
2269 return false;
2270 }
2271
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2272 struct resource_pool *dcn31_create_resource_pool(
2273 const struct dc_init_data *init_data,
2274 struct dc *dc)
2275 {
2276 struct dcn31_resource_pool *pool =
2277 kzalloc_obj(struct dcn31_resource_pool);
2278
2279 if (!pool)
2280 return NULL;
2281
2282 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2283 return &pool->base;
2284
2285 BREAK_TO_DEBUGGER();
2286 kfree(pool);
2287 return NULL;
2288 }
2289
dcn31_update_dc_state_for_encoder_switch(struct dc_link * link,struct dc_link_settings * link_setting,uint8_t pipe_count,struct pipe_ctx * pipes,struct audio_output * audio_output)2290 enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,
2291 struct dc_link_settings *link_setting,
2292 uint8_t pipe_count,
2293 struct pipe_ctx *pipes,
2294 struct audio_output *audio_output)
2295 {
2296 (void)link_setting;
2297 struct dc_state *state = link->dc->current_state;
2298 int i;
2299
2300 #if defined(CONFIG_DRM_AMD_DC_FP)
2301 if (link->dc->hwss.calculate_pix_rate_divider) {
2302 for (i = 0; i < state->stream_count; i++)
2303 if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
2304 link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
2305 }
2306
2307 for (i = 0; i < pipe_count; i++) {
2308 if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)
2309 link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
2310
2311 // Setup audio
2312 if (pipes[i].stream_res.audio != NULL)
2313 build_audio_output(state, &pipes[i], &audio_output[i]);
2314 }
2315 #else
2316 /* This DCN requires rate divider updates and audio reprogramming to allow DP1<-->DP2 link rate switching,
2317 * but the above will not compile on architectures without an FPU.
2318 */
2319 DC_LOG_WARNING("%s: DP1<-->DP2 link retraining will not work on this DCN on non-FPU platforms", __func__);
2320 ASSERT(0);
2321 #endif
2322
2323 return DC_OK;
2324 }
2325