1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "basics/conversion.h"
35 #include "dcn315_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39 #include "dcn31/dcn31_resource.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn315/irq_service_dcn315.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
58 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
59 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
60 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
61 #include "dcn31/dcn31_apg.h"
62 #include "dcn31/dcn31_dio_link_encoder.h"
63 #include "dcn31/dcn31_vpg.h"
64 #include "dcn31/dcn31_afmt.h"
65 #include "dce/dce_clock_source.h"
66 #include "dce/dce_audio.h"
67 #include "dce/dce_hwseq.h"
68 #include "clk_mgr.h"
69 #include "dio/dcn10/dcn10_dio.h"
70 #include "dio/virtual/virtual_stream_encoder.h"
71 #include "dce110/dce110_resource.h"
72 #include "dml/display_mode_vba.h"
73 #include "dml/dcn31/dcn31_fpu.h"
74 #include "dcn31/dcn31_dccg.h"
75 #include "dcn10/dcn10_resource.h"
76 #include "dcn31/dcn31_panel_cntl.h"
77
78 #include "dcn30/dcn30_dwb.h"
79 #include "dcn30/dcn30_mmhubbub.h"
80
81 #include "dcn/dcn_3_1_5_offset.h"
82 #include "dcn/dcn_3_1_5_sh_mask.h"
83 #include "dpcs/dpcs_4_2_2_offset.h"
84 #include "dpcs/dpcs_4_2_2_sh_mask.h"
85
86 #define NBIO_BASE__INST0_SEG0 0x00000000
87 #define NBIO_BASE__INST0_SEG1 0x00000014
88 #define NBIO_BASE__INST0_SEG2 0x00000D20
89 #define NBIO_BASE__INST0_SEG3 0x00010400
90 #define NBIO_BASE__INST0_SEG4 0x0241B000
91 #define NBIO_BASE__INST0_SEG5 0x04040000
92
93 #define DPCS_BASE__INST0_SEG0 0x00000012
94 #define DPCS_BASE__INST0_SEG1 0x000000C0
95 #define DPCS_BASE__INST0_SEG2 0x000034C0
96 #define DPCS_BASE__INST0_SEG3 0x00009000
97 #define DPCS_BASE__INST0_SEG4 0x02403C00
98 #define DPCS_BASE__INST0_SEG5 0
99
100 #define DCN_BASE__INST0_SEG0 0x00000012
101 #define DCN_BASE__INST0_SEG1 0x000000C0
102 #define DCN_BASE__INST0_SEG2 0x000034C0
103 #define DCN_BASE__INST0_SEG3 0x00009000
104 #define DCN_BASE__INST0_SEG4 0x02403C00
105 #define DCN_BASE__INST0_SEG5 0
106
107 #define regBIF_BX_PF2_RSMU_INDEX 0x0000
108 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1
109 #define regBIF_BX_PF2_RSMU_DATA 0x0001
110 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1
111 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
112 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
113 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
114 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
115 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
116 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
117 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
118 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
119 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
120 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
121 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
122 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
123
124 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
125 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
126 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
127 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
128
129 #include "reg_helper.h"
130 #include "dce/dmub_abm.h"
131 #include "dce/dmub_psr.h"
132 #include "dce/dmub_replay.h"
133 #include "dce/dce_aux.h"
134 #include "dce/dce_i2c.h"
135
136 #include "dml/dcn30/display_mode_vba_30.h"
137 #include "vm_helper.h"
138 #include "dcn20/dcn20_vmid.h"
139
140 #include "link_enc_cfg.h"
141
142 #define DCN3_15_MAX_DET_SIZE 384
143 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64
144 #define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB)
145 /* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */
146 #define MIN_RESERVED_DET_SEGS 3
147
148 enum dcn31_clk_src_array_id {
149 DCN31_CLK_SRC_PLL0,
150 DCN31_CLK_SRC_PLL1,
151 DCN31_CLK_SRC_PLL2,
152 DCN31_CLK_SRC_PLL3,
153 DCN31_CLK_SRC_PLL4,
154 DCN30_CLK_SRC_TOTAL
155 };
156
157 /* begin *********************
158 * macros to expend register list macro defined in HW object header file
159 */
160
161 /* DCN */
162 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
163
164 #define BASE(seg) BASE_INNER(seg)
165
166 #define SR(reg_name)\
167 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
168 reg ## reg_name
169
170 #define SRI(reg_name, block, id)\
171 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
172 reg ## block ## id ## _ ## reg_name
173
174 #define SRI2(reg_name, block, id)\
175 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
176 reg ## reg_name
177
178 #define SRIR(var_name, reg_name, block, id)\
179 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 reg ## block ## id ## _ ## reg_name
181
182 #define SRII(reg_name, block, id)\
183 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
184 reg ## block ## id ## _ ## reg_name
185
186 #define SRII_MPC_RMU(reg_name, block, id)\
187 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
188 reg ## block ## id ## _ ## reg_name
189
190 #define SRII_DWB(reg_name, temp_name, block, id)\
191 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
192 reg ## block ## id ## _ ## temp_name
193
194 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
195 .field_name = reg_name ## __ ## field_name ## post_fix
196
197 #define DCCG_SRII(reg_name, block, id)\
198 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
199 reg ## block ## id ## _ ## reg_name
200
201 #define VUPDATE_SRII(reg_name, block, id)\
202 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
203 reg ## reg_name ## _ ## block ## id
204
205 /* NBIO */
206 #define NBIO_BASE_INNER(seg) \
207 NBIO_BASE__INST0_SEG ## seg
208
209 #define NBIO_BASE(seg) \
210 NBIO_BASE_INNER(seg)
211
212 #define NBIO_SR(reg_name)\
213 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
214 regBIF_BX2_ ## reg_name
215
216 static const struct bios_registers bios_regs = {
217 NBIO_SR(BIOS_SCRATCH_3),
218 NBIO_SR(BIOS_SCRATCH_6)
219 };
220
221 #define clk_src_regs(index, pllid)\
222 [index] = {\
223 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
224 }
225
226 static const struct dce110_clk_src_regs clk_src_regs[] = {
227 clk_src_regs(0, A),
228 clk_src_regs(1, B),
229 clk_src_regs(2, C),
230 clk_src_regs(3, D),
231 clk_src_regs(4, E)
232 };
233
234 static const struct dce110_clk_src_shift cs_shift = {
235 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
236 };
237
238 static const struct dce110_clk_src_mask cs_mask = {
239 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
240 };
241
242 #define abm_regs(id)\
243 [id] = {\
244 ABM_DCN302_REG_LIST(id)\
245 }
246
247 static const struct dce_abm_registers abm_regs[] = {
248 abm_regs(0),
249 abm_regs(1),
250 abm_regs(2),
251 abm_regs(3),
252 };
253
254 static const struct dce_abm_shift abm_shift = {
255 ABM_MASK_SH_LIST_DCN30(__SHIFT)
256 };
257
258 static const struct dce_abm_mask abm_mask = {
259 ABM_MASK_SH_LIST_DCN30(_MASK)
260 };
261
262 #define audio_regs(id)\
263 [id] = {\
264 AUD_COMMON_REG_LIST(id)\
265 }
266
267 static const struct dce_audio_registers audio_regs[] = {
268 audio_regs(0),
269 audio_regs(1),
270 audio_regs(2),
271 audio_regs(3),
272 audio_regs(4),
273 audio_regs(5),
274 audio_regs(6)
275 };
276
277 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
278 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
279 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
280 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
281
282 static const struct dce_audio_shift audio_shift = {
283 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
284 };
285
286 static const struct dce_audio_mask audio_mask = {
287 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
288 };
289
290 #define vpg_regs(id)\
291 [id] = {\
292 VPG_DCN31_REG_LIST(id)\
293 }
294
295 static const struct dcn31_vpg_registers vpg_regs[] = {
296 vpg_regs(0),
297 vpg_regs(1),
298 vpg_regs(2),
299 vpg_regs(3),
300 vpg_regs(4),
301 vpg_regs(5),
302 vpg_regs(6),
303 vpg_regs(7),
304 vpg_regs(8),
305 vpg_regs(9),
306 };
307
308 static const struct dcn31_vpg_shift vpg_shift = {
309 DCN31_VPG_MASK_SH_LIST(__SHIFT)
310 };
311
312 static const struct dcn31_vpg_mask vpg_mask = {
313 DCN31_VPG_MASK_SH_LIST(_MASK)
314 };
315
316 #define afmt_regs(id)\
317 [id] = {\
318 AFMT_DCN31_REG_LIST(id)\
319 }
320
321 static const struct dcn31_afmt_registers afmt_regs[] = {
322 afmt_regs(0),
323 afmt_regs(1),
324 afmt_regs(2),
325 afmt_regs(3),
326 afmt_regs(4),
327 afmt_regs(5)
328 };
329
330 static const struct dcn31_afmt_shift afmt_shift = {
331 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
332 };
333
334 static const struct dcn31_afmt_mask afmt_mask = {
335 DCN31_AFMT_MASK_SH_LIST(_MASK)
336 };
337
338 #define apg_regs(id)\
339 [id] = {\
340 APG_DCN31_REG_LIST(id)\
341 }
342
343 static const struct dcn31_apg_registers apg_regs[] = {
344 apg_regs(0),
345 apg_regs(1),
346 apg_regs(2),
347 apg_regs(3)
348 };
349
350 static const struct dcn31_apg_shift apg_shift = {
351 DCN31_APG_MASK_SH_LIST(__SHIFT)
352 };
353
354 static const struct dcn31_apg_mask apg_mask = {
355 DCN31_APG_MASK_SH_LIST(_MASK)
356 };
357
358 #define stream_enc_regs(id)\
359 [id] = {\
360 SE_DCN3_REG_LIST(id)\
361 }
362
363 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
364 stream_enc_regs(0),
365 stream_enc_regs(1),
366 stream_enc_regs(2),
367 stream_enc_regs(3),
368 stream_enc_regs(4)
369 };
370
371 static const struct dcn10_stream_encoder_shift se_shift = {
372 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
373 };
374
375 static const struct dcn10_stream_encoder_mask se_mask = {
376 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
377 };
378
379
380 #define aux_regs(id)\
381 [id] = {\
382 DCN2_AUX_REG_LIST(id)\
383 }
384
385 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
386 aux_regs(0),
387 aux_regs(1),
388 aux_regs(2),
389 aux_regs(3),
390 aux_regs(4)
391 };
392
393 #define hpd_regs(id)\
394 [id] = {\
395 HPD_REG_LIST(id)\
396 }
397
398 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
399 hpd_regs(0),
400 hpd_regs(1),
401 hpd_regs(2),
402 hpd_regs(3),
403 hpd_regs(4)
404 };
405
406 #define link_regs(id, phyid)\
407 [id] = {\
408 LE_DCN31_REG_LIST(id), \
409 UNIPHY_DCN2_REG_LIST(phyid), \
410 DPCS_DCN31_REG_LIST(id), \
411 }
412
413 static const struct dce110_aux_registers_shift aux_shift = {
414 DCN_AUX_MASK_SH_LIST(__SHIFT)
415 };
416
417 static const struct dce110_aux_registers_mask aux_mask = {
418 DCN_AUX_MASK_SH_LIST(_MASK)
419 };
420
421 static const struct dcn10_link_enc_registers link_enc_regs[] = {
422 link_regs(0, A),
423 link_regs(1, B),
424 link_regs(2, C),
425 link_regs(3, D),
426 link_regs(4, E)
427 };
428
429 static const struct dcn10_link_enc_shift le_shift = {
430 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
431 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
432 };
433
434 static const struct dcn10_link_enc_mask le_mask = {
435 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
436 DPCS_DCN31_MASK_SH_LIST(_MASK)
437 };
438
439 #define hpo_frl_stream_encoder_reg_list(id)\
440 [id] = {\
441 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id)\
442 }
443
444 #define hpo_frl_stream_encoder_dme_reg_list(id)\
445 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 6)
446
447
448 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
449 hpo_frl_stream_encoder_reg_list(0),
450 hpo_frl_stream_encoder_dme_reg_list(6),
451 };
452
453 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
454 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
455 };
456
457 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
458 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
459 };
460
461 #define hpo_frl_link_encoder_reg_list(id)\
462 [id] = {\
463 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id)\
464 }
465
466 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
467 hpo_frl_link_encoder_reg_list(0),
468 };
469
470 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
471 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
472 };
473
474 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
475 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
476 };
477
478 #define hpo_dp_stream_encoder_reg_list(id)\
479 [id] = {\
480 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
481 }
482
483 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
484 hpo_dp_stream_encoder_reg_list(0),
485 hpo_dp_stream_encoder_reg_list(1),
486 hpo_dp_stream_encoder_reg_list(2),
487 hpo_dp_stream_encoder_reg_list(3),
488 };
489
490 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
491 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
492 };
493
494 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
495 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
496 };
497
498
499 #define hpo_dp_link_encoder_reg_list(id)\
500 [id] = {\
501 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
502 DCN3_1_RDPCSTX_REG_LIST(0),\
503 DCN3_1_RDPCSTX_REG_LIST(1),\
504 DCN3_1_RDPCSTX_REG_LIST(2),\
505 DCN3_1_RDPCSTX_REG_LIST(3),\
506 DCN3_1_RDPCSTX_REG_LIST(4)\
507 }
508
509 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
510 hpo_dp_link_encoder_reg_list(0),
511 hpo_dp_link_encoder_reg_list(1),
512 };
513
514 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
515 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
516 };
517
518 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
519 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
520 };
521
522 #define dpp_regs(id)\
523 [id] = {\
524 DPP_REG_LIST_DCN30(id),\
525 }
526
527 static const struct dcn3_dpp_registers dpp_regs[] = {
528 dpp_regs(0),
529 dpp_regs(1),
530 dpp_regs(2),
531 dpp_regs(3)
532 };
533
534 static const struct dcn3_dpp_shift tf_shift = {
535 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
536 };
537
538 static const struct dcn3_dpp_mask tf_mask = {
539 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
540 };
541
542 #define opp_regs(id)\
543 [id] = {\
544 OPP_REG_LIST_DCN30(id),\
545 }
546
547 static const struct dcn20_opp_registers opp_regs[] = {
548 opp_regs(0),
549 opp_regs(1),
550 opp_regs(2),
551 opp_regs(3)
552 };
553
554 static const struct dcn20_opp_shift opp_shift = {
555 OPP_MASK_SH_LIST_DCN20(__SHIFT)
556 };
557
558 static const struct dcn20_opp_mask opp_mask = {
559 OPP_MASK_SH_LIST_DCN20(_MASK)
560 };
561
562 #define aux_engine_regs(id)\
563 [id] = {\
564 AUX_COMMON_REG_LIST0(id), \
565 .AUXN_IMPCAL = 0, \
566 .AUXP_IMPCAL = 0, \
567 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
568 }
569
570 static const struct dce110_aux_registers aux_engine_regs[] = {
571 aux_engine_regs(0),
572 aux_engine_regs(1),
573 aux_engine_regs(2),
574 aux_engine_regs(3),
575 aux_engine_regs(4)
576 };
577
578 #define dwbc_regs_dcn3(id)\
579 [id] = {\
580 DWBC_COMMON_REG_LIST_DCN30(id),\
581 }
582
583 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
584 dwbc_regs_dcn3(0),
585 };
586
587 static const struct dcn30_dwbc_shift dwbc30_shift = {
588 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
589 };
590
591 static const struct dcn30_dwbc_mask dwbc30_mask = {
592 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
593 };
594
595 #define mcif_wb_regs_dcn3(id)\
596 [id] = {\
597 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
598 }
599
600 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
601 mcif_wb_regs_dcn3(0)
602 };
603
604 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
605 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
606 };
607
608 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
609 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
610 };
611
612 #define dsc_regsDCN20(id)\
613 [id] = {\
614 DSC_REG_LIST_DCN20(id)\
615 }
616
617 static const struct dcn20_dsc_registers dsc_regs[] = {
618 dsc_regsDCN20(0),
619 dsc_regsDCN20(1),
620 dsc_regsDCN20(2)
621 };
622
623 static const struct dcn20_dsc_shift dsc_shift = {
624 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
625 };
626
627 static const struct dcn20_dsc_mask dsc_mask = {
628 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
629 };
630
631 static const struct dcn30_mpc_registers mpc_regs = {
632 MPC_REG_LIST_DCN3_0(0),
633 MPC_REG_LIST_DCN3_0(1),
634 MPC_REG_LIST_DCN3_0(2),
635 MPC_REG_LIST_DCN3_0(3),
636 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
637 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
638 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
639 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
640 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
641 };
642
643 static const struct dcn30_mpc_shift mpc_shift = {
644 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
645 };
646
647 static const struct dcn30_mpc_mask mpc_mask = {
648 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
649 };
650
651 #define optc_regs(id)\
652 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
653
654 static const struct dcn_optc_registers optc_regs[] = {
655 optc_regs(0),
656 optc_regs(1),
657 optc_regs(2),
658 optc_regs(3)
659 };
660
661 static const struct dcn_optc_shift optc_shift = {
662 OPTC_COMMON_MASK_SH_LIST_DCN31X(__SHIFT)
663 };
664
665 static const struct dcn_optc_mask optc_mask = {
666 OPTC_COMMON_MASK_SH_LIST_DCN31X(_MASK)
667 };
668
669 #define hubp_regs(id)\
670 [id] = {\
671 HUBP_REG_LIST_DCN30(id)\
672 }
673
674 static const struct dcn_hubp2_registers hubp_regs[] = {
675 hubp_regs(0),
676 hubp_regs(1),
677 hubp_regs(2),
678 hubp_regs(3)
679 };
680
681
682 static const struct dcn_hubp2_shift hubp_shift = {
683 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
684 };
685
686 static const struct dcn_hubp2_mask hubp_mask = {
687 HUBP_MASK_SH_LIST_DCN31(_MASK)
688 };
689 static const struct dcn_hubbub_registers hubbub_reg = {
690 HUBBUB_REG_LIST_DCN31(0)
691 };
692
693 static const struct dcn_hubbub_shift hubbub_shift = {
694 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
695 };
696
697 static const struct dcn_hubbub_mask hubbub_mask = {
698 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
699 };
700
701 static const struct dccg_registers dccg_regs = {
702 DCCG_REG_LIST_DCN31()
703 };
704
705 static const struct dccg_shift dccg_shift = {
706 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
707 };
708
709 static const struct dccg_mask dccg_mask = {
710 DCCG_MASK_SH_LIST_DCN31(_MASK)
711 };
712
713
714 #define SRII2(reg_name_pre, reg_name_post, id)\
715 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
716 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
717 reg ## reg_name_pre ## id ## _ ## reg_name_post
718
719
720 #define HWSEQ_DCN31_REG_LIST()\
721 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
722 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
723 SR(DIO_MEM_PWR_CTRL), \
724 SR(ODM_MEM_PWR_CTRL3), \
725 SR(DMU_MEM_PWR_CNTL), \
726 SR(MMHUBBUB_MEM_PWR_CNTL), \
727 SR(DCCG_GATE_DISABLE_CNTL), \
728 SR(DCCG_GATE_DISABLE_CNTL2), \
729 SR(DCFCLK_CNTL),\
730 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
731 SRII(PIXEL_RATE_CNTL, OTG, 0), \
732 SRII(PIXEL_RATE_CNTL, OTG, 1),\
733 SRII(PIXEL_RATE_CNTL, OTG, 2),\
734 SRII(PIXEL_RATE_CNTL, OTG, 3),\
735 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
736 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
737 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
738 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
739 SR(MICROSECOND_TIME_BASE_DIV), \
740 SR(MILLISECOND_TIME_BASE_DIV), \
741 SR(DISPCLK_FREQ_CHANGE_CNTL), \
742 SR(RBBMIF_TIMEOUT_DIS), \
743 SR(RBBMIF_TIMEOUT_DIS_2), \
744 SR(DCHUBBUB_CRC_CTRL), \
745 SR(DPP_TOP0_DPP_CRC_CTRL), \
746 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
747 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
748 SR(MPC_CRC_CTRL), \
749 SR(MPC_CRC_RESULT_GB), \
750 SR(MPC_CRC_RESULT_C), \
751 SR(MPC_CRC_RESULT_AR), \
752 SR(DOMAIN0_PG_CONFIG), \
753 SR(DOMAIN1_PG_CONFIG), \
754 SR(DOMAIN2_PG_CONFIG), \
755 SR(DOMAIN3_PG_CONFIG), \
756 SR(DOMAIN16_PG_CONFIG), \
757 SR(DOMAIN17_PG_CONFIG), \
758 SR(DOMAIN18_PG_CONFIG), \
759 SR(DOMAIN0_PG_STATUS), \
760 SR(DOMAIN1_PG_STATUS), \
761 SR(DOMAIN2_PG_STATUS), \
762 SR(DOMAIN3_PG_STATUS), \
763 SR(DOMAIN16_PG_STATUS), \
764 SR(DOMAIN17_PG_STATUS), \
765 SR(DOMAIN18_PG_STATUS), \
766 SR(D1VGA_CONTROL), \
767 SR(D2VGA_CONTROL), \
768 SR(D3VGA_CONTROL), \
769 SR(D4VGA_CONTROL), \
770 SR(D5VGA_CONTROL), \
771 SR(D6VGA_CONTROL), \
772 SR(DC_IP_REQUEST_CNTL), \
773 SR(AZALIA_AUDIO_DTO), \
774 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
775 SR(HPO_TOP_HW_CONTROL)
776
777 static const struct dce_hwseq_registers hwseq_reg = {
778 HWSEQ_DCN31_REG_LIST()
779 };
780
781 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
782 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
783 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
784 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
785 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
786 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
787 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
788 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
789 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
790 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
791 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
792 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
793 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
794 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
795 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
796 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
797 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
798 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
799 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
800 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
801 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
802 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
803 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
804 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
805 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
806 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
807 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
808 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
809 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
810 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
811 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
812 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
813 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
814 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
815
816 static const struct dce_hwseq_shift hwseq_shift = {
817 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
818 };
819
820 static const struct dce_hwseq_mask hwseq_mask = {
821 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
822 };
823 #define vmid_regs(id)\
824 [id] = {\
825 DCN20_VMID_REG_LIST(id)\
826 }
827
828 static const struct dcn_vmid_registers vmid_regs[] = {
829 vmid_regs(0),
830 vmid_regs(1),
831 vmid_regs(2),
832 vmid_regs(3),
833 vmid_regs(4),
834 vmid_regs(5),
835 vmid_regs(6),
836 vmid_regs(7),
837 vmid_regs(8),
838 vmid_regs(9),
839 vmid_regs(10),
840 vmid_regs(11),
841 vmid_regs(12),
842 vmid_regs(13),
843 vmid_regs(14),
844 vmid_regs(15)
845 };
846
847 static const struct dcn20_vmid_shift vmid_shifts = {
848 DCN20_VMID_MASK_SH_LIST(__SHIFT)
849 };
850
851 static const struct dcn20_vmid_mask vmid_masks = {
852 DCN20_VMID_MASK_SH_LIST(_MASK)
853 };
854
855 static const struct dcn_dio_registers dio_regs = {
856 DIO_REG_LIST_DCN10()
857 };
858
859 #define DIO_MASK_SH_LIST(mask_sh)\
860 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
861
862 static const struct dcn_dio_shift dio_shift = {
863 DIO_MASK_SH_LIST(__SHIFT)
864 };
865
866 static const struct dcn_dio_mask dio_mask = {
867 DIO_MASK_SH_LIST(_MASK)
868 };
869
870 static const struct resource_caps res_cap_dcn31 = {
871 .num_timing_generator = 4,
872 .num_opp = 4,
873 .num_video_plane = 4,
874 .num_audio = 5,
875 .num_stream_encoder = 5,
876 .num_dig_link_enc = 5,
877 .num_hpo_frl = 1,
878 .num_hpo_dp_stream_encoder = 4,
879 .num_hpo_dp_link_encoder = 2,
880 .num_pll = 5,
881 .num_dwb = 1,
882 .num_ddc = 5,
883 .num_vmid = 16,
884 .num_mpc_3dlut = 2,
885 .num_dsc = 3,
886 };
887
888 static const struct dc_plane_cap plane_cap = {
889 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
890 .per_pixel_alpha = true,
891
892 .pixel_format_support = {
893 .argb8888 = true,
894 .nv12 = true,
895 .fp16 = true,
896 .p010 = true,
897 .ayuv = false,
898 },
899
900 .max_upscale_factor = {
901 .argb8888 = 16000,
902 .nv12 = 16000,
903 .fp16 = 16000
904 },
905
906 // 6:1 downscaling ratio: 1000/6 = 166.666
907 .max_downscale_factor = {
908 .argb8888 = 167,
909 .nv12 = 167,
910 .fp16 = 167
911 },
912 64,
913 64
914 };
915
916 static const struct dc_debug_options debug_defaults_drv = {
917 .limit_ffe = 3,
918 .disable_z10 = true, /*hw not support it*/
919 .disable_dmcu = true,
920 .force_abm_enable = false,
921 .clock_trace = true,
922 .disable_pplib_clock_request = false,
923 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
924 .force_single_disp_pipe_split = false,
925 .disable_dcc = DCC_ENABLE,
926 .vsr_support = true,
927 .performance_trace = false,
928 .max_downscale_src_width = 4096,/*upto true 4k*/
929 .disable_pplib_wm_range = false,
930 .scl_reset_length10 = true,
931 .sanity_checks = false,
932 .underflow_assert_delay_us = 0xFFFFFFFF,
933 .dwb_fi_phase = -1, // -1 = disable,
934 .dmub_command_table = true,
935 .pstate_enabled = true,
936 .use_max_lb = true,
937 .enable_mem_low_power = {
938 .bits = {
939 .vga = true,
940 .i2c = true,
941 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
942 .dscl = true,
943 .cm = true,
944 .mpc = true,
945 .optc = true,
946 .vpg = true,
947 .afmt = true,
948 }
949 },
950 .max_frl_rate = HDMI_FRL_LINK_RATE_12GBPS,
951 .psr_power_use_phy_fsm = 0,
952 .using_dml2 = false,
953 .min_disp_clk_khz = 100000,
954 };
955
956 static const struct dc_check_config config_defaults = {
957 .enable_legacy_fast_update = true,
958 };
959
960 static const struct dc_panel_config panel_config_defaults = {
961 .psr = {
962 .disable_psr = false,
963 .disallow_psrsu = false,
964 .disallow_replay = false,
965 },
966 .ilr = {
967 .optimize_edp_link_rate = true,
968 },
969 };
970
dcn31_dpp_destroy(struct dpp ** dpp)971 static void dcn31_dpp_destroy(struct dpp **dpp)
972 {
973 kfree(TO_DCN20_DPP(*dpp));
974 *dpp = NULL;
975 }
976
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)977 static struct dpp *dcn31_dpp_create(
978 struct dc_context *ctx,
979 uint32_t inst)
980 {
981 struct dcn3_dpp *dpp =
982 kzalloc_obj(struct dcn3_dpp);
983
984 if (!dpp)
985 return NULL;
986
987 if (dpp3_construct(dpp, ctx, inst,
988 &dpp_regs[inst], &tf_shift, &tf_mask))
989 return &dpp->base;
990
991 BREAK_TO_DEBUGGER();
992 kfree(dpp);
993 return NULL;
994 }
995
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)996 static struct output_pixel_processor *dcn31_opp_create(
997 struct dc_context *ctx, uint32_t inst)
998 {
999 struct dcn20_opp *opp =
1000 kzalloc_obj(struct dcn20_opp);
1001
1002 if (!opp) {
1003 BREAK_TO_DEBUGGER();
1004 return NULL;
1005 }
1006
1007 dcn20_opp_construct(opp, ctx, inst,
1008 &opp_regs[inst], &opp_shift, &opp_mask);
1009 return &opp->base;
1010 }
1011
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1012 static struct dce_aux *dcn31_aux_engine_create(
1013 struct dc_context *ctx,
1014 uint32_t inst)
1015 {
1016 struct aux_engine_dce110 *aux_engine =
1017 kzalloc_obj(struct aux_engine_dce110);
1018
1019 if (!aux_engine)
1020 return NULL;
1021
1022 dce110_aux_engine_construct(aux_engine, ctx, inst,
1023 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1024 &aux_engine_regs[inst],
1025 &aux_mask,
1026 &aux_shift,
1027 ctx->dc->caps.extended_aux_timeout_support);
1028
1029 return &aux_engine->base;
1030 }
1031 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1032
1033 static const struct dce_i2c_registers i2c_hw_regs[] = {
1034 i2c_inst_regs(1),
1035 i2c_inst_regs(2),
1036 i2c_inst_regs(3),
1037 i2c_inst_regs(4),
1038 i2c_inst_regs(5),
1039 };
1040
1041 static const struct dce_i2c_shift i2c_shifts = {
1042 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1043 };
1044
1045 static const struct dce_i2c_mask i2c_masks = {
1046 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1047 };
1048
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1049 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1050 struct dc_context *ctx,
1051 uint32_t inst)
1052 {
1053 struct dce_i2c_hw *dce_i2c_hw =
1054 kzalloc_obj(struct dce_i2c_hw);
1055
1056 if (!dce_i2c_hw)
1057 return NULL;
1058
1059 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1060 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1061
1062 return dce_i2c_hw;
1063 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1064 static struct mpc *dcn31_mpc_create(
1065 struct dc_context *ctx,
1066 int num_mpcc,
1067 int num_rmu)
1068 {
1069 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1070
1071 if (!mpc30)
1072 return NULL;
1073
1074 dcn30_mpc_construct(mpc30, ctx,
1075 &mpc_regs,
1076 &mpc_shift,
1077 &mpc_mask,
1078 num_mpcc,
1079 num_rmu);
1080
1081 return &mpc30->base;
1082 }
1083
dcn315_dio_create(struct dc_context * ctx)1084 static struct dio *dcn315_dio_create(struct dc_context *ctx)
1085 {
1086 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1087
1088 if (!dio10)
1089 return NULL;
1090
1091 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1092
1093 return &dio10->base;
1094 }
1095
dcn31_hubbub_create(struct dc_context * ctx)1096 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1097 {
1098 int i;
1099
1100 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1101
1102 if (!hubbub3)
1103 return NULL;
1104
1105 hubbub31_construct(hubbub3, ctx,
1106 &hubbub_reg,
1107 &hubbub_shift,
1108 &hubbub_mask,
1109 dcn3_15_ip.det_buffer_size_kbytes,
1110 dcn3_15_ip.pixel_chunk_size_kbytes,
1111 dcn3_15_ip.config_return_buffer_size_in_kbytes);
1112
1113
1114 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1115 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1116
1117 vmid->ctx = ctx;
1118
1119 vmid->regs = &vmid_regs[i];
1120 vmid->shifts = &vmid_shifts;
1121 vmid->masks = &vmid_masks;
1122 }
1123
1124 return &hubbub3->base;
1125 }
1126
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1127 static struct timing_generator *dcn31_timing_generator_create(
1128 struct dc_context *ctx,
1129 uint32_t instance)
1130 {
1131 struct optc *tgn10 =
1132 kzalloc_obj(struct optc);
1133
1134 if (!tgn10)
1135 return NULL;
1136
1137 tgn10->base.inst = instance;
1138 tgn10->base.ctx = ctx;
1139
1140 tgn10->tg_regs = &optc_regs[instance];
1141 tgn10->tg_shift = &optc_shift;
1142 tgn10->tg_mask = &optc_mask;
1143
1144 dcn31_timing_generator_init(tgn10);
1145
1146 return &tgn10->base;
1147 }
1148
1149 static const struct encoder_feature_support link_enc_feature = {
1150 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1151 .max_hdmi_pixel_clock = 600000,
1152 .hdmi_ycbcr420_supported = true,
1153 .dp_ycbcr420_supported = true,
1154 .fec_supported = true,
1155 .flags.bits.IS_HBR2_CAPABLE = true,
1156 .flags.bits.IS_HBR3_CAPABLE = true,
1157 .flags.bits.IS_TPS3_CAPABLE = true,
1158 .flags.bits.IS_TPS4_CAPABLE = true
1159 };
1160
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1161 static struct link_encoder *dcn31_link_encoder_create(
1162 struct dc_context *ctx,
1163 const struct encoder_init_data *enc_init_data)
1164 {
1165 (void)ctx;
1166 struct dcn20_link_encoder *enc20 =
1167 kzalloc_obj(struct dcn20_link_encoder);
1168
1169 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1170 return NULL;
1171
1172 dcn31_link_encoder_construct(enc20,
1173 enc_init_data,
1174 &link_enc_feature,
1175 &link_enc_regs[enc_init_data->transmitter],
1176 &link_enc_aux_regs[enc_init_data->channel - 1],
1177 &link_enc_hpd_regs[enc_init_data->hpd_source],
1178 &le_shift,
1179 &le_mask);
1180
1181 return &enc20->enc10.base;
1182 }
1183
1184 /* Create a minimal link encoder object not associated with a particular
1185 * physical connector.
1186 * resource_funcs.link_enc_create_minimal
1187 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1188 static struct link_encoder *dcn31_link_enc_create_minimal(
1189 struct dc_context *ctx, enum engine_id eng_id)
1190 {
1191 struct dcn20_link_encoder *enc20;
1192
1193 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1194 return NULL;
1195
1196 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1197 if (!enc20)
1198 return NULL;
1199
1200 dcn31_link_encoder_construct_minimal(
1201 enc20,
1202 ctx,
1203 &link_enc_feature,
1204 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1205 &le_shift,
1206 &le_mask,
1207 eng_id);
1208
1209 return &enc20->enc10.base;
1210 }
1211
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1212 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1213 {
1214 struct dcn31_panel_cntl *panel_cntl =
1215 kzalloc_obj(struct dcn31_panel_cntl);
1216
1217 if (!panel_cntl)
1218 return NULL;
1219
1220 dcn31_panel_cntl_construct(panel_cntl, init_data);
1221
1222 return &panel_cntl->base;
1223 }
1224
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1225 static void read_dce_straps(
1226 struct dc_context *ctx,
1227 struct resource_straps *straps)
1228 {
1229 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1230 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1231
1232 }
1233
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1234 static struct audio *dcn31_create_audio(
1235 struct dc_context *ctx, unsigned int inst)
1236 {
1237 return dce_audio_create(ctx, inst,
1238 &audio_regs[inst], &audio_shift, &audio_mask);
1239 }
1240
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1241 static struct vpg *dcn31_vpg_create(
1242 struct dc_context *ctx,
1243 uint32_t inst)
1244 {
1245 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1246
1247 if (!vpg31)
1248 return NULL;
1249
1250 vpg31_construct(vpg31, ctx, inst,
1251 &vpg_regs[inst],
1252 &vpg_shift,
1253 &vpg_mask);
1254
1255 return &vpg31->base;
1256 }
1257
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1258 static struct afmt *dcn31_afmt_create(
1259 struct dc_context *ctx,
1260 uint32_t inst)
1261 {
1262 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1263
1264 if (!afmt31)
1265 return NULL;
1266
1267 afmt31_construct(afmt31, ctx, inst,
1268 &afmt_regs[inst],
1269 &afmt_shift,
1270 &afmt_mask);
1271
1272 // Light sleep by default, no need to power down here
1273
1274 return &afmt31->base;
1275 }
1276
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1277 static struct apg *dcn31_apg_create(
1278 struct dc_context *ctx,
1279 uint32_t inst)
1280 {
1281 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1282
1283 if (!apg31)
1284 return NULL;
1285
1286 apg31_construct(apg31, ctx, inst,
1287 &apg_regs[inst],
1288 &apg_shift,
1289 &apg_mask);
1290
1291 return &apg31->base;
1292 }
1293
dcn315_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1294 static struct stream_encoder *dcn315_stream_encoder_create(
1295 enum engine_id eng_id,
1296 struct dc_context *ctx)
1297 {
1298 struct dcn10_stream_encoder *enc1;
1299 struct vpg *vpg;
1300 struct afmt *afmt;
1301 int vpg_inst;
1302 int afmt_inst;
1303
1304 /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/
1305
1306 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1307 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1308 return NULL;
1309
1310 vpg_inst = eng_id;
1311 afmt_inst = eng_id;
1312
1313 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1314 vpg = dcn31_vpg_create(ctx, vpg_inst);
1315 afmt = dcn31_afmt_create(ctx, afmt_inst);
1316
1317 if (!enc1 || !vpg || !afmt) {
1318 kfree(enc1);
1319 kfree(vpg);
1320 kfree(afmt);
1321 return NULL;
1322 }
1323
1324 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1325 eng_id, vpg, afmt,
1326 &stream_enc_regs[eng_id],
1327 &se_shift, &se_mask);
1328
1329 return &enc1->base;
1330 }
1331
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1332 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1333 struct dc_context *ctx)
1334 {
1335 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1336 struct afmt *afmt;
1337 struct vpg *vpg;
1338 int afmt_inst;
1339 int vpg_inst;
1340
1341 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1342 if (eng_id == ENGINE_ID_HPO_0) {
1343 vpg_inst = 5;
1344 afmt_inst = 5;
1345 } else {
1346 return NULL;
1347 }
1348
1349 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1350 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1351 vpg = dcn31_vpg_create(ctx, vpg_inst);
1352 afmt = dcn31_afmt_create(ctx, afmt_inst);
1353
1354 if (!hpo_enc3 || !vpg || !afmt) {
1355 kfree(hpo_enc3);
1356 kfree(vpg);
1357 kfree(afmt);
1358 return NULL;
1359 }
1360
1361 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1362 ctx,
1363 ctx->dc_bios,
1364 eng_id,
1365 vpg,
1366 afmt,
1367 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1368 &hpo_se_shift,
1369 &hpo_se_mask);
1370
1371 return &hpo_enc3->base;
1372 }
1373
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1374 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,
1375 struct dc_context *ctx)
1376 {
1377 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1378
1379 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1380
1381 /* allocate HPO link encoder */
1382 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1383 if (!hpo_enc3)
1384 return NULL; /* out of memory */
1385
1386 hpo_frl_link_encoder3_construct(hpo_enc3,
1387 ctx,
1388 eng_id - ENGINE_ID_HPO_0,
1389 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1390 &hpo_le_shift,
1391 &hpo_le_mask);
1392
1393 return &hpo_enc3->base;
1394 }
1395
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1396 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1397 enum engine_id eng_id,
1398 struct dc_context *ctx)
1399 {
1400 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1401 struct vpg *vpg;
1402 struct apg *apg;
1403 uint32_t hpo_dp_inst;
1404 uint32_t vpg_inst;
1405 uint32_t apg_inst;
1406
1407 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1408 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1409
1410 /* Mapping of VPG register blocks to HPO DP block instance:
1411 * VPG[6] -> HPO_DP[0]
1412 * VPG[7] -> HPO_DP[1]
1413 * VPG[8] -> HPO_DP[2]
1414 * VPG[9] -> HPO_DP[3]
1415 */
1416 vpg_inst = hpo_dp_inst + 6;
1417
1418 /* Mapping of APG register blocks to HPO DP block instance:
1419 * APG[0] -> HPO_DP[0]
1420 * APG[1] -> HPO_DP[1]
1421 * APG[2] -> HPO_DP[2]
1422 * APG[3] -> HPO_DP[3]
1423 */
1424 apg_inst = hpo_dp_inst;
1425
1426 /* allocate HPO stream encoder and create VPG sub-block */
1427 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1428 vpg = dcn31_vpg_create(ctx, vpg_inst);
1429 apg = dcn31_apg_create(ctx, apg_inst);
1430
1431 if (!hpo_dp_enc31 || !vpg || !apg) {
1432 kfree(hpo_dp_enc31);
1433 kfree(vpg);
1434 kfree(apg);
1435 return NULL;
1436 }
1437
1438 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1439 hpo_dp_inst, eng_id, vpg, apg,
1440 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1441 &hpo_dp_se_shift, &hpo_dp_se_mask);
1442
1443 return &hpo_dp_enc31->base;
1444 }
1445
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1446 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1447 uint8_t inst,
1448 struct dc_context *ctx)
1449 {
1450 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1451
1452 /* allocate HPO link encoder */
1453 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1454 if (!hpo_dp_enc31)
1455 return NULL; /* out of memory */
1456
1457 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1458 &hpo_dp_link_enc_regs[inst],
1459 &hpo_dp_le_shift, &hpo_dp_le_mask);
1460
1461 return &hpo_dp_enc31->base;
1462 }
1463
dcn31_hwseq_create(struct dc_context * ctx)1464 static struct dce_hwseq *dcn31_hwseq_create(
1465 struct dc_context *ctx)
1466 {
1467 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1468
1469 if (hws) {
1470 hws->ctx = ctx;
1471 hws->regs = &hwseq_reg;
1472 hws->shifts = &hwseq_shift;
1473 hws->masks = &hwseq_mask;
1474 }
1475 return hws;
1476 }
1477 static const struct resource_create_funcs res_create_funcs = {
1478 .read_dce_straps = read_dce_straps,
1479 .create_audio = dcn31_create_audio,
1480 .create_stream_encoder = dcn315_stream_encoder_create,
1481 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1482 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1483 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1484 .create_hwseq = dcn31_hwseq_create,
1485 };
1486
dcn315_resource_destruct(struct dcn315_resource_pool * pool)1487 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
1488 {
1489 unsigned int i;
1490
1491 for (i = 0; i < pool->base.stream_enc_count; i++) {
1492 if (pool->base.stream_enc[i] != NULL) {
1493 if (pool->base.stream_enc[i]->vpg != NULL) {
1494 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1495 pool->base.stream_enc[i]->vpg = NULL;
1496 }
1497 if (pool->base.stream_enc[i]->afmt != NULL) {
1498 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1499 pool->base.stream_enc[i]->afmt = NULL;
1500 }
1501 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1502 pool->base.stream_enc[i] = NULL;
1503 }
1504 }
1505
1506 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1507 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1508 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1509 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1510 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1511 }
1512
1513 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1514 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1515 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1516 }
1517
1518 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1519 pool->base.hpo_frl_stream_enc[i] = NULL;
1520 }
1521 }
1522
1523 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1524 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1525 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1526 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1527 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1528 }
1529 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1530 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1531 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1532 }
1533 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1534 pool->base.hpo_dp_stream_enc[i] = NULL;
1535 }
1536 }
1537
1538 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1539 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1540 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1541 pool->base.hpo_dp_link_enc[i] = NULL;
1542 }
1543 }
1544
1545 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1546 if (pool->base.dscs[i] != NULL)
1547 dcn20_dsc_destroy(&pool->base.dscs[i]);
1548 }
1549
1550 if (pool->base.mpc != NULL) {
1551 kfree(TO_DCN20_MPC(pool->base.mpc));
1552 pool->base.mpc = NULL;
1553 }
1554 if (pool->base.hubbub != NULL) {
1555 kfree(pool->base.hubbub);
1556 pool->base.hubbub = NULL;
1557 }
1558 if (pool->base.dio != NULL) {
1559 kfree(TO_DCN10_DIO(pool->base.dio));
1560 pool->base.dio = NULL;
1561 }
1562 for (i = 0; i < pool->base.pipe_count; i++) {
1563 if (pool->base.dpps[i] != NULL)
1564 dcn31_dpp_destroy(&pool->base.dpps[i]);
1565
1566 if (pool->base.ipps[i] != NULL)
1567 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1568
1569 if (pool->base.hubps[i] != NULL) {
1570 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1571 pool->base.hubps[i] = NULL;
1572 }
1573
1574 if (pool->base.irqs != NULL) {
1575 dal_irq_service_destroy(&pool->base.irqs);
1576 }
1577 }
1578
1579 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1580 if (pool->base.engines[i] != NULL)
1581 dce110_engine_destroy(&pool->base.engines[i]);
1582 if (pool->base.hw_i2cs[i] != NULL) {
1583 kfree(pool->base.hw_i2cs[i]);
1584 pool->base.hw_i2cs[i] = NULL;
1585 }
1586 if (pool->base.sw_i2cs[i] != NULL) {
1587 kfree(pool->base.sw_i2cs[i]);
1588 pool->base.sw_i2cs[i] = NULL;
1589 }
1590 }
1591
1592 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1593 if (pool->base.opps[i] != NULL)
1594 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1595 }
1596
1597 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1598 if (pool->base.timing_generators[i] != NULL) {
1599 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1600 pool->base.timing_generators[i] = NULL;
1601 }
1602 }
1603
1604 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1605 if (pool->base.dwbc[i] != NULL) {
1606 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1607 pool->base.dwbc[i] = NULL;
1608 }
1609 if (pool->base.mcif_wb[i] != NULL) {
1610 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1611 pool->base.mcif_wb[i] = NULL;
1612 }
1613 }
1614
1615 for (i = 0; i < pool->base.audio_count; i++) {
1616 if (pool->base.audios[i])
1617 dce_aud_destroy(&pool->base.audios[i]);
1618 }
1619
1620 for (i = 0; i < pool->base.clk_src_count; i++) {
1621 if (pool->base.clock_sources[i] != NULL) {
1622 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1623 pool->base.clock_sources[i] = NULL;
1624 }
1625 }
1626
1627 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1628 if (pool->base.mpc_lut[i] != NULL) {
1629 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1630 pool->base.mpc_lut[i] = NULL;
1631 }
1632 if (pool->base.mpc_shaper[i] != NULL) {
1633 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1634 pool->base.mpc_shaper[i] = NULL;
1635 }
1636 }
1637
1638 if (pool->base.dp_clock_source != NULL) {
1639 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1640 pool->base.dp_clock_source = NULL;
1641 }
1642
1643 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1644 if (pool->base.multiple_abms[i] != NULL)
1645 dce_abm_destroy(&pool->base.multiple_abms[i]);
1646 }
1647
1648 if (pool->base.psr != NULL)
1649 dmub_psr_destroy(&pool->base.psr);
1650
1651 if (pool->base.replay != NULL)
1652 dmub_replay_destroy(&pool->base.replay);
1653
1654 if (pool->base.dccg != NULL)
1655 dcn_dccg_destroy(&pool->base.dccg);
1656 }
1657
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1658 static struct hubp *dcn31_hubp_create(
1659 struct dc_context *ctx,
1660 uint32_t inst)
1661 {
1662 struct dcn20_hubp *hubp2 =
1663 kzalloc_obj(struct dcn20_hubp);
1664
1665 if (!hubp2)
1666 return NULL;
1667
1668 if (hubp31_construct(hubp2, ctx, inst,
1669 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1670 return &hubp2->base;
1671
1672 BREAK_TO_DEBUGGER();
1673 kfree(hubp2);
1674 return NULL;
1675 }
1676
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1677 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1678 {
1679 unsigned int i;
1680 uint32_t pipe_count = pool->res_cap->num_dwb;
1681
1682 for (i = 0; i < pipe_count; i++) {
1683 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1684
1685 if (!dwbc30) {
1686 dm_error("DC: failed to create dwbc30!\n");
1687 return false;
1688 }
1689
1690 dcn30_dwbc_construct(dwbc30, ctx,
1691 &dwbc30_regs[i],
1692 &dwbc30_shift,
1693 &dwbc30_mask,
1694 i);
1695
1696 pool->dwbc[i] = &dwbc30->base;
1697 }
1698 return true;
1699 }
1700
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1701 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1702 {
1703 unsigned int i;
1704 uint32_t pipe_count = pool->res_cap->num_dwb;
1705
1706 for (i = 0; i < pipe_count; i++) {
1707 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1708
1709 if (!mcif_wb30) {
1710 dm_error("DC: failed to create mcif_wb30!\n");
1711 return false;
1712 }
1713
1714 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1715 &mcif_wb30_regs[i],
1716 &mcif_wb30_shift,
1717 &mcif_wb30_mask,
1718 i);
1719
1720 pool->mcif_wb[i] = &mcif_wb30->base;
1721 }
1722 return true;
1723 }
1724
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1725 static struct display_stream_compressor *dcn31_dsc_create(
1726 struct dc_context *ctx, uint32_t inst)
1727 {
1728 struct dcn20_dsc *dsc =
1729 kzalloc_obj(struct dcn20_dsc);
1730
1731 if (!dsc) {
1732 BREAK_TO_DEBUGGER();
1733 return NULL;
1734 }
1735
1736 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1737 return &dsc->base;
1738 }
1739
dcn315_destroy_resource_pool(struct resource_pool ** pool)1740 static void dcn315_destroy_resource_pool(struct resource_pool **pool)
1741 {
1742 struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);
1743
1744 dcn315_resource_destruct(dcn31_pool);
1745 kfree(dcn31_pool);
1746 *pool = NULL;
1747 }
1748
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1749 static struct clock_source *dcn31_clock_source_create(
1750 struct dc_context *ctx,
1751 struct dc_bios *bios,
1752 enum clock_source_id id,
1753 const struct dce110_clk_src_regs *regs,
1754 bool dp_clk_src)
1755 {
1756 struct dce110_clk_src *clk_src =
1757 kzalloc_obj(struct dce110_clk_src);
1758
1759 if (!clk_src)
1760 return NULL;
1761
1762 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1763 regs, &cs_shift, &cs_mask)) {
1764 clk_src->base.dp_clk_src = dp_clk_src;
1765 return &clk_src->base;
1766 }
1767
1768 kfree(clk_src);
1769 BREAK_TO_DEBUGGER();
1770 return NULL;
1771 }
1772
is_dual_plane(enum surface_pixel_format format)1773 static bool is_dual_plane(enum surface_pixel_format format)
1774 {
1775 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1776 }
1777
source_format_to_bpp(enum source_format_class SourcePixelFormat)1778 static int source_format_to_bpp (enum source_format_class SourcePixelFormat)
1779 {
1780 if (SourcePixelFormat == dm_444_64)
1781 return 8;
1782 else if (SourcePixelFormat == dm_444_16)
1783 return 2;
1784 else if (SourcePixelFormat == dm_444_8)
1785 return 1;
1786 else if (SourcePixelFormat == dm_rgbe_alpha)
1787 return 5;
1788 else if (SourcePixelFormat == dm_420_8)
1789 return 3;
1790 else if (SourcePixelFormat == dm_420_12)
1791 return 6;
1792 else
1793 return 4;
1794 }
1795
allow_pixel_rate_crb(struct dc * dc,struct dc_state * context)1796 static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
1797 {
1798 unsigned int i;
1799 struct resource_context *res_ctx = &context->res_ctx;
1800
1801 /* Only apply for dual stream scenarios with edp*/
1802 if (context->stream_count != 2)
1803 return false;
1804 if (context->streams[0]->signal != SIGNAL_TYPE_EDP && context->streams[1]->signal != SIGNAL_TYPE_EDP)
1805 return false;
1806
1807 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1808 if (!res_ctx->pipe_ctx[i].stream)
1809 continue;
1810
1811 /*Don't apply if scaling*/
1812 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||
1813 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||
1814 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width
1815 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||
1816 res_ctx->pipe_ctx[i].plane_state->src_rect.height
1817 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))
1818 return false;
1819 /*Don't apply if MPO to avoid transition issues*/
1820 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)
1821 return false;
1822 }
1823 return true;
1824 }
1825
dcn315_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1826 static int dcn315_populate_dml_pipes_from_context(
1827 struct dc *dc, struct dc_state *context,
1828 display_e2e_pipe_params_st *pipes,
1829 enum dc_validate_mode validate_mode)
1830 {
1831 unsigned int i;
1832 int pipe_cnt, crb_idx, crb_pipes;
1833 struct resource_context *res_ctx = &context->res_ctx;
1834 struct pipe_ctx *pipe = NULL;
1835 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
1836 int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;
1837 bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
1838
1839 DC_FP_START();
1840 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1841 DC_FP_END();
1842
1843 for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1844 struct dc_crtc_timing *timing;
1845
1846 if (!res_ctx->pipe_ctx[i].stream)
1847 continue;
1848 pipe = &res_ctx->pipe_ctx[i];
1849 timing = &pipe->stream->timing;
1850
1851 /*
1852 * Immediate flip can be set dynamically after enabling the plane.
1853 * We need to require support for immediate flip or underflow can be
1854 * intermittently experienced depending on peak b/w requirements.
1855 */
1856 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1857
1858 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1859 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1860 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1861 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1862 DC_FP_START();
1863 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1864 if (pixel_rate_crb) {
1865 int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);
1866 /* Ceil to crb segment size */
1867 int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate(
1868 &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
1869
1870 if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {
1871 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
1872 split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
1873 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1874
1875 /* Minimum 2 segments to allow mpc/odm combine if its used later */
1876 if (approx_det_segs_required_for_pstate < 2)
1877 approx_det_segs_required_for_pstate = 2;
1878 if (split_required)
1879 approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2;
1880 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate;
1881 remaining_det_segs -= approx_det_segs_required_for_pstate;
1882 } else
1883 remaining_det_segs = -1;
1884 crb_pipes++;
1885 }
1886 DC_FP_END();
1887
1888 if (pipes[pipe_cnt].dout.dsc_enable) {
1889 switch (timing->display_color_depth) {
1890 case COLOR_DEPTH_888:
1891 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1892 break;
1893 case COLOR_DEPTH_101010:
1894 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1895 break;
1896 case COLOR_DEPTH_121212:
1897 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1898 break;
1899 default:
1900 ASSERT(0);
1901 break;
1902 }
1903 }
1904 pipe_cnt++;
1905 }
1906
1907 /* Spread remaining unreserved crb evenly among all pipes*/
1908 if (pixel_rate_crb) {
1909 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
1910 pipe = &res_ctx->pipe_ctx[i];
1911 if (!pipe->stream)
1912 continue;
1913
1914 /* Do not use asymetric crb if not enough for pstate support */
1915 if (remaining_det_segs < 0) {
1916 pipes[pipe_cnt].pipe.src.det_size_override = 0;
1917 pipe_cnt++;
1918 continue;
1919 }
1920
1921 bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
1922 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1923
1924 if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0)
1925 pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +
1926 (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
1927 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) {
1928 /* Clamp to 2 pipe split max det segments */
1929 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);
1930 pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;
1931 }
1932 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) {
1933 /* If we are splitting we must have an even number of segments */
1934 remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;
1935 pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;
1936 }
1937 /* Convert segments into size for DML use */
1938 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;
1939
1940 crb_idx++;
1941 pipe_cnt++;
1942 }
1943 }
1944
1945 if (pipe_cnt)
1946 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1947 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1948 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)
1949 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;
1950
1951 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1952 if (is_dual_plane(pipe->plane_state->format)
1953 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1954 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1955 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1956 } else if (!is_dual_plane(pipe->plane_state->format)
1957 && pipe->plane_state->src_rect.width <= 5120
1958 && (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
1959 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1960 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1961 pipes[0].pipe.src.unbounded_req_mode = true;
1962 }
1963 }
1964
1965 return pipe_cnt;
1966 }
1967
dcn315_get_panel_config_defaults(struct dc_panel_config * panel_config)1968 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config)
1969 {
1970 *panel_config = panel_config_defaults;
1971 }
1972
dcn315_get_power_profile(const struct dc_state * context)1973 static int dcn315_get_power_profile(const struct dc_state *context)
1974 {
1975 return !context->bw_ctx.bw.dcn.clk.p_state_change_support;
1976 }
1977
1978 static struct dc_cap_funcs cap_funcs = {
1979 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1980 };
1981
dcn315_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1982 static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1983 {
1984 DC_FP_START();
1985 dcn315_update_bw_bounding_box_fpu(dc, bw_params);
1986 DC_FP_END();
1987 }
1988
1989 static struct resource_funcs dcn315_res_pool_funcs = {
1990 .destroy = dcn315_destroy_resource_pool,
1991 .link_enc_create = dcn31_link_encoder_create,
1992 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1993 .link_encs_assign = link_enc_cfg_link_encs_assign,
1994 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1995 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1996 .panel_cntl_create = dcn31_panel_cntl_create,
1997 .validate_bandwidth = dcn31_validate_bandwidth,
1998 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1999 .update_soc_for_wm_a = dcn315_update_soc_for_wm_a,
2000 .populate_dml_pipes = dcn315_populate_dml_pipes_from_context,
2001 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2002 .release_pipe = dcn20_release_pipe,
2003 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2004 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2005 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2006 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
2007 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
2008 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2009 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2010 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2011 .update_bw_bounding_box = dcn315_update_bw_bounding_box,
2012 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2013 .get_panel_config_defaults = dcn315_get_panel_config_defaults,
2014 .get_power_profile = dcn315_get_power_profile,
2015 .get_det_buffer_size = dcn31_get_det_buffer_size,
2016 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2017 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
2018 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
2019 .get_default_tiling_info = dcn10_get_default_tiling_info
2020 };
2021
dcn315_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn315_resource_pool * pool)2022 static bool dcn315_resource_construct(
2023 uint8_t num_virtual_links,
2024 struct dc *dc,
2025 struct dcn315_resource_pool *pool)
2026 {
2027 int i;
2028 struct dc_context *ctx = dc->ctx;
2029 struct irq_service_init_data init_data;
2030
2031 ctx->dc_bios->regs = &bios_regs;
2032
2033 pool->base.res_cap = &res_cap_dcn31;
2034
2035 pool->base.funcs = &dcn315_res_pool_funcs;
2036
2037 /*************************************************
2038 * Resource + asic cap harcoding *
2039 *************************************************/
2040 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2041 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2042
2043 /* Enable 4to1MPC by default */
2044 dc->config.allow_4to1MPC = true;
2045 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2046 dc->caps.max_downscale_ratio = 600;
2047 dc->caps.i2c_speed_in_khz = 100;
2048 dc->caps.i2c_speed_in_khz_hdcp = 100;
2049 dc->caps.max_cursor_size = 256;
2050 dc->caps.min_horizontal_blanking_period = 80;
2051 dc->caps.dmdata_alloc_size = 2048;
2052 dc->caps.max_slave_planes = 2;
2053 dc->caps.max_slave_yuv_planes = 2;
2054 dc->caps.max_slave_rgb_planes = 2;
2055 dc->caps.post_blend_color_processing = true;
2056 dc->caps.force_dp_tps4_for_cp2520 = true;
2057 if (dc->config.forceHBR2CP2520)
2058 dc->caps.force_dp_tps4_for_cp2520 = false;
2059 dc->caps.hdmi_hpo = true;
2060 dc->caps.dp_hpo = true;
2061 dc->caps.dp_hdmi21_pcon_support = true;
2062 dc->caps.edp_dsc_support = true;
2063 dc->caps.extended_aux_timeout_support = true;
2064 dc->caps.dmcub_support = true;
2065 dc->caps.is_apu = true;
2066
2067 /* Color pipeline capabilities */
2068 dc->caps.color.dpp.dcn_arch = 1;
2069 dc->caps.color.dpp.input_lut_shared = 0;
2070 dc->caps.color.dpp.icsc = 1;
2071 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2072 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2073 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2074 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2075 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2076 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2077 dc->caps.color.dpp.post_csc = 1;
2078 dc->caps.color.dpp.gamma_corr = 1;
2079 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2080 dc->caps.color.dpp.upsp_pre_scaler = 0;
2081
2082 dc->caps.color.dpp.hw_3d_lut = 1;
2083 dc->caps.color.dpp.ogam_ram = 1;
2084 // no OGAM ROM on DCN301
2085 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2086 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2087 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2088 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2089 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2090 dc->caps.color.dpp.ocsc = 0;
2091
2092 dc->caps.color.mpc.gamut_remap = 1;
2093 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
2094 dc->caps.color.mpc.ogam_ram = 1;
2095 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2096 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2097 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2098 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2099 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2100 dc->caps.color.mpc.ocsc = 1;
2101 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2102
2103 dc->config.no_native422_support = true;
2104
2105 /* read VBIOS LTTPR caps */
2106 {
2107 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2108 enum bp_result bp_query_result;
2109 uint8_t is_vbios_lttpr_enable = 0;
2110
2111 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2112 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2113 }
2114
2115 /* interop bit is implicit */
2116 {
2117 dc->caps.vbios_lttpr_aware = true;
2118 }
2119 }
2120 dc->check_config = config_defaults;
2121
2122 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2123 dc->debug = debug_defaults_drv;
2124
2125 // Init the vm_helper
2126 if (dc->vm_helper)
2127 vm_helper_init(dc->vm_helper, 16);
2128
2129 /*************************************************
2130 * Create resources *
2131 *************************************************/
2132
2133 /* Clock Sources for Pixel Clock*/
2134 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2135 dcn31_clock_source_create(ctx, ctx->dc_bios,
2136 CLOCK_SOURCE_COMBO_PHY_PLL0,
2137 &clk_src_regs[0], false);
2138 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2139 dcn31_clock_source_create(ctx, ctx->dc_bios,
2140 CLOCK_SOURCE_COMBO_PHY_PLL1,
2141 &clk_src_regs[1], false);
2142 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2143 dcn31_clock_source_create(ctx, ctx->dc_bios,
2144 CLOCK_SOURCE_COMBO_PHY_PLL2,
2145 &clk_src_regs[2], false);
2146 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2147 dcn31_clock_source_create(ctx, ctx->dc_bios,
2148 CLOCK_SOURCE_COMBO_PHY_PLL3,
2149 &clk_src_regs[3], false);
2150 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2151 dcn31_clock_source_create(ctx, ctx->dc_bios,
2152 CLOCK_SOURCE_COMBO_PHY_PLL4,
2153 &clk_src_regs[4], false);
2154
2155 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2156
2157 /* todo: not reuse phy_pll registers */
2158 pool->base.dp_clock_source =
2159 dcn31_clock_source_create(ctx, ctx->dc_bios,
2160 CLOCK_SOURCE_ID_DP_DTO,
2161 &clk_src_regs[0], true);
2162
2163 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2164 if (pool->base.clock_sources[i] == NULL) {
2165 dm_error("DC: failed to create clock sources!\n");
2166 BREAK_TO_DEBUGGER();
2167 goto create_fail;
2168 }
2169 }
2170
2171 /* TODO: DCCG */
2172 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2173 if (pool->base.dccg == NULL) {
2174 dm_error("DC: failed to create dccg!\n");
2175 BREAK_TO_DEBUGGER();
2176 goto create_fail;
2177 }
2178
2179 /* TODO: IRQ */
2180 init_data.ctx = dc->ctx;
2181 pool->base.irqs = dal_irq_service_dcn315_create(&init_data);
2182 if (!pool->base.irqs)
2183 goto create_fail;
2184
2185 /* HUBBUB */
2186 pool->base.hubbub = dcn31_hubbub_create(ctx);
2187 if (pool->base.hubbub == NULL) {
2188 BREAK_TO_DEBUGGER();
2189 dm_error("DC: failed to create hubbub!\n");
2190 goto create_fail;
2191 }
2192
2193 /* DIO */
2194 pool->base.dio = dcn315_dio_create(ctx);
2195 if (pool->base.dio == NULL) {
2196 BREAK_TO_DEBUGGER();
2197 dm_error("DC: failed to create dio!\n");
2198 goto create_fail;
2199 }
2200
2201 /* HUBPs, DPPs, OPPs and TGs */
2202 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2203 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2204 if (pool->base.hubps[i] == NULL) {
2205 BREAK_TO_DEBUGGER();
2206 dm_error(
2207 "DC: failed to create hubps!\n");
2208 goto create_fail;
2209 }
2210
2211 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2212 if (pool->base.dpps[i] == NULL) {
2213 BREAK_TO_DEBUGGER();
2214 dm_error(
2215 "DC: failed to create dpps!\n");
2216 goto create_fail;
2217 }
2218 }
2219
2220 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2221 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2222 if (pool->base.opps[i] == NULL) {
2223 BREAK_TO_DEBUGGER();
2224 dm_error(
2225 "DC: failed to create output pixel processor!\n");
2226 goto create_fail;
2227 }
2228 }
2229
2230 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2231 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2232 ctx, i);
2233 if (pool->base.timing_generators[i] == NULL) {
2234 BREAK_TO_DEBUGGER();
2235 dm_error("DC: failed to create tg!\n");
2236 goto create_fail;
2237 }
2238 }
2239 pool->base.timing_generator_count = i;
2240
2241 /* PSR */
2242 pool->base.psr = dmub_psr_create(ctx);
2243 if (pool->base.psr == NULL) {
2244 dm_error("DC: failed to create psr obj!\n");
2245 BREAK_TO_DEBUGGER();
2246 goto create_fail;
2247 }
2248
2249 /* Replay */
2250 pool->base.replay = dmub_replay_create(ctx);
2251 if (pool->base.replay == NULL) {
2252 dm_error("DC: failed to create replay obj!\n");
2253 BREAK_TO_DEBUGGER();
2254 goto create_fail;
2255 }
2256
2257 /* ABM */
2258 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2259 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2260 &abm_regs[i],
2261 &abm_shift,
2262 &abm_mask);
2263 if (pool->base.multiple_abms[i] == NULL) {
2264 dm_error("DC: failed to create abm for pipe %d!\n", i);
2265 BREAK_TO_DEBUGGER();
2266 goto create_fail;
2267 }
2268 }
2269
2270 /* MPC and DSC */
2271 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2272 if (pool->base.mpc == NULL) {
2273 BREAK_TO_DEBUGGER();
2274 dm_error("DC: failed to create mpc!\n");
2275 goto create_fail;
2276 }
2277
2278 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2279 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2280 if (pool->base.dscs[i] == NULL) {
2281 BREAK_TO_DEBUGGER();
2282 dm_error("DC: failed to create display stream compressor %d!\n", i);
2283 goto create_fail;
2284 }
2285 }
2286
2287 /* DWB and MMHUBBUB */
2288 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2289 BREAK_TO_DEBUGGER();
2290 dm_error("DC: failed to create dwbc!\n");
2291 goto create_fail;
2292 }
2293
2294 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2295 BREAK_TO_DEBUGGER();
2296 dm_error("DC: failed to create mcif_wb!\n");
2297 goto create_fail;
2298 }
2299
2300 /* AUX and I2C */
2301 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2302 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2303 if (pool->base.engines[i] == NULL) {
2304 BREAK_TO_DEBUGGER();
2305 dm_error(
2306 "DC:failed to create aux engine!!\n");
2307 goto create_fail;
2308 }
2309 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2310 if (pool->base.hw_i2cs[i] == NULL) {
2311 BREAK_TO_DEBUGGER();
2312 dm_error(
2313 "DC:failed to create hw i2c!!\n");
2314 goto create_fail;
2315 }
2316 pool->base.sw_i2cs[i] = NULL;
2317 }
2318
2319 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2320 if (!resource_construct(num_virtual_links, dc, &pool->base,
2321 &res_create_funcs))
2322 goto create_fail;
2323
2324 /* HW Sequencer and Plane caps */
2325 dcn31_hw_sequencer_construct(dc);
2326
2327 dc->caps.max_planes = pool->base.pipe_count;
2328
2329 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2330 dc->caps.planes[i] = plane_cap;
2331
2332 dc->caps.max_odm_combine_factor = 4;
2333
2334 dc->cap_funcs = cap_funcs;
2335
2336 dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;
2337
2338 return true;
2339
2340 create_fail:
2341
2342 dcn315_resource_destruct(pool);
2343
2344 return false;
2345 }
2346
dcn315_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2347 struct resource_pool *dcn315_create_resource_pool(
2348 const struct dc_init_data *init_data,
2349 struct dc *dc)
2350 {
2351 struct dcn315_resource_pool *pool =
2352 kzalloc_obj(struct dcn315_resource_pool);
2353
2354 if (!pool)
2355 return NULL;
2356
2357 if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2358 return &pool->base;
2359
2360 BREAK_TO_DEBUGGER();
2361 kfree(pool);
2362 return NULL;
2363 }
2364