1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28 #include "dm_services.h"
29 #include "dm_helpers.h"
30 #include "core_types.h"
31 #include "resource.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "clk_mgr.h"
35 #include "reg_helper.h"
36 #include "abm.h"
37 #include "hubp.h"
38 #include "dchubbub.h"
39 #include "timing_generator.h"
40 #include "opp.h"
41 #include "ipp.h"
42 #include "mpc.h"
43 #include "mcif_wb.h"
44 #include "dc_dmub_srv.h"
45 #include "dcn314_hwseq.h"
46 #include "link_hwss.h"
47 #include "dpcd_defs.h"
48 #include "dce/dmub_outbox.h"
49 #include "link.h"
50 #include "dcn10/dcn10_hwseq.h"
51 #include "inc/link_enc_cfg.h"
52 #include "dcn30/dcn30_vpg.h"
53 #include "dce/dce_i2c_hw.h"
54 #include "dsc.h"
55 #include "dcn20/dcn20_optc.h"
56 #include "dcn30/dcn30_cm_common.h"
57
58 #define DC_LOGGER_INIT(logger)
59
60 #define CTX \
61 hws->ctx
62 #define REG(reg)\
63 hws->regs->reg
64 #define DC_LOGGER \
65 stream->ctx->logger
66
67
68 #undef FN
69 #define FN(reg_name, field_name) \
70 hws->shifts->field_name, hws->masks->field_name
71
update_dsc_on_stream(struct pipe_ctx * pipe_ctx,bool enable)72 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
73 {
74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
75 struct dc_stream_state *stream = pipe_ctx->stream;
76 struct pipe_ctx *odm_pipe;
77 int opp_cnt = 1;
78
79 ASSERT(dsc);
80 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
81 opp_cnt++;
82
83 if (enable) {
84 struct dsc_config dsc_cfg;
85 struct dsc_optc_config dsc_optc_cfg = {0};
86 enum optc_dsc_mode optc_dsc_mode;
87 struct dcn_dsc_state dsc_state = {0};
88
89 if (!dsc) {
90 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
91 return;
92 }
93
94 if (dsc->funcs->dsc_read_state) {
95 dsc->funcs->dsc_read_state(dsc, &dsc_state);
96 if (!dsc_state.dsc_fw_en) {
97 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
98 return;
99 }
100 }
101
102 /* Enable DSC hw block */
103 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
104 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
105 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
106 dsc_cfg.color_depth = stream->timing.display_color_depth;
107 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
108 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
109 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
110 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
111
112 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
113 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
114 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
115 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
116
117 ASSERT(odm_dsc);
118 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
119 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
120 }
121 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
122 dsc_cfg.pic_width *= opp_cnt;
123
124 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
125
126 /* Enable DSC in OPTC */
127 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
128 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
129 optc_dsc_mode,
130 dsc_optc_cfg.bytes_per_pixel,
131 dsc_optc_cfg.slice_width);
132 } else {
133 /* disable DSC in OPTC */
134 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
135 pipe_ctx->stream_res.tg,
136 OPTC_DSC_DISABLED, 0, 0);
137
138 /* disable DSC block */
139 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
140 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
141 ASSERT(odm_pipe->stream_res.dsc);
142 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
143 }
144 }
145 }
146
147 // Given any pipe_ctx, return the total ODM combine factor, and optionally return
148 // the OPPids which are used
get_odm_config(struct pipe_ctx * pipe_ctx,unsigned int * opp_instances)149 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
150 {
151 unsigned int opp_count = 1;
152 struct pipe_ctx *odm_pipe;
153
154 // First get to the top pipe
155 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
156 ;
157
158 // First pipe is always used
159 if (opp_instances)
160 opp_instances[0] = odm_pipe->stream_res.opp->inst;
161
162 // Find and count odm pipes, if any
163 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
164 if (opp_instances)
165 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
166 opp_count++;
167 }
168
169 return opp_count;
170 }
171
dcn314_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)172 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
173 {
174 struct pipe_ctx *odm_pipe;
175 int opp_cnt = 0;
176 int opp_inst[MAX_PIPES] = {0};
177 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
178 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
179 struct mpc *mpc = dc->res_pool->mpc;
180 int i;
181
182 opp_cnt = get_odm_config(pipe_ctx, opp_inst);
183
184 if (opp_cnt > 1)
185 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
186 pipe_ctx->stream_res.tg,
187 opp_inst, opp_cnt,
188 odm_slice_width, last_odm_slice_width);
189 else
190 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
191 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
192
193 if (mpc->funcs->set_out_rate_control) {
194 for (i = 0; i < opp_cnt; ++i) {
195 mpc->funcs->set_out_rate_control(
196 mpc, opp_inst[i],
197 false,
198 0,
199 NULL);
200 }
201 }
202
203 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
204 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
205 odm_pipe->stream_res.opp,
206 true);
207 }
208
209 if (pipe_ctx->stream_res.dsc) {
210 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
211
212 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
213
214 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
215 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
216 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
217 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
218 /* disconnect DSC block from stream */
219 dsc->funcs->dsc_disconnect(dsc);
220 }
221 }
222 }
223
dcn314_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)224 void dcn314_dsc_pg_control(
225 struct dce_hwseq *hws,
226 unsigned int dsc_inst,
227 bool power_on)
228 {
229 uint32_t power_gate = power_on ? 0 : 1;
230 uint32_t pwr_status = power_on ? 0 : 2;
231 uint32_t org_ip_request_cntl = 0;
232
233 if (hws->ctx->dc->debug.disable_dsc_power_gate)
234 return;
235
236 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
237 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
238 power_on)
239 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
240 hws->ctx->dc->res_pool->dccg, dsc_inst);
241
242 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
243 if (org_ip_request_cntl == 0)
244 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
245
246 switch (dsc_inst) {
247 case 0: /* DSC0 */
248 REG_UPDATE(DOMAIN16_PG_CONFIG,
249 DOMAIN_POWER_GATE, power_gate);
250
251 REG_WAIT(DOMAIN16_PG_STATUS,
252 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
253 1, 1000);
254 break;
255 case 1: /* DSC1 */
256 REG_UPDATE(DOMAIN17_PG_CONFIG,
257 DOMAIN_POWER_GATE, power_gate);
258
259 REG_WAIT(DOMAIN17_PG_STATUS,
260 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
261 1, 1000);
262 break;
263 case 2: /* DSC2 */
264 REG_UPDATE(DOMAIN18_PG_CONFIG,
265 DOMAIN_POWER_GATE, power_gate);
266
267 REG_WAIT(DOMAIN18_PG_STATUS,
268 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
269 1, 1000);
270 break;
271 case 3: /* DSC3 */
272 REG_UPDATE(DOMAIN19_PG_CONFIG,
273 DOMAIN_POWER_GATE, power_gate);
274
275 REG_WAIT(DOMAIN19_PG_STATUS,
276 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
277 1, 1000);
278 break;
279 default:
280 BREAK_TO_DEBUGGER();
281 break;
282 }
283
284 if (org_ip_request_cntl == 0)
285 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
286
287 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
288 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
289 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
290 hws->ctx->dc->res_pool->dccg, dsc_inst);
291 }
292
293 }
294
dcn314_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)295 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
296 {
297 bool force_on = true; /* disable power gating */
298 uint32_t org_ip_request_cntl = 0;
299
300 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
301 force_on = false;
302
303 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
304 if (org_ip_request_cntl == 0)
305 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
306 /* DCHUBP0/1/2/3/4/5 */
307 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
308 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
309 /* DPP0/1/2/3/4/5 */
310 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
311 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
312
313 force_on = true; /* disable power gating */
314 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
315 force_on = false;
316
317 /* DCS0/1/2/3/4 */
318 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
319 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
320 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
321 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
322
323 if (org_ip_request_cntl == 0)
324 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
325 }
326
dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx * pipe_ctx,unsigned int * k1_div,unsigned int * k2_div)327 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
328 {
329 struct dc_stream_state *stream = pipe_ctx->stream;
330 unsigned int odm_combine_factor = 0;
331 bool two_pix_per_container = false;
332
333 two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
334 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
335
336 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
337 *k1_div = PIXEL_RATE_DIV_BY_1;
338 *k2_div = PIXEL_RATE_DIV_BY_1;
339 } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
340 *k1_div = PIXEL_RATE_DIV_BY_1;
341 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
342 *k2_div = PIXEL_RATE_DIV_BY_2;
343 else
344 *k2_div = PIXEL_RATE_DIV_BY_4;
345 } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {
346 if (two_pix_per_container) {
347 *k1_div = PIXEL_RATE_DIV_BY_1;
348 *k2_div = PIXEL_RATE_DIV_BY_2;
349 } else {
350 *k1_div = PIXEL_RATE_DIV_BY_1;
351 *k2_div = PIXEL_RATE_DIV_BY_4;
352 if (odm_combine_factor == 2)
353 *k2_div = PIXEL_RATE_DIV_BY_2;
354 }
355 }
356
357 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
358 ASSERT(false);
359
360 return odm_combine_factor;
361 }
362
dcn314_calculate_pix_rate_divider(struct dc * dc,struct dc_state * context,const struct dc_stream_state * stream)363 void dcn314_calculate_pix_rate_divider(
364 struct dc *dc,
365 struct dc_state *context,
366 const struct dc_stream_state *stream)
367 {
368 struct dce_hwseq *hws = dc->hwseq;
369 struct pipe_ctx *pipe_ctx = NULL;
370 unsigned int k1_div = PIXEL_RATE_DIV_NA;
371 unsigned int k2_div = PIXEL_RATE_DIV_NA;
372
373 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
374
375 if (pipe_ctx) {
376 if (hws->funcs.calculate_dccg_k1_k2_values)
377 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
378
379 pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;
380 pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;
381 }
382 }
383
dcn314_is_pipe_dig_fifo_on(struct pipe_ctx * pipe)384 static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)
385 {
386 return pipe && pipe->stream
387 // Check dig's otg instance.
388 && pipe->stream_res.stream_enc
389 && pipe->stream_res.stream_enc->funcs->dig_source_otg
390 && pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)
391 && pipe->stream->link && pipe->stream->link->link_enc
392 && pipe->stream->link->link_enc->funcs->is_dig_enabled
393 && pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc)
394 && pipe->stream_res.stream_enc->funcs->is_fifo_enabled
395 && pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc);
396 }
397
dcn314_resync_fifo_dccg_dio(struct dce_hwseq * hws,struct dc * dc,struct dc_state * context,unsigned int current_pipe_idx)398 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
399 {
400 unsigned int i;
401 struct pipe_ctx *pipe = NULL;
402 bool otg_disabled[MAX_PIPES] = {false};
403
404 for (i = 0; i < dc->res_pool->pipe_count; i++) {
405 if (i <= current_pipe_idx) {
406 pipe = &context->res_ctx.pipe_ctx[i];
407 } else {
408 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
409 }
410
411 if (pipe->top_pipe || pipe->prev_odm_pipe)
412 continue;
413
414 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) &&
415 !pipe->stream->apply_seamless_boot_optimization &&
416 !pipe->stream->apply_edp_fast_boot_optimization) {
417 if (dcn314_is_pipe_dig_fifo_on(pipe))
418 continue;
419 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
420 reset_sync_context_for_pipe(dc, context, i);
421 otg_disabled[i] = true;
422 }
423 }
424
425 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
426
427 for (i = 0; i < dc->res_pool->pipe_count; i++) {
428 if (i <= current_pipe_idx)
429 pipe = &context->res_ctx.pipe_ctx[i];
430 else
431 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
432
433 if (otg_disabled[i]) {
434 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
435 int opp_cnt = 1;
436 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
437 int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
438 struct pipe_ctx *odm_pipe;
439
440 for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
441 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
442 opp_cnt++;
443 }
444 if (opp_cnt > 1)
445 pipe->stream_res.tg->funcs->set_odm_combine(
446 pipe->stream_res.tg,
447 opp_inst, opp_cnt,
448 odm_slice_width,
449 last_odm_slice_width);
450 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
451 }
452 }
453 }
454
dcn314_dpp_root_clock_control(struct dce_hwseq * hws,unsigned int dpp_inst,bool clock_on)455 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
456 {
457 if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
458 return;
459
460 if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)
461 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
462 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
463 }
464
apply_symclk_on_tx_off_wa(struct dc_link * link)465 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
466 {
467 /* There are use cases where SYMCLK is referenced by OTG. For instance
468 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
469 * However current link interface will power off PHY when disabling link
470 * output. This will turn off SYMCLK generated by PHY. The workaround is
471 * to identify such case where SYMCLK is still in use by OTG when we
472 * power off PHY. When this is detected, we will temporarily power PHY
473 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
474 * program_pix_clk interface. When OTG is disabled, we will then power
475 * off PHY by calling disable link output again.
476 *
477 * In future dcn generations, we plan to rework transmitter control
478 * interface so that we could have an option to set SYMCLK ON TX OFF
479 * state in one step without this workaround
480 */
481
482 struct dc *dc = link->ctx->dc;
483 struct pipe_ctx *pipe_ctx = NULL;
484 uint8_t i;
485
486 if (link->phy_state.symclk_ref_cnts.otg > 0) {
487 for (i = 0; i < MAX_PIPES; i++) {
488 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
489 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
490 pipe_ctx->clock_source->funcs->program_pix_clk(
491 pipe_ctx->clock_source,
492 &pipe_ctx->stream_res.pix_clk_params,
493 dc->link_srv->dp_get_encoding_format(
494 &pipe_ctx->link_config.dp_link_settings),
495 &pipe_ctx->pll_settings);
496 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
497 break;
498 }
499 }
500 }
501 }
502
dcn314_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)503 void dcn314_disable_link_output(struct dc_link *link,
504 const struct link_resource *link_res,
505 enum signal_type signal)
506 {
507 struct dc *dc = link->ctx->dc;
508 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
509 struct dmcu *dmcu = dc->res_pool->dmcu;
510
511 if (signal == SIGNAL_TYPE_EDP &&
512 link->dc->hwss.edp_backlight_control &&
513 !link->skip_implict_edp_power_control)
514 link->dc->hwss.edp_backlight_control(link, false);
515 else if (dmcu != NULL && dmcu->funcs->lock_phy)
516 dmcu->funcs->lock_phy(dmcu);
517
518 link_hwss->disable_link_output(link, link_res, signal);
519 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
520 /*
521 * Add the logic to extract BOTH power up and power down sequences
522 * from enable/disable link output and only call edp panel control
523 * in enable_link_dp and disable_link_dp once.
524 */
525 if (dmcu != NULL && dmcu->funcs->unlock_phy)
526 dmcu->funcs->unlock_phy(dmcu);
527 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
528
529 apply_symclk_on_tx_off_wa(link);
530 }
531
532 /**
533 * dcn314_dpp_pg_control - DPP power gate control.
534 *
535 * @hws: dce_hwseq reference.
536 * @dpp_inst: DPP instance reference.
537 * @power_on: true if we want to enable power gate, false otherwise.
538 *
539 * Enable or disable power gate in the specific DPP instance.
540 * If power gating is disabled, will force disable cursor in the DPP instance.
541 */
dcn314_dpp_pg_control(struct dce_hwseq * hws,unsigned int dpp_inst,bool power_on)542 void dcn314_dpp_pg_control(
543 struct dce_hwseq *hws,
544 unsigned int dpp_inst,
545 bool power_on)
546 {
547 uint32_t power_gate = power_on ? 0 : 1;
548 uint32_t pwr_status = power_on ? 0 : 2;
549
550
551 if (hws->ctx->dc->debug.disable_dpp_power_gate) {
552 /* Workaround for DCN314 with disabled power gating */
553 if (!power_on) {
554
555 /* Force disable cursor if power gating is disabled */
556 struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];
557 if (dpp && dpp->funcs->dpp_force_disable_cursor)
558 dpp->funcs->dpp_force_disable_cursor(dpp);
559 }
560 return;
561 }
562 if (REG(DOMAIN1_PG_CONFIG) == 0)
563 return;
564
565 switch (dpp_inst) {
566 case 0: /* DPP0 */
567 REG_UPDATE(DOMAIN1_PG_CONFIG,
568 DOMAIN1_POWER_GATE, power_gate);
569
570 REG_WAIT(DOMAIN1_PG_STATUS,
571 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
572 1, 1000);
573 break;
574 case 1: /* DPP1 */
575 REG_UPDATE(DOMAIN3_PG_CONFIG,
576 DOMAIN3_POWER_GATE, power_gate);
577
578 REG_WAIT(DOMAIN3_PG_STATUS,
579 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
580 1, 1000);
581 break;
582 case 2: /* DPP2 */
583 REG_UPDATE(DOMAIN5_PG_CONFIG,
584 DOMAIN5_POWER_GATE, power_gate);
585
586 REG_WAIT(DOMAIN5_PG_STATUS,
587 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
588 1, 1000);
589 break;
590 case 3: /* DPP3 */
591 REG_UPDATE(DOMAIN7_PG_CONFIG,
592 DOMAIN7_POWER_GATE, power_gate);
593
594 REG_WAIT(DOMAIN7_PG_STATUS,
595 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
596 1, 1000);
597 break;
598 default:
599 BREAK_TO_DEBUGGER();
600 break;
601 }
602 }
603