1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn31/dcn31_init.h"
32 #include "dcn314/dcn314_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "basics/conversion.h"
37 #include "dcn314_resource.h"
38
39 #include "dcn20/dcn20_resource.h"
40 #include "dcn30/dcn30_resource.h"
41 #include "dcn31/dcn31_resource.h"
42
43 #include "dcn10/dcn10_ipp.h"
44 #include "dcn30/dcn30_hubbub.h"
45 #include "dcn31/dcn31_hubbub.h"
46 #include "dcn30/dcn30_mpc.h"
47 #include "dcn31/dcn31_hubp.h"
48 #include "irq/dcn31/irq_service_dcn31.h"
49 #include "irq/dcn314/irq_service_dcn314.h"
50 #include "dcn30/dcn30_dpp.h"
51 #include "dcn314/dcn314_optc.h"
52 #include "dcn20/dcn20_hwseq.h"
53 #include "dcn30/dcn30_hwseq.h"
54 #include "dce110/dce110_hwseq.h"
55 #include "dcn30/dcn30_opp.h"
56 #include "dcn20/dcn20_dsc.h"
57 #include "dcn30/dcn30_vpg.h"
58 #include "dcn30/dcn30_afmt.h"
59 #include "dcn31/dcn31_dio_link_encoder.h"
60 #include "dcn314/dcn314_dio_stream_encoder.h"
61 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
62 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
63 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
64 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
65 #include "dcn31/dcn31_apg.h"
66 #include "dcn31/dcn31_vpg.h"
67 #include "dcn31/dcn31_afmt.h"
68 #include "dce/dce_clock_source.h"
69 #include "dce/dce_audio.h"
70 #include "dce/dce_hwseq.h"
71 #include "clk_mgr.h"
72 #include "dio/dcn10/dcn10_dio.h"
73 #include "dio/virtual/virtual_stream_encoder.h"
74 #include "dce110/dce110_resource.h"
75 #include "dml/display_mode_vba.h"
76 #include "dml/dcn31/dcn31_fpu.h"
77 #include "dml/dcn314/dcn314_fpu.h"
78 #include "dcn314/dcn314_dccg.h"
79 #include "dcn10/dcn10_resource.h"
80 #include "dcn31/dcn31_panel_cntl.h"
81 #include "dcn314/dcn314_hwseq.h"
82
83 #include "dcn30/dcn30_dwb.h"
84 #include "dcn30/dcn30_mmhubbub.h"
85
86 #include "dcn/dcn_3_1_4_offset.h"
87 #include "dcn/dcn_3_1_4_sh_mask.h"
88 #include "dpcs/dpcs_3_1_4_offset.h"
89 #include "dpcs/dpcs_3_1_4_sh_mask.h"
90
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
95 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
96
97 #include "reg_helper.h"
98 #include "dce/dmub_abm.h"
99 #include "dce/dmub_psr.h"
100 #include "dce/dmub_replay.h"
101 #include "dce/dce_aux.h"
102 #include "dce/dce_i2c.h"
103 #include "dml/dcn314/display_mode_vba_314.h"
104 #include "vm_helper.h"
105 #include "dcn20/dcn20_vmid.h"
106
107 #include "link_enc_cfg.h"
108
109 #define DCN_BASE__INST0_SEG1 0x000000C0
110 #define DCN_BASE__INST0_SEG2 0x000034C0
111 #define DCN_BASE__INST0_SEG3 0x00009000
112
113 #define NBIO_BASE__INST0_SEG1 0x00000014
114
115 #define MAX_INSTANCE 7
116 #define MAX_SEGMENT 8
117
118 #define regBIF_BX2_BIOS_SCRATCH_2 0x003a
119 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
120 #define regBIF_BX2_BIOS_SCRATCH_3 0x003b
121 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
122 #define regBIF_BX2_BIOS_SCRATCH_6 0x003e
123 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
124
125 #define DC_LOGGER \
126 dc->ctx->logger
127 #define DC_LOGGER_INIT(logger)
128
129 enum dcn31_clk_src_array_id {
130 DCN31_CLK_SRC_PLL0,
131 DCN31_CLK_SRC_PLL1,
132 DCN31_CLK_SRC_PLL2,
133 DCN31_CLK_SRC_PLL3,
134 DCN31_CLK_SRC_PLL4,
135 DCN30_CLK_SRC_TOTAL
136 };
137
138 /* begin *********************
139 * macros to expend register list macro defined in HW object header file
140 */
141
142 /* DCN */
143 /* TODO awful hack. fixup dcn20_dwb.h */
144 #undef BASE_INNER
145 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
146
147 #define BASE(seg) BASE_INNER(seg)
148
149 #define SR(reg_name)\
150 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
151 reg ## reg_name
152
153 #define SRI(reg_name, block, id)\
154 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## reg_name
156
157 #define SRI2(reg_name, block, id)\
158 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
159 reg ## reg_name
160
161 #define SRIR(var_name, reg_name, block, id)\
162 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 reg ## block ## id ## _ ## reg_name
164
165 #define SRII(reg_name, block, id)\
166 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
168
169 #define SRII_MPC_RMU(reg_name, block, id)\
170 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## reg_name
172
173 #define SRII_DWB(reg_name, temp_name, block, id)\
174 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## temp_name
176
177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
178 .field_name = reg_name ## __ ## field_name ## post_fix
179
180 #define DCCG_SRII(reg_name, block, id)\
181 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## reg_name
183
184 #define VUPDATE_SRII(reg_name, block, id)\
185 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
186 reg ## reg_name ## _ ## block ## id
187
188 /* NBIO */
189 #define NBIO_BASE_INNER(seg) \
190 NBIO_BASE__INST0_SEG ## seg
191
192 #define NBIO_BASE(seg) \
193 NBIO_BASE_INNER(seg)
194
195 #define NBIO_SR(reg_name)\
196 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
197 regBIF_BX2_ ## reg_name
198
199 /* MMHUB */
200 #define MMHUB_BASE_INNER(seg) \
201 MMHUB_BASE__INST0_SEG ## seg
202
203 #define MMHUB_BASE(seg) \
204 MMHUB_BASE_INNER(seg)
205
206 #define MMHUB_SR(reg_name)\
207 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
208 reg ## reg_name
209
210 /* CLOCK */
211 #define CLK_BASE_INNER(seg) \
212 CLK_BASE__INST0_SEG ## seg
213
214 #define CLK_BASE(seg) \
215 CLK_BASE_INNER(seg)
216
217 #define CLK_SRI(reg_name, block, inst)\
218 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
219 reg ## block ## _ ## inst ## _ ## reg_name
220
221
222 static const struct bios_registers bios_regs = {
223 NBIO_SR(BIOS_SCRATCH_3),
224 NBIO_SR(BIOS_SCRATCH_6)
225 };
226
227 #define clk_src_regs(index, pllid)\
228 [index] = {\
229 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
230 }
231
232 static const struct dce110_clk_src_regs clk_src_regs[] = {
233 clk_src_regs(0, A),
234 clk_src_regs(1, B),
235 clk_src_regs(2, C),
236 clk_src_regs(3, D),
237 clk_src_regs(4, E)
238 };
239
240 static const struct dce110_clk_src_shift cs_shift = {
241 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
242 };
243
244 static const struct dce110_clk_src_mask cs_mask = {
245 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
246 };
247
248 #define abm_regs(id)\
249 [id] = {\
250 ABM_DCN302_REG_LIST(id)\
251 }
252
253 static const struct dce_abm_registers abm_regs[] = {
254 abm_regs(0),
255 abm_regs(1),
256 abm_regs(2),
257 abm_regs(3),
258 };
259
260 static const struct dce_abm_shift abm_shift = {
261 ABM_MASK_SH_LIST_DCN30(__SHIFT)
262 };
263
264 static const struct dce_abm_mask abm_mask = {
265 ABM_MASK_SH_LIST_DCN30(_MASK)
266 };
267
268 #define audio_regs(id)\
269 [id] = {\
270 AUD_COMMON_REG_LIST(id)\
271 }
272
273 static const struct dce_audio_registers audio_regs[] = {
274 audio_regs(0),
275 audio_regs(1),
276 audio_regs(2),
277 audio_regs(3),
278 audio_regs(4),
279 audio_regs(5),
280 audio_regs(6)
281 };
282
283 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
284 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
285 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
286 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
287
288 static const struct dce_audio_shift audio_shift = {
289 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
290 };
291
292 static const struct dce_audio_mask audio_mask = {
293 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
294 };
295
296 #define vpg_regs(id)\
297 [id] = {\
298 VPG_DCN31_REG_LIST(id)\
299 }
300
301 static const struct dcn31_vpg_registers vpg_regs[] = {
302 vpg_regs(0),
303 vpg_regs(1),
304 vpg_regs(2),
305 vpg_regs(3),
306 vpg_regs(4),
307 vpg_regs(5),
308 vpg_regs(6),
309 vpg_regs(7),
310 vpg_regs(8),
311 vpg_regs(9),
312 };
313
314 static const struct dcn31_vpg_shift vpg_shift = {
315 DCN31_VPG_MASK_SH_LIST(__SHIFT)
316 };
317
318 static const struct dcn31_vpg_mask vpg_mask = {
319 DCN31_VPG_MASK_SH_LIST(_MASK)
320 };
321
322 #define afmt_regs(id)\
323 [id] = {\
324 AFMT_DCN31_REG_LIST(id)\
325 }
326
327 static const struct dcn31_afmt_registers afmt_regs[] = {
328 afmt_regs(0),
329 afmt_regs(1),
330 afmt_regs(2),
331 afmt_regs(3),
332 afmt_regs(4),
333 afmt_regs(5)
334 };
335
336 static const struct dcn31_afmt_shift afmt_shift = {
337 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
338 };
339
340 static const struct dcn31_afmt_mask afmt_mask = {
341 DCN31_AFMT_MASK_SH_LIST(_MASK)
342 };
343
344 #define apg_regs(id)\
345 [id] = {\
346 APG_DCN31_REG_LIST(id)\
347 }
348
349 static const struct dcn31_apg_registers apg_regs[] = {
350 apg_regs(0),
351 apg_regs(1),
352 apg_regs(2),
353 apg_regs(3)
354 };
355
356 static const struct dcn31_apg_shift apg_shift = {
357 DCN31_APG_MASK_SH_LIST(__SHIFT)
358 };
359
360 static const struct dcn31_apg_mask apg_mask = {
361 DCN31_APG_MASK_SH_LIST(_MASK)
362 };
363
364 #define stream_enc_regs(id)\
365 [id] = {\
366 SE_DCN314_REG_LIST(id)\
367 }
368
369 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
370 stream_enc_regs(0),
371 stream_enc_regs(1),
372 stream_enc_regs(2),
373 stream_enc_regs(3),
374 stream_enc_regs(4)
375 };
376
377 static const struct dcn10_stream_encoder_shift se_shift = {
378 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
379 };
380
381 static const struct dcn10_stream_encoder_mask se_mask = {
382 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
383 };
384
385
386 #define aux_regs(id)\
387 [id] = {\
388 DCN2_AUX_REG_LIST(id)\
389 }
390
391 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
392 aux_regs(0),
393 aux_regs(1),
394 aux_regs(2),
395 aux_regs(3),
396 aux_regs(4)
397 };
398
399 #define hpd_regs(id)\
400 [id] = {\
401 HPD_REG_LIST(id)\
402 }
403
404 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
405 hpd_regs(0),
406 hpd_regs(1),
407 hpd_regs(2),
408 hpd_regs(3),
409 hpd_regs(4)
410 };
411
412 #define link_regs(id, phyid)\
413 [id] = {\
414 LE_DCN31_REG_LIST(id), \
415 UNIPHY_DCN2_REG_LIST(phyid), \
416 }
417
418 static const struct dce110_aux_registers_shift aux_shift = {
419 DCN_AUX_MASK_SH_LIST(__SHIFT)
420 };
421
422 static const struct dce110_aux_registers_mask aux_mask = {
423 DCN_AUX_MASK_SH_LIST(_MASK)
424 };
425
426 static const struct dcn10_link_enc_registers link_enc_regs[] = {
427 link_regs(0, A),
428 link_regs(1, B),
429 link_regs(2, C),
430 link_regs(3, D),
431 link_regs(4, E)
432 };
433
434 static const struct dcn10_link_enc_shift le_shift = {
435 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
436 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
437 };
438
439 static const struct dcn10_link_enc_mask le_mask = {
440 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
441 DPCS_DCN31_MASK_SH_LIST(_MASK)
442 };
443
444 #define hpo_frl_stream_encoder_reg_list(id)\
445 [id] = {\
446 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST(id)\
447 }
448
449 #define hpo_frl_stream_encoder_dme_reg_list(id)\
450 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST(id, 6)
451
452
453 static const struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[] = {
454 hpo_frl_stream_encoder_reg_list(0),
455 hpo_frl_stream_encoder_dme_reg_list(6),
456 };
457
458 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
459 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
460 };
461
462 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
463 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
464 };
465
466 #define hpo_frl_link_encoder_reg_list(id)\
467 [id] = {\
468 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST(id)\
469 }
470
471 static const struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[] = {
472 hpo_frl_link_encoder_reg_list(0),
473 };
474
475 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
476 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
477 };
478
479 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
480 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
481 };
482
483 #define hpo_dp_stream_encoder_reg_list(id)\
484 [id] = {\
485 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
486 }
487
488 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
489 hpo_dp_stream_encoder_reg_list(0),
490 hpo_dp_stream_encoder_reg_list(1),
491 hpo_dp_stream_encoder_reg_list(2),
492 hpo_dp_stream_encoder_reg_list(3)
493 };
494
495 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
496 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
497 };
498
499 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
500 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
501 };
502
503
504 #define hpo_dp_link_encoder_reg_list(id)\
505 [id] = {\
506 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
507 DCN3_1_RDPCSTX_REG_LIST(0),\
508 DCN3_1_RDPCSTX_REG_LIST(1),\
509 DCN3_1_RDPCSTX_REG_LIST(2),\
510 }
511
512 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
513 hpo_dp_link_encoder_reg_list(0),
514 hpo_dp_link_encoder_reg_list(1),
515 };
516
517 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
518 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
519 };
520
521 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
522 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
523 };
524
525 #define dpp_regs(id)\
526 [id] = {\
527 DPP_REG_LIST_DCN30(id),\
528 }
529
530 static const struct dcn3_dpp_registers dpp_regs[] = {
531 dpp_regs(0),
532 dpp_regs(1),
533 dpp_regs(2),
534 dpp_regs(3)
535 };
536
537 static const struct dcn3_dpp_shift tf_shift = {
538 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
539 };
540
541 static const struct dcn3_dpp_mask tf_mask = {
542 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
543 };
544
545 #define opp_regs(id)\
546 [id] = {\
547 OPP_REG_LIST_DCN30(id),\
548 }
549
550 static const struct dcn20_opp_registers opp_regs[] = {
551 opp_regs(0),
552 opp_regs(1),
553 opp_regs(2),
554 opp_regs(3)
555 };
556
557 static const struct dcn20_opp_shift opp_shift = {
558 OPP_MASK_SH_LIST_DCN20(__SHIFT)
559 };
560
561 static const struct dcn20_opp_mask opp_mask = {
562 OPP_MASK_SH_LIST_DCN20(_MASK)
563 };
564
565 #define aux_engine_regs(id)\
566 [id] = {\
567 AUX_COMMON_REG_LIST0(id), \
568 .AUXN_IMPCAL = 0, \
569 .AUXP_IMPCAL = 0, \
570 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
571 }
572
573 static const struct dce110_aux_registers aux_engine_regs[] = {
574 aux_engine_regs(0),
575 aux_engine_regs(1),
576 aux_engine_regs(2),
577 aux_engine_regs(3),
578 aux_engine_regs(4)
579 };
580
581 #define dwbc_regs_dcn3(id)\
582 [id] = {\
583 DWBC_COMMON_REG_LIST_DCN30(id),\
584 }
585
586 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
587 dwbc_regs_dcn3(0),
588 };
589
590 static const struct dcn30_dwbc_shift dwbc30_shift = {
591 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
592 };
593
594 static const struct dcn30_dwbc_mask dwbc30_mask = {
595 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
596 };
597
598 #define mcif_wb_regs_dcn3(id)\
599 [id] = {\
600 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
601 }
602
603 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
604 mcif_wb_regs_dcn3(0)
605 };
606
607 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
608 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
609 };
610
611 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
612 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
613 };
614
615 #define dsc_regsDCN314(id)\
616 [id] = {\
617 DSC_REG_LIST_DCN20(id)\
618 }
619
620 static const struct dcn20_dsc_registers dsc_regs[] = {
621 dsc_regsDCN314(0),
622 dsc_regsDCN314(1),
623 dsc_regsDCN314(2),
624 dsc_regsDCN314(3)
625 };
626
627 static const struct dcn20_dsc_shift dsc_shift = {
628 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
629 };
630
631 static const struct dcn20_dsc_mask dsc_mask = {
632 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
633 };
634
635 static const struct dcn30_mpc_registers mpc_regs = {
636 MPC_REG_LIST_DCN3_0(0),
637 MPC_REG_LIST_DCN3_0(1),
638 MPC_REG_LIST_DCN3_0(2),
639 MPC_REG_LIST_DCN3_0(3),
640 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
641 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
642 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
643 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
644 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
645 MPC_RMU_REG_LIST_DCN3AG(0),
646 MPC_RMU_REG_LIST_DCN3AG(1),
647 //MPC_RMU_REG_LIST_DCN3AG(2),
648 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
649 };
650
651 static const struct dcn30_mpc_shift mpc_shift = {
652 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
653 };
654
655 static const struct dcn30_mpc_mask mpc_mask = {
656 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
657 };
658
659 #define optc_regs(id)\
660 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
661
662 static const struct dcn_optc_registers optc_regs[] = {
663 optc_regs(0),
664 optc_regs(1),
665 optc_regs(2),
666 optc_regs(3)
667 };
668
669 static const struct dcn_optc_shift optc_shift = {
670 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
671 };
672
673 static const struct dcn_optc_mask optc_mask = {
674 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
675 };
676
677 #define hubp_regs(id)\
678 [id] = {\
679 HUBP_REG_LIST_DCN30(id)\
680 }
681
682 static const struct dcn_hubp2_registers hubp_regs[] = {
683 hubp_regs(0),
684 hubp_regs(1),
685 hubp_regs(2),
686 hubp_regs(3)
687 };
688
689
690 static const struct dcn_hubp2_shift hubp_shift = {
691 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
692 };
693
694 static const struct dcn_hubp2_mask hubp_mask = {
695 HUBP_MASK_SH_LIST_DCN31(_MASK)
696 };
697 static const struct dcn_hubbub_registers hubbub_reg = {
698 HUBBUB_REG_LIST_DCN31(0)
699 };
700
701 static const struct dcn_hubbub_shift hubbub_shift = {
702 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
703 };
704
705 static const struct dcn_hubbub_mask hubbub_mask = {
706 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
707 };
708
709 static const struct dccg_registers dccg_regs = {
710 DCCG_REG_LIST_DCN314()
711 };
712
713 static const struct dccg_shift dccg_shift = {
714 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
715 };
716
717 static const struct dccg_mask dccg_mask = {
718 DCCG_MASK_SH_LIST_DCN314(_MASK)
719 };
720
721
722 #define SRII2(reg_name_pre, reg_name_post, id)\
723 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
724 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
725 reg ## reg_name_pre ## id ## _ ## reg_name_post
726
727
728 #define HWSEQ_DCN31_REG_LIST()\
729 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
730 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
731 SR(DIO_MEM_PWR_CTRL), \
732 SR(ODM_MEM_PWR_CTRL3), \
733 SR(DMU_MEM_PWR_CNTL), \
734 SR(MMHUBBUB_MEM_PWR_CNTL), \
735 SR(DCCG_GATE_DISABLE_CNTL), \
736 SR(DCCG_GATE_DISABLE_CNTL2), \
737 SR(DCFCLK_CNTL),\
738 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
739 SRII(PIXEL_RATE_CNTL, OTG, 0), \
740 SRII(PIXEL_RATE_CNTL, OTG, 1),\
741 SRII(PIXEL_RATE_CNTL, OTG, 2),\
742 SRII(PIXEL_RATE_CNTL, OTG, 3),\
743 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
744 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
745 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
746 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
747 SR(MICROSECOND_TIME_BASE_DIV), \
748 SR(MILLISECOND_TIME_BASE_DIV), \
749 SR(DISPCLK_FREQ_CHANGE_CNTL), \
750 SR(RBBMIF_TIMEOUT_DIS), \
751 SR(RBBMIF_TIMEOUT_DIS_2), \
752 SR(DCHUBBUB_CRC_CTRL), \
753 SR(DPP_TOP0_DPP_CRC_CTRL), \
754 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
755 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
756 SR(MPC_CRC_CTRL), \
757 SR(MPC_CRC_RESULT_GB), \
758 SR(MPC_CRC_RESULT_C), \
759 SR(MPC_CRC_RESULT_AR), \
760 SR(DOMAIN0_PG_CONFIG), \
761 SR(DOMAIN1_PG_CONFIG), \
762 SR(DOMAIN2_PG_CONFIG), \
763 SR(DOMAIN3_PG_CONFIG), \
764 SR(DOMAIN16_PG_CONFIG), \
765 SR(DOMAIN17_PG_CONFIG), \
766 SR(DOMAIN18_PG_CONFIG), \
767 SR(DOMAIN19_PG_CONFIG), \
768 SR(DOMAIN0_PG_STATUS), \
769 SR(DOMAIN1_PG_STATUS), \
770 SR(DOMAIN2_PG_STATUS), \
771 SR(DOMAIN3_PG_STATUS), \
772 SR(DOMAIN16_PG_STATUS), \
773 SR(DOMAIN17_PG_STATUS), \
774 SR(DOMAIN18_PG_STATUS), \
775 SR(DOMAIN19_PG_STATUS), \
776 SR(D1VGA_CONTROL), \
777 SR(D2VGA_CONTROL), \
778 SR(D3VGA_CONTROL), \
779 SR(D4VGA_CONTROL), \
780 SR(D5VGA_CONTROL), \
781 SR(D6VGA_CONTROL), \
782 SR(DC_IP_REQUEST_CNTL), \
783 SR(AZALIA_AUDIO_DTO), \
784 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
785 SR(HPO_TOP_HW_CONTROL)
786
787 static const struct dce_hwseq_registers hwseq_reg = {
788 HWSEQ_DCN31_REG_LIST()
789 };
790
791 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
792 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
793 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
794 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
795 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
796 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
797 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
798 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
799 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
800 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
801 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
802 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
803 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
804 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
805 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
806 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
807 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
808 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
809 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
810 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
811 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
812 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
813 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
814 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
815 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
816 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
817 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
818 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
819 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
820 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
821 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
822 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
823 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
824 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
825 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
826 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
827 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
828
829 static const struct dce_hwseq_shift hwseq_shift = {
830 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
831 };
832
833 static const struct dce_hwseq_mask hwseq_mask = {
834 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
835 };
836 #define vmid_regs(id)\
837 [id] = {\
838 DCN20_VMID_REG_LIST(id)\
839 }
840
841 static const struct dcn_vmid_registers vmid_regs[] = {
842 vmid_regs(0),
843 vmid_regs(1),
844 vmid_regs(2),
845 vmid_regs(3),
846 vmid_regs(4),
847 vmid_regs(5),
848 vmid_regs(6),
849 vmid_regs(7),
850 vmid_regs(8),
851 vmid_regs(9),
852 vmid_regs(10),
853 vmid_regs(11),
854 vmid_regs(12),
855 vmid_regs(13),
856 vmid_regs(14),
857 vmid_regs(15)
858 };
859
860 static const struct dcn20_vmid_shift vmid_shifts = {
861 DCN20_VMID_MASK_SH_LIST(__SHIFT)
862 };
863
864 static const struct dcn20_vmid_mask vmid_masks = {
865 DCN20_VMID_MASK_SH_LIST(_MASK)
866 };
867
868 static const struct dcn_dio_registers dio_regs = {
869 DIO_REG_LIST_DCN10()
870 };
871
872 #define DIO_MASK_SH_LIST(mask_sh)\
873 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
874
875 static const struct dcn_dio_shift dio_shift = {
876 DIO_MASK_SH_LIST(__SHIFT)
877 };
878
879 static const struct dcn_dio_mask dio_mask = {
880 DIO_MASK_SH_LIST(_MASK)
881 };
882
883 static const struct resource_caps res_cap_dcn314 = {
884 .num_timing_generator = 4,
885 .num_opp = 4,
886 .num_video_plane = 4,
887 .num_audio = 5,
888 .num_stream_encoder = 5,
889 .num_dig_link_enc = 5,
890 .num_hpo_frl = 1,
891 .num_hpo_dp_stream_encoder = 4,
892 .num_hpo_dp_link_encoder = 2,
893 .num_pll = 5,
894 .num_dwb = 1,
895 .num_ddc = 5,
896 .num_vmid = 16,
897 .num_mpc_3dlut = 2,
898 .num_dsc = 4,
899 };
900
901 static const struct dc_plane_cap plane_cap = {
902 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
903 .per_pixel_alpha = true,
904
905 .pixel_format_support = {
906 .argb8888 = true,
907 .nv12 = true,
908 .fp16 = true,
909 .p010 = true,
910 .ayuv = false,
911 },
912
913 .max_upscale_factor = {
914 .argb8888 = 16000,
915 .nv12 = 16000,
916 .fp16 = 16000
917 },
918
919 // 6:1 downscaling ratio: 1000/6 = 166.666
920 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
921 .max_downscale_factor = {
922 .argb8888 = 250,
923 .nv12 = 167,
924 .fp16 = 167
925 },
926 64,
927 64
928 };
929
930 static const struct dc_debug_options debug_defaults_drv = {
931 .limit_ffe = 3,
932 .disable_z10 = false,
933 .enable_z9_disable_interface = true,
934 .minimum_z8_residency_time = 2100,
935 .psr_skip_crtc_disable = true,
936 .replay_skip_crtc_disabled = true,
937 .disable_dmcu = true,
938 .force_abm_enable = false,
939 .clock_trace = true,
940 .disable_dpp_power_gate = false,
941 .disable_hubp_power_gate = false,
942 .disable_pplib_clock_request = false,
943 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
944 .force_single_disp_pipe_split = false,
945 .disable_dcc = DCC_ENABLE,
946 .vsr_support = true,
947 .performance_trace = false,
948 .max_downscale_src_width = 4096,/*upto true 4k*/
949 .disable_pplib_wm_range = false,
950 .scl_reset_length10 = true,
951 .sanity_checks = false,
952 .underflow_assert_delay_us = 0xFFFFFFFF,
953 .dwb_fi_phase = -1, // -1 = disable,
954 .dmub_command_table = true,
955 .pstate_enabled = true,
956 .use_max_lb = true,
957 .enable_mem_low_power = {
958 .bits = {
959 .vga = true,
960 .i2c = true,
961 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
962 .dscl = true,
963 .cm = true,
964 .mpc = true,
965 .optc = true,
966 .vpg = true,
967 .afmt = true,
968 }
969 },
970
971 .root_clock_optimization = {
972 .bits = {
973 .dpp = true,
974 .dsc = true,
975 .hdmistream = true,
976 .hdmichar = true,
977 .dpstream = true,
978 .symclk32_se = false,
979 .symclk32_le = true,
980 .symclk_fe = true,
981 .physymclk = true,
982 .dpiasymclk = true,
983 }
984 },
985
986 .seamless_boot_odm_combine = true,
987 .using_dml2 = false,
988 .disable_dsc_power_gate = true,
989 .min_disp_clk_khz = 100000,
990 };
991
992 static const struct dc_check_config config_defaults = {
993 .enable_legacy_fast_update = true,
994 };
995
996 static const struct dc_panel_config panel_config_defaults = {
997 .psr = {
998 .disable_psr = false,
999 .disallow_psrsu = false,
1000 .disallow_replay = false,
1001 },
1002 .ilr = {
1003 .optimize_edp_link_rate = true,
1004 },
1005 };
1006
dcn31_dpp_destroy(struct dpp ** dpp)1007 static void dcn31_dpp_destroy(struct dpp **dpp)
1008 {
1009 kfree(TO_DCN20_DPP(*dpp));
1010 *dpp = NULL;
1011 }
1012
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)1013 static struct dpp *dcn31_dpp_create(
1014 struct dc_context *ctx,
1015 uint32_t inst)
1016 {
1017 struct dcn3_dpp *dpp =
1018 kzalloc_obj(struct dcn3_dpp);
1019
1020 if (!dpp)
1021 return NULL;
1022
1023 if (dpp3_construct(dpp, ctx, inst,
1024 &dpp_regs[inst], &tf_shift, &tf_mask))
1025 return &dpp->base;
1026
1027 BREAK_TO_DEBUGGER();
1028 kfree(dpp);
1029 return NULL;
1030 }
1031
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)1032 static struct output_pixel_processor *dcn31_opp_create(
1033 struct dc_context *ctx, uint32_t inst)
1034 {
1035 struct dcn20_opp *opp =
1036 kzalloc_obj(struct dcn20_opp);
1037
1038 if (!opp) {
1039 BREAK_TO_DEBUGGER();
1040 return NULL;
1041 }
1042
1043 dcn20_opp_construct(opp, ctx, inst,
1044 &opp_regs[inst], &opp_shift, &opp_mask);
1045 return &opp->base;
1046 }
1047
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1048 static struct dce_aux *dcn31_aux_engine_create(
1049 struct dc_context *ctx,
1050 uint32_t inst)
1051 {
1052 struct aux_engine_dce110 *aux_engine =
1053 kzalloc_obj(struct aux_engine_dce110);
1054
1055 if (!aux_engine)
1056 return NULL;
1057
1058 dce110_aux_engine_construct(aux_engine, ctx, inst,
1059 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1060 &aux_engine_regs[inst],
1061 &aux_mask,
1062 &aux_shift,
1063 ctx->dc->caps.extended_aux_timeout_support);
1064
1065 return &aux_engine->base;
1066 }
1067 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1068
1069 static const struct dce_i2c_registers i2c_hw_regs[] = {
1070 i2c_inst_regs(1),
1071 i2c_inst_regs(2),
1072 i2c_inst_regs(3),
1073 i2c_inst_regs(4),
1074 i2c_inst_regs(5),
1075 };
1076
1077 static const struct dce_i2c_shift i2c_shifts = {
1078 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1079 };
1080
1081 static const struct dce_i2c_mask i2c_masks = {
1082 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1083 };
1084
1085 /* ========================================================== */
1086
1087 /*
1088 * DPIA index | Preferred Encoder | Host Router
1089 * 0 | C | 0
1090 * 1 | First Available | 0
1091 * 2 | D | 1
1092 * 3 | First Available | 1
1093 */
1094 /* ========================================================== */
1095 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1096 ENGINE_ID_DIGC,
1097 ENGINE_ID_DIGC,
1098 ENGINE_ID_DIGD,
1099 ENGINE_ID_DIGD
1100 };
1101
dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)1102 static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1103 {
1104 return dpia_to_preferred_enc_id_table[dpia_index];
1105 }
1106
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1107 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1108 struct dc_context *ctx,
1109 uint32_t inst)
1110 {
1111 struct dce_i2c_hw *dce_i2c_hw =
1112 kzalloc_obj(struct dce_i2c_hw);
1113
1114 if (!dce_i2c_hw)
1115 return NULL;
1116
1117 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1118 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1119
1120 return dce_i2c_hw;
1121 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1122 static struct mpc *dcn31_mpc_create(
1123 struct dc_context *ctx,
1124 int num_mpcc,
1125 int num_rmu)
1126 {
1127 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1128
1129 if (!mpc30)
1130 return NULL;
1131
1132 dcn30_mpc_construct(mpc30, ctx,
1133 &mpc_regs,
1134 &mpc_shift,
1135 &mpc_mask,
1136 num_mpcc,
1137 num_rmu);
1138
1139 return &mpc30->base;
1140 }
1141
dcn314_dio_create(struct dc_context * ctx)1142 static struct dio *dcn314_dio_create(struct dc_context *ctx)
1143 {
1144 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1145
1146 if (!dio10)
1147 return NULL;
1148
1149 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1150
1151 return &dio10->base;
1152 }
1153
dcn31_hubbub_create(struct dc_context * ctx)1154 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1155 {
1156 int i;
1157
1158 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1159
1160 if (!hubbub3)
1161 return NULL;
1162
1163 hubbub31_construct(hubbub3, ctx,
1164 &hubbub_reg,
1165 &hubbub_shift,
1166 &hubbub_mask,
1167 dcn3_14_ip.det_buffer_size_kbytes,
1168 dcn3_14_ip.pixel_chunk_size_kbytes,
1169 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1170
1171
1172 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1173 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1174
1175 vmid->ctx = ctx;
1176
1177 vmid->regs = &vmid_regs[i];
1178 vmid->shifts = &vmid_shifts;
1179 vmid->masks = &vmid_masks;
1180 }
1181
1182 return &hubbub3->base;
1183 }
1184
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1185 static struct timing_generator *dcn31_timing_generator_create(
1186 struct dc_context *ctx,
1187 uint32_t instance)
1188 {
1189 struct optc *tgn10 =
1190 kzalloc_obj(struct optc);
1191
1192 if (!tgn10)
1193 return NULL;
1194
1195 tgn10->base.inst = instance;
1196 tgn10->base.ctx = ctx;
1197
1198 tgn10->tg_regs = &optc_regs[instance];
1199 tgn10->tg_shift = &optc_shift;
1200 tgn10->tg_mask = &optc_mask;
1201
1202 dcn314_timing_generator_init(tgn10);
1203
1204 return &tgn10->base;
1205 }
1206
1207 static const struct encoder_feature_support link_enc_feature = {
1208 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1209 .max_hdmi_pixel_clock = 600000,
1210 .hdmi_ycbcr420_supported = true,
1211 .dp_ycbcr420_supported = true,
1212 .fec_supported = true,
1213 .flags.bits.IS_HBR2_CAPABLE = true,
1214 .flags.bits.IS_HBR3_CAPABLE = true,
1215 .flags.bits.IS_TPS3_CAPABLE = true,
1216 .flags.bits.IS_TPS4_CAPABLE = true
1217 };
1218
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1219 static struct link_encoder *dcn31_link_encoder_create(
1220 struct dc_context *ctx,
1221 const struct encoder_init_data *enc_init_data)
1222 {
1223 (void)ctx;
1224 struct dcn20_link_encoder *enc20 =
1225 kzalloc_obj(struct dcn20_link_encoder);
1226
1227 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1228 return NULL;
1229
1230 dcn31_link_encoder_construct(enc20,
1231 enc_init_data,
1232 &link_enc_feature,
1233 &link_enc_regs[enc_init_data->transmitter],
1234 &link_enc_aux_regs[enc_init_data->channel - 1],
1235 &link_enc_hpd_regs[enc_init_data->hpd_source],
1236 &le_shift,
1237 &le_mask);
1238
1239 return &enc20->enc10.base;
1240 }
1241
1242 /* Create a minimal link encoder object not associated with a particular
1243 * physical connector.
1244 * resource_funcs.link_enc_create_minimal
1245 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1246 static struct link_encoder *dcn31_link_enc_create_minimal(
1247 struct dc_context *ctx, enum engine_id eng_id)
1248 {
1249 struct dcn20_link_encoder *enc20;
1250
1251 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1252 return NULL;
1253
1254 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1255 if (!enc20)
1256 return NULL;
1257
1258 dcn31_link_encoder_construct_minimal(
1259 enc20,
1260 ctx,
1261 &link_enc_feature,
1262 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1263 &le_shift,
1264 &le_mask,
1265 eng_id);
1266
1267 return &enc20->enc10.base;
1268 }
1269
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1270 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1271 {
1272 struct dcn31_panel_cntl *panel_cntl =
1273 kzalloc_obj(struct dcn31_panel_cntl);
1274
1275 if (!panel_cntl)
1276 return NULL;
1277
1278 dcn31_panel_cntl_construct(panel_cntl, init_data);
1279
1280 return &panel_cntl->base;
1281 }
1282
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1283 static void read_dce_straps(
1284 struct dc_context *ctx,
1285 struct resource_straps *straps)
1286 {
1287 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1288 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1289
1290 }
1291
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1292 static struct audio *dcn31_create_audio(
1293 struct dc_context *ctx, unsigned int inst)
1294 {
1295 return dce_audio_create(ctx, inst,
1296 &audio_regs[inst], &audio_shift, &audio_mask);
1297 }
1298
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1299 static struct vpg *dcn31_vpg_create(
1300 struct dc_context *ctx,
1301 uint32_t inst)
1302 {
1303 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1304
1305 if (!vpg31)
1306 return NULL;
1307
1308 vpg31_construct(vpg31, ctx, inst,
1309 &vpg_regs[inst],
1310 &vpg_shift,
1311 &vpg_mask);
1312
1313 return &vpg31->base;
1314 }
1315
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1316 static struct afmt *dcn31_afmt_create(
1317 struct dc_context *ctx,
1318 uint32_t inst)
1319 {
1320 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1321
1322 if (!afmt31)
1323 return NULL;
1324
1325 afmt31_construct(afmt31, ctx, inst,
1326 &afmt_regs[inst],
1327 &afmt_shift,
1328 &afmt_mask);
1329
1330 // Light sleep by default, no need to power down here
1331
1332 return &afmt31->base;
1333 }
1334
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1335 static struct apg *dcn31_apg_create(
1336 struct dc_context *ctx,
1337 uint32_t inst)
1338 {
1339 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1340
1341 if (!apg31)
1342 return NULL;
1343
1344 apg31_construct(apg31, ctx, inst,
1345 &apg_regs[inst],
1346 &apg_shift,
1347 &apg_mask);
1348
1349 return &apg31->base;
1350 }
1351
dcn314_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1352 static struct stream_encoder *dcn314_stream_encoder_create(
1353 enum engine_id eng_id,
1354 struct dc_context *ctx)
1355 {
1356 struct dcn10_stream_encoder *enc1;
1357 struct vpg *vpg;
1358 struct afmt *afmt;
1359 int vpg_inst;
1360 int afmt_inst;
1361
1362 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1363 if (eng_id < ENGINE_ID_DIGF) {
1364 vpg_inst = eng_id;
1365 afmt_inst = eng_id;
1366 } else
1367 return NULL;
1368
1369 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1370 vpg = dcn31_vpg_create(ctx, vpg_inst);
1371 afmt = dcn31_afmt_create(ctx, afmt_inst);
1372
1373 if (!enc1 || !vpg || !afmt) {
1374 kfree(enc1);
1375 kfree(vpg);
1376 kfree(afmt);
1377 return NULL;
1378 }
1379
1380 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1381 eng_id, vpg, afmt,
1382 &stream_enc_regs[eng_id],
1383 &se_shift, &se_mask);
1384
1385 return &enc1->base;
1386 }
1387
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1388 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,
1389 struct dc_context *ctx)
1390 {
1391 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1392 struct afmt *afmt;
1393 struct vpg *vpg;
1394 int afmt_inst;
1395 int vpg_inst;
1396
1397 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1398 if (eng_id == ENGINE_ID_HPO_0) {
1399 //Maps to VPG INST 5, vpg_inst 5 reg offset padded to inst 9
1400 vpg_inst = 9;
1401 afmt_inst = 5;
1402 } else {
1403 return NULL;
1404 }
1405
1406 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1407 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1408 vpg = dcn31_vpg_create(ctx, vpg_inst);
1409 afmt = dcn31_afmt_create(ctx, afmt_inst);
1410
1411 if (!hpo_enc3 || !vpg || !afmt) {
1412 kfree(hpo_enc3);
1413 kfree(vpg);
1414 kfree(afmt);
1415 return NULL;
1416 }
1417
1418 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3,
1419 ctx,
1420 ctx->dc_bios,
1421 eng_id,
1422 vpg,
1423 afmt,
1424 &hpo_frl_stream_enc_regs[eng_id - ENGINE_ID_HPO_0],
1425 &hpo_se_shift,
1426 &hpo_se_mask);
1427
1428 return &hpo_enc3->base;
1429 }
1430
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1431 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,
1432 struct dc_context *ctx)
1433 {
1434 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1435
1436 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1437
1438 /* allocate HPO link encoder */
1439 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1440 if (!hpo_enc3)
1441 return NULL; /* out of memory */
1442
1443 hpo_frl_link_encoder3_construct(hpo_enc3,
1444 ctx,
1445 eng_id - ENGINE_ID_HPO_0,
1446 &hpo_frl_link_enc_regs[eng_id - ENGINE_ID_HPO_0],
1447 &hpo_le_shift,
1448 &hpo_le_mask);
1449
1450 return &hpo_enc3->base;
1451 }
1452
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1453 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1454 enum engine_id eng_id,
1455 struct dc_context *ctx)
1456 {
1457 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1458 struct vpg *vpg;
1459 struct apg *apg;
1460 uint32_t hpo_dp_inst;
1461 uint32_t vpg_inst;
1462 uint32_t apg_inst;
1463
1464 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1465 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1466
1467 /* Mapping of VPG register blocks to HPO DP block instance:
1468 * VPG[6] -> HPO_DP[0]
1469 * VPG[7] -> HPO_DP[1]
1470 * VPG[8] -> HPO_DP[2]
1471 * VPG[9] -> HPO_DP[3]
1472 */
1473 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1474 vpg_inst = hpo_dp_inst + 5;
1475
1476 /* Mapping of APG register blocks to HPO DP block instance:
1477 * APG[0] -> HPO_DP[0]
1478 * APG[1] -> HPO_DP[1]
1479 * APG[2] -> HPO_DP[2]
1480 * APG[3] -> HPO_DP[3]
1481 */
1482 apg_inst = hpo_dp_inst;
1483
1484 /* allocate HPO stream encoder and create VPG sub-block */
1485 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1486 vpg = dcn31_vpg_create(ctx, vpg_inst);
1487 apg = dcn31_apg_create(ctx, apg_inst);
1488
1489 if (!hpo_dp_enc31 || !vpg || !apg) {
1490 kfree(hpo_dp_enc31);
1491 kfree(vpg);
1492 kfree(apg);
1493 return NULL;
1494 }
1495
1496 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1497 hpo_dp_inst, eng_id, vpg, apg,
1498 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1499 &hpo_dp_se_shift, &hpo_dp_se_mask);
1500
1501 return &hpo_dp_enc31->base;
1502 }
1503
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1504 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1505 uint8_t inst,
1506 struct dc_context *ctx)
1507 {
1508 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1509
1510 /* allocate HPO link encoder */
1511 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1512 if (!hpo_dp_enc31)
1513 return NULL; /* out of memory */
1514
1515 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1516 &hpo_dp_link_enc_regs[inst],
1517 &hpo_dp_le_shift, &hpo_dp_le_mask);
1518
1519 return &hpo_dp_enc31->base;
1520 }
1521
dcn314_hwseq_create(struct dc_context * ctx)1522 static struct dce_hwseq *dcn314_hwseq_create(
1523 struct dc_context *ctx)
1524 {
1525 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1526
1527 if (hws) {
1528 hws->ctx = ctx;
1529 hws->regs = &hwseq_reg;
1530 hws->shifts = &hwseq_shift;
1531 hws->masks = &hwseq_mask;
1532 }
1533 return hws;
1534 }
1535 static const struct resource_create_funcs res_create_funcs = {
1536 .read_dce_straps = read_dce_straps,
1537 .create_audio = dcn31_create_audio,
1538 .create_stream_encoder = dcn314_stream_encoder_create,
1539 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1540 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1541 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1542 .create_hwseq = dcn314_hwseq_create,
1543 };
1544
dcn314_resource_destruct(struct dcn314_resource_pool * pool)1545 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1546 {
1547 unsigned int i;
1548
1549 for (i = 0; i < pool->base.stream_enc_count; i++) {
1550 if (pool->base.stream_enc[i] != NULL) {
1551 if (pool->base.stream_enc[i]->vpg != NULL) {
1552 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1553 pool->base.stream_enc[i]->vpg = NULL;
1554 }
1555 if (pool->base.stream_enc[i]->afmt != NULL) {
1556 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1557 pool->base.stream_enc[i]->afmt = NULL;
1558 }
1559 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1560 pool->base.stream_enc[i] = NULL;
1561 }
1562 }
1563
1564 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1565 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1566 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1567 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1568 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1569 }
1570
1571 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1572 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1573 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1574 }
1575
1576 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1577 pool->base.hpo_frl_stream_enc[i] = NULL;
1578 }
1579 }
1580
1581 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1582 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1583 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1584 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1585 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1586 }
1587 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1588 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1589 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1590 }
1591 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1592 pool->base.hpo_dp_stream_enc[i] = NULL;
1593 }
1594 }
1595
1596 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1597 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1598 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1599 pool->base.hpo_dp_link_enc[i] = NULL;
1600 }
1601 }
1602
1603 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1604 if (pool->base.dscs[i] != NULL)
1605 dcn20_dsc_destroy(&pool->base.dscs[i]);
1606 }
1607
1608 if (pool->base.mpc != NULL) {
1609 kfree(TO_DCN20_MPC(pool->base.mpc));
1610 pool->base.mpc = NULL;
1611 }
1612 if (pool->base.hubbub != NULL) {
1613 kfree(pool->base.hubbub);
1614 pool->base.hubbub = NULL;
1615 }
1616 if (pool->base.dio != NULL) {
1617 kfree(TO_DCN10_DIO(pool->base.dio));
1618 pool->base.dio = NULL;
1619 }
1620 for (i = 0; i < pool->base.pipe_count; i++) {
1621 if (pool->base.dpps[i] != NULL)
1622 dcn31_dpp_destroy(&pool->base.dpps[i]);
1623
1624 if (pool->base.ipps[i] != NULL)
1625 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1626
1627 if (pool->base.hubps[i] != NULL) {
1628 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1629 pool->base.hubps[i] = NULL;
1630 }
1631
1632 if (pool->base.irqs != NULL)
1633 dal_irq_service_destroy(&pool->base.irqs);
1634 }
1635
1636 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1637 if (pool->base.engines[i] != NULL)
1638 dce110_engine_destroy(&pool->base.engines[i]);
1639 if (pool->base.hw_i2cs[i] != NULL) {
1640 kfree(pool->base.hw_i2cs[i]);
1641 pool->base.hw_i2cs[i] = NULL;
1642 }
1643 if (pool->base.sw_i2cs[i] != NULL) {
1644 kfree(pool->base.sw_i2cs[i]);
1645 pool->base.sw_i2cs[i] = NULL;
1646 }
1647 }
1648
1649 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1650 if (pool->base.opps[i] != NULL)
1651 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1652 }
1653
1654 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1655 if (pool->base.timing_generators[i] != NULL) {
1656 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1657 pool->base.timing_generators[i] = NULL;
1658 }
1659 }
1660
1661 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1662 if (pool->base.dwbc[i] != NULL) {
1663 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1664 pool->base.dwbc[i] = NULL;
1665 }
1666 if (pool->base.mcif_wb[i] != NULL) {
1667 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1668 pool->base.mcif_wb[i] = NULL;
1669 }
1670 }
1671
1672 for (i = 0; i < pool->base.audio_count; i++) {
1673 if (pool->base.audios[i])
1674 dce_aud_destroy(&pool->base.audios[i]);
1675 }
1676
1677 for (i = 0; i < pool->base.clk_src_count; i++) {
1678 if (pool->base.clock_sources[i] != NULL) {
1679 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1680 pool->base.clock_sources[i] = NULL;
1681 }
1682 }
1683
1684 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1685 if (pool->base.mpc_lut[i] != NULL) {
1686 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1687 pool->base.mpc_lut[i] = NULL;
1688 }
1689 if (pool->base.mpc_shaper[i] != NULL) {
1690 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1691 pool->base.mpc_shaper[i] = NULL;
1692 }
1693 }
1694
1695 if (pool->base.dp_clock_source != NULL) {
1696 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1697 pool->base.dp_clock_source = NULL;
1698 }
1699
1700 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1701 if (pool->base.multiple_abms[i] != NULL)
1702 dce_abm_destroy(&pool->base.multiple_abms[i]);
1703 }
1704
1705 if (pool->base.psr != NULL)
1706 dmub_psr_destroy(&pool->base.psr);
1707
1708 if (pool->base.replay != NULL)
1709 dmub_replay_destroy(&pool->base.replay);
1710
1711 if (pool->base.dccg != NULL)
1712 dcn_dccg_destroy(&pool->base.dccg);
1713 }
1714
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1715 static struct hubp *dcn31_hubp_create(
1716 struct dc_context *ctx,
1717 uint32_t inst)
1718 {
1719 struct dcn20_hubp *hubp2 =
1720 kzalloc_obj(struct dcn20_hubp);
1721
1722 if (!hubp2)
1723 return NULL;
1724
1725 if (hubp31_construct(hubp2, ctx, inst,
1726 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1727 return &hubp2->base;
1728
1729 BREAK_TO_DEBUGGER();
1730 kfree(hubp2);
1731 return NULL;
1732 }
1733
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1734 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1735 {
1736 unsigned int i;
1737 uint32_t pipe_count = pool->res_cap->num_dwb;
1738
1739 for (i = 0; i < pipe_count; i++) {
1740 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1741
1742 if (!dwbc30) {
1743 dm_error("DC: failed to create dwbc30!\n");
1744 return false;
1745 }
1746
1747 dcn30_dwbc_construct(dwbc30, ctx,
1748 &dwbc30_regs[i],
1749 &dwbc30_shift,
1750 &dwbc30_mask,
1751 i);
1752
1753 pool->dwbc[i] = &dwbc30->base;
1754 }
1755 return true;
1756 }
1757
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1758 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1759 {
1760 unsigned int i;
1761 uint32_t pipe_count = pool->res_cap->num_dwb;
1762
1763 for (i = 0; i < pipe_count; i++) {
1764 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1765
1766 if (!mcif_wb30) {
1767 dm_error("DC: failed to create mcif_wb30!\n");
1768 return false;
1769 }
1770
1771 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1772 &mcif_wb30_regs[i],
1773 &mcif_wb30_shift,
1774 &mcif_wb30_mask,
1775 i);
1776
1777 pool->mcif_wb[i] = &mcif_wb30->base;
1778 }
1779 return true;
1780 }
1781
dcn314_dsc_create(struct dc_context * ctx,uint32_t inst)1782 static struct display_stream_compressor *dcn314_dsc_create(
1783 struct dc_context *ctx, uint32_t inst)
1784 {
1785 struct dcn20_dsc *dsc =
1786 kzalloc_obj(struct dcn20_dsc);
1787
1788 if (!dsc) {
1789 BREAK_TO_DEBUGGER();
1790 return NULL;
1791 }
1792
1793 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1794 return &dsc->base;
1795 }
1796
dcn314_destroy_resource_pool(struct resource_pool ** pool)1797 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1798 {
1799 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1800
1801 dcn314_resource_destruct(dcn314_pool);
1802 kfree(dcn314_pool);
1803 *pool = NULL;
1804 }
1805
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1806 static struct clock_source *dcn31_clock_source_create(
1807 struct dc_context *ctx,
1808 struct dc_bios *bios,
1809 enum clock_source_id id,
1810 const struct dce110_clk_src_regs *regs,
1811 bool dp_clk_src)
1812 {
1813 struct dce110_clk_src *clk_src =
1814 kzalloc_obj(struct dce110_clk_src);
1815
1816 if (!clk_src)
1817 return NULL;
1818
1819 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1820 regs, &cs_shift, &cs_mask)) {
1821 clk_src->base.dp_clk_src = dp_clk_src;
1822 return &clk_src->base;
1823 }
1824
1825 kfree(clk_src);
1826 BREAK_TO_DEBUGGER();
1827 return NULL;
1828 }
1829
dcn314_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1830 static int dcn314_populate_dml_pipes_from_context(
1831 struct dc *dc, struct dc_state *context,
1832 display_e2e_pipe_params_st *pipes,
1833 enum dc_validate_mode validate_mode)
1834 {
1835 int pipe_cnt;
1836
1837 DC_FP_START();
1838 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1839 DC_FP_END();
1840
1841 return pipe_cnt;
1842 }
1843
1844 static struct dc_cap_funcs cap_funcs = {
1845 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1846 };
1847
dcn314_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1848 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1849 {
1850 DC_FP_START();
1851 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1852 DC_FP_END();
1853 }
1854
dcn314_get_panel_config_defaults(struct dc_panel_config * panel_config)1855 static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1856 {
1857 *panel_config = panel_config_defaults;
1858 }
1859
dcn314_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1860 enum dc_status dcn314_validate_bandwidth(struct dc *dc,
1861 struct dc_state *context,
1862 enum dc_validate_mode validate_mode)
1863 {
1864 bool out = false;
1865
1866 BW_VAL_TRACE_SETUP();
1867
1868 int vlevel = 0;
1869 int pipe_cnt = 0;
1870 display_e2e_pipe_params_st *pipes = kzalloc_objs(display_e2e_pipe_params_st,
1871 dc->res_pool->pipe_count);
1872 DC_LOGGER_INIT(dc->ctx->logger);
1873
1874 BW_VAL_TRACE_COUNT();
1875
1876 if (!pipes)
1877 goto validate_fail;
1878
1879 DC_FP_START();
1880 // do not support self refresh only
1881 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);
1882 DC_FP_END();
1883
1884 // Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1885 if (pipe_cnt == 0)
1886 validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1887
1888 if (!out)
1889 goto validate_fail;
1890
1891 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1892
1893 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1894 BW_VAL_TRACE_SKIP(fast);
1895 goto validate_out;
1896 }
1897 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1898 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1899
1900 BW_VAL_TRACE_END_WATERMARKS();
1901
1902 goto validate_out;
1903
1904 validate_fail:
1905 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1906 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1907
1908 BW_VAL_TRACE_SKIP(fail);
1909 out = false;
1910
1911 validate_out:
1912 kfree(pipes);
1913
1914 BW_VAL_TRACE_FINISH();
1915
1916 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1917 }
1918
1919 static struct resource_funcs dcn314_res_pool_funcs = {
1920 .destroy = dcn314_destroy_resource_pool,
1921 .link_enc_create = dcn31_link_encoder_create,
1922 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1923 .link_encs_assign = link_enc_cfg_link_encs_assign,
1924 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1925 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1926 .panel_cntl_create = dcn31_panel_cntl_create,
1927 .validate_bandwidth = dcn314_validate_bandwidth,
1928 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1929 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1930 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1931 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1932 .release_pipe = dcn20_release_pipe,
1933 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1934 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1935 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1936 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1937 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1938 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1939 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1940 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1941 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1942 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1943 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1944 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1945 .get_det_buffer_size = dcn31_get_det_buffer_size,
1946 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1947 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1948 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1949 .get_default_tiling_info = dcn10_get_default_tiling_info
1950 };
1951
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1952 static struct clock_source *dcn30_clock_source_create(
1953 struct dc_context *ctx,
1954 struct dc_bios *bios,
1955 enum clock_source_id id,
1956 const struct dce110_clk_src_regs *regs,
1957 bool dp_clk_src)
1958 {
1959 struct dce110_clk_src *clk_src =
1960 kzalloc_obj(struct dce110_clk_src);
1961
1962 if (!clk_src)
1963 return NULL;
1964
1965 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1966 regs, &cs_shift, &cs_mask)) {
1967 clk_src->base.dp_clk_src = dp_clk_src;
1968 return &clk_src->base;
1969 }
1970
1971 kfree(clk_src);
1972 BREAK_TO_DEBUGGER();
1973 return NULL;
1974 }
1975
dcn314_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn314_resource_pool * pool)1976 static bool dcn314_resource_construct(
1977 uint8_t num_virtual_links,
1978 struct dc *dc,
1979 struct dcn314_resource_pool *pool)
1980 {
1981 int i;
1982 struct dc_context *ctx = dc->ctx;
1983 struct irq_service_init_data init_data;
1984
1985 ctx->dc_bios->regs = &bios_regs;
1986
1987 pool->base.res_cap = &res_cap_dcn314;
1988 pool->base.funcs = &dcn314_res_pool_funcs;
1989
1990 /*************************************************
1991 * Resource + asic cap harcoding *
1992 *************************************************/
1993 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1994 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1995 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1996
1997 /* Enable 4to1MPC by default */
1998 dc->config.allow_4to1MPC = true;
1999 dc->caps.max_downscale_ratio = 400;
2000 dc->caps.i2c_speed_in_khz = 100;
2001 dc->caps.i2c_speed_in_khz_hdcp = 100;
2002 dc->caps.max_cursor_size = 256;
2003 dc->caps.min_horizontal_blanking_period = 80;
2004 dc->caps.dmdata_alloc_size = 2048;
2005 dc->caps.max_slave_planes = 2;
2006 dc->caps.max_slave_yuv_planes = 2;
2007 dc->caps.max_slave_rgb_planes = 2;
2008 dc->caps.post_blend_color_processing = true;
2009 dc->caps.force_dp_tps4_for_cp2520 = true;
2010 if (dc->config.forceHBR2CP2520)
2011 dc->caps.force_dp_tps4_for_cp2520 = false;
2012 dc->caps.hdmi_hpo = true;
2013 dc->caps.dp_hpo = true;
2014 dc->caps.dp_hdmi21_pcon_support = true;
2015 dc->caps.edp_dsc_support = true;
2016 dc->caps.extended_aux_timeout_support = true;
2017 dc->caps.dmcub_support = true;
2018 dc->caps.is_apu = true;
2019 dc->caps.seamless_odm = true;
2020
2021 dc->caps.zstate_support = true;
2022
2023 /* Color pipeline capabilities */
2024 dc->caps.color.dpp.dcn_arch = 1;
2025 dc->caps.color.dpp.input_lut_shared = 0;
2026 dc->caps.color.dpp.icsc = 1;
2027 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2028 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2029 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2030 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2031 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2032 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2033 dc->caps.color.dpp.post_csc = 1;
2034 dc->caps.color.dpp.gamma_corr = 1;
2035 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2036 dc->caps.color.dpp.upsp_pre_scaler = 0;
2037
2038 dc->caps.color.dpp.hw_3d_lut = 1;
2039 dc->caps.color.dpp.ogam_ram = 1;
2040 // no OGAM ROM on DCN301
2041 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2042 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2043 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2044 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2045 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2046 dc->caps.color.dpp.ocsc = 0;
2047
2048 dc->caps.color.mpc.gamut_remap = 1;
2049 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
2050 dc->caps.color.mpc.ogam_ram = 1;
2051 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2052 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2053 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2054 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2055 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2056 dc->caps.color.mpc.ocsc = 1;
2057 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2058
2059 dc->caps.max_disp_clock_khz_at_vmin = 650000;
2060
2061 dc->caps.num_of_host_routers = 2;
2062 dc->caps.num_of_dpias_per_host_router = 2;
2063
2064 /* Use pipe context based otg sync logic */
2065 dc->config.use_pipe_ctx_sync_logic = true;
2066
2067 /* read VBIOS LTTPR caps */
2068 {
2069 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2070 enum bp_result bp_query_result;
2071 uint8_t is_vbios_lttpr_enable = 0;
2072
2073 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2074 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2075 }
2076
2077 /* interop bit is implicit */
2078 {
2079 dc->caps.vbios_lttpr_aware = true;
2080 }
2081 }
2082 dc->check_config = config_defaults;
2083
2084 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2085 dc->debug = debug_defaults_drv;
2086
2087 /* Disable pipe power gating */
2088 dc->debug.disable_dpp_power_gate = true;
2089 dc->debug.disable_hubp_power_gate = true;
2090
2091 /* Disable root clock optimization */
2092 dc->debug.root_clock_optimization.u32All = 0;
2093
2094 // Init the vm_helper
2095 if (dc->vm_helper)
2096 vm_helper_init(dc->vm_helper, 16);
2097
2098 /*************************************************
2099 * Create resources *
2100 *************************************************/
2101
2102 /* Clock Sources for Pixel Clock*/
2103 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2104 dcn30_clock_source_create(ctx, ctx->dc_bios,
2105 CLOCK_SOURCE_COMBO_PHY_PLL0,
2106 &clk_src_regs[0], false);
2107 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2108 dcn30_clock_source_create(ctx, ctx->dc_bios,
2109 CLOCK_SOURCE_COMBO_PHY_PLL1,
2110 &clk_src_regs[1], false);
2111 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2112 dcn30_clock_source_create(ctx, ctx->dc_bios,
2113 CLOCK_SOURCE_COMBO_PHY_PLL2,
2114 &clk_src_regs[2], false);
2115 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2116 dcn30_clock_source_create(ctx, ctx->dc_bios,
2117 CLOCK_SOURCE_COMBO_PHY_PLL3,
2118 &clk_src_regs[3], false);
2119 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2120 dcn30_clock_source_create(ctx, ctx->dc_bios,
2121 CLOCK_SOURCE_COMBO_PHY_PLL4,
2122 &clk_src_regs[4], false);
2123
2124 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2125
2126 /* todo: not reuse phy_pll registers */
2127 pool->base.dp_clock_source =
2128 dcn31_clock_source_create(ctx, ctx->dc_bios,
2129 CLOCK_SOURCE_ID_DP_DTO,
2130 &clk_src_regs[0], true);
2131
2132 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2133 if (pool->base.clock_sources[i] == NULL) {
2134 dm_error("DC: failed to create clock sources!\n");
2135 BREAK_TO_DEBUGGER();
2136 goto create_fail;
2137 }
2138 }
2139
2140 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2141 if (pool->base.dccg == NULL) {
2142 dm_error("DC: failed to create dccg!\n");
2143 BREAK_TO_DEBUGGER();
2144 goto create_fail;
2145 }
2146
2147 init_data.ctx = dc->ctx;
2148 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
2149 if (!pool->base.irqs)
2150 goto create_fail;
2151
2152 /* HUBBUB */
2153 pool->base.hubbub = dcn31_hubbub_create(ctx);
2154 if (pool->base.hubbub == NULL) {
2155 BREAK_TO_DEBUGGER();
2156 dm_error("DC: failed to create hubbub!\n");
2157 goto create_fail;
2158 }
2159
2160 /* DIO */
2161 pool->base.dio = dcn314_dio_create(ctx);
2162 if (pool->base.dio == NULL) {
2163 BREAK_TO_DEBUGGER();
2164 dm_error("DC: failed to create dio!\n");
2165 goto create_fail;
2166 }
2167
2168 /* HUBPs, DPPs, OPPs and TGs */
2169 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2170 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2171 if (pool->base.hubps[i] == NULL) {
2172 BREAK_TO_DEBUGGER();
2173 dm_error(
2174 "DC: failed to create hubps!\n");
2175 goto create_fail;
2176 }
2177
2178 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2179 if (pool->base.dpps[i] == NULL) {
2180 BREAK_TO_DEBUGGER();
2181 dm_error(
2182 "DC: failed to create dpps!\n");
2183 goto create_fail;
2184 }
2185 }
2186
2187 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2188 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2189 if (pool->base.opps[i] == NULL) {
2190 BREAK_TO_DEBUGGER();
2191 dm_error(
2192 "DC: failed to create output pixel processor!\n");
2193 goto create_fail;
2194 }
2195 }
2196
2197 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2198 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2199 ctx, i);
2200 if (pool->base.timing_generators[i] == NULL) {
2201 BREAK_TO_DEBUGGER();
2202 dm_error("DC: failed to create tg!\n");
2203 goto create_fail;
2204 }
2205 }
2206 pool->base.timing_generator_count = i;
2207
2208 /* PSR */
2209 pool->base.psr = dmub_psr_create(ctx);
2210 if (pool->base.psr == NULL) {
2211 dm_error("DC: failed to create psr obj!\n");
2212 BREAK_TO_DEBUGGER();
2213 goto create_fail;
2214 }
2215
2216 /* Replay */
2217 pool->base.replay = dmub_replay_create(ctx);
2218 if (pool->base.replay == NULL) {
2219 dm_error("DC: failed to create replay obj!\n");
2220 BREAK_TO_DEBUGGER();
2221 goto create_fail;
2222 }
2223
2224 /* ABM */
2225 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2226 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2227 &abm_regs[i],
2228 &abm_shift,
2229 &abm_mask);
2230 if (pool->base.multiple_abms[i] == NULL) {
2231 dm_error("DC: failed to create abm for pipe %d!\n", i);
2232 BREAK_TO_DEBUGGER();
2233 goto create_fail;
2234 }
2235 }
2236
2237 /* MPC and DSC */
2238 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2239 if (pool->base.mpc == NULL) {
2240 BREAK_TO_DEBUGGER();
2241 dm_error("DC: failed to create mpc!\n");
2242 goto create_fail;
2243 }
2244
2245 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2246 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2247 if (pool->base.dscs[i] == NULL) {
2248 BREAK_TO_DEBUGGER();
2249 dm_error("DC: failed to create display stream compressor %d!\n", i);
2250 goto create_fail;
2251 }
2252 }
2253
2254 /* DWB and MMHUBBUB */
2255 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2256 BREAK_TO_DEBUGGER();
2257 dm_error("DC: failed to create dwbc!\n");
2258 goto create_fail;
2259 }
2260
2261 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2262 BREAK_TO_DEBUGGER();
2263 dm_error("DC: failed to create mcif_wb!\n");
2264 goto create_fail;
2265 }
2266
2267 /* AUX and I2C */
2268 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2269 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2270 if (pool->base.engines[i] == NULL) {
2271 BREAK_TO_DEBUGGER();
2272 dm_error(
2273 "DC:failed to create aux engine!!\n");
2274 goto create_fail;
2275 }
2276 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2277 if (pool->base.hw_i2cs[i] == NULL) {
2278 BREAK_TO_DEBUGGER();
2279 dm_error(
2280 "DC:failed to create hw i2c!!\n");
2281 goto create_fail;
2282 }
2283 pool->base.sw_i2cs[i] = NULL;
2284 }
2285
2286 /* DCN314 has 4 DPIA */
2287 pool->base.usb4_dpia_count = 4;
2288
2289 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2290 if (!resource_construct(num_virtual_links, dc, &pool->base,
2291 &res_create_funcs))
2292 goto create_fail;
2293
2294 /* HW Sequencer and Plane caps */
2295 dcn314_hw_sequencer_construct(dc);
2296
2297 dc->caps.max_planes = pool->base.pipe_count;
2298
2299 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2300 dc->caps.planes[i] = plane_cap;
2301
2302 dc->caps.max_odm_combine_factor = 4;
2303
2304 dc->cap_funcs = cap_funcs;
2305
2306 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2307
2308 return true;
2309
2310 create_fail:
2311
2312 dcn314_resource_destruct(pool);
2313
2314 return false;
2315 }
2316
dcn314_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2317 struct resource_pool *dcn314_create_resource_pool(
2318 const struct dc_init_data *init_data,
2319 struct dc *dc)
2320 {
2321 struct dcn314_resource_pool *pool =
2322 kzalloc_obj(struct dcn314_resource_pool);
2323
2324 if (!pool)
2325 return NULL;
2326
2327 if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2328 return &pool->base;
2329
2330 BREAK_TO_DEBUGGER();
2331 kfree(pool);
2332 return NULL;
2333 }
2334