1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn30_hwseq.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30/dcn30_mpc.h"
35 #include "dcn30/dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30/dcn30_cm_common.h"
38 #include "reg_helper.h"
39 #include "abm.h"
40 #include "clk_mgr.h"
41 #include "hubp.h"
42 #include "dchubbub.h"
43 #include "timing_generator.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "mpc.h"
47 #include "mcif_wb.h"
48 #include "dc_dmub_srv.h"
49 #include "link_hwss.h"
50 #include "dpcd_defs.h"
51 #include "dcn20/dcn20_hwseq.h"
52 #include "dcn30/dcn30_resource.h"
53 #include "link.h"
54 #include "dc_state_priv.h"
55
56
57
58 #define DC_LOGGER_INIT(logger)
59
60 #define CTX \
61 hws->ctx
62 #define REG(reg)\
63 hws->regs->reg
64 #define DC_LOGGER \
65 dc->ctx->logger
66
67
68 #undef FN
69 #define FN(reg_name, field_name) \
70 hws->shifts->field_name, hws->masks->field_name
71
dcn30_log_color_state(struct dc * dc,struct dc_log_buffer_ctx * log_ctx)72 void dcn30_log_color_state(struct dc *dc,
73 struct dc_log_buffer_ctx *log_ctx)
74 {
75 struct dc_context *dc_ctx = dc->ctx;
76 struct resource_pool *pool = dc->res_pool;
77 int i;
78
79 DTN_INFO("DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode"
80 " 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode"
81 " GAMUT adjust "
82 "C11 C12 C13 C14 "
83 "C21 C22 C23 C24 "
84 "C31 C32 C33 C34 \n");
85
86 for (i = 0; i < pool->pipe_count; i++) {
87 struct dpp *dpp = pool->dpps[i];
88 struct dcn_dpp_state s = {0};
89
90 dpp->funcs->dpp_read_state(dpp, &s);
91 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
92
93 if (!s.is_enabled)
94 continue;
95
96 DTN_INFO("[%2d]: %7x %13s %8s %11s %10s %15s %10s %9s"
97 " %12s "
98 "%010lld %010lld %010lld %010lld "
99 "%010lld %010lld %010lld %010lld "
100 "%010lld %010lld %010lld %010lld",
101 dpp->inst,
102 s.pre_dgam_mode,
103 (s.pre_dgam_select == 0) ? "sRGB" :
104 ((s.pre_dgam_select == 1) ? "Gamma 2.2" :
105 ((s.pre_dgam_select == 2) ? "Gamma 2.4" :
106 ((s.pre_dgam_select == 3) ? "Gamma 2.6" :
107 ((s.pre_dgam_select == 4) ? "BT.709" :
108 ((s.pre_dgam_select == 5) ? "PQ" :
109 ((s.pre_dgam_select == 6) ? "HLG" :
110 "Unknown")))))),
111 (s.gamcor_mode == 0) ? "Bypass" :
112 ((s.gamcor_mode == 1) ? "RAM A" :
113 "RAM B"),
114 (s.shaper_lut_mode == 1) ? "RAM A" :
115 ((s.shaper_lut_mode == 2) ? "RAM B" :
116 "Bypass"),
117 (s.lut3d_mode == 1) ? "RAM A" :
118 ((s.lut3d_mode == 2) ? "RAM B" :
119 "Bypass"),
120 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
121 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
122 (s.rgam_lut_mode == 0) ? "Bypass" :
123 ((s.rgam_lut_mode == 1) ? "RAM A" :
124 "RAM B"),
125 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
126 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
127 "SW"),
128 s.gamut_remap.temperature_matrix[0].value,
129 s.gamut_remap.temperature_matrix[1].value,
130 s.gamut_remap.temperature_matrix[2].value,
131 s.gamut_remap.temperature_matrix[3].value,
132 s.gamut_remap.temperature_matrix[4].value,
133 s.gamut_remap.temperature_matrix[5].value,
134 s.gamut_remap.temperature_matrix[6].value,
135 s.gamut_remap.temperature_matrix[7].value,
136 s.gamut_remap.temperature_matrix[8].value,
137 s.gamut_remap.temperature_matrix[9].value,
138 s.gamut_remap.temperature_matrix[10].value,
139 s.gamut_remap.temperature_matrix[11].value);
140 DTN_INFO("\n");
141 }
142 DTN_INFO("\n");
143 DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
144 " dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
145 " post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
146 " blnd_lut:%d oscs:%d\n\n",
147 dc->caps.color.dpp.input_lut_shared,
148 dc->caps.color.dpp.icsc,
149 dc->caps.color.dpp.dgam_ram,
150 dc->caps.color.dpp.dgam_rom_caps.srgb,
151 dc->caps.color.dpp.dgam_rom_caps.bt2020,
152 dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
153 dc->caps.color.dpp.dgam_rom_caps.pq,
154 dc->caps.color.dpp.dgam_rom_caps.hlg,
155 dc->caps.color.dpp.post_csc,
156 dc->caps.color.dpp.gamma_corr,
157 dc->caps.color.dpp.dgam_rom_for_yuv,
158 dc->caps.color.dpp.hw_3d_lut,
159 dc->caps.color.dpp.ogam_ram,
160 dc->caps.color.dpp.ocsc);
161
162 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"
163 " SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT"
164 " GAMUT adjust "
165 "C11 C12 C13 C14 "
166 "C21 C22 C23 C24 "
167 "C31 C32 C33 C34 \n");
168
169 for (i = 0; i < pool->mpcc_count; i++) {
170 struct mpcc_state s = {0};
171
172 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
173 mpc3_get_gamut_remap(pool->mpc, i, &s.gamut_remap);
174
175 if (s.opp_id != 0xf)
176 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %11s %11s %16s %11s %10s %9s"
177 " %-12s "
178 "%010lld %010lld %010lld %010lld "
179 "%010lld %010lld %010lld %010lld "
180 "%010lld %010lld %010lld %010lld\n",
181 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
182 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
183 s.idle,
184 (s.shaper_lut_mode == 1) ? "RAM A" :
185 ((s.shaper_lut_mode == 2) ? "RAM B" :
186 "Bypass"),
187 (s.lut3d_mode == 1) ? "RAM A" :
188 ((s.lut3d_mode == 2) ? "RAM B" :
189 "Bypass"),
190 (s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
191 (s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
192 (s.rgam_mode == 0) ? "Bypass" :
193 ((s.rgam_mode == 2) ? "RAM" :
194 "Unknown"),
195 (s.rgam_mode == 1) ? "B" : "A",
196 (s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
197 ((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
198 "SW"),
199 s.gamut_remap.temperature_matrix[0].value,
200 s.gamut_remap.temperature_matrix[1].value,
201 s.gamut_remap.temperature_matrix[2].value,
202 s.gamut_remap.temperature_matrix[3].value,
203 s.gamut_remap.temperature_matrix[4].value,
204 s.gamut_remap.temperature_matrix[5].value,
205 s.gamut_remap.temperature_matrix[6].value,
206 s.gamut_remap.temperature_matrix[7].value,
207 s.gamut_remap.temperature_matrix[8].value,
208 s.gamut_remap.temperature_matrix[9].value,
209 s.gamut_remap.temperature_matrix[10].value,
210 s.gamut_remap.temperature_matrix[11].value);
211
212 }
213 DTN_INFO("\n");
214 DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
215 dc->caps.color.mpc.gamut_remap,
216 dc->caps.color.mpc.num_3dluts,
217 dc->caps.color.mpc.ogam_ram,
218 dc->caps.color.mpc.ocsc);
219 }
220
dcn30_set_blend_lut(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)221 bool dcn30_set_blend_lut(
222 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
223 {
224 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
225 bool result = true;
226 const struct pwl_params *blend_lut = NULL;
227
228 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
229 blend_lut = &plane_state->blend_tf.pwl;
230 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
231 result = cm3_helper_translate_curve_to_hw_format(
232 &plane_state->blend_tf, &dpp_base->regamma_params, false);
233 if (!result)
234 return result;
235
236 blend_lut = &dpp_base->regamma_params;
237 }
238 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
239
240 return result;
241 }
242
dcn30_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)243 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
244 const struct dc_stream_state *stream)
245 {
246 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
247 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
248 struct dc *dc = pipe_ctx->stream->ctx->dc;
249 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
250 bool result = false;
251 int acquired_rmu = 0;
252 int mpcc_id_projected = 0;
253
254 const struct pwl_params *shaper_lut = NULL;
255 //get the shaper lut params
256 if (stream->func_shaper) {
257 if (stream->func_shaper->type == TF_TYPE_HWPWL) {
258 shaper_lut = &stream->func_shaper->pwl;
259 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
260 cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
261 &dpp_base->shaper_params, true);
262 shaper_lut = &dpp_base->shaper_params;
263 }
264 }
265
266 if (stream->lut3d_func &&
267 stream->lut3d_func->state.bits.initialized == 1 &&
268 stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
269 if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
270 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
271 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
272 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
273 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
274 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
275 if (mpcc_id_projected != mpcc_id)
276 BREAK_TO_DEBUGGER();
277 /* find the reason why logical layer assigned a different
278 * mpcc_id into acquire_post_bldn_3dlut
279 */
280 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
281 stream->lut3d_func->state.bits.rmu_mux_num);
282 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
283 BREAK_TO_DEBUGGER();
284
285 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
286 stream->lut3d_func->state.bits.rmu_mux_num);
287 if (!result)
288 DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);
289
290 result = mpc->funcs->program_shaper(mpc, shaper_lut,
291 stream->lut3d_func->state.bits.rmu_mux_num);
292 if (!result)
293 DC_LOG_ERROR("%s: program_shaper failed\n", __func__);
294
295 } else {
296 // loop through the available mux and release the requested mpcc_id
297 mpc->funcs->release_rmu(mpc, mpcc_id);
298 }
299
300 return result;
301 }
302
dcn30_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)303 bool dcn30_set_input_transfer_func(struct dc *dc,
304 struct pipe_ctx *pipe_ctx,
305 const struct dc_plane_state *plane_state)
306 {
307 struct dce_hwseq *hws = dc->hwseq;
308 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
309 enum dc_transfer_func_predefined tf;
310 bool result = true;
311 const struct pwl_params *params = NULL;
312
313 if (dpp_base == NULL || plane_state == NULL)
314 return false;
315
316 tf = TRANSFER_FUNCTION_UNITY;
317
318 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)
319 tf = plane_state->in_transfer_func.tf;
320
321 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
322
323 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
324 params = &plane_state->in_transfer_func.pwl;
325 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
326 cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,
327 &dpp_base->degamma_params, false))
328 params = &dpp_base->degamma_params;
329
330 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
331
332 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
333 if (dpp_base->funcs->dpp_program_blnd_lut)
334 hws->funcs.set_blend_lut(pipe_ctx, plane_state);
335 if (dpp_base->funcs->dpp_program_shaper_lut &&
336 dpp_base->funcs->dpp_program_3dlut)
337 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
338 }
339
340 return result;
341 }
342
dcn30_program_gamut_remap(struct pipe_ctx * pipe_ctx)343 void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx)
344 {
345 int i = 0;
346 struct dpp_grph_csc_adjustment dpp_adjust;
347 struct mpc_grph_gamut_adjustment mpc_adjust;
348 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
349 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
350
351 memset(&dpp_adjust, 0, sizeof(dpp_adjust));
352 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
353
354 if (pipe_ctx->plane_state &&
355 pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
356 dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
357 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
358 dpp_adjust.temperature_matrix[i] =
359 pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
360 }
361
362 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,
363 &dpp_adjust);
364
365 memset(&mpc_adjust, 0, sizeof(mpc_adjust));
366 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
367
368 if (pipe_ctx->top_pipe == NULL) {
369 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
370 mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
371 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
372 mpc_adjust.temperature_matrix[i] =
373 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
374 }
375 }
376
377 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
378 }
379
dcn30_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)380 bool dcn30_set_output_transfer_func(struct dc *dc,
381 struct pipe_ctx *pipe_ctx,
382 const struct dc_stream_state *stream)
383 {
384 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
385 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
386 const struct pwl_params *params = NULL;
387 bool ret = false;
388
389 /* program OGAM or 3DLUT only for the top pipe*/
390 if (pipe_ctx->top_pipe == NULL) {
391 /*program rmu shaper and 3dlut in MPC*/
392 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
393 if (ret == false && mpc->funcs->set_output_gamma) {
394 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
395 params = &stream->out_transfer_func.pwl;
396 else if (pipe_ctx->stream->out_transfer_func.type ==
397 TF_TYPE_DISTRIBUTED_POINTS &&
398 cm3_helper_translate_curve_to_hw_format(
399 &stream->out_transfer_func,
400 &mpc->blender_params, false))
401 params = &mpc->blender_params;
402 /* there are no ROM LUTs in OUTGAM */
403 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)
404 BREAK_TO_DEBUGGER();
405 }
406 }
407
408 if (mpc->funcs->set_output_gamma)
409 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
410 else
411 DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__);
412
413 return ret;
414 }
415
dcn30_set_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)416 static void dcn30_set_writeback(
417 struct dc *dc,
418 struct dc_writeback_info *wb_info,
419 struct dc_state *context)
420 {
421 struct mcif_wb *mcif_wb;
422 struct mcif_buf_params *mcif_buf_params;
423
424 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
425 ASSERT(wb_info->wb_enabled);
426 ASSERT(wb_info->mpcc_inst >= 0);
427 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
428 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
429 mcif_buf_params = &wb_info->mcif_buf_params;
430
431 /* set DWB MPC mux */
432 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
433 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
434 /* set MCIF_WB buffer and arbitration configuration */
435 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
436 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
437 }
438
dcn30_update_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)439 void dcn30_update_writeback(
440 struct dc *dc,
441 struct dc_writeback_info *wb_info,
442 struct dc_state *context)
443 {
444 struct dwbc *dwb;
445 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
446 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
447 __func__, wb_info->dwb_pipe_inst,\
448 wb_info->mpcc_inst);
449
450 dcn30_set_writeback(dc, wb_info, context);
451
452 /* update DWB */
453 dwb->funcs->update(dwb, &wb_info->dwb_params);
454 }
455
dcn30_mmhubbub_warmup(struct dc * dc,unsigned int num_dwb,struct dc_writeback_info * wb_info)456 bool dcn30_mmhubbub_warmup(
457 struct dc *dc,
458 unsigned int num_dwb,
459 struct dc_writeback_info *wb_info)
460 {
461 struct dwbc *dwb;
462 struct mcif_wb *mcif_wb;
463 struct mcif_warmup_params warmup_params = {0};
464 unsigned int i, i_buf;
465 /* make sure there is no active DWB enabled */
466 for (i = 0; i < num_dwb; i++) {
467 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
468 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
469 /*can not do warmup while any dwb enabled*/
470 return false;
471 }
472 }
473
474 if (wb_info->mcif_warmup_params.p_vmid == 0)
475 return false;
476
477 /*check whether this is new interface: warmup big buffer once*/
478 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
479 wb_info->mcif_warmup_params.region_size != 0) {
480 /*mmhubbub is shared, so it does not matter which MCIF*/
481 mcif_wb = dc->res_pool->mcif_wb[0];
482 /*warmup a big chunk of VM buffer at once*/
483 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
484 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;
485 warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
486 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
487
488 if (warmup_params.address_increment == 0)
489 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
490
491 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
492 return true;
493 }
494 /*following is the original: warmup each DWB's mcif buffer*/
495 for (i = 0; i < num_dwb; i++) {
496 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
497 /*warmup is for VM mode only*/
498 if (wb_info[i].mcif_buf_params.p_vmid == 0)
499 return false;
500
501 /* Warmup MCIF_WB */
502 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
503 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
504 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
505 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
506 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
507 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
508 }
509 }
510 return true;
511 }
512
dcn30_enable_writeback(struct dc * dc,struct dc_writeback_info * wb_info,struct dc_state * context)513 void dcn30_enable_writeback(
514 struct dc *dc,
515 struct dc_writeback_info *wb_info,
516 struct dc_state *context)
517 {
518 struct dwbc *dwb;
519 struct mcif_wb *mcif_wb;
520
521 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
522 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
523
524 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
525 __func__, wb_info->dwb_pipe_inst,\
526 wb_info->mpcc_inst);
527
528 /* Warmup interface */
529 dcn30_mmhubbub_warmup(dc, 1, wb_info);
530
531 /* Update writeback pipe */
532 dcn30_set_writeback(dc, wb_info, context);
533
534 /* Enable MCIF_WB */
535 mcif_wb->funcs->enable_mcif(mcif_wb);
536 /* Enable DWB */
537 dwb->funcs->enable(dwb, &wb_info->dwb_params);
538 }
539
dcn30_disable_writeback(struct dc * dc,unsigned int dwb_pipe_inst)540 void dcn30_disable_writeback(
541 struct dc *dc,
542 unsigned int dwb_pipe_inst)
543 {
544 struct dwbc *dwb;
545 struct mcif_wb *mcif_wb;
546
547 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
548 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
549 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
550 DC_LOG_DWB("%s dwb_pipe_inst = %d",\
551 __func__, dwb_pipe_inst);
552
553 /* disable DWB */
554 dwb->funcs->disable(dwb);
555 /* disable MCIF */
556 mcif_wb->funcs->disable_mcif(mcif_wb);
557 /* disable MPC DWB mux */
558 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
559 }
560
dcn30_program_all_writeback_pipes_in_tree(struct dc * dc,const struct dc_stream_state * stream,struct dc_state * context)561 void dcn30_program_all_writeback_pipes_in_tree(
562 struct dc *dc,
563 const struct dc_stream_state *stream,
564 struct dc_state *context)
565 {
566 struct dc_writeback_info wb_info;
567 struct dwbc *dwb;
568 struct dc_stream_status *stream_status = NULL;
569 int i_wb, i_pipe, i_stream;
570 DC_LOG_DWB("%s", __func__);
571
572 ASSERT(stream);
573 for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
574 if (context->streams[i_stream] == stream) {
575 stream_status = &context->stream_status[i_stream];
576 break;
577 }
578 }
579 ASSERT(stream_status);
580
581 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
582 /* For each writeback pipe */
583 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
584
585 /* copy writeback info to local non-const so mpcc_inst can be set */
586 wb_info = stream->writeback_info[i_wb];
587 if (wb_info.wb_enabled) {
588
589 /* get the MPCC instance for writeback_source_plane */
590 wb_info.mpcc_inst = -1;
591 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
592 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
593
594 if (!pipe_ctx->plane_state)
595 continue;
596
597 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
598 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
599 break;
600 }
601 }
602
603 if (wb_info.mpcc_inst == -1) {
604 /* Disable writeback pipe and disconnect from MPCC
605 * if source plane has been removed
606 */
607 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
608 continue;
609 }
610
611 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
612 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
613 if (dwb->funcs->is_enabled(dwb)) {
614 /* writeback pipe already enabled, only need to update */
615 dc->hwss.update_writeback(dc, &wb_info, context);
616 } else {
617 /* Enable writeback pipe and connect to MPCC */
618 dc->hwss.enable_writeback(dc, &wb_info, context);
619 }
620 } else {
621 /* Disable writeback pipe and disconnect from MPCC */
622 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
623 }
624 }
625 }
626
dcn30_init_hw(struct dc * dc)627 void dcn30_init_hw(struct dc *dc)
628 {
629 struct abm **abms = dc->res_pool->multiple_abms;
630 struct dce_hwseq *hws = dc->hwseq;
631 struct dc_bios *dcb = dc->ctx->dc_bios;
632 struct resource_pool *res_pool = dc->res_pool;
633 int i;
634 int edp_num;
635 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
636 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
637
638 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)
639 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
640
641 // Initialize the dccg
642 if (res_pool->dccg->funcs->dccg_init)
643 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
644
645 if (!dcb->funcs->is_accelerated_mode(dcb)) {
646 hws->funcs.bios_golden_init(dc);
647 hws->funcs.disable_vga(dc->hwseq);
648 }
649
650 if (dc->debug.enable_mem_low_power.bits.dmcu) {
651 // Force ERAM to shutdown if DMCU is not enabled
652 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
653 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
654 }
655 }
656
657 // Set default OPTC memory power states
658 if (dc->debug.enable_mem_low_power.bits.optc) {
659 // Shutdown when unassigned and light sleep in VBLANK
660 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
661 }
662
663 if (dc->debug.enable_mem_low_power.bits.vga) {
664 // Power down VGA memory
665 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
666 }
667
668 if (dc->ctx->dc_bios->fw_info_valid) {
669 res_pool->ref_clocks.xtalin_clock_inKhz =
670 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
671
672 if (res_pool->hubbub) {
673
674 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
675 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
676 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
677
678 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
679 res_pool->ref_clocks.dccg_ref_clock_inKhz,
680 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
681 } else {
682 // Not all ASICs have DCCG sw component
683 res_pool->ref_clocks.dccg_ref_clock_inKhz =
684 res_pool->ref_clocks.xtalin_clock_inKhz;
685 res_pool->ref_clocks.dchub_ref_clock_inKhz =
686 res_pool->ref_clocks.xtalin_clock_inKhz;
687 }
688 } else
689 ASSERT_CRITICAL(false);
690
691 for (i = 0; i < dc->link_count; i++) {
692 /* Power up AND update implementation according to the
693 * required signal (which may be different from the
694 * default signal on connector).
695 */
696 struct dc_link *link = dc->links[i];
697
698 link->link_enc->funcs->hw_init(link->link_enc);
699
700 /* Check for enabled DIG to identify enabled display */
701 if (link->link_enc->funcs->is_dig_enabled &&
702 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
703 link->link_status.link_active = true;
704 if (link->link_enc->funcs->fec_is_active &&
705 link->link_enc->funcs->fec_is_active(link->link_enc))
706 link->fec_state = dc_link_fec_enabled;
707 }
708 }
709
710 /* we want to turn off all dp displays before doing detection */
711 dc->link_srv->blank_all_dp_displays(dc);
712
713 if (hws->funcs.enable_power_gating_plane)
714 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
715
716 /* If taking control over from VBIOS, we may want to optimize our first
717 * mode set, so we need to skip powering down pipes until we know which
718 * pipes we want to use.
719 * Otherwise, if taking control is not possible, we need to power
720 * everything down.
721 */
722 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
723 hws->funcs.init_pipes(dc, dc->current_state);
724 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
725 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
726 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
727 }
728
729 /* In headless boot cases, DIG may be turned
730 * on which causes HW/SW discrepancies.
731 * To avoid this, power down hardware on boot
732 * if DIG is turned on and seamless boot not enabled
733 */
734 if (!dc->config.seamless_boot_edp_requested) {
735 struct dc_link *edp_links[MAX_NUM_EDP];
736 struct dc_link *edp_link = NULL;
737
738 dc_get_edp_links(dc, edp_links, &edp_num);
739 if (edp_num)
740 edp_link = edp_links[0];
741 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
742 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
743 dc->hwss.edp_backlight_control &&
744 hws->funcs.power_down &&
745 dc->hwss.edp_power_control) {
746 dc->hwss.edp_backlight_control(edp_link, false);
747 hws->funcs.power_down(dc);
748 dc->hwss.edp_power_control(edp_link, false);
749 } else {
750 for (i = 0; i < dc->link_count; i++) {
751 struct dc_link *link = dc->links[i];
752
753 if (link->link_enc->funcs->is_dig_enabled &&
754 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
755 hws->funcs.power_down) {
756 hws->funcs.power_down(dc);
757 break;
758 }
759
760 }
761 }
762 }
763
764 for (i = 0; i < res_pool->audio_count; i++) {
765 struct audio *audio = res_pool->audios[i];
766
767 audio->funcs->hw_init(audio);
768 }
769
770 for (i = 0; i < dc->link_count; i++) {
771 struct dc_link *link = dc->links[i];
772
773 if (link->panel_cntl) {
774 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
775 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
776 }
777 }
778
779 for (i = 0; i < dc->res_pool->pipe_count; i++) {
780 if (abms[i] != NULL)
781 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
782 }
783
784 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
785 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
786
787 if (!dc->debug.disable_clock_gate) {
788 /* enable all DCN clock gating */
789 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
790
791 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
792
793 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
794 }
795
796 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
797 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
798
799 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)
800 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
801
802 //if softmax is enabled then hardmax will be set by a different call
803 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&
804 !dc->clk_mgr->dc_mode_softmax_enabled)
805 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
806
807 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
808 dc->res_pool->hubbub->funcs->force_pstate_change_control(
809 dc->res_pool->hubbub, false, false);
810 if (dc->res_pool->hubbub->funcs->init_crb)
811 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
812
813 // Get DMCUB capabilities
814 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
815 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
816 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
817 }
818
dcn30_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)819 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
820 {
821 if (pipe_ctx == NULL)
822 return;
823
824 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) {
825 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
826 pipe_ctx->stream_res.stream_enc,
827 enable);
828
829 /* Wait for two frame to make sure AV mute is sent out */
830 if (enable && pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) {
831 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
832 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
833 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
834 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
835 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
836 }
837 }
838 }
839
dcn30_update_info_frame(struct pipe_ctx * pipe_ctx)840 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
841 {
842 bool is_hdmi_tmds;
843 bool is_dp;
844
845 ASSERT(pipe_ctx->stream);
846
847 if (pipe_ctx->stream_res.stream_enc == NULL)
848 return; /* this is not root pipe */
849
850 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
851 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
852
853 if (!is_hdmi_tmds && !is_dp)
854 return;
855
856 if (is_hdmi_tmds)
857 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
858 pipe_ctx->stream_res.stream_enc,
859 &pipe_ctx->stream_res.encoder_info_frame);
860 else {
861 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
862 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
863 pipe_ctx->stream_res.stream_enc,
864 &pipe_ctx->stream_res.encoder_info_frame);
865
866 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
867 pipe_ctx->stream_res.stream_enc,
868 &pipe_ctx->stream_res.encoder_info_frame);
869 }
870 }
871
dcn30_program_dmdata_engine(struct pipe_ctx * pipe_ctx)872 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
873 {
874 struct dc_stream_state *stream = pipe_ctx->stream;
875 struct hubp *hubp = pipe_ctx->plane_res.hubp;
876 bool enable = false;
877 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
878 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal)
879 ? dmdata_dp
880 : dmdata_hdmi;
881
882 /* if using dynamic meta, don't set up generic infopackets */
883 if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
884 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
885 enable = true;
886 }
887
888 if (!hubp)
889 return;
890
891 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
892 return;
893
894 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
895 hubp->inst, mode);
896 }
897
dcn30_apply_idle_power_optimizations(struct dc * dc,bool enable)898 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
899 {
900 union dmub_rb_cmd cmd;
901 uint32_t tmr_delay = 0, tmr_scale = 0;
902 struct dc_cursor_attributes cursor_attr = {0};
903 bool cursor_cache_enable = false;
904 struct dc_stream_state *stream = NULL;
905 struct dc_plane_state *plane = NULL;
906
907 if (!dc->ctx->dmub_srv)
908 return false;
909
910 if (enable) {
911 if (dc->current_state) {
912 int i;
913
914 /* First, check no-memory-requests case */
915 for (i = 0; i < dc->current_state->stream_count; i++) {
916 if (dc->current_state->stream_status[i].plane_count)
917 /* Fail eligibility on a visible stream */
918 break;
919 }
920
921 if (i == dc->current_state->stream_count) {
922 /* Enable no-memory-requests case */
923 memset(&cmd, 0, sizeof(cmd));
924 cmd.mall.header.type = DMUB_CMD__MALL;
925 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
926 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
927
928 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
929
930 return true;
931 }
932
933 stream = dc->current_state->streams[0];
934 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
935
936 if (!stream || !plane)
937 return false;
938
939 if (stream && plane) {
940 cursor_cache_enable = stream->cursor_position.enable &&
941 plane->address.grph.cursor_cache_addr.quad_part;
942 cursor_attr = stream->cursor_attributes;
943 }
944
945 /*
946 * Second, check MALL eligibility
947 *
948 * single display only, single surface only, 8 and 16 bit formats only, no VM,
949 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
950 *
951 * TODO: When we implement multi-display, PSR displays will be allowed if there is
952 * a non-PSR display present, since in that case we can't do D0i3.2
953 */
954 if (dc->current_state->stream_count == 1 &&
955 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
956 dc->current_state->stream_status[0].plane_count == 1 &&
957 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
958 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
959 plane->address.page_table_base.quad_part == 0 &&
960 dc->hwss.does_plane_fit_in_mall &&
961 dc->hwss.does_plane_fit_in_mall(dc, plane->plane_size.surface_pitch,
962 plane->plane_size.surface_size.height, plane->format,
963 cursor_cache_enable ? &cursor_attr : NULL)) {
964 unsigned int v_total = stream->adjust.v_total_max ?
965 stream->adjust.v_total_max : stream->timing.v_total;
966 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
967 100LL, (v_total * stream->timing.h_total));
968
969 /*
970 * one frame time in microsec:
971 * Delay_Us = 1000000 / refresh
972 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
973 *
974 * one frame time modified by 'additional timer percent' (p):
975 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
976 * = dynamic_delay_us * (1 + p / 100)
977 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
978 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
979 *
980 * formula for timer duration based on parameters, from regspec:
981 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
982 *
983 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
984 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
985 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
986 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
987 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
988 *
989 * need to round up the result of the division before the subtraction
990 */
991 unsigned int denom = refresh_hz * 6528;
992 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
993
994 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
995 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
996 denom) - 64LL;
997
998 /* In some cases the stutter period is really big (tiny modes) in these
999 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
1000 *
1001 * We can check if stutter_period is more than 1/10th the frame time to
1002 * consider if we can actually meet the range of hysteresis timer
1003 */
1004 if (stutter_period > 100000/refresh_hz)
1005 return false;
1006
1007 /* scale should be increased until it fits into 6 bits */
1008 while (tmr_delay & ~0x3F) {
1009 tmr_scale++;
1010
1011 if (tmr_scale > 3) {
1012 /* Delay exceeds range of hysteresis timer */
1013 ASSERT(false);
1014 return false;
1015 }
1016
1017 denom *= 2;
1018 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
1019 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
1020 denom) - 64LL;
1021 }
1022
1023 /* Copy HW cursor */
1024 if (cursor_cache_enable) {
1025 memset(&cmd, 0, sizeof(cmd));
1026 cmd.mall.header.type = DMUB_CMD__MALL;
1027 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
1028 cmd.mall.header.payload_bytes =
1029 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1030
1031 switch (cursor_attr.color_format) {
1032 case CURSOR_MODE_MONO:
1033 cmd.mall.cursor_bpp = 2;
1034 break;
1035 case CURSOR_MODE_COLOR_1BIT_AND:
1036 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1037 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1038 cmd.mall.cursor_bpp = 32;
1039 break;
1040
1041 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1042 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1043 cmd.mall.cursor_bpp = 64;
1044 break;
1045 }
1046
1047 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
1048 cmd.mall.cursor_copy_dst.quad_part =
1049 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
1050 cmd.mall.cursor_width = cursor_attr.width;
1051 cmd.mall.cursor_height = cursor_attr.height;
1052 cmd.mall.cursor_pitch = cursor_attr.pitch;
1053
1054 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1055
1056 /* Use copied cursor, and it's okay to not switch back */
1057 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
1058 dc_stream_program_cursor_attributes(stream, &cursor_attr);
1059 }
1060
1061 /* Enable MALL */
1062 memset(&cmd, 0, sizeof(cmd));
1063 cmd.mall.header.type = DMUB_CMD__MALL;
1064 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
1065 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
1066 cmd.mall.tmr_delay = tmr_delay;
1067 cmd.mall.tmr_scale = tmr_scale;
1068 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
1069
1070 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
1071
1072 return true;
1073 }
1074 }
1075
1076 /* No applicable optimizations */
1077 return false;
1078 }
1079
1080 /* Disable MALL */
1081 memset(&cmd, 0, sizeof(cmd));
1082 cmd.mall.header.type = DMUB_CMD__MALL;
1083 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
1084 cmd.mall.header.payload_bytes =
1085 sizeof(cmd.mall) - sizeof(cmd.mall.header);
1086
1087 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
1088
1089 return true;
1090 }
1091
dcn30_does_plane_fit_in_mall(struct dc * dc,unsigned int pitch,unsigned int height,enum surface_pixel_format format,struct dc_cursor_attributes * cursor_attr)1092 bool dcn30_does_plane_fit_in_mall(struct dc *dc,
1093 unsigned int pitch,
1094 unsigned int height,
1095 enum surface_pixel_format format,
1096 struct dc_cursor_attributes *cursor_attr)
1097 {
1098 // add meta size?
1099 unsigned int surface_size = pitch * height *
1100 (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
1101 unsigned int mall_size = dc->caps.mall_size_total;
1102 unsigned int cursor_size = 0;
1103
1104 if (dc->debug.mall_size_override)
1105 mall_size = 1024 * 1024 * dc->debug.mall_size_override;
1106
1107 if (cursor_attr) {
1108 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
1109
1110 switch (cursor_attr->color_format) {
1111 case CURSOR_MODE_MONO:
1112 cursor_size /= 2;
1113 break;
1114 case CURSOR_MODE_COLOR_1BIT_AND:
1115 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
1116 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
1117 cursor_size *= 4;
1118 break;
1119
1120 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
1121 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
1122 cursor_size *= 8;
1123 break;
1124 }
1125 }
1126
1127 return (surface_size + cursor_size) < mall_size;
1128 }
1129
dcn30_hardware_release(struct dc * dc)1130 void dcn30_hardware_release(struct dc *dc)
1131 {
1132 bool subvp_in_use = false;
1133 uint32_t i;
1134
1135 dc_dmub_srv_p_state_delegate(dc, false, NULL);
1136 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
1137
1138 /* SubVP treated the same way as FPO. If driver disable and
1139 * we are using a SubVP config, disable and force on DCN side
1140 * to prevent P-State hang on driver enable.
1141 */
1142 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1143 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1144
1145 if (!pipe->stream)
1146 continue;
1147
1148 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_MAIN) {
1149 subvp_in_use = true;
1150 break;
1151 }
1152 }
1153 /* If pstate unsupported, or still supported
1154 * by firmware, force it supported by dcn
1155 */
1156 if (dc->current_state)
1157 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
1158 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
1159 dc->res_pool->hubbub->funcs->force_pstate_change_control)
1160 dc->res_pool->hubbub->funcs->force_pstate_change_control(
1161 dc->res_pool->hubbub, true, true);
1162 }
1163
dcn30_set_disp_pattern_generator(const struct dc * dc,struct pipe_ctx * pipe_ctx,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,const struct tg_color * solid_color,int width,int height,int offset)1164 void dcn30_set_disp_pattern_generator(const struct dc *dc,
1165 struct pipe_ctx *pipe_ctx,
1166 enum controller_dp_test_pattern test_pattern,
1167 enum controller_dp_color_space color_space,
1168 enum dc_color_depth color_depth,
1169 const struct tg_color *solid_color,
1170 int width, int height, int offset)
1171 {
1172 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
1173 color_space, color_depth, solid_color, width, height, offset);
1174 }
1175
dcn30_prepare_bandwidth(struct dc * dc,struct dc_state * context)1176 void dcn30_prepare_bandwidth(struct dc *dc,
1177 struct dc_state *context)
1178 {
1179 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {
1180 dc->optimized_required = true;
1181 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1182 }
1183
1184 if (dc->clk_mgr->dc_mode_softmax_enabled)
1185 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1186 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1187 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1188
1189 dcn20_prepare_bandwidth(dc, context);
1190
1191 if (!dc->clk_mgr->clks.fw_based_mclk_switching)
1192 dc_dmub_srv_p_state_delegate(dc, false, context);
1193 }
1194
dcn30_wait_for_all_pending_updates(const struct pipe_ctx * pipe_ctx)1195 void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx)
1196 {
1197 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1198 bool pending_updates = false;
1199 unsigned int i;
1200
1201 if (tg && tg->funcs->is_tg_enabled(tg)) {
1202 // Poll for 100ms maximum
1203 for (i = 0; i < 100000; i++) {
1204 pending_updates = false;
1205 if (tg->funcs->get_optc_double_buffer_pending)
1206 pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg);
1207
1208 if (tg->funcs->get_otg_double_buffer_pending)
1209 pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg);
1210
1211 if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state)
1212 pending_updates |= tg->funcs->get_pipe_update_pending(tg);
1213
1214 if (!pending_updates)
1215 break;
1216
1217 udelay(1);
1218 }
1219 }
1220 }
1221