1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn20_optc.h"
28 #include "dc.h"
29
30 #define REG(reg)\
31 optc1->tg_regs->reg
32
33 #define CTX \
34 optc1->base.ctx
35
36 #undef FN
37 #define FN(reg_name, field_name) \
38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
39
40 /**
41 * optc2_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
42 *
43 * @optc: timing_generator instance.
44 *
45 * Return: If CRTC is enabled, return true.
46 *
47 */
optc2_enable_crtc(struct timing_generator * optc)48 bool optc2_enable_crtc(struct timing_generator *optc)
49 {
50 /* TODO FPGA wait for answer
51 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
52 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
53 */
54 struct optc *optc1 = DCN10TG_FROM_TG(optc);
55
56 /* opp instance for OTG. For DCN1.0, ODM is remoed.
57 * OPP and OPTC should 1:1 mapping
58 */
59 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
60 OPTC_SEG0_SRC_SEL, optc->inst);
61
62 /* VTG enable first is for HW workaround */
63 REG_UPDATE(CONTROL,
64 VTG0_ENABLE, 1);
65
66 REG_SEQ_START();
67
68 /* Enable CRTC */
69 REG_UPDATE_2(OTG_CONTROL,
70 OTG_DISABLE_POINT_CNTL, 3,
71 OTG_MASTER_EN, 1);
72
73 REG_SEQ_SUBMIT();
74 REG_SEQ_WAIT_DONE();
75
76 return true;
77 }
78
79 /**
80 * optc2_set_gsl() - Assign OTG to GSL groups,
81 * set one of the OTGs to be master & rest are slaves
82 *
83 * @optc: timing_generator instance.
84 * @params: pointer to gsl_params
85 */
optc2_set_gsl(struct timing_generator * optc,const struct gsl_params * params)86 void optc2_set_gsl(struct timing_generator *optc,
87 const struct gsl_params *params)
88 {
89 struct optc *optc1 = DCN10TG_FROM_TG(optc);
90
91 /*
92 * There are (MAX_OPTC+1)/2 gsl groups available for use.
93 * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
94 * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
95 */
96 REG_UPDATE_5(OTG_GSL_CONTROL,
97 OTG_GSL0_EN, params->gsl0_en,
98 OTG_GSL1_EN, params->gsl1_en,
99 OTG_GSL2_EN, params->gsl2_en,
100 OTG_GSL_MASTER_EN, params->gsl_master_en,
101 OTG_GSL_MASTER_MODE, params->gsl_master_mode);
102 }
103
104
optc2_set_gsl_source_select(struct timing_generator * optc,int group_idx,uint32_t gsl_ready_signal)105 void optc2_set_gsl_source_select(
106 struct timing_generator *optc,
107 int group_idx,
108 uint32_t gsl_ready_signal)
109 {
110 struct optc *optc1 = DCN10TG_FROM_TG(optc);
111
112 switch (group_idx) {
113 case 1:
114 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
115 break;
116 case 2:
117 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
118 break;
119 case 3:
120 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
121 break;
122 default:
123 break;
124 }
125 }
126
127 /* Set DSC-related configuration.
128 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
129 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
130 * dsc_slice_width: Slice width in pixels
131 */
optc2_set_dsc_config(struct timing_generator * optc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)132 void optc2_set_dsc_config(struct timing_generator *optc,
133 enum optc_dsc_mode dsc_mode,
134 uint32_t dsc_bytes_per_pixel,
135 uint32_t dsc_slice_width)
136 {
137 struct optc *optc1 = DCN10TG_FROM_TG(optc);
138
139 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
140 OPTC_DSC_MODE, dsc_mode);
141
142 REG_SET(OPTC_BYTES_PER_PIXEL, 0,
143 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
144
145 REG_UPDATE(OPTC_WIDTH_CONTROL,
146 OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
147 }
148
149 /* Get DSC-related configuration.
150 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
151 */
optc2_get_dsc_status(struct timing_generator * optc,uint32_t * dsc_mode)152 void optc2_get_dsc_status(struct timing_generator *optc,
153 uint32_t *dsc_mode)
154 {
155 struct optc *optc1 = DCN10TG_FROM_TG(optc);
156
157 REG_GET(OPTC_DATA_FORMAT_CONTROL,
158 OPTC_DSC_MODE, dsc_mode);
159 }
160
optc2_set_odm_bypass(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing)161 void optc2_set_odm_bypass(struct timing_generator *optc,
162 const struct dc_crtc_timing *dc_crtc_timing)
163 {
164 struct optc *optc1 = DCN10TG_FROM_TG(optc);
165 uint32_t h_div_2 = 0;
166
167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
168 OPTC_NUM_OF_INPUT_SEGMENT, 0,
169 OPTC_SEG0_SRC_SEL, optc->inst,
170 OPTC_SEG1_SRC_SEL, 0xf);
171 REG_WRITE(OTG_H_TIMING_CNTL, 0);
172
173 h_div_2 = optc->funcs->is_two_pixels_per_container(dc_crtc_timing);
174 REG_UPDATE(OTG_H_TIMING_CNTL,
175 OTG_H_TIMING_DIV_BY2, h_div_2);
176 REG_SET(OPTC_MEMORY_CONFIG, 0,
177 OPTC_MEM_SEL, 0);
178 optc1->opp_count = 1;
179 }
180
optc2_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,int segment_width,int last_segment_width)181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
182 int segment_width, int last_segment_width)
183 {
184 struct optc *optc1 = DCN10TG_FROM_TG(optc);
185 uint32_t memory_mask;
186
187 ASSERT(opp_cnt == 2);
188
189 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
190 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
191 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
192 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
193 * MASTER_UPDATE_LOCK_DB_X, 160,
194 * MASTER_UPDATE_LOCK_DB_Y, 240);
195 */
196
197 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
198 * however, for ODM combine we can simplify by always using 4.
199 * To make sure there's no overlap, each instance "reserves" 2 memories and
200 * they are uniquely combined here.
201 */
202 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
203
204 if (REG(OPTC_MEMORY_CONFIG))
205 REG_SET(OPTC_MEMORY_CONFIG, 0,
206 OPTC_MEM_SEL, memory_mask);
207
208 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
209 OPTC_NUM_OF_INPUT_SEGMENT, 1,
210 OPTC_SEG0_SRC_SEL, opp_id[0],
211 OPTC_SEG1_SRC_SEL, opp_id[1]);
212
213 REG_UPDATE(OPTC_WIDTH_CONTROL,
214 OPTC_SEGMENT_WIDTH, segment_width);
215
216 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
217 optc1->opp_count = opp_cnt;
218 }
219
optc2_get_optc_source(struct timing_generator * optc,uint32_t * num_of_src_opp,uint32_t * src_opp_id_0,uint32_t * src_opp_id_1)220 void optc2_get_optc_source(struct timing_generator *optc,
221 uint32_t *num_of_src_opp,
222 uint32_t *src_opp_id_0,
223 uint32_t *src_opp_id_1)
224 {
225 uint32_t num_of_input_segments;
226 struct optc *optc1 = DCN10TG_FROM_TG(optc);
227
228 REG_GET_3(OPTC_DATA_SOURCE_SELECT,
229 OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
230 OPTC_SEG0_SRC_SEL, src_opp_id_0,
231 OPTC_SEG1_SRC_SEL, src_opp_id_1);
232
233 if (num_of_input_segments == 1)
234 *num_of_src_opp = 2;
235 else
236 *num_of_src_opp = 1;
237
238 /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
239 if (*src_opp_id_1 == 0xf)
240 *num_of_src_opp = 1;
241 }
242
optc2_set_dwb_source(struct timing_generator * optc,uint32_t dwb_pipe_inst)243 static void optc2_set_dwb_source(struct timing_generator *optc,
244 uint32_t dwb_pipe_inst)
245 {
246 struct optc *optc1 = DCN10TG_FROM_TG(optc);
247
248 if (dwb_pipe_inst == 0)
249 REG_UPDATE(DWB_SOURCE_SELECT,
250 OPTC_DWB0_SOURCE_SELECT, optc->inst);
251 else if (dwb_pipe_inst == 1)
252 REG_UPDATE(DWB_SOURCE_SELECT,
253 OPTC_DWB1_SOURCE_SELECT, optc->inst);
254 }
255
optc2_align_vblanks(struct timing_generator * optc_master,struct timing_generator * optc_slave,uint32_t master_pixel_clock_100Hz,uint32_t slave_pixel_clock_100Hz,uint8_t master_clock_divider,uint8_t slave_clock_divider)256 static void optc2_align_vblanks(
257 struct timing_generator *optc_master,
258 struct timing_generator *optc_slave,
259 uint32_t master_pixel_clock_100Hz,
260 uint32_t slave_pixel_clock_100Hz,
261 uint8_t master_clock_divider,
262 uint8_t slave_clock_divider)
263 {
264 /* accessing slave OTG registers */
265 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
266
267 uint32_t master_v_active = 0;
268 uint32_t master_h_total = 0;
269 uint32_t slave_h_total = 0;
270 uint64_t L, XY;
271 uint32_t X, Y, p = 10000;
272 uint32_t master_update_lock;
273
274 /* disable slave OTG */
275 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
276 /* wait until disabled */
277 REG_WAIT(OTG_CONTROL,
278 OTG_CURRENT_MASTER_EN_STATE,
279 0, 10, 5000);
280
281 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
282
283 /* assign slave OTG to be controlled by master update lock */
284 REG_SET(OTG_GLOBAL_CONTROL0, 0,
285 OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
286
287 /* accessing master OTG registers */
288 optc1 = DCN10TG_FROM_TG(optc_master);
289
290 /* saving update lock state, not sure if it's needed */
291 REG_GET(OTG_MASTER_UPDATE_LOCK,
292 OTG_MASTER_UPDATE_LOCK, &master_update_lock);
293 /* unlocking master OTG */
294 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
295 OTG_MASTER_UPDATE_LOCK, 0);
296
297 REG_GET(OTG_V_BLANK_START_END,
298 OTG_V_BLANK_START, &master_v_active);
299 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
300
301 /* calculate when to enable slave OTG */
302 L = (uint64_t)p * slave_h_total * master_pixel_clock_100Hz;
303 L = div_u64(L, master_h_total);
304 L = div_u64(L, slave_pixel_clock_100Hz);
305 XY = div_u64(L, p);
306 Y = master_v_active - XY - 1;
307 X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
308
309 /*
310 * set master OTG to unlock when V/H
311 * counters reach calculated values
312 */
313 REG_UPDATE(OTG_GLOBAL_CONTROL1,
314 MASTER_UPDATE_LOCK_DB_EN, 1);
315 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
316 MASTER_UPDATE_LOCK_DB_X,
317 X,
318 MASTER_UPDATE_LOCK_DB_Y,
319 Y);
320
321 /* lock master OTG */
322 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
323 OTG_MASTER_UPDATE_LOCK, 1);
324 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
325 UPDATE_LOCK_STATUS, 1, 1, 10);
326
327 /* accessing slave OTG registers */
328 optc1 = DCN10TG_FROM_TG(optc_slave);
329
330 /*
331 * enable slave OTG, the OTG is locked with
332 * master's update lock, so it will not run
333 */
334 REG_UPDATE(OTG_CONTROL,
335 OTG_MASTER_EN, 1);
336
337 /* accessing master OTG registers */
338 optc1 = DCN10TG_FROM_TG(optc_master);
339
340 /*
341 * unlock master OTG. When master H/V counters reach
342 * DB_XY point, slave OTG will start
343 */
344 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
345 OTG_MASTER_UPDATE_LOCK, 0);
346
347 /* accessing slave OTG registers */
348 optc1 = DCN10TG_FROM_TG(optc_slave);
349
350 /* wait for slave OTG to start running*/
351 REG_WAIT(OTG_CONTROL,
352 OTG_CURRENT_MASTER_EN_STATE,
353 1, 10, 5000);
354
355 /* accessing master OTG registers */
356 optc1 = DCN10TG_FROM_TG(optc_master);
357
358 /* disable the XY point*/
359 REG_UPDATE(OTG_GLOBAL_CONTROL1,
360 MASTER_UPDATE_LOCK_DB_EN, 0);
361 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
362 MASTER_UPDATE_LOCK_DB_X,
363 0,
364 MASTER_UPDATE_LOCK_DB_Y,
365 0);
366
367 /*restore master update lock*/
368 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
369 OTG_MASTER_UPDATE_LOCK, master_update_lock);
370
371 /* accessing slave OTG registers */
372 optc1 = DCN10TG_FROM_TG(optc_slave);
373 /* restore slave to be controlled by it's own */
374 REG_SET(OTG_GLOBAL_CONTROL0, 0,
375 OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
376
377 }
378
optc2_triplebuffer_lock(struct timing_generator * optc)379 void optc2_triplebuffer_lock(struct timing_generator *optc)
380 {
381 struct optc *optc1 = DCN10TG_FROM_TG(optc);
382
383 REG_SET(OTG_GLOBAL_CONTROL0, 0,
384 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
385
386 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
387 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
388
389 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
390 OTG_MASTER_UPDATE_LOCK, 1);
391
392 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
393 UPDATE_LOCK_STATUS, 1,
394 1, 10);
395 }
396
optc2_triplebuffer_unlock(struct timing_generator * optc)397 void optc2_triplebuffer_unlock(struct timing_generator *optc)
398 {
399 struct optc *optc1 = DCN10TG_FROM_TG(optc);
400
401 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
402 OTG_MASTER_UPDATE_LOCK, 0);
403
404 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
405 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
406
407 }
408
optc2_lock_doublebuffer_enable(struct timing_generator * optc)409 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
410 {
411 struct optc *optc1 = DCN10TG_FROM_TG(optc);
412 uint32_t v_blank_start = 0;
413 uint32_t h_blank_start = 0;
414
415 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
416
417 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
418 DIG_UPDATE_LOCATION, 20);
419
420 REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
421
422 REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
423
424 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
425 MASTER_UPDATE_LOCK_DB_X,
426 (h_blank_start - 200 - 1) / optc1->opp_count,
427 MASTER_UPDATE_LOCK_DB_Y,
428 v_blank_start - 1);
429
430 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
431 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
432 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
433 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
434 }
435
optc2_lock_doublebuffer_disable(struct timing_generator * optc)436 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
437 {
438 struct optc *optc1 = DCN10TG_FROM_TG(optc);
439
440 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
441 MASTER_UPDATE_LOCK_DB_X,
442 0,
443 MASTER_UPDATE_LOCK_DB_Y,
444 0);
445
446 REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
447 DIG_UPDATE_LOCATION, 0);
448
449 REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
450 }
451
optc2_setup_manual_trigger(struct timing_generator * optc)452 void optc2_setup_manual_trigger(struct timing_generator *optc)
453 {
454 struct optc *optc1 = DCN10TG_FROM_TG(optc);
455
456 /* Set the min/max selectors unconditionally so that
457 * DMCUB fw may change OTG timings when necessary
458 * TODO: Remove the w/a after fixing the issue in DMCUB firmware
459 */
460 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
461 OTG_V_TOTAL_MIN_SEL, 1,
462 OTG_V_TOTAL_MAX_SEL, 1,
463 OTG_FORCE_LOCK_ON_EVENT, 0,
464 OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
465
466 REG_SET_8(OTG_TRIGA_CNTL, 0,
467 OTG_TRIGA_SOURCE_SELECT, 21,
468 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
469 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
470 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
471 OTG_TRIGA_POLARITY_SELECT, 0,
472 OTG_TRIGA_FREQUENCY_SELECT, 0,
473 OTG_TRIGA_DELAY, 0,
474 OTG_TRIGA_CLEAR, 1);
475 }
476
optc2_program_manual_trigger(struct timing_generator * optc)477 void optc2_program_manual_trigger(struct timing_generator *optc)
478 {
479 struct optc *optc1 = DCN10TG_FROM_TG(optc);
480
481 REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
482 OTG_TRIGA_MANUAL_TRIG, 1);
483 }
484
optc2_configure_crc(struct timing_generator * optc,const struct crc_params * params)485 bool optc2_configure_crc(struct timing_generator *optc,
486 const struct crc_params *params)
487 {
488 struct optc *optc1 = DCN10TG_FROM_TG(optc);
489
490 REG_SET_2(OTG_CRC_CNTL2, 0,
491 OTG_CRC_DSC_MODE, params->dsc_mode,
492 OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
493
494 return optc1_configure_crc(optc, params);
495 }
496
497
optc2_get_last_used_drr_vtotal(struct timing_generator * optc,uint32_t * refresh_rate)498 void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
499 {
500 struct optc *optc1 = DCN10TG_FROM_TG(optc);
501
502 REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
503 }
504
505 static struct timing_generator_funcs dcn20_tg_funcs = {
506 .validate_timing = optc1_validate_timing,
507 .program_timing = optc1_program_timing,
508 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
509 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
510 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
511 .program_global_sync = optc1_program_global_sync,
512 .enable_crtc = optc2_enable_crtc,
513 .disable_crtc = optc1_disable_crtc,
514 /* used by enable_timing_synchronization. Not need for FPGA */
515 .is_counter_moving = optc1_is_counter_moving,
516 .get_position = optc1_get_position,
517 .get_frame_count = optc1_get_vblank_counter,
518 .get_scanoutpos = optc1_get_crtc_scanoutpos,
519 .get_otg_active_size = optc1_get_otg_active_size,
520 .set_early_control = optc1_set_early_control,
521 /* used by enable_timing_synchronization. Not need for FPGA */
522 .wait_for_state = optc1_wait_for_state,
523 .set_blank = optc1_set_blank,
524 .is_blanked = optc1_is_blanked,
525 .set_blank_color = optc1_program_blank_color,
526 .enable_reset_trigger = optc1_enable_reset_trigger,
527 .enable_crtc_reset = optc1_enable_crtc_reset,
528 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
529 .triplebuffer_lock = optc2_triplebuffer_lock,
530 .triplebuffer_unlock = optc2_triplebuffer_unlock,
531 .disable_reset_trigger = optc1_disable_reset_trigger,
532 .lock = optc1_lock,
533 .unlock = optc1_unlock,
534 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
535 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
536 .enable_optc_clock = optc1_enable_optc_clock,
537 .set_drr = optc1_set_drr,
538 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
539 .set_vtotal_min_max = optc1_set_vtotal_min_max,
540 .set_static_screen_control = optc1_set_static_screen_control,
541 .program_stereo = optc1_program_stereo,
542 .is_stereo_left_eye = optc1_is_stereo_left_eye,
543 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
544 .tg_init = optc1_tg_init,
545 .is_tg_enabled = optc1_is_tg_enabled,
546 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
547 .clear_optc_underflow = optc1_clear_optc_underflow,
548 .setup_global_swap_lock = NULL,
549 .get_crc = optc1_get_crc,
550 .configure_crc = optc2_configure_crc,
551 .set_dsc_config = optc2_set_dsc_config,
552 .get_dsc_status = optc2_get_dsc_status,
553 .set_dwb_source = optc2_set_dwb_source,
554 .set_odm_bypass = optc2_set_odm_bypass,
555 .set_odm_combine = optc2_set_odm_combine,
556 .get_optc_source = optc2_get_optc_source,
557 .set_gsl = optc2_set_gsl,
558 .set_gsl_source_select = optc2_set_gsl_source_select,
559 .set_vtg_params = optc1_set_vtg_params,
560 .program_manual_trigger = optc2_program_manual_trigger,
561 .setup_manual_trigger = optc2_setup_manual_trigger,
562 .get_hw_timing = optc1_get_hw_timing,
563 .align_vblanks = optc2_align_vblanks,
564 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
565 };
566
dcn20_timing_generator_init(struct optc * optc1)567 void dcn20_timing_generator_init(struct optc *optc1)
568 {
569 optc1->base.funcs = &dcn20_tg_funcs;
570
571 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
572 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
573
574 optc1->min_h_blank = 32;
575 optc1->min_v_blank = 3;
576 optc1->min_v_blank_interlace = 5;
577 optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
578 optc1->min_v_sync_width = 1;
579 }
580