1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_status.h" 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn10/dcn10_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn10/dcn10_resource.h" 35 #include "dcn10/dcn10_ipp.h" 36 #include "dcn10/dcn10_mpc.h" 37 38 #include "dcn10/dcn10_dwb.h" 39 40 #include "irq/dcn10/irq_service_dcn10.h" 41 #include "dcn10/dcn10_dpp.h" 42 #include "dcn10/dcn10_optc.h" 43 #include "dcn10/dcn10_hwseq.h" 44 #include "dce110/dce110_hwseq.h" 45 #include "dcn10/dcn10_opp.h" 46 #include "dcn10/dcn10_link_encoder.h" 47 #include "dcn10/dcn10_stream_encoder.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dio/virtual/virtual_stream_encoder.h" 52 #include "dce110/dce110_resource.h" 53 #include "dce112/dce112_resource.h" 54 #include "dcn10/dcn10_hubp.h" 55 #include "dcn10/dcn10_hubbub.h" 56 #include "dce/dce_panel_cntl.h" 57 58 #include "soc15_hw_ip.h" 59 #include "vega10_ip_offset.h" 60 61 #include "dcn/dcn_1_0_offset.h" 62 #include "dcn/dcn_1_0_sh_mask.h" 63 64 #include "nbio/nbio_7_0_offset.h" 65 66 #include "mmhub/mmhub_9_1_offset.h" 67 #include "mmhub/mmhub_9_1_sh_mask.h" 68 69 #include "reg_helper.h" 70 #include "dce/dce_abm.h" 71 #include "dce/dce_dmcu.h" 72 #include "dce/dce_aux.h" 73 #include "dce/dce_i2c.h" 74 #include "dio/dcn10/dcn10_dio.h" 75 76 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 77 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 78 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 79 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 80 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 81 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 82 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 83 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 84 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 85 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 86 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 87 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 88 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 89 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 90 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 91 #endif 92 93 94 enum dcn10_clk_src_array_id { 95 DCN10_CLK_SRC_PLL0, 96 DCN10_CLK_SRC_PLL1, 97 DCN10_CLK_SRC_PLL2, 98 DCN10_CLK_SRC_PLL3, 99 DCN10_CLK_SRC_TOTAL, 100 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file */ 105 106 /* DCN */ 107 #define BASE_INNER(seg) \ 108 DCE_BASE__INST0_SEG ## seg 109 110 #define BASE(seg) \ 111 BASE_INNER(seg) 112 113 #define SR(reg_name)\ 114 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 115 mm ## reg_name 116 117 #define SRI(reg_name, block, id)\ 118 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 119 mm ## block ## id ## _ ## reg_name 120 121 122 #define SRII(reg_name, block, id)\ 123 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 124 mm ## block ## id ## _ ## reg_name 125 126 #define VUPDATE_SRII(reg_name, block, id)\ 127 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \ 128 mm ## reg_name ## 0 ## _ ## block ## id 129 130 /* set field/register/bitfield name */ 131 #define SFRB(field_name, reg_name, bitfield, post_fix)\ 132 .field_name = reg_name ## __ ## bitfield ## post_fix 133 134 /* NBIO */ 135 #define NBIO_BASE_INNER(seg) \ 136 NBIF_BASE__INST0_SEG ## seg 137 138 #define NBIO_BASE(seg) \ 139 NBIO_BASE_INNER(seg) 140 141 #define NBIO_SR(reg_name)\ 142 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 143 mm ## reg_name 144 145 /* MMHUB */ 146 #define MMHUB_BASE_INNER(seg) \ 147 MMHUB_BASE__INST0_SEG ## seg 148 149 #define MMHUB_BASE(seg) \ 150 MMHUB_BASE_INNER(seg) 151 152 #define MMHUB_SR(reg_name)\ 153 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 154 mm ## reg_name 155 156 /* macros to expend register list macro defined in HW object header file 157 * end *********************/ 158 159 160 static const struct dce_dmcu_registers dmcu_regs = { 161 DMCU_DCN10_REG_LIST() 162 }; 163 164 static const struct dce_dmcu_shift dmcu_shift = { 165 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 166 }; 167 168 static const struct dce_dmcu_mask dmcu_mask = { 169 DMCU_MASK_SH_LIST_DCN10(_MASK) 170 }; 171 172 static const struct dce_abm_registers abm_regs = { 173 ABM_DCN10_REG_LIST(0) 174 }; 175 176 static const struct dce_abm_shift abm_shift = { 177 ABM_MASK_SH_LIST_DCN10(__SHIFT) 178 }; 179 180 static const struct dce_abm_mask abm_mask = { 181 ABM_MASK_SH_LIST_DCN10(_MASK) 182 }; 183 184 #define stream_enc_regs(id)\ 185 [id] = {\ 186 SE_DCN_REG_LIST(id)\ 187 } 188 189 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 190 stream_enc_regs(0), 191 stream_enc_regs(1), 192 stream_enc_regs(2), 193 stream_enc_regs(3), 194 }; 195 196 static const struct dcn10_stream_encoder_shift se_shift = { 197 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 198 }; 199 200 static const struct dcn10_stream_encoder_mask se_mask = { 201 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 202 }; 203 204 #define audio_regs(id)\ 205 [id] = {\ 206 AUD_COMMON_REG_LIST(id)\ 207 } 208 209 static const struct dce_audio_registers audio_regs[] = { 210 audio_regs(0), 211 audio_regs(1), 212 audio_regs(2), 213 audio_regs(3), 214 }; 215 216 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 217 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 218 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 219 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 220 221 static const struct dce_audio_shift audio_shift = { 222 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 223 }; 224 225 static const struct dce_audio_mask audio_mask = { 226 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 227 }; 228 229 #define aux_regs(id)\ 230 [id] = {\ 231 AUX_REG_LIST(id)\ 232 } 233 234 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 235 aux_regs(0), 236 aux_regs(1), 237 aux_regs(2), 238 aux_regs(3) 239 }; 240 241 #define hpd_regs(id)\ 242 [id] = {\ 243 HPD_REG_LIST(id)\ 244 } 245 246 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 247 hpd_regs(0), 248 hpd_regs(1), 249 hpd_regs(2), 250 hpd_regs(3) 251 }; 252 253 #define link_regs(id)\ 254 [id] = {\ 255 LE_DCN10_REG_LIST(id), \ 256 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 257 } 258 259 static const struct dcn10_link_enc_registers link_enc_regs[] = { 260 link_regs(0), 261 link_regs(1), 262 link_regs(2), 263 link_regs(3) 264 }; 265 266 static const struct dcn10_link_enc_shift le_shift = { 267 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 268 }; 269 270 static const struct dcn10_link_enc_mask le_mask = { 271 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 272 }; 273 274 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 275 { DCN_PANEL_CNTL_REG_LIST() } 276 }; 277 278 static const struct dce_panel_cntl_shift panel_cntl_shift = { 279 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 280 }; 281 282 static const struct dce_panel_cntl_mask panel_cntl_mask = { 283 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 284 }; 285 286 static const struct dce110_aux_registers_shift aux_shift = { 287 DCN10_AUX_MASK_SH_LIST(__SHIFT) 288 }; 289 290 static const struct dce110_aux_registers_mask aux_mask = { 291 DCN10_AUX_MASK_SH_LIST(_MASK) 292 }; 293 294 #define ipp_regs(id)\ 295 [id] = {\ 296 IPP_REG_LIST_DCN10(id),\ 297 } 298 299 static const struct dcn10_ipp_registers ipp_regs[] = { 300 ipp_regs(0), 301 ipp_regs(1), 302 ipp_regs(2), 303 ipp_regs(3), 304 }; 305 306 static const struct dcn10_ipp_shift ipp_shift = { 307 IPP_MASK_SH_LIST_DCN10(__SHIFT) 308 }; 309 310 static const struct dcn10_ipp_mask ipp_mask = { 311 IPP_MASK_SH_LIST_DCN10(_MASK), 312 }; 313 314 #define opp_regs(id)\ 315 [id] = {\ 316 OPP_REG_LIST_DCN10(id),\ 317 } 318 319 static const struct dcn10_opp_registers opp_regs[] = { 320 opp_regs(0), 321 opp_regs(1), 322 opp_regs(2), 323 opp_regs(3), 324 }; 325 326 static const struct dcn10_opp_shift opp_shift = { 327 OPP_MASK_SH_LIST_DCN10(__SHIFT) 328 }; 329 330 static const struct dcn10_opp_mask opp_mask = { 331 OPP_MASK_SH_LIST_DCN10(_MASK), 332 }; 333 334 #define aux_engine_regs(id)\ 335 [id] = {\ 336 AUX_COMMON_REG_LIST(id), \ 337 .AUX_RESET_MASK = 0 \ 338 } 339 340 static const struct dce110_aux_registers aux_engine_regs[] = { 341 aux_engine_regs(0), 342 aux_engine_regs(1), 343 aux_engine_regs(2), 344 aux_engine_regs(3), 345 aux_engine_regs(4), 346 aux_engine_regs(5) 347 }; 348 349 #define tf_regs(id)\ 350 [id] = {\ 351 TF_REG_LIST_DCN10(id),\ 352 } 353 354 static const struct dcn_dpp_registers tf_regs[] = { 355 tf_regs(0), 356 tf_regs(1), 357 tf_regs(2), 358 tf_regs(3), 359 }; 360 361 static const struct dcn_dpp_shift tf_shift = { 362 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 363 TF_DEBUG_REG_LIST_SH_DCN10 364 365 }; 366 367 static const struct dcn_dpp_mask tf_mask = { 368 TF_REG_LIST_SH_MASK_DCN10(_MASK), 369 TF_DEBUG_REG_LIST_MASK_DCN10 370 }; 371 372 static const struct dcn_mpc_registers mpc_regs = { 373 MPC_COMMON_REG_LIST_DCN1_0(0), 374 MPC_COMMON_REG_LIST_DCN1_0(1), 375 MPC_COMMON_REG_LIST_DCN1_0(2), 376 MPC_COMMON_REG_LIST_DCN1_0(3), 377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 379 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 380 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 381 }; 382 383 static const struct dcn_mpc_shift mpc_shift = { 384 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\ 385 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT) 386 }; 387 388 static const struct dcn_mpc_mask mpc_mask = { 389 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\ 390 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK) 391 }; 392 393 #define tg_regs(id)\ 394 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 395 396 static const struct dcn_optc_registers tg_regs[] = { 397 tg_regs(0), 398 tg_regs(1), 399 tg_regs(2), 400 tg_regs(3), 401 }; 402 403 static const struct dcn_optc_shift tg_shift = { 404 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 405 }; 406 407 static const struct dcn_optc_mask tg_mask = { 408 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 409 }; 410 411 static const struct bios_registers bios_regs = { 412 NBIO_SR(BIOS_SCRATCH_3), 413 NBIO_SR(BIOS_SCRATCH_6) 414 }; 415 416 #define hubp_regs(id)\ 417 [id] = {\ 418 HUBP_REG_LIST_DCN10(id)\ 419 } 420 421 static const struct dcn_mi_registers hubp_regs[] = { 422 hubp_regs(0), 423 hubp_regs(1), 424 hubp_regs(2), 425 hubp_regs(3), 426 }; 427 428 static const struct dcn_mi_shift hubp_shift = { 429 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 430 }; 431 432 static const struct dcn_mi_mask hubp_mask = { 433 HUBP_MASK_SH_LIST_DCN10(_MASK) 434 }; 435 436 static const struct dcn_hubbub_registers hubbub_reg = { 437 HUBBUB_REG_LIST_DCN10(0) 438 }; 439 440 static const struct dcn_hubbub_shift hubbub_shift = { 441 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 442 }; 443 444 static const struct dcn_hubbub_mask hubbub_mask = { 445 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 446 }; 447 448 static const struct dcn_dio_registers dio_regs = { 449 DIO_REG_LIST_DCN10() 450 }; 451 452 #define DIO_MASK_SH_LIST(mask_sh)\ 453 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 454 455 static const struct dcn_dio_shift dio_shift = { 456 DIO_MASK_SH_LIST(__SHIFT) 457 }; 458 459 static const struct dcn_dio_mask dio_mask = { 460 DIO_MASK_SH_LIST(_MASK) 461 }; 462 463 static struct dio *dcn10_dio_create(struct dc_context *ctx) 464 { 465 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 466 467 if (!dio10) 468 return NULL; 469 470 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 471 472 return &dio10->base; 473 } 474 475 static int map_transmitter_id_to_phy_instance( 476 enum transmitter transmitter) 477 { 478 switch (transmitter) { 479 case TRANSMITTER_UNIPHY_A: 480 return 0; 481 break; 482 case TRANSMITTER_UNIPHY_B: 483 return 1; 484 break; 485 case TRANSMITTER_UNIPHY_C: 486 return 2; 487 break; 488 case TRANSMITTER_UNIPHY_D: 489 return 3; 490 break; 491 default: 492 ASSERT(0); 493 return 0; 494 } 495 } 496 497 #define clk_src_regs(index, pllid)\ 498 [index] = {\ 499 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 500 } 501 502 static const struct dce110_clk_src_regs clk_src_regs[] = { 503 clk_src_regs(0, A), 504 clk_src_regs(1, B), 505 clk_src_regs(2, C), 506 clk_src_regs(3, D) 507 }; 508 509 static const struct dce110_clk_src_shift cs_shift = { 510 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 511 }; 512 513 static const struct dce110_clk_src_mask cs_mask = { 514 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 515 }; 516 517 static const struct resource_caps res_cap = { 518 .num_timing_generator = 4, 519 .num_opp = 4, 520 .num_video_plane = 4, 521 .num_audio = 4, 522 .num_stream_encoder = 4, 523 .num_pll = 4, 524 .num_ddc = 4, 525 }; 526 527 static const struct resource_caps rv2_res_cap = { 528 .num_timing_generator = 3, 529 .num_opp = 3, 530 .num_video_plane = 3, 531 .num_audio = 3, 532 .num_stream_encoder = 3, 533 .num_pll = 3, 534 .num_ddc = 4, 535 }; 536 537 static const struct dc_plane_cap plane_cap = { 538 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 539 .per_pixel_alpha = true, 540 541 .pixel_format_support = { 542 .argb8888 = true, 543 .nv12 = true, 544 .fp16 = true, 545 .p010 = false 546 }, 547 548 .max_upscale_factor = { 549 .argb8888 = 16000, 550 .nv12 = 16000, 551 .fp16 = 1 552 }, 553 554 .max_downscale_factor = { 555 .argb8888 = 250, 556 .nv12 = 250, 557 .fp16 = 1 558 } 559 }; 560 561 static const struct dc_debug_options debug_defaults_drv = { 562 .sanity_checks = true, 563 .disable_dmcu = false, 564 .force_abm_enable = false, 565 .clock_trace = true, 566 567 /* raven smu dones't allow 0 disp clk, 568 * smu min disp clk limit is 50Mhz 569 * keep min disp clk 100Mhz avoid smu hang 570 */ 571 .min_disp_clk_khz = 100000, 572 573 .disable_pplib_clock_request = false, 574 .disable_pplib_wm_range = false, 575 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 576 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 577 .force_single_disp_pipe_split = true, 578 .disable_dcc = DCC_ENABLE, 579 .voltage_align_fclk = true, 580 .disable_stereo_support = true, 581 .vsr_support = true, 582 .performance_trace = false, 583 .az_endpoint_mute_only = true, 584 .recovery_enabled = false, /*enable this by default after testing.*/ 585 .max_downscale_src_width = 3840, 586 .underflow_assert_delay_us = 0xFFFFFFFF, 587 .using_dml2 = false, 588 }; 589 590 static const struct dc_check_config config_defaults = { 591 .enable_legacy_fast_update = true, 592 }; 593 594 static void dcn10_dpp_destroy(struct dpp **dpp) 595 { 596 kfree(TO_DCN10_DPP(*dpp)); 597 *dpp = NULL; 598 } 599 600 static struct dpp *dcn10_dpp_create( 601 struct dc_context *ctx, 602 uint32_t inst) 603 { 604 struct dcn10_dpp *dpp = 605 kzalloc_obj(struct dcn10_dpp); 606 607 if (!dpp) 608 return NULL; 609 610 dpp1_construct(dpp, ctx, inst, 611 &tf_regs[inst], &tf_shift, &tf_mask); 612 return &dpp->base; 613 } 614 615 static struct input_pixel_processor *dcn10_ipp_create( 616 struct dc_context *ctx, uint32_t inst) 617 { 618 struct dcn10_ipp *ipp = 619 kzalloc_obj(struct dcn10_ipp); 620 621 if (!ipp) { 622 BREAK_TO_DEBUGGER(); 623 return NULL; 624 } 625 626 dcn10_ipp_construct(ipp, ctx, inst, 627 &ipp_regs[inst], &ipp_shift, &ipp_mask); 628 return &ipp->base; 629 } 630 631 632 static struct output_pixel_processor *dcn10_opp_create( 633 struct dc_context *ctx, uint32_t inst) 634 { 635 struct dcn10_opp *opp = 636 kzalloc_obj(struct dcn10_opp); 637 638 if (!opp) { 639 BREAK_TO_DEBUGGER(); 640 return NULL; 641 } 642 643 dcn10_opp_construct(opp, ctx, inst, 644 &opp_regs[inst], &opp_shift, &opp_mask); 645 return &opp->base; 646 } 647 648 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, 649 uint32_t inst) 650 { 651 struct aux_engine_dce110 *aux_engine = 652 kzalloc_obj(struct aux_engine_dce110); 653 654 if (!aux_engine) 655 return NULL; 656 657 dce110_aux_engine_construct(aux_engine, ctx, inst, 658 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 659 &aux_engine_regs[inst], 660 &aux_mask, 661 &aux_shift, 662 ctx->dc->caps.extended_aux_timeout_support); 663 664 return &aux_engine->base; 665 } 666 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 667 668 static const struct dce_i2c_registers i2c_hw_regs[] = { 669 i2c_inst_regs(1), 670 i2c_inst_regs(2), 671 i2c_inst_regs(3), 672 i2c_inst_regs(4), 673 i2c_inst_regs(5), 674 i2c_inst_regs(6), 675 }; 676 677 static const struct dce_i2c_shift i2c_shifts = { 678 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 679 }; 680 681 static const struct dce_i2c_mask i2c_masks = { 682 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 683 }; 684 685 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, 686 uint32_t inst) 687 { 688 struct dce_i2c_hw *dce_i2c_hw = 689 kzalloc_obj(struct dce_i2c_hw); 690 691 if (!dce_i2c_hw) 692 return NULL; 693 694 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 695 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 696 697 return dce_i2c_hw; 698 } 699 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 700 { 701 struct dcn10_mpc *mpc10 = kzalloc_obj(struct dcn10_mpc); 702 703 if (!mpc10) 704 return NULL; 705 706 dcn10_mpc_construct(mpc10, ctx, 707 &mpc_regs, 708 &mpc_shift, 709 &mpc_mask, 710 4); 711 712 return &mpc10->base; 713 } 714 715 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 716 { 717 struct dcn10_hubbub *dcn10_hubbub = kzalloc_obj(struct dcn10_hubbub); 718 719 if (!dcn10_hubbub) 720 return NULL; 721 722 hubbub1_construct(&dcn10_hubbub->base, ctx, 723 &hubbub_reg, 724 &hubbub_shift, 725 &hubbub_mask); 726 727 return &dcn10_hubbub->base; 728 } 729 730 static struct timing_generator *dcn10_timing_generator_create( 731 struct dc_context *ctx, 732 uint32_t instance) 733 { 734 struct optc *tgn10 = 735 kzalloc_obj(struct optc); 736 737 if (!tgn10) 738 return NULL; 739 740 tgn10->base.inst = instance; 741 tgn10->base.ctx = ctx; 742 743 tgn10->tg_regs = &tg_regs[instance]; 744 tgn10->tg_shift = &tg_shift; 745 tgn10->tg_mask = &tg_mask; 746 747 dcn10_timing_generator_init(tgn10); 748 749 return &tgn10->base; 750 } 751 752 static const struct encoder_feature_support link_enc_feature = { 753 .max_hdmi_deep_color = COLOR_DEPTH_121212, 754 .max_hdmi_pixel_clock = 600000, 755 .hdmi_ycbcr420_supported = true, 756 .dp_ycbcr420_supported = true, 757 .flags.bits.IS_HBR2_CAPABLE = true, 758 .flags.bits.IS_HBR3_CAPABLE = true, 759 .flags.bits.IS_TPS3_CAPABLE = true, 760 .flags.bits.IS_TPS4_CAPABLE = true 761 }; 762 763 static struct link_encoder *dcn10_link_encoder_create( 764 struct dc_context *ctx, 765 const struct encoder_init_data *enc_init_data) 766 { 767 struct dcn10_link_encoder *enc10 = 768 kzalloc_obj(struct dcn10_link_encoder); 769 int link_regs_id; 770 771 if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 772 return NULL; 773 774 link_regs_id = 775 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 776 777 dcn10_link_encoder_construct(enc10, 778 enc_init_data, 779 &link_enc_feature, 780 &link_enc_regs[link_regs_id], 781 &link_enc_aux_regs[enc_init_data->channel - 1], 782 &link_enc_hpd_regs[enc_init_data->hpd_source], 783 &le_shift, 784 &le_mask); 785 786 return &enc10->base; 787 } 788 789 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) 790 { 791 struct dce_panel_cntl *panel_cntl = 792 kzalloc_obj(struct dce_panel_cntl); 793 794 if (!panel_cntl) 795 return NULL; 796 797 dce_panel_cntl_construct(panel_cntl, 798 init_data, 799 &panel_cntl_regs[init_data->inst], 800 &panel_cntl_shift, 801 &panel_cntl_mask); 802 803 return &panel_cntl->base; 804 } 805 806 static struct clock_source *dcn10_clock_source_create( 807 struct dc_context *ctx, 808 struct dc_bios *bios, 809 enum clock_source_id id, 810 const struct dce110_clk_src_regs *regs, 811 bool dp_clk_src) 812 { 813 struct dce110_clk_src *clk_src = 814 kzalloc_obj(struct dce110_clk_src); 815 816 if (!clk_src) 817 return NULL; 818 819 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 820 regs, &cs_shift, &cs_mask)) { 821 clk_src->base.dp_clk_src = dp_clk_src; 822 return &clk_src->base; 823 } 824 825 kfree(clk_src); 826 BREAK_TO_DEBUGGER(); 827 return NULL; 828 } 829 830 static void read_dce_straps( 831 struct dc_context *ctx, 832 struct resource_straps *straps) 833 { 834 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 835 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 836 } 837 838 static struct audio *create_audio( 839 struct dc_context *ctx, unsigned int inst) 840 { 841 return dce_audio_create(ctx, inst, 842 &audio_regs[inst], &audio_shift, &audio_mask); 843 } 844 845 static struct stream_encoder *dcn10_stream_encoder_create( 846 enum engine_id eng_id, 847 struct dc_context *ctx) 848 { 849 struct dcn10_stream_encoder *enc1 = 850 kzalloc_obj(struct dcn10_stream_encoder); 851 852 if (!enc1) 853 return NULL; 854 855 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 856 &stream_enc_regs[eng_id], 857 &se_shift, &se_mask); 858 return &enc1->base; 859 } 860 861 static const struct dce_hwseq_registers hwseq_reg = { 862 HWSEQ_DCN1_REG_LIST() 863 }; 864 865 static const struct dce_hwseq_shift hwseq_shift = { 866 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 867 }; 868 869 static const struct dce_hwseq_mask hwseq_mask = { 870 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 871 }; 872 873 static struct dce_hwseq *dcn10_hwseq_create( 874 struct dc_context *ctx) 875 { 876 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 877 878 if (hws) { 879 hws->ctx = ctx; 880 hws->regs = &hwseq_reg; 881 hws->shifts = &hwseq_shift; 882 hws->masks = &hwseq_mask; 883 hws->wa.DEGVIDCN10_253 = true; 884 hws->wa.false_optc_underflow = true; 885 hws->wa.DEGVIDCN10_254 = true; 886 887 if ((ctx->asic_id.chip_family == FAMILY_RV) && 888 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev)) 889 switch (ctx->asic_id.pci_revision_id) { 890 case PRID_POLLOCK_94: 891 case PRID_POLLOCK_95: 892 case PRID_POLLOCK_E9: 893 case PRID_POLLOCK_EA: 894 case PRID_POLLOCK_EB: 895 hws->wa.wait_hubpret_read_start_during_mpo_transition = true; 896 break; 897 default: 898 hws->wa.wait_hubpret_read_start_during_mpo_transition = false; 899 break; 900 } 901 } 902 return hws; 903 } 904 905 static const struct resource_create_funcs res_create_funcs = { 906 .read_dce_straps = read_dce_straps, 907 .create_audio = create_audio, 908 .create_stream_encoder = dcn10_stream_encoder_create, 909 .create_hwseq = dcn10_hwseq_create, 910 }; 911 912 static void dcn10_clock_source_destroy(struct clock_source **clk_src) 913 { 914 kfree(TO_DCE110_CLK_SRC(*clk_src)); 915 *clk_src = NULL; 916 } 917 918 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 919 { 920 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu); 921 922 if (!pp_smu) 923 return pp_smu; 924 925 dm_pp_get_funcs(ctx, pp_smu); 926 return pp_smu; 927 } 928 929 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) 930 { 931 unsigned int i; 932 933 for (i = 0; i < pool->base.stream_enc_count; i++) { 934 if (pool->base.stream_enc[i] != NULL) { 935 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 936 pool->base.stream_enc[i] = NULL; 937 } 938 } 939 940 if (pool->base.mpc != NULL) { 941 kfree(TO_DCN10_MPC(pool->base.mpc)); 942 pool->base.mpc = NULL; 943 } 944 945 kfree(pool->base.hubbub); 946 pool->base.hubbub = NULL; 947 948 if (pool->base.dio != NULL) { 949 kfree(TO_DCN10_DIO(pool->base.dio)); 950 pool->base.dio = NULL; 951 } 952 953 for (i = 0; i < pool->base.pipe_count; i++) { 954 if (pool->base.opps[i] != NULL) 955 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 956 957 if (pool->base.dpps[i] != NULL) 958 dcn10_dpp_destroy(&pool->base.dpps[i]); 959 960 if (pool->base.ipps[i] != NULL) 961 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 962 963 if (pool->base.hubps[i] != NULL) { 964 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 965 pool->base.hubps[i] = NULL; 966 } 967 968 if (pool->base.irqs != NULL) { 969 dal_irq_service_destroy(&pool->base.irqs); 970 } 971 972 if (pool->base.timing_generators[i] != NULL) { 973 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 974 pool->base.timing_generators[i] = NULL; 975 } 976 } 977 978 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 979 if (pool->base.engines[i] != NULL) 980 dce110_engine_destroy(&pool->base.engines[i]); 981 kfree(pool->base.hw_i2cs[i]); 982 pool->base.hw_i2cs[i] = NULL; 983 kfree(pool->base.sw_i2cs[i]); 984 pool->base.sw_i2cs[i] = NULL; 985 } 986 987 for (i = 0; i < pool->base.audio_count; i++) { 988 if (pool->base.audios[i]) 989 dce_aud_destroy(&pool->base.audios[i]); 990 } 991 992 for (i = 0; i < pool->base.clk_src_count; i++) { 993 if (pool->base.clock_sources[i] != NULL) { 994 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 995 pool->base.clock_sources[i] = NULL; 996 } 997 } 998 999 if (pool->base.dp_clock_source != NULL) { 1000 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 1001 pool->base.dp_clock_source = NULL; 1002 } 1003 1004 if (pool->base.abm != NULL) 1005 dce_abm_destroy(&pool->base.abm); 1006 1007 if (pool->base.dmcu != NULL) 1008 dce_dmcu_destroy(&pool->base.dmcu); 1009 1010 kfree(pool->base.pp_smu); 1011 } 1012 1013 static struct hubp *dcn10_hubp_create( 1014 struct dc_context *ctx, 1015 uint32_t inst) 1016 { 1017 struct dcn10_hubp *hubp1 = 1018 kzalloc_obj(struct dcn10_hubp); 1019 1020 if (!hubp1) 1021 return NULL; 1022 1023 dcn10_hubp_construct(hubp1, ctx, inst, 1024 &hubp_regs[inst], &hubp_shift, &hubp_mask); 1025 return &hubp1->base; 1026 } 1027 1028 static void get_pixel_clock_parameters( 1029 const struct pipe_ctx *pipe_ctx, 1030 struct pixel_clk_params *pixel_clk_params) 1031 { 1032 const struct dc_stream_state *stream = pipe_ctx->stream; 1033 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1034 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1035 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1036 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1037 /* TODO: un-hardcode*/ 1038 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1039 LINK_RATE_REF_FREQ_IN_KHZ; 1040 pixel_clk_params->flags.ENABLE_SS = 0; 1041 pixel_clk_params->color_depth = 1042 stream->timing.display_color_depth; 1043 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1044 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1045 1046 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1047 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1048 1049 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1050 pixel_clk_params->requested_pix_clk_100hz /= 2; 1051 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1052 pixel_clk_params->requested_pix_clk_100hz *= 2; 1053 1054 } 1055 1056 static void build_clamping_params(struct dc_stream_state *stream) 1057 { 1058 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1059 stream->clamping.c_depth = stream->timing.display_color_depth; 1060 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1061 } 1062 1063 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1064 { 1065 1066 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1067 1068 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1069 pipe_ctx->clock_source, 1070 &pipe_ctx->stream_res.pix_clk_params, 1071 &pipe_ctx->pll_settings); 1072 1073 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1074 1075 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1076 &pipe_ctx->stream->bit_depth_params); 1077 build_clamping_params(pipe_ctx->stream); 1078 } 1079 1080 static enum dc_status build_mapped_resource( 1081 const struct dc *dc, 1082 struct dc_state *context, 1083 struct dc_stream_state *stream) 1084 { 1085 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1086 1087 if (!pipe_ctx) 1088 return DC_ERROR_UNEXPECTED; 1089 1090 build_pipe_hw_param(pipe_ctx); 1091 return DC_OK; 1092 } 1093 1094 static enum dc_status dcn10_add_stream_to_ctx( 1095 struct dc *dc, 1096 struct dc_state *new_ctx, 1097 struct dc_stream_state *dc_stream) 1098 { 1099 enum dc_status result = DC_ERROR_UNEXPECTED; 1100 1101 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1102 1103 if (result == DC_OK) 1104 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1105 1106 1107 if (result == DC_OK) 1108 result = build_mapped_resource(dc, new_ctx, dc_stream); 1109 1110 return result; 1111 } 1112 1113 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( 1114 const struct dc_state *cur_ctx, 1115 struct dc_state *new_ctx, 1116 const struct resource_pool *pool, 1117 const struct pipe_ctx *opp_head_pipe) 1118 { 1119 struct resource_context *res_ctx = &new_ctx->res_ctx; 1120 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream); 1121 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe); 1122 1123 if (!head_pipe) { 1124 ASSERT(0); 1125 return NULL; 1126 } 1127 1128 if (!idle_pipe) 1129 return NULL; 1130 1131 idle_pipe->stream = head_pipe->stream; 1132 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1133 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1134 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1135 1136 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1137 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1138 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1139 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1140 1141 return idle_pipe; 1142 } 1143 1144 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1145 const struct dc_dcc_surface_param *input, 1146 struct dc_surface_dcc_cap *output) 1147 { 1148 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1149 dc->res_pool->hubbub, 1150 input, 1151 output); 1152 } 1153 1154 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1155 { 1156 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1157 1158 dcn10_resource_destruct(dcn10_pool); 1159 kfree(dcn10_pool); 1160 *pool = NULL; 1161 } 1162 1163 static enum dc_status dcn10_validate_bandwidth( 1164 struct dc *dc, 1165 struct dc_state *context, 1166 enum dc_validate_mode validate_mode) 1167 { 1168 bool voltage_supported; 1169 1170 DC_FP_START(); 1171 voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode); 1172 DC_FP_END(); 1173 1174 return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1175 } 1176 1177 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1178 { 1179 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1180 && caps->max_video_width != 0 1181 && plane_state->src_rect.width > caps->max_video_width) 1182 return DC_FAIL_SURFACE_VALIDATE; 1183 1184 return DC_OK; 1185 } 1186 1187 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1188 { 1189 int i, j; 1190 bool video_down_scaled = false; 1191 bool video_large = false; 1192 bool desktop_large = false; 1193 bool dcc_disabled = false; 1194 bool mpo_enabled = false; 1195 1196 for (i = 0; i < context->stream_count; i++) { 1197 if (context->stream_status[i].plane_count == 0) 1198 continue; 1199 1200 if (context->stream_status[i].plane_count > 2) 1201 return DC_FAIL_UNSUPPORTED_1; 1202 1203 if (context->stream_status[i].plane_count > 1) 1204 mpo_enabled = true; 1205 1206 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1207 struct dc_plane_state *plane = 1208 context->stream_status[i].plane_states[j]; 1209 1210 1211 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1212 1213 if (plane->src_rect.width > plane->dst_rect.width || 1214 plane->src_rect.height > plane->dst_rect.height) 1215 video_down_scaled = true; 1216 1217 if (plane->src_rect.width >= 3840) 1218 video_large = true; 1219 1220 } else { 1221 if (plane->src_rect.width >= 3840) 1222 desktop_large = true; 1223 if (!plane->dcc.enable) 1224 dcc_disabled = true; 1225 } 1226 } 1227 } 1228 1229 /* Disable MPO in multi-display configurations. */ 1230 if (context->stream_count > 1 && mpo_enabled) 1231 return DC_FAIL_UNSUPPORTED_1; 1232 1233 /* 1234 * Workaround: On DCN10 there is UMC issue that causes underflow when 1235 * playing 4k video on 4k desktop with video downscaled and single channel 1236 * memory 1237 */ 1238 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1239 dc->dcn_soc->number_of_channels == 1) 1240 return DC_FAIL_SURFACE_VALIDATE; 1241 1242 return DC_OK; 1243 } 1244 1245 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1246 { 1247 enum surface_pixel_format surf_pix_format = plane_state->format; 1248 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1249 1250 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1251 1252 if (bpp == 64) 1253 swizzle = DC_SW_64KB_D; 1254 else 1255 swizzle = DC_SW_64KB_S; 1256 1257 plane_state->tiling_info.gfx9.swizzle = swizzle; 1258 return DC_OK; 1259 } 1260 1261 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1262 struct resource_context *res_ctx, 1263 const struct resource_pool *pool, 1264 struct dc_stream_state *stream) 1265 { 1266 int i; 1267 int j = -1; 1268 struct dc_link *link = stream->link; 1269 1270 for (i = 0; i < pool->stream_enc_count; i++) { 1271 if (!res_ctx->is_stream_enc_acquired[i] && 1272 pool->stream_enc[i]) { 1273 /* Store first available for MST second display 1274 * in daisy chain use case 1275 */ 1276 1277 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL) 1278 j = i; 1279 1280 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == 1281 link->link_enc->preferred_engine) 1282 return pool->stream_enc[i]; 1283 1284 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id == 1285 link->dpia_preferred_eng_id) 1286 return pool->stream_enc[i]; 1287 } 1288 } 1289 1290 /* 1291 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1292 */ 1293 1294 if (j >= 0) 1295 return pool->stream_enc[j]; 1296 1297 return NULL; 1298 } 1299 1300 unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) 1301 { 1302 return pipe_ctx->pipe_dlg_param.vstartup_start; 1303 } 1304 1305 static const struct dc_cap_funcs cap_funcs = { 1306 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1307 }; 1308 1309 static const struct resource_funcs dcn10_res_pool_funcs = { 1310 .destroy = dcn10_destroy_resource_pool, 1311 .link_enc_create = dcn10_link_encoder_create, 1312 .panel_cntl_create = dcn10_panel_cntl_create, 1313 .validate_bandwidth = dcn10_validate_bandwidth, 1314 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer, 1315 .validate_plane = dcn10_validate_plane, 1316 .validate_global = dcn10_validate_global, 1317 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1318 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, 1319 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1320 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe 1321 }; 1322 1323 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1324 { 1325 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1326 /* RV1 support max 4 pipes */ 1327 value = value & 0xf; 1328 return value; 1329 } 1330 1331 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1332 { 1333 int i; 1334 1335 if (clks->num_levels == 0) 1336 return false; 1337 1338 for (i = 0; i < clks->num_levels; i++) 1339 /* Ensure that the result is sane */ 1340 if (clks->data[i].clocks_in_khz == 0) 1341 return false; 1342 1343 return true; 1344 } 1345 1346 static bool dcn10_resource_construct( 1347 uint8_t num_virtual_links, 1348 struct dc *dc, 1349 struct dcn10_resource_pool *pool) 1350 { 1351 int i; 1352 int j; 1353 struct dc_context *ctx = dc->ctx; 1354 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1355 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; 1356 int min_fclk_khz, min_dcfclk_khz, socclk_khz; 1357 bool res; 1358 1359 ctx->dc_bios->regs = &bios_regs; 1360 1361 if (ctx->dce_version == DCN_VERSION_1_01) 1362 pool->base.res_cap = &rv2_res_cap; 1363 else 1364 pool->base.res_cap = &res_cap; 1365 pool->base.funcs = &dcn10_res_pool_funcs; 1366 1367 /* 1368 * TODO fill in from actual raven resource when we create 1369 * more than virtual encoder 1370 */ 1371 1372 /************************************************* 1373 * Resource + asic cap harcoding * 1374 *************************************************/ 1375 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1376 1377 /* max pipe num for ASIC before check pipe fuses */ 1378 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1379 1380 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1381 pool->base.pipe_count = 3; 1382 dc->caps.max_video_width = 3840; 1383 dc->caps.max_downscale_ratio = 200; 1384 dc->caps.i2c_speed_in_khz = 100; 1385 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1386 dc->caps.max_cursor_size = 256; 1387 dc->caps.min_horizontal_blanking_period = 80; 1388 dc->caps.max_slave_planes = 1; 1389 dc->caps.max_slave_yuv_planes = 1; 1390 dc->caps.max_slave_rgb_planes = 0; 1391 dc->caps.is_apu = true; 1392 dc->caps.post_blend_color_processing = false; 1393 dc->caps.extended_aux_timeout_support = false; 1394 1395 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1396 dc->caps.force_dp_tps4_for_cp2520 = true; 1397 1398 /* Color pipeline capabilities */ 1399 dc->caps.color.dpp.dcn_arch = 1; 1400 dc->caps.color.dpp.input_lut_shared = 1; 1401 dc->caps.color.dpp.icsc = 1; 1402 dc->caps.color.dpp.dgam_ram = 1; 1403 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1404 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1405 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1406 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1407 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1408 dc->caps.color.dpp.post_csc = 0; 1409 dc->caps.color.dpp.gamma_corr = 0; 1410 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1411 1412 dc->caps.color.dpp.hw_3d_lut = 0; 1413 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1 1414 dc->caps.color.dpp.ogam_rom_caps.srgb = 1; 1415 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1; 1416 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1417 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1418 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1419 dc->caps.color.dpp.ocsc = 1; 1420 1421 /* no post-blend color operations */ 1422 dc->caps.color.mpc.gamut_remap = 0; 1423 dc->caps.color.mpc.num_3dluts = 0; 1424 dc->caps.color.mpc.shared_3d_lut = 0; 1425 dc->caps.color.mpc.ogam_ram = 0; 1426 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1427 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1428 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1429 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1430 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1431 dc->caps.color.mpc.ocsc = 0; 1432 dc->debug = debug_defaults_drv; 1433 dc->check_config = config_defaults; 1434 1435 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1436 dc->debug = debug_defaults_drv; 1437 1438 /************************************************* 1439 * Create resources * 1440 *************************************************/ 1441 1442 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1443 dcn10_clock_source_create(ctx, ctx->dc_bios, 1444 CLOCK_SOURCE_COMBO_PHY_PLL0, 1445 &clk_src_regs[0], false); 1446 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1447 dcn10_clock_source_create(ctx, ctx->dc_bios, 1448 CLOCK_SOURCE_COMBO_PHY_PLL1, 1449 &clk_src_regs[1], false); 1450 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1451 dcn10_clock_source_create(ctx, ctx->dc_bios, 1452 CLOCK_SOURCE_COMBO_PHY_PLL2, 1453 &clk_src_regs[2], false); 1454 1455 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1456 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1457 dcn10_clock_source_create(ctx, ctx->dc_bios, 1458 CLOCK_SOURCE_COMBO_PHY_PLL3, 1459 &clk_src_regs[3], false); 1460 } 1461 1462 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1463 1464 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1465 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1466 1467 pool->base.dp_clock_source = 1468 dcn10_clock_source_create(ctx, ctx->dc_bios, 1469 CLOCK_SOURCE_ID_DP_DTO, 1470 /* todo: not reuse phy_pll registers */ 1471 &clk_src_regs[0], true); 1472 1473 for (i = 0; i < pool->base.clk_src_count; i++) { 1474 if (pool->base.clock_sources[i] == NULL) { 1475 dm_error("DC: failed to create clock sources!\n"); 1476 BREAK_TO_DEBUGGER(); 1477 goto fail; 1478 } 1479 } 1480 1481 pool->base.dmcu = dcn10_dmcu_create(ctx, 1482 &dmcu_regs, 1483 &dmcu_shift, 1484 &dmcu_mask); 1485 if (pool->base.dmcu == NULL) { 1486 dm_error("DC: failed to create dmcu!\n"); 1487 BREAK_TO_DEBUGGER(); 1488 goto fail; 1489 } 1490 1491 pool->base.abm = dce_abm_create(ctx, 1492 &abm_regs, 1493 &abm_shift, 1494 &abm_mask); 1495 if (pool->base.abm == NULL) { 1496 dm_error("DC: failed to create abm!\n"); 1497 BREAK_TO_DEBUGGER(); 1498 goto fail; 1499 } 1500 1501 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1502 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1503 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1504 1505 DC_FP_START(); 1506 dcn10_resource_construct_fp(dc); 1507 DC_FP_END(); 1508 1509 if (!dc->config.is_vmin_only_asic) 1510 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev)) 1511 switch (dc->ctx->asic_id.pci_revision_id) { 1512 case PRID_DALI_DE: 1513 case PRID_DALI_DF: 1514 case PRID_DALI_E3: 1515 case PRID_DALI_E4: 1516 case PRID_POLLOCK_94: 1517 case PRID_POLLOCK_95: 1518 case PRID_POLLOCK_E9: 1519 case PRID_POLLOCK_EA: 1520 case PRID_POLLOCK_EB: 1521 dc->config.is_vmin_only_asic = true; 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1528 1529 /* 1530 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1531 * implemented. So AZ D3 should work.For issue 197007. * 1532 */ 1533 if (pool->base.pp_smu != NULL 1534 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1535 dc->debug.az_endpoint_mute_only = false; 1536 1537 1538 if (!dc->debug.disable_pplib_clock_request) { 1539 /* 1540 * TODO: This is not the proper way to obtain 1541 * fabric_and_dram_bandwidth, should be min(fclk, memclk). 1542 */ 1543 res = dm_pp_get_clock_levels_by_type_with_voltage( 1544 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); 1545 1546 DC_FP_START(); 1547 1548 if (res) 1549 res = verify_clock_values(&fclks); 1550 1551 if (res) 1552 dcn_bw_update_from_pplib_fclks(dc, &fclks); 1553 else 1554 BREAK_TO_DEBUGGER(); 1555 1556 DC_FP_END(); 1557 1558 res = dm_pp_get_clock_levels_by_type_with_voltage( 1559 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); 1560 1561 DC_FP_START(); 1562 1563 if (res) 1564 res = verify_clock_values(&dcfclks); 1565 1566 if (res) 1567 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks); 1568 else 1569 BREAK_TO_DEBUGGER(); 1570 1571 DC_FP_END(); 1572 } 1573 1574 dcn_bw_sync_calcs_and_dml(dc); 1575 if (!dc->debug.disable_pplib_wm_range) { 1576 dc->res_pool = &pool->base; 1577 DC_FP_START(); 1578 dcn_get_soc_clks( 1579 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz); 1580 DC_FP_END(); 1581 dcn_bw_notify_pplib_of_wm_ranges( 1582 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz); 1583 } 1584 1585 { 1586 struct irq_service_init_data init_data; 1587 init_data.ctx = dc->ctx; 1588 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1589 if (!pool->base.irqs) 1590 goto fail; 1591 } 1592 1593 /* index to valid pipe resource */ 1594 j = 0; 1595 /* mem input -> ipp -> dpp -> opp -> TG */ 1596 for (i = 0; i < pool->base.pipe_count; i++) { 1597 /* if pipe is disabled, skip instance of HW pipe, 1598 * i.e, skip ASIC register instance 1599 */ 1600 if ((pipe_fuses & (1 << i)) != 0) 1601 continue; 1602 1603 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1604 if (pool->base.hubps[j] == NULL) { 1605 BREAK_TO_DEBUGGER(); 1606 dm_error( 1607 "DC: failed to create memory input!\n"); 1608 goto fail; 1609 } 1610 1611 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1612 if (pool->base.ipps[j] == NULL) { 1613 BREAK_TO_DEBUGGER(); 1614 dm_error( 1615 "DC: failed to create input pixel processor!\n"); 1616 goto fail; 1617 } 1618 1619 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1620 if (pool->base.dpps[j] == NULL) { 1621 BREAK_TO_DEBUGGER(); 1622 dm_error( 1623 "DC: failed to create dpp!\n"); 1624 goto fail; 1625 } 1626 1627 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1628 if (pool->base.opps[j] == NULL) { 1629 BREAK_TO_DEBUGGER(); 1630 dm_error( 1631 "DC: failed to create output pixel processor!\n"); 1632 goto fail; 1633 } 1634 1635 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1636 ctx, i); 1637 if (pool->base.timing_generators[j] == NULL) { 1638 BREAK_TO_DEBUGGER(); 1639 dm_error("DC: failed to create tg!\n"); 1640 goto fail; 1641 } 1642 /* check next valid pipe */ 1643 j++; 1644 } 1645 1646 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1647 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1648 if (pool->base.engines[i] == NULL) { 1649 BREAK_TO_DEBUGGER(); 1650 dm_error( 1651 "DC:failed to create aux engine!!\n"); 1652 goto fail; 1653 } 1654 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1655 if (pool->base.hw_i2cs[i] == NULL) { 1656 BREAK_TO_DEBUGGER(); 1657 dm_error( 1658 "DC:failed to create hw i2c!!\n"); 1659 goto fail; 1660 } 1661 pool->base.sw_i2cs[i] = NULL; 1662 } 1663 1664 /* valid pipe num */ 1665 pool->base.pipe_count = j; 1666 pool->base.timing_generator_count = j; 1667 pool->base.mpcc_count = j; 1668 1669 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1670 * the value may be changed 1671 */ 1672 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1673 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1674 1675 pool->base.mpc = dcn10_mpc_create(ctx); 1676 if (pool->base.mpc == NULL) { 1677 BREAK_TO_DEBUGGER(); 1678 dm_error("DC: failed to create mpc!\n"); 1679 goto fail; 1680 } 1681 1682 pool->base.hubbub = dcn10_hubbub_create(ctx); 1683 if (pool->base.hubbub == NULL) { 1684 BREAK_TO_DEBUGGER(); 1685 dm_error("DC: failed to create hubbub!\n"); 1686 goto fail; 1687 } 1688 1689 /* DIO */ 1690 pool->base.dio = dcn10_dio_create(ctx); 1691 if (pool->base.dio == NULL) { 1692 BREAK_TO_DEBUGGER(); 1693 dm_error("DC: failed to create dio!\n"); 1694 goto fail; 1695 } 1696 1697 if (!resource_construct(num_virtual_links, dc, &pool->base, 1698 &res_create_funcs)) 1699 goto fail; 1700 1701 dcn10_hw_sequencer_construct(dc); 1702 dc->caps.max_planes = pool->base.pipe_count; 1703 1704 for (i = 0; i < dc->caps.max_planes; ++i) 1705 dc->caps.planes[i] = plane_cap; 1706 1707 dc->cap_funcs = cap_funcs; 1708 1709 return true; 1710 1711 fail: 1712 1713 dcn10_resource_destruct(pool); 1714 1715 return false; 1716 } 1717 1718 struct resource_pool *dcn10_create_resource_pool( 1719 const struct dc_init_data *init_data, 1720 struct dc *dc) 1721 { 1722 struct dcn10_resource_pool *pool = 1723 kzalloc_obj(struct dcn10_resource_pool); 1724 1725 if (!pool) 1726 return NULL; 1727 1728 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) 1729 return &pool->base; 1730 1731 kfree(pool); 1732 BREAK_TO_DEBUGGER(); 1733 return NULL; 1734 } 1735