1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce/dce_8_0_d.h"
27 #include "dce/dce_8_0_sh_mask.h"
28
29 #include "dm_services.h"
30
31 #include "link_encoder.h"
32 #include "stream_encoder.h"
33
34 #include "resource.h"
35 #include "clk_mgr.h"
36 #include "include/irq_service_interface.h"
37 #include "irq/dce80/irq_service_dce80.h"
38 #include "dce110/dce110_timing_generator.h"
39 #include "dce110/dce110_resource.h"
40 #include "dce80/dce80_timing_generator.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_link_encoder.h"
43 #include "dce/dce_stream_encoder.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_transform.h"
46 #include "dce/dce_opp.h"
47 #include "dce/dce_clock_source.h"
48 #include "dce/dce_audio.h"
49 #include "dce/dce_hwseq.h"
50 #include "dce80/dce80_hwseq.h"
51 #include "dce100/dce100_resource.h"
52 #include "dce/dce_panel_cntl.h"
53
54 #include "reg_helper.h"
55
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_abm.h"
59 #include "dce/dce_i2c.h"
60
61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
62 #include "gmc/gmc_7_1_d.h"
63 #include "gmc/gmc_7_1_sh_mask.h"
64 #endif
65
66 #include "dce80/dce80_resource.h"
67
68 #ifndef mmDP_DPHY_INTERNAL_CTRL
69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
76 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
77 #endif
78
79
80 #ifndef mmBIOS_SCRATCH_2
81 #define mmBIOS_SCRATCH_0 0x05C9
82 #define mmBIOS_SCRATCH_2 0x05CB
83 #define mmBIOS_SCRATCH_3 0x05CC
84 #define mmBIOS_SCRATCH_6 0x05CF
85 #endif
86
87 #ifndef mmDP_DPHY_FAST_TRAINING
88 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
89 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
90 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
91 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
92 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
93 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
94 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
95 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
96 #endif
97
98
99 #ifndef mmHPD_DC_HPD_CONTROL
100 #define mmHPD_DC_HPD_CONTROL 0x189A
101 #define mmHPD0_DC_HPD_CONTROL 0x189A
102 #define mmHPD1_DC_HPD_CONTROL 0x18A2
103 #define mmHPD2_DC_HPD_CONTROL 0x18AA
104 #define mmHPD3_DC_HPD_CONTROL 0x18B2
105 #define mmHPD4_DC_HPD_CONTROL 0x18BA
106 #define mmHPD5_DC_HPD_CONTROL 0x18C2
107 #endif
108
109 #define DCE11_DIG_FE_CNTL 0x4a00
110 #define DCE11_DIG_BE_CNTL 0x4a47
111 #define DCE11_DP_SEC 0x4ac3
112
113 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
114 {
115 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
117 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
118 - mmDPG_WATERMARK_MASK_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
123 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
124 - mmDPG_WATERMARK_MASK_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
129 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
130 - mmDPG_WATERMARK_MASK_CONTROL),
131 },
132 {
133 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
134 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
135 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
136 - mmDPG_WATERMARK_MASK_CONTROL),
137 },
138 {
139 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
140 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
141 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
142 - mmDPG_WATERMARK_MASK_CONTROL),
143 },
144 {
145 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
146 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
147 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
148 - mmDPG_WATERMARK_MASK_CONTROL),
149 }
150 };
151
152 /* set register offset */
153 #define SR(reg_name)\
154 .reg_name = mm ## reg_name
155
156 /* set register offset with instance */
157 #define SRI(reg_name, block, id)\
158 .reg_name = mm ## block ## id ## _ ## reg_name
159
160 #define ipp_regs(id)\
161 [id] = {\
162 IPP_COMMON_REG_LIST_DCE_BASE(id)\
163 }
164
165 static const struct dce_ipp_registers ipp_regs[] = {
166 ipp_regs(0),
167 ipp_regs(1),
168 ipp_regs(2),
169 ipp_regs(3),
170 ipp_regs(4),
171 ipp_regs(5)
172 };
173
174 static const struct dce_ipp_shift ipp_shift = {
175 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
176 };
177
178 static const struct dce_ipp_mask ipp_mask = {
179 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
180 };
181
182 #define transform_regs(id)\
183 [id] = {\
184 XFM_COMMON_REG_LIST_DCE80(id)\
185 }
186
187 static const struct dce_transform_registers xfm_regs[] = {
188 transform_regs(0),
189 transform_regs(1),
190 transform_regs(2),
191 transform_regs(3),
192 transform_regs(4),
193 transform_regs(5)
194 };
195
196 static const struct dce_transform_shift xfm_shift = {
197 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
198 };
199
200 static const struct dce_transform_mask xfm_mask = {
201 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
202 };
203
204 #define aux_regs(id)\
205 [id] = {\
206 AUX_REG_LIST(id)\
207 }
208
209 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
210 aux_regs(0),
211 aux_regs(1),
212 aux_regs(2),
213 aux_regs(3),
214 aux_regs(4),
215 aux_regs(5)
216 };
217
218 #define hpd_regs(id)\
219 [id] = {\
220 HPD_REG_LIST(id)\
221 }
222
223 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
224 hpd_regs(0),
225 hpd_regs(1),
226 hpd_regs(2),
227 hpd_regs(3),
228 hpd_regs(4),
229 hpd_regs(5)
230 };
231
232 #define link_regs(id)\
233 [id] = {\
234 LE_DCE80_REG_LIST(id)\
235 }
236
237 static const struct dce110_link_enc_registers link_enc_regs[] = {
238 link_regs(0),
239 link_regs(1),
240 link_regs(2),
241 link_regs(3),
242 link_regs(4),
243 link_regs(5),
244 link_regs(6),
245 {0}
246 };
247
248 #define stream_enc_regs(id)\
249 [id] = {\
250 SE_COMMON_REG_LIST_DCE_BASE(id),\
251 .AFMT_CNTL = 0,\
252 }
253
254 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
255 stream_enc_regs(0),
256 stream_enc_regs(1),
257 stream_enc_regs(2),
258 stream_enc_regs(3),
259 stream_enc_regs(4),
260 stream_enc_regs(5),
261 stream_enc_regs(6),
262 {SR(DAC_SOURCE_SELECT),} /* DACA */
263 };
264
265 static const struct dce_stream_encoder_shift se_shift = {
266 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
267 };
268
269 static const struct dce_stream_encoder_mask se_mask = {
270 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
271 };
272
273 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
274 { DCE_PANEL_CNTL_REG_LIST() }
275 };
276
277 static const struct dce_panel_cntl_shift panel_cntl_shift = {
278 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dce_panel_cntl_mask panel_cntl_mask = {
282 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
283 };
284
285 #define opp_regs(id)\
286 [id] = {\
287 OPP_DCE_80_REG_LIST(id),\
288 }
289
290 static const struct dce_opp_registers opp_regs[] = {
291 opp_regs(0),
292 opp_regs(1),
293 opp_regs(2),
294 opp_regs(3),
295 opp_regs(4),
296 opp_regs(5)
297 };
298
299 static const struct dce_opp_shift opp_shift = {
300 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
301 };
302
303 static const struct dce_opp_mask opp_mask = {
304 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
305 };
306
307 static const struct dce110_aux_registers_shift aux_shift = {
308 DCE10_AUX_MASK_SH_LIST(__SHIFT)
309 };
310
311 static const struct dce110_aux_registers_mask aux_mask = {
312 DCE10_AUX_MASK_SH_LIST(_MASK)
313 };
314
315 #define aux_engine_regs(id)\
316 [id] = {\
317 AUX_COMMON_REG_LIST(id), \
318 .AUX_RESET_MASK = 0 \
319 }
320
321 static const struct dce110_aux_registers aux_engine_regs[] = {
322 aux_engine_regs(0),
323 aux_engine_regs(1),
324 aux_engine_regs(2),
325 aux_engine_regs(3),
326 aux_engine_regs(4),
327 aux_engine_regs(5)
328 };
329
330 #define audio_regs(id)\
331 [id] = {\
332 AUD_COMMON_REG_LIST(id)\
333 }
334
335 static const struct dce_audio_registers audio_regs[] = {
336 audio_regs(0),
337 audio_regs(1),
338 audio_regs(2),
339 audio_regs(3),
340 audio_regs(4),
341 audio_regs(5),
342 audio_regs(6),
343 };
344
345 static const struct dce_audio_shift audio_shift = {
346 AUD_COMMON_MASK_SH_LIST(__SHIFT)
347 };
348
349 static const struct dce_audio_mask audio_mask = {
350 AUD_COMMON_MASK_SH_LIST(_MASK)
351 };
352
353 #define clk_src_regs(id)\
354 [id] = {\
355 CS_COMMON_REG_LIST_DCE_80(id),\
356 }
357
358
359 static const struct dce110_clk_src_regs clk_src_regs[] = {
360 clk_src_regs(0),
361 clk_src_regs(1),
362 clk_src_regs(2)
363 };
364
365 static const struct dce110_clk_src_shift cs_shift = {
366 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
367 };
368
369 static const struct dce110_clk_src_mask cs_mask = {
370 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
371 };
372
373 static const struct bios_registers bios_regs = {
374 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0,
375 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
376 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
377 };
378
379 static const struct resource_caps res_cap = {
380 .num_timing_generator = 6,
381 .num_audio = 6,
382 .num_analog_stream_encoder = 1,
383 .num_stream_encoder = 6,
384 .num_pll = 3,
385 .num_ddc = 6,
386 };
387
388 static const struct resource_caps res_cap_81 = {
389 .num_timing_generator = 4,
390 .num_audio = 7,
391 .num_analog_stream_encoder = 1,
392 .num_stream_encoder = 7,
393 .num_pll = 3,
394 .num_ddc = 6,
395 };
396
397 static const struct resource_caps res_cap_83 = {
398 .num_timing_generator = 2,
399 .num_audio = 6,
400 .num_analog_stream_encoder = 1,
401 .num_stream_encoder = 6,
402 .num_pll = 2,
403 .num_ddc = 2,
404 };
405
406 static const struct dc_plane_cap plane_cap = {
407 .type = DC_PLANE_TYPE_DCE_RGB,
408
409 .pixel_format_support = {
410 .argb8888 = true,
411 .nv12 = false,
412 .fp16 = true
413 },
414
415 .max_upscale_factor = {
416 .argb8888 = 16000,
417 .nv12 = 1,
418 .fp16 = 1
419 },
420
421 .max_downscale_factor = {
422 .argb8888 = 250,
423 .nv12 = 1,
424 .fp16 = 1
425 }
426 };
427
428 static const struct dc_debug_options debug_defaults = { 0 };
429
430 static const struct dc_check_config config_defaults = {
431 .enable_legacy_fast_update = true,
432 };
433
434 static const struct dce_dmcu_registers dmcu_regs = {
435 DMCU_DCE80_REG_LIST()
436 };
437
438 static const struct dce_dmcu_shift dmcu_shift = {
439 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
440 };
441
442 static const struct dce_dmcu_mask dmcu_mask = {
443 DMCU_MASK_SH_LIST_DCE80(_MASK)
444 };
445 static const struct dce_abm_registers abm_regs = {
446 ABM_DCE110_COMMON_REG_LIST()
447 };
448
449 static const struct dce_abm_shift abm_shift = {
450 ABM_MASK_SH_LIST_DCE110(__SHIFT)
451 };
452
453 static const struct dce_abm_mask abm_mask = {
454 ABM_MASK_SH_LIST_DCE110(_MASK)
455 };
456
457 #define CTX ctx
458 #define REG(reg) mm ## reg
459
460 #ifndef mmCC_DC_HDMI_STRAPS
461 #define mmCC_DC_HDMI_STRAPS 0x1918
462 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
463 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
464 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
465 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
466 #endif
467
map_transmitter_id_to_phy_instance(enum transmitter transmitter)468 static int map_transmitter_id_to_phy_instance(
469 enum transmitter transmitter)
470 {
471 switch (transmitter) {
472 case TRANSMITTER_UNIPHY_A:
473 return 0;
474 case TRANSMITTER_UNIPHY_B:
475 return 1;
476 case TRANSMITTER_UNIPHY_C:
477 return 2;
478 case TRANSMITTER_UNIPHY_D:
479 return 3;
480 case TRANSMITTER_UNIPHY_E:
481 return 4;
482 case TRANSMITTER_UNIPHY_F:
483 return 5;
484 case TRANSMITTER_UNIPHY_G:
485 return 6;
486 default:
487 ASSERT(0);
488 return 0;
489 }
490 }
491
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)492 static void read_dce_straps(
493 struct dc_context *ctx,
494 struct resource_straps *straps)
495 {
496 REG_GET_2(CC_DC_HDMI_STRAPS,
497 HDMI_DISABLE, &straps->hdmi_disable,
498 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
499
500 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
501 }
502
create_audio(struct dc_context * ctx,unsigned int inst)503 static struct audio *create_audio(
504 struct dc_context *ctx, unsigned int inst)
505 {
506 return dce_audio_create(ctx, inst,
507 &audio_regs[inst], &audio_shift, &audio_mask);
508 }
509
dce80_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)510 static struct timing_generator *dce80_timing_generator_create(
511 struct dc_context *ctx,
512 uint32_t instance,
513 const struct dce110_timing_generator_offsets *offsets)
514 {
515 struct dce110_timing_generator *tg110 =
516 kzalloc_obj(struct dce110_timing_generator);
517
518 if (!tg110)
519 return NULL;
520
521 dce80_timing_generator_construct(tg110, ctx, instance, offsets);
522 return &tg110->base;
523 }
524
dce80_opp_create(struct dc_context * ctx,uint32_t inst)525 static struct output_pixel_processor *dce80_opp_create(
526 struct dc_context *ctx,
527 uint32_t inst)
528 {
529 struct dce110_opp *opp =
530 kzalloc_obj(struct dce110_opp);
531
532 if (!opp)
533 return NULL;
534
535 dce110_opp_construct(opp,
536 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
537 return &opp->base;
538 }
539
dce80_aux_engine_create(struct dc_context * ctx,uint32_t inst)540 static struct dce_aux *dce80_aux_engine_create(
541 struct dc_context *ctx,
542 uint32_t inst)
543 {
544 struct aux_engine_dce110 *aux_engine =
545 kzalloc_obj(struct aux_engine_dce110);
546
547 if (!aux_engine)
548 return NULL;
549
550 dce110_aux_engine_construct(aux_engine, ctx, inst,
551 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
552 &aux_engine_regs[inst],
553 &aux_mask,
554 &aux_shift,
555 ctx->dc->caps.extended_aux_timeout_support);
556
557 return &aux_engine->base;
558 }
559 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
560
561 static const struct dce_i2c_registers i2c_hw_regs[] = {
562 i2c_inst_regs(1),
563 i2c_inst_regs(2),
564 i2c_inst_regs(3),
565 i2c_inst_regs(4),
566 i2c_inst_regs(5),
567 i2c_inst_regs(6),
568 };
569
570 static const struct dce_i2c_shift i2c_shifts = {
571 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
572 };
573
574 static const struct dce_i2c_mask i2c_masks = {
575 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
576 };
577
dce80_i2c_hw_create(struct dc_context * ctx,uint32_t inst)578 static struct dce_i2c_hw *dce80_i2c_hw_create(
579 struct dc_context *ctx,
580 uint32_t inst)
581 {
582 struct dce_i2c_hw *dce_i2c_hw =
583 kzalloc_obj(struct dce_i2c_hw);
584
585 if (!dce_i2c_hw)
586 return NULL;
587
588 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
589 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
590
591 return dce_i2c_hw;
592 }
593
dce80_i2c_sw_create(struct dc_context * ctx)594 static struct dce_i2c_sw *dce80_i2c_sw_create(
595 struct dc_context *ctx)
596 {
597 struct dce_i2c_sw *dce_i2c_sw =
598 kzalloc_obj(struct dce_i2c_sw);
599
600 if (!dce_i2c_sw)
601 return NULL;
602
603 dce_i2c_sw_construct(dce_i2c_sw, ctx);
604
605 return dce_i2c_sw;
606 }
dce80_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)607 static struct stream_encoder *dce80_stream_encoder_create(
608 enum engine_id eng_id,
609 struct dc_context *ctx)
610 {
611 struct dce110_stream_encoder *enc110 =
612 kzalloc_obj(struct dce110_stream_encoder);
613
614 if (!enc110)
615 return NULL;
616
617 if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) {
618 dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
619 &stream_enc_regs[eng_id], &se_shift, &se_mask);
620 return &enc110->base;
621 }
622
623 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
624 &stream_enc_regs[eng_id],
625 &se_shift, &se_mask);
626 return &enc110->base;
627 }
628
629 #define SRII(reg_name, block, id)\
630 .reg_name[id] = mm ## block ## id ## _ ## reg_name
631
632 static const struct dce_hwseq_registers hwseq_reg = {
633 HWSEQ_DCE8_REG_LIST()
634 };
635
636 static const struct dce_hwseq_shift hwseq_shift = {
637 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
638 };
639
640 static const struct dce_hwseq_mask hwseq_mask = {
641 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
642 };
643
dce80_hwseq_create(struct dc_context * ctx)644 static struct dce_hwseq *dce80_hwseq_create(
645 struct dc_context *ctx)
646 {
647 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
648
649 if (hws) {
650 hws->ctx = ctx;
651 hws->regs = &hwseq_reg;
652 hws->shifts = &hwseq_shift;
653 hws->masks = &hwseq_mask;
654 }
655 return hws;
656 }
657
658 static const struct resource_create_funcs res_create_funcs = {
659 .read_dce_straps = read_dce_straps,
660 .create_audio = create_audio,
661 .create_stream_encoder = dce80_stream_encoder_create,
662 .create_hwseq = dce80_hwseq_create,
663 };
664
665 #define mi_inst_regs(id) { \
666 MI_DCE8_REG_LIST(id), \
667 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
668 }
669 static const struct dce_mem_input_registers mi_regs[] = {
670 mi_inst_regs(0),
671 mi_inst_regs(1),
672 mi_inst_regs(2),
673 mi_inst_regs(3),
674 mi_inst_regs(4),
675 mi_inst_regs(5),
676 };
677
678 static const struct dce_mem_input_shift mi_shifts = {
679 MI_DCE8_MASK_SH_LIST(__SHIFT),
680 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
681 };
682
683 static const struct dce_mem_input_mask mi_masks = {
684 MI_DCE8_MASK_SH_LIST(_MASK),
685 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
686 };
687
dce80_mem_input_create(struct dc_context * ctx,uint32_t inst)688 static struct mem_input *dce80_mem_input_create(
689 struct dc_context *ctx,
690 uint32_t inst)
691 {
692 struct dce_mem_input *dce_mi = kzalloc_obj(struct dce_mem_input);
693
694 if (!dce_mi) {
695 BREAK_TO_DEBUGGER();
696 return NULL;
697 }
698
699 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
700 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
701 return &dce_mi->base;
702 }
703
dce80_transform_destroy(struct transform ** xfm)704 static void dce80_transform_destroy(struct transform **xfm)
705 {
706 kfree(TO_DCE_TRANSFORM(*xfm));
707 *xfm = NULL;
708 }
709
dce80_transform_create(struct dc_context * ctx,uint32_t inst)710 static struct transform *dce80_transform_create(
711 struct dc_context *ctx,
712 uint32_t inst)
713 {
714 struct dce_transform *transform =
715 kzalloc_obj(struct dce_transform);
716
717 if (!transform)
718 return NULL;
719
720 dce_transform_construct(transform, ctx, inst,
721 &xfm_regs[inst], &xfm_shift, &xfm_mask);
722 transform->prescaler_on = false;
723 return &transform->base;
724 }
725
726 static const struct encoder_feature_support link_enc_feature = {
727 .max_hdmi_deep_color = COLOR_DEPTH_121212,
728 .max_hdmi_pixel_clock = 297000,
729 .flags.bits.IS_HBR2_CAPABLE = true,
730 .flags.bits.IS_TPS3_CAPABLE = true
731 };
732
dce80_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)733 static struct link_encoder *dce80_link_encoder_create(
734 struct dc_context *ctx,
735 const struct encoder_init_data *enc_init_data)
736 {
737 (void)ctx;
738 struct dce110_link_encoder *enc110 =
739 kzalloc_obj(struct dce110_link_encoder);
740 int link_regs_id;
741
742 if (!enc110)
743 return NULL;
744
745 if (enc_init_data->connector.id == CONNECTOR_ID_VGA &&
746 enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) {
747 dce110_link_encoder_construct(enc110,
748 enc_init_data,
749 &link_enc_feature,
750 &link_enc_regs[ENGINE_ID_DACA],
751 NULL,
752 NULL);
753 return &enc110->base;
754 }
755
756 link_regs_id =
757 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
758
759 dce110_link_encoder_construct(enc110,
760 enc_init_data,
761 &link_enc_feature,
762 &link_enc_regs[link_regs_id],
763 enc_init_data->channel == CHANNEL_ID_UNKNOWN ?
764 NULL : &link_enc_aux_regs[enc_init_data->channel - 1],
765 enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ?
766 NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]);
767 return &enc110->base;
768 }
769
dce80_panel_cntl_create(const struct panel_cntl_init_data * init_data)770 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
771 {
772 struct dce_panel_cntl *panel_cntl =
773 kzalloc_obj(struct dce_panel_cntl);
774
775 if (!panel_cntl)
776 return NULL;
777
778 dce_panel_cntl_construct(panel_cntl,
779 init_data,
780 &panel_cntl_regs[init_data->inst],
781 &panel_cntl_shift,
782 &panel_cntl_mask);
783
784 return &panel_cntl->base;
785 }
786
dce80_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)787 static struct clock_source *dce80_clock_source_create(
788 struct dc_context *ctx,
789 struct dc_bios *bios,
790 enum clock_source_id id,
791 const struct dce110_clk_src_regs *regs,
792 bool dp_clk_src)
793 {
794 struct dce110_clk_src *clk_src =
795 kzalloc_obj(struct dce110_clk_src);
796
797 if (!clk_src)
798 return NULL;
799
800 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
801 regs, &cs_shift, &cs_mask)) {
802 clk_src->base.dp_clk_src = dp_clk_src;
803 return &clk_src->base;
804 }
805
806 kfree(clk_src);
807 BREAK_TO_DEBUGGER();
808 return NULL;
809 }
810
dce80_clock_source_destroy(struct clock_source ** clk_src)811 static void dce80_clock_source_destroy(struct clock_source **clk_src)
812 {
813 kfree(TO_DCE110_CLK_SRC(*clk_src));
814 *clk_src = NULL;
815 }
816
dce80_ipp_create(struct dc_context * ctx,uint32_t inst)817 static struct input_pixel_processor *dce80_ipp_create(
818 struct dc_context *ctx, uint32_t inst)
819 {
820 struct dce_ipp *ipp = kzalloc_obj(struct dce_ipp);
821
822 if (!ipp) {
823 BREAK_TO_DEBUGGER();
824 return NULL;
825 }
826
827 dce_ipp_construct(ipp, ctx, inst,
828 &ipp_regs[inst], &ipp_shift, &ipp_mask);
829 return &ipp->base;
830 }
831
dce80_resource_destruct(struct dce110_resource_pool * pool)832 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
833 {
834 unsigned int i;
835
836 for (i = 0; i < pool->base.pipe_count; i++) {
837 if (pool->base.opps[i] != NULL)
838 dce110_opp_destroy(&pool->base.opps[i]);
839
840 if (pool->base.transforms[i] != NULL)
841 dce80_transform_destroy(&pool->base.transforms[i]);
842
843 if (pool->base.ipps[i] != NULL)
844 dce_ipp_destroy(&pool->base.ipps[i]);
845
846 if (pool->base.mis[i] != NULL) {
847 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
848 pool->base.mis[i] = NULL;
849 }
850
851 if (pool->base.timing_generators[i] != NULL) {
852 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
853 pool->base.timing_generators[i] = NULL;
854 }
855 }
856
857 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
858 if (pool->base.engines[i] != NULL)
859 dce110_engine_destroy(&pool->base.engines[i]);
860 if (pool->base.hw_i2cs[i] != NULL) {
861 kfree(pool->base.hw_i2cs[i]);
862 pool->base.hw_i2cs[i] = NULL;
863 }
864 if (pool->base.sw_i2cs[i] != NULL) {
865 kfree(pool->base.sw_i2cs[i]);
866 pool->base.sw_i2cs[i] = NULL;
867 }
868 }
869
870 for (i = 0; i < pool->base.stream_enc_count; i++) {
871 if (pool->base.stream_enc[i] != NULL)
872 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
873 }
874
875 for (i = 0; i < pool->base.clk_src_count; i++) {
876 if (pool->base.clock_sources[i] != NULL) {
877 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
878 }
879 }
880
881 if (pool->base.abm != NULL)
882 dce_abm_destroy(&pool->base.abm);
883
884 if (pool->base.dmcu != NULL)
885 dce_dmcu_destroy(&pool->base.dmcu);
886
887 if (pool->base.dp_clock_source != NULL)
888 dce80_clock_source_destroy(&pool->base.dp_clock_source);
889
890 for (i = 0; i < pool->base.audio_count; i++) {
891 if (pool->base.audios[i] != NULL) {
892 dce_aud_destroy(&pool->base.audios[i]);
893 }
894 }
895
896 if (pool->base.irqs != NULL) {
897 dal_irq_service_destroy(&pool->base.irqs);
898 }
899 }
900
dce80_destroy_resource_pool(struct resource_pool ** pool)901 static void dce80_destroy_resource_pool(struct resource_pool **pool)
902 {
903 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
904
905 dce80_resource_destruct(dce110_pool);
906 kfree(dce110_pool);
907 *pool = NULL;
908 }
909
910 static const struct resource_funcs dce80_res_pool_funcs = {
911 .destroy = dce80_destroy_resource_pool,
912 .link_enc_create = dce80_link_encoder_create,
913 .panel_cntl_create = dce80_panel_cntl_create,
914 .validate_bandwidth = dce100_validate_bandwidth,
915 .validate_plane = dce100_validate_plane,
916 .add_stream_to_ctx = dce100_add_stream_to_ctx,
917 .validate_global = dce100_validate_global,
918 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
919 };
920
dce80_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)921 static bool dce80_construct(
922 uint8_t num_virtual_links,
923 struct dc *dc,
924 struct dce110_resource_pool *pool)
925 {
926 unsigned int i;
927 struct dc_context *ctx = dc->ctx;
928 struct dc_bios *bp;
929
930 ctx->dc_bios->regs = &bios_regs;
931
932 pool->base.res_cap = &res_cap;
933 pool->base.funcs = &dce80_res_pool_funcs;
934
935
936 /*************************************************
937 * Resource + asic cap harcoding *
938 *************************************************/
939 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
940 pool->base.pipe_count = res_cap.num_timing_generator;
941 pool->base.timing_generator_count = res_cap.num_timing_generator;
942 dc->caps.max_downscale_ratio = 200;
943 dc->caps.i2c_speed_in_khz = 40;
944 dc->caps.i2c_speed_in_khz_hdcp = 40;
945 dc->caps.max_cursor_size = 128;
946 dc->caps.min_horizontal_blanking_period = 80;
947 dc->caps.dual_link_dvi = true;
948 dc->caps.extended_aux_timeout_support = false;
949 dc->debug = debug_defaults;
950 dc->check_config = config_defaults;
951
952 /*************************************************
953 * Create resources *
954 *************************************************/
955
956 bp = ctx->dc_bios;
957
958 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
959 pool->base.dp_clock_source =
960 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
961
962 pool->base.clock_sources[0] =
963 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
964 pool->base.clock_sources[1] =
965 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
966 pool->base.clock_sources[2] =
967 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
968 pool->base.clk_src_count = 3;
969
970 } else {
971 pool->base.dp_clock_source =
972 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
973
974 pool->base.clock_sources[0] =
975 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
976 pool->base.clock_sources[1] =
977 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
978 pool->base.clk_src_count = 2;
979 }
980
981 if (pool->base.dp_clock_source == NULL) {
982 dm_error("DC: failed to create dp clock source!\n");
983 BREAK_TO_DEBUGGER();
984 goto res_create_fail;
985 }
986
987 for (i = 0; i < pool->base.clk_src_count; i++) {
988 if (pool->base.clock_sources[i] == NULL) {
989 dm_error("DC: failed to create clock sources!\n");
990 BREAK_TO_DEBUGGER();
991 goto res_create_fail;
992 }
993 }
994
995 pool->base.dmcu = dce_dmcu_create(ctx,
996 &dmcu_regs,
997 &dmcu_shift,
998 &dmcu_mask);
999 if (pool->base.dmcu == NULL) {
1000 dm_error("DC: failed to create dmcu!\n");
1001 BREAK_TO_DEBUGGER();
1002 goto res_create_fail;
1003 }
1004
1005 pool->base.abm = dce_abm_create(ctx,
1006 &abm_regs,
1007 &abm_shift,
1008 &abm_mask);
1009 if (pool->base.abm == NULL) {
1010 dm_error("DC: failed to create abm!\n");
1011 BREAK_TO_DEBUGGER();
1012 goto res_create_fail;
1013 }
1014
1015 {
1016 struct irq_service_init_data init_data;
1017 init_data.ctx = dc->ctx;
1018 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1019 if (!pool->base.irqs)
1020 goto res_create_fail;
1021 }
1022
1023 for (i = 0; i < pool->base.pipe_count; i++) {
1024 pool->base.timing_generators[i] = dce80_timing_generator_create(
1025 ctx, i, &dce80_tg_offsets[i]);
1026 if (pool->base.timing_generators[i] == NULL) {
1027 BREAK_TO_DEBUGGER();
1028 dm_error("DC: failed to create tg!\n");
1029 goto res_create_fail;
1030 }
1031
1032 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1033 if (pool->base.mis[i] == NULL) {
1034 BREAK_TO_DEBUGGER();
1035 dm_error("DC: failed to create memory input!\n");
1036 goto res_create_fail;
1037 }
1038
1039 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1040 if (pool->base.ipps[i] == NULL) {
1041 BREAK_TO_DEBUGGER();
1042 dm_error("DC: failed to create input pixel processor!\n");
1043 goto res_create_fail;
1044 }
1045
1046 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1047 if (pool->base.transforms[i] == NULL) {
1048 BREAK_TO_DEBUGGER();
1049 dm_error("DC: failed to create transform!\n");
1050 goto res_create_fail;
1051 }
1052
1053 pool->base.opps[i] = dce80_opp_create(ctx, i);
1054 if (pool->base.opps[i] == NULL) {
1055 BREAK_TO_DEBUGGER();
1056 dm_error("DC: failed to create output pixel processor!\n");
1057 goto res_create_fail;
1058 }
1059 }
1060
1061 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1062 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1063 if (pool->base.engines[i] == NULL) {
1064 BREAK_TO_DEBUGGER();
1065 dm_error(
1066 "DC:failed to create aux engine!!\n");
1067 goto res_create_fail;
1068 }
1069 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1070 if (pool->base.hw_i2cs[i] == NULL) {
1071 BREAK_TO_DEBUGGER();
1072 dm_error(
1073 "DC:failed to create i2c engine!!\n");
1074 goto res_create_fail;
1075 }
1076 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1077 if (pool->base.sw_i2cs[i] == NULL) {
1078 BREAK_TO_DEBUGGER();
1079 dm_error(
1080 "DC:failed to create sw i2c!!\n");
1081 goto res_create_fail;
1082 }
1083 }
1084
1085 dc->caps.max_planes = pool->base.pipe_count;
1086
1087 for (i = 0; i < dc->caps.max_planes; ++i)
1088 dc->caps.planes[i] = plane_cap;
1089
1090 dc->caps.disable_dp_clk_share = true;
1091
1092 if (!resource_construct(num_virtual_links, dc, &pool->base,
1093 &res_create_funcs))
1094 goto res_create_fail;
1095
1096 /* Create hardware sequencer */
1097 dce80_hw_sequencer_construct(dc);
1098
1099 return true;
1100
1101 res_create_fail:
1102 dce80_resource_destruct(pool);
1103 return false;
1104 }
1105
dce80_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1106 struct resource_pool *dce80_create_resource_pool(
1107 uint8_t num_virtual_links,
1108 struct dc *dc)
1109 {
1110 struct dce110_resource_pool *pool =
1111 kzalloc_obj(struct dce110_resource_pool);
1112
1113 if (!pool)
1114 return NULL;
1115
1116 if (dce80_construct(num_virtual_links, dc, pool))
1117 return &pool->base;
1118
1119 kfree(pool);
1120 BREAK_TO_DEBUGGER();
1121 return NULL;
1122 }
1123
dce81_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1124 static bool dce81_construct(
1125 uint8_t num_virtual_links,
1126 struct dc *dc,
1127 struct dce110_resource_pool *pool)
1128 {
1129 unsigned int i;
1130 struct dc_context *ctx = dc->ctx;
1131 struct dc_bios *bp;
1132
1133 ctx->dc_bios->regs = &bios_regs;
1134
1135 pool->base.res_cap = &res_cap_81;
1136 pool->base.funcs = &dce80_res_pool_funcs;
1137
1138
1139 /*************************************************
1140 * Resource + asic cap harcoding *
1141 *************************************************/
1142 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1143 pool->base.pipe_count = res_cap_81.num_timing_generator;
1144 pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1145 dc->caps.max_downscale_ratio = 200;
1146 dc->caps.i2c_speed_in_khz = 40;
1147 dc->caps.i2c_speed_in_khz_hdcp = 40;
1148 dc->caps.max_cursor_size = 128;
1149 dc->caps.min_horizontal_blanking_period = 80;
1150 dc->caps.is_apu = true;
1151
1152 /*************************************************
1153 * Create resources *
1154 *************************************************/
1155
1156 bp = ctx->dc_bios;
1157
1158 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1159 pool->base.dp_clock_source =
1160 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1161
1162 pool->base.clock_sources[0] =
1163 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1164 pool->base.clock_sources[1] =
1165 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1166 pool->base.clock_sources[2] =
1167 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1168 pool->base.clk_src_count = 3;
1169
1170 } else {
1171 pool->base.dp_clock_source =
1172 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1173
1174 pool->base.clock_sources[0] =
1175 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1176 pool->base.clock_sources[1] =
1177 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1178 pool->base.clk_src_count = 2;
1179 }
1180
1181 if (pool->base.dp_clock_source == NULL) {
1182 dm_error("DC: failed to create dp clock source!\n");
1183 BREAK_TO_DEBUGGER();
1184 goto res_create_fail;
1185 }
1186
1187 for (i = 0; i < pool->base.clk_src_count; i++) {
1188 if (pool->base.clock_sources[i] == NULL) {
1189 dm_error("DC: failed to create clock sources!\n");
1190 BREAK_TO_DEBUGGER();
1191 goto res_create_fail;
1192 }
1193 }
1194
1195 pool->base.dmcu = dce_dmcu_create(ctx,
1196 &dmcu_regs,
1197 &dmcu_shift,
1198 &dmcu_mask);
1199 if (pool->base.dmcu == NULL) {
1200 dm_error("DC: failed to create dmcu!\n");
1201 BREAK_TO_DEBUGGER();
1202 goto res_create_fail;
1203 }
1204
1205 pool->base.abm = dce_abm_create(ctx,
1206 &abm_regs,
1207 &abm_shift,
1208 &abm_mask);
1209 if (pool->base.abm == NULL) {
1210 dm_error("DC: failed to create abm!\n");
1211 BREAK_TO_DEBUGGER();
1212 goto res_create_fail;
1213 }
1214
1215 {
1216 struct irq_service_init_data init_data;
1217 init_data.ctx = dc->ctx;
1218 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1219 if (!pool->base.irqs)
1220 goto res_create_fail;
1221 }
1222
1223 for (i = 0; i < pool->base.pipe_count; i++) {
1224 pool->base.timing_generators[i] = dce80_timing_generator_create(
1225 ctx, i, &dce80_tg_offsets[i]);
1226 if (pool->base.timing_generators[i] == NULL) {
1227 BREAK_TO_DEBUGGER();
1228 dm_error("DC: failed to create tg!\n");
1229 goto res_create_fail;
1230 }
1231
1232 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1233 if (pool->base.mis[i] == NULL) {
1234 BREAK_TO_DEBUGGER();
1235 dm_error("DC: failed to create memory input!\n");
1236 goto res_create_fail;
1237 }
1238
1239 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1240 if (pool->base.ipps[i] == NULL) {
1241 BREAK_TO_DEBUGGER();
1242 dm_error("DC: failed to create input pixel processor!\n");
1243 goto res_create_fail;
1244 }
1245
1246 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1247 if (pool->base.transforms[i] == NULL) {
1248 BREAK_TO_DEBUGGER();
1249 dm_error("DC: failed to create transform!\n");
1250 goto res_create_fail;
1251 }
1252
1253 pool->base.opps[i] = dce80_opp_create(ctx, i);
1254 if (pool->base.opps[i] == NULL) {
1255 BREAK_TO_DEBUGGER();
1256 dm_error("DC: failed to create output pixel processor!\n");
1257 goto res_create_fail;
1258 }
1259 }
1260
1261 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1262 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1263 if (pool->base.engines[i] == NULL) {
1264 BREAK_TO_DEBUGGER();
1265 dm_error(
1266 "DC:failed to create aux engine!!\n");
1267 goto res_create_fail;
1268 }
1269 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1270 if (pool->base.hw_i2cs[i] == NULL) {
1271 BREAK_TO_DEBUGGER();
1272 dm_error(
1273 "DC:failed to create i2c engine!!\n");
1274 goto res_create_fail;
1275 }
1276 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1277 if (pool->base.sw_i2cs[i] == NULL) {
1278 BREAK_TO_DEBUGGER();
1279 dm_error(
1280 "DC:failed to create sw i2c!!\n");
1281 goto res_create_fail;
1282 }
1283 }
1284
1285 dc->caps.max_planes = pool->base.pipe_count;
1286
1287 for (i = 0; i < dc->caps.max_planes; ++i)
1288 dc->caps.planes[i] = plane_cap;
1289
1290 dc->caps.disable_dp_clk_share = true;
1291
1292 if (!resource_construct(num_virtual_links, dc, &pool->base,
1293 &res_create_funcs))
1294 goto res_create_fail;
1295
1296 /* Create hardware sequencer */
1297 dce80_hw_sequencer_construct(dc);
1298
1299 return true;
1300
1301 res_create_fail:
1302 dce80_resource_destruct(pool);
1303 return false;
1304 }
1305
dce81_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1306 struct resource_pool *dce81_create_resource_pool(
1307 uint8_t num_virtual_links,
1308 struct dc *dc)
1309 {
1310 struct dce110_resource_pool *pool =
1311 kzalloc_obj(struct dce110_resource_pool);
1312
1313 if (!pool)
1314 return NULL;
1315
1316 if (dce81_construct(num_virtual_links, dc, pool))
1317 return &pool->base;
1318
1319 kfree(pool);
1320 BREAK_TO_DEBUGGER();
1321 return NULL;
1322 }
1323
dce83_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1324 static bool dce83_construct(
1325 uint8_t num_virtual_links,
1326 struct dc *dc,
1327 struct dce110_resource_pool *pool)
1328 {
1329 unsigned int i;
1330 struct dc_context *ctx = dc->ctx;
1331 struct dc_bios *bp;
1332
1333 ctx->dc_bios->regs = &bios_regs;
1334
1335 pool->base.res_cap = &res_cap_83;
1336 pool->base.funcs = &dce80_res_pool_funcs;
1337
1338
1339 /*************************************************
1340 * Resource + asic cap harcoding *
1341 *************************************************/
1342 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1343 pool->base.pipe_count = res_cap_83.num_timing_generator;
1344 pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1345 dc->caps.max_downscale_ratio = 200;
1346 dc->caps.i2c_speed_in_khz = 40;
1347 dc->caps.i2c_speed_in_khz_hdcp = 40;
1348 dc->caps.max_cursor_size = 128;
1349 dc->caps.min_horizontal_blanking_period = 80;
1350 dc->caps.is_apu = true;
1351 dc->debug = debug_defaults;
1352 dc->check_config = config_defaults;
1353
1354 /*************************************************
1355 * Create resources *
1356 *************************************************/
1357
1358 bp = ctx->dc_bios;
1359
1360 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1361 pool->base.dp_clock_source =
1362 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1363
1364 pool->base.clock_sources[0] =
1365 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1366 pool->base.clock_sources[1] =
1367 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1368 pool->base.clk_src_count = 2;
1369
1370 } else {
1371 pool->base.dp_clock_source =
1372 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1373
1374 pool->base.clock_sources[0] =
1375 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1376 pool->base.clk_src_count = 1;
1377 }
1378
1379 if (pool->base.dp_clock_source == NULL) {
1380 dm_error("DC: failed to create dp clock source!\n");
1381 BREAK_TO_DEBUGGER();
1382 goto res_create_fail;
1383 }
1384
1385 for (i = 0; i < pool->base.clk_src_count; i++) {
1386 if (pool->base.clock_sources[i] == NULL) {
1387 dm_error("DC: failed to create clock sources!\n");
1388 BREAK_TO_DEBUGGER();
1389 goto res_create_fail;
1390 }
1391 }
1392
1393 pool->base.dmcu = dce_dmcu_create(ctx,
1394 &dmcu_regs,
1395 &dmcu_shift,
1396 &dmcu_mask);
1397 if (pool->base.dmcu == NULL) {
1398 dm_error("DC: failed to create dmcu!\n");
1399 BREAK_TO_DEBUGGER();
1400 goto res_create_fail;
1401 }
1402
1403 pool->base.abm = dce_abm_create(ctx,
1404 &abm_regs,
1405 &abm_shift,
1406 &abm_mask);
1407 if (pool->base.abm == NULL) {
1408 dm_error("DC: failed to create abm!\n");
1409 BREAK_TO_DEBUGGER();
1410 goto res_create_fail;
1411 }
1412
1413 {
1414 struct irq_service_init_data init_data;
1415 init_data.ctx = dc->ctx;
1416 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1417 if (!pool->base.irqs)
1418 goto res_create_fail;
1419 }
1420
1421 for (i = 0; i < pool->base.pipe_count; i++) {
1422 pool->base.timing_generators[i] = dce80_timing_generator_create(
1423 ctx, i, &dce80_tg_offsets[i]);
1424 if (pool->base.timing_generators[i] == NULL) {
1425 BREAK_TO_DEBUGGER();
1426 dm_error("DC: failed to create tg!\n");
1427 goto res_create_fail;
1428 }
1429
1430 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1431 if (pool->base.mis[i] == NULL) {
1432 BREAK_TO_DEBUGGER();
1433 dm_error("DC: failed to create memory input!\n");
1434 goto res_create_fail;
1435 }
1436
1437 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1438 if (pool->base.ipps[i] == NULL) {
1439 BREAK_TO_DEBUGGER();
1440 dm_error("DC: failed to create input pixel processor!\n");
1441 goto res_create_fail;
1442 }
1443
1444 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1445 if (pool->base.transforms[i] == NULL) {
1446 BREAK_TO_DEBUGGER();
1447 dm_error("DC: failed to create transform!\n");
1448 goto res_create_fail;
1449 }
1450
1451 pool->base.opps[i] = dce80_opp_create(ctx, i);
1452 if (pool->base.opps[i] == NULL) {
1453 BREAK_TO_DEBUGGER();
1454 dm_error("DC: failed to create output pixel processor!\n");
1455 goto res_create_fail;
1456 }
1457 }
1458
1459 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1460 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1461 if (pool->base.engines[i] == NULL) {
1462 BREAK_TO_DEBUGGER();
1463 dm_error(
1464 "DC:failed to create aux engine!!\n");
1465 goto res_create_fail;
1466 }
1467 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1468 if (pool->base.hw_i2cs[i] == NULL) {
1469 BREAK_TO_DEBUGGER();
1470 dm_error(
1471 "DC:failed to create i2c engine!!\n");
1472 goto res_create_fail;
1473 }
1474 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1475 if (pool->base.sw_i2cs[i] == NULL) {
1476 BREAK_TO_DEBUGGER();
1477 dm_error(
1478 "DC:failed to create sw i2c!!\n");
1479 goto res_create_fail;
1480 }
1481 }
1482
1483 dc->caps.max_planes = pool->base.pipe_count;
1484
1485 for (i = 0; i < dc->caps.max_planes; ++i)
1486 dc->caps.planes[i] = plane_cap;
1487
1488 dc->caps.disable_dp_clk_share = true;
1489
1490 if (!resource_construct(num_virtual_links, dc, &pool->base,
1491 &res_create_funcs))
1492 goto res_create_fail;
1493
1494 /* Create hardware sequencer */
1495 dce80_hw_sequencer_construct(dc);
1496
1497 return true;
1498
1499 res_create_fail:
1500 dce80_resource_destruct(pool);
1501 return false;
1502 }
1503
dce83_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1504 struct resource_pool *dce83_create_resource_pool(
1505 uint8_t num_virtual_links,
1506 struct dc *dc)
1507 {
1508 struct dce110_resource_pool *pool =
1509 kzalloc_obj(struct dce110_resource_pool);
1510
1511 if (!pool)
1512 return NULL;
1513
1514 if (dce83_construct(num_virtual_links, dc, pool))
1515 return &pool->base;
1516
1517 kfree(pool);
1518 BREAK_TO_DEBUGGER();
1519 return NULL;
1520 }
1521