1 /* 2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_6_0_d.h" 29 #include "dce/dce_6_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "clk_mgr.h" 38 #include "include/irq_service_interface.h" 39 #include "irq/dce60/irq_service_dce60.h" 40 #include "dce110/dce110_timing_generator.h" 41 #include "dce110/dce110_resource.h" 42 #include "dce60/dce60_timing_generator.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_link_encoder.h" 45 #include "dce/dce_stream_encoder.h" 46 #include "dce/dce_ipp.h" 47 #include "dce/dce_transform.h" 48 #include "dce/dce_opp.h" 49 #include "dce/dce_clock_source.h" 50 #include "dce/dce_audio.h" 51 #include "dce/dce_hwseq.h" 52 #include "dce60/dce60_hwseq.h" 53 #include "dce100/dce100_resource.h" 54 #include "dce/dce_panel_cntl.h" 55 56 #include "reg_helper.h" 57 58 #include "dce/dce_dmcu.h" 59 #include "dce/dce_aux.h" 60 #include "dce/dce_abm.h" 61 #include "dce/dce_i2c.h" 62 /* TODO remove this include */ 63 64 #include "dce60_resource.h" 65 66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 67 #include "gmc/gmc_6_0_d.h" 68 #include "gmc/gmc_6_0_sh_mask.h" 69 #endif 70 71 #ifndef mmDP_DPHY_INTERNAL_CTRL 72 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 79 #endif 80 81 82 #ifndef mmBIOS_SCRATCH_2 83 #define mmBIOS_SCRATCH_0 0x05C9 84 #define mmBIOS_SCRATCH_2 0x05CB 85 #define mmBIOS_SCRATCH_3 0x05CC 86 #define mmBIOS_SCRATCH_6 0x05CF 87 #endif 88 89 #ifndef mmDP_DPHY_FAST_TRAINING 90 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 91 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 92 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 93 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 94 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 95 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 96 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 97 #endif 98 99 100 #ifndef mmHPD_DC_HPD_CONTROL 101 #define mmHPD_DC_HPD_CONTROL 0x189A 102 #define mmHPD0_DC_HPD_CONTROL 0x189A 103 #define mmHPD1_DC_HPD_CONTROL 0x18A2 104 #define mmHPD2_DC_HPD_CONTROL 0x18AA 105 #define mmHPD3_DC_HPD_CONTROL 0x18B2 106 #define mmHPD4_DC_HPD_CONTROL 0x18BA 107 #define mmHPD5_DC_HPD_CONTROL 0x18C2 108 #endif 109 110 #define DCE11_DIG_FE_CNTL 0x4a00 111 #define DCE11_DIG_BE_CNTL 0x4a47 112 #define DCE11_DP_SEC 0x4ac3 113 114 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = { 115 { 116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 118 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 119 - mmDPG_PIPE_ARBITRATION_CONTROL3), 120 }, 121 { 122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 124 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 125 - mmDPG_PIPE_ARBITRATION_CONTROL3), 126 }, 127 { 128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 130 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 131 - mmDPG_PIPE_ARBITRATION_CONTROL3), 132 }, 133 { 134 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 135 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 136 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 137 - mmDPG_PIPE_ARBITRATION_CONTROL3), 138 }, 139 { 140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 142 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 143 - mmDPG_PIPE_ARBITRATION_CONTROL3), 144 }, 145 { 146 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 147 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 148 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 149 - mmDPG_PIPE_ARBITRATION_CONTROL3), 150 } 151 }; 152 153 /* set register offset */ 154 #define SR(reg_name)\ 155 .reg_name = mm ## reg_name 156 157 /* set register offset with instance */ 158 #define SRI(reg_name, block, id)\ 159 .reg_name = mm ## block ## id ## _ ## reg_name 160 161 #define ipp_regs(id)\ 162 [id] = {\ 163 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 164 } 165 166 static const struct dce_ipp_registers ipp_regs[] = { 167 ipp_regs(0), 168 ipp_regs(1), 169 ipp_regs(2), 170 ipp_regs(3), 171 ipp_regs(4), 172 ipp_regs(5) 173 }; 174 175 static const struct dce_ipp_shift ipp_shift = { 176 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 177 }; 178 179 static const struct dce_ipp_mask ipp_mask = { 180 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 181 }; 182 183 #define transform_regs(id)\ 184 [id] = {\ 185 XFM_COMMON_REG_LIST_DCE60(id)\ 186 } 187 188 static const struct dce_transform_registers xfm_regs[] = { 189 transform_regs(0), 190 transform_regs(1), 191 transform_regs(2), 192 transform_regs(3), 193 transform_regs(4), 194 transform_regs(5) 195 }; 196 197 static const struct dce_transform_shift xfm_shift = { 198 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT) 199 }; 200 201 static const struct dce_transform_mask xfm_mask = { 202 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK) 203 }; 204 205 #define aux_regs(id)\ 206 [id] = {\ 207 AUX_REG_LIST(id)\ 208 } 209 210 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 211 aux_regs(0), 212 aux_regs(1), 213 aux_regs(2), 214 aux_regs(3), 215 aux_regs(4), 216 aux_regs(5) 217 }; 218 219 #define hpd_regs(id)\ 220 [id] = {\ 221 HPD_REG_LIST(id)\ 222 } 223 224 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 225 hpd_regs(0), 226 hpd_regs(1), 227 hpd_regs(2), 228 hpd_regs(3), 229 hpd_regs(4), 230 hpd_regs(5) 231 }; 232 233 #define link_regs(id)\ 234 [id] = {\ 235 LE_DCE60_REG_LIST(id)\ 236 } 237 238 static const struct dce110_link_enc_registers link_enc_regs[] = { 239 link_regs(0), 240 link_regs(1), 241 link_regs(2), 242 link_regs(3), 243 link_regs(4), 244 link_regs(5), 245 {0}, 246 { .DAC_ENABLE = mmDAC_ENABLE }, 247 }; 248 249 #define stream_enc_regs(id)\ 250 [id] = {\ 251 SE_COMMON_REG_LIST_DCE_BASE(id),\ 252 .AFMT_CNTL = 0,\ 253 } 254 255 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 256 stream_enc_regs(0), 257 stream_enc_regs(1), 258 stream_enc_regs(2), 259 stream_enc_regs(3), 260 stream_enc_regs(4), 261 stream_enc_regs(5) 262 }; 263 264 static const struct dce_stream_encoder_shift se_shift = { 265 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 266 }; 267 268 static const struct dce_stream_encoder_mask se_mask = { 269 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 270 }; 271 272 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 273 { DCE_PANEL_CNTL_REG_LIST() } 274 }; 275 276 static const struct dce_panel_cntl_shift panel_cntl_shift = { 277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 278 }; 279 280 static const struct dce_panel_cntl_mask panel_cntl_mask = { 281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 282 }; 283 284 #define opp_regs(id)\ 285 [id] = {\ 286 OPP_DCE_60_REG_LIST(id),\ 287 } 288 289 static const struct dce_opp_registers opp_regs[] = { 290 opp_regs(0), 291 opp_regs(1), 292 opp_regs(2), 293 opp_regs(3), 294 opp_regs(4), 295 opp_regs(5) 296 }; 297 298 static const struct dce_opp_shift opp_shift = { 299 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT) 300 }; 301 302 static const struct dce_opp_mask opp_mask = { 303 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK) 304 }; 305 306 static const struct dce110_aux_registers_shift aux_shift = { 307 DCE10_AUX_MASK_SH_LIST(__SHIFT) 308 }; 309 310 static const struct dce110_aux_registers_mask aux_mask = { 311 DCE10_AUX_MASK_SH_LIST(_MASK) 312 }; 313 314 #define aux_engine_regs(id)\ 315 [id] = {\ 316 AUX_COMMON_REG_LIST(id), \ 317 .AUX_RESET_MASK = 0 \ 318 } 319 320 static const struct dce110_aux_registers aux_engine_regs[] = { 321 aux_engine_regs(0), 322 aux_engine_regs(1), 323 aux_engine_regs(2), 324 aux_engine_regs(3), 325 aux_engine_regs(4), 326 aux_engine_regs(5) 327 }; 328 329 #define audio_regs(id)\ 330 [id] = {\ 331 AUD_COMMON_REG_LIST(id)\ 332 } 333 334 static const struct dce_audio_registers audio_regs[] = { 335 audio_regs(0), 336 audio_regs(1), 337 audio_regs(2), 338 audio_regs(3), 339 audio_regs(4), 340 audio_regs(5), 341 }; 342 343 static const struct dce_audio_shift audio_shift = { 344 AUD_DCE60_MASK_SH_LIST(__SHIFT) 345 }; 346 347 static const struct dce_audio_mask audio_mask = { 348 AUD_DCE60_MASK_SH_LIST(_MASK) 349 }; 350 351 #define clk_src_regs(id)\ 352 [id] = {\ 353 CS_COMMON_REG_LIST_DCE_80(id),\ 354 } 355 356 357 static const struct dce110_clk_src_regs clk_src_regs[] = { 358 clk_src_regs(0), 359 clk_src_regs(1), 360 clk_src_regs(2) 361 }; 362 363 static const struct dce110_clk_src_shift cs_shift = { 364 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 365 }; 366 367 static const struct dce110_clk_src_mask cs_mask = { 368 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 369 }; 370 371 static const struct bios_registers bios_regs = { 372 .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, 373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 375 }; 376 377 static const struct resource_caps res_cap = { 378 .num_timing_generator = 6, 379 .num_audio = 6, 380 .num_analog_stream_encoder = 1, 381 .num_stream_encoder = 6, 382 .num_pll = 3, 383 .num_ddc = 6, 384 }; 385 386 static const struct resource_caps res_cap_61 = { 387 .num_timing_generator = 4, 388 .num_audio = 6, 389 .num_stream_encoder = 6, 390 .num_analog_stream_encoder = 1, 391 .num_pll = 3, 392 .num_ddc = 6, 393 }; 394 395 static const struct resource_caps res_cap_64 = { 396 .num_timing_generator = 2, 397 .num_audio = 2, 398 .num_analog_stream_encoder = 1, 399 .num_stream_encoder = 2, 400 .num_pll = 3, 401 .num_ddc = 2, 402 }; 403 404 static const struct dc_plane_cap plane_cap = { 405 .type = DC_PLANE_TYPE_DCE_RGB, 406 407 .pixel_format_support = { 408 .argb8888 = true, 409 .nv12 = false, 410 .fp16 = false 411 }, 412 413 .max_upscale_factor = { 414 .argb8888 = 1, 415 .nv12 = 1, 416 .fp16 = 1 417 }, 418 419 .max_downscale_factor = { 420 .argb8888 = 1, 421 .nv12 = 1, 422 .fp16 = 1 423 } 424 }; 425 426 static const struct dce_dmcu_registers dmcu_regs = { 427 DMCU_DCE60_REG_LIST() 428 }; 429 430 static const struct dce_dmcu_shift dmcu_shift = { 431 DMCU_MASK_SH_LIST_DCE60(__SHIFT) 432 }; 433 434 static const struct dce_dmcu_mask dmcu_mask = { 435 DMCU_MASK_SH_LIST_DCE60(_MASK) 436 }; 437 static const struct dce_abm_registers abm_regs = { 438 ABM_DCE110_COMMON_REG_LIST() 439 }; 440 441 static const struct dce_abm_shift abm_shift = { 442 ABM_MASK_SH_LIST_DCE110(__SHIFT) 443 }; 444 445 static const struct dce_abm_mask abm_mask = { 446 ABM_MASK_SH_LIST_DCE110(_MASK) 447 }; 448 449 #define CTX ctx 450 #define REG(reg) mm ## reg 451 452 #ifndef mmCC_DC_HDMI_STRAPS 453 #define mmCC_DC_HDMI_STRAPS 0x1918 454 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 455 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 456 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 457 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 458 #endif 459 460 static int map_transmitter_id_to_phy_instance( 461 enum transmitter transmitter) 462 { 463 switch (transmitter) { 464 case TRANSMITTER_UNIPHY_A: 465 return 0; 466 case TRANSMITTER_UNIPHY_B: 467 return 1; 468 case TRANSMITTER_UNIPHY_C: 469 return 2; 470 case TRANSMITTER_UNIPHY_D: 471 return 3; 472 case TRANSMITTER_UNIPHY_E: 473 return 4; 474 case TRANSMITTER_UNIPHY_F: 475 return 5; 476 case TRANSMITTER_UNIPHY_G: 477 return 6; 478 default: 479 ASSERT(0); 480 return 0; 481 } 482 } 483 484 static void read_dce_straps( 485 struct dc_context *ctx, 486 struct resource_straps *straps) 487 { 488 REG_GET_2(CC_DC_HDMI_STRAPS, 489 HDMI_DISABLE, &straps->hdmi_disable, 490 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 491 492 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 493 } 494 495 static struct audio *create_audio( 496 struct dc_context *ctx, unsigned int inst) 497 { 498 return dce60_audio_create(ctx, inst, 499 &audio_regs[inst], &audio_shift, &audio_mask); 500 } 501 502 static struct timing_generator *dce60_timing_generator_create( 503 struct dc_context *ctx, 504 uint32_t instance, 505 const struct dce110_timing_generator_offsets *offsets) 506 { 507 struct dce110_timing_generator *tg110 = 508 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 509 510 if (!tg110) 511 return NULL; 512 513 dce60_timing_generator_construct(tg110, ctx, instance, offsets); 514 return &tg110->base; 515 } 516 517 static struct output_pixel_processor *dce60_opp_create( 518 struct dc_context *ctx, 519 uint32_t inst) 520 { 521 struct dce110_opp *opp = 522 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 523 524 if (!opp) 525 return NULL; 526 527 dce60_opp_construct(opp, 528 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 529 return &opp->base; 530 } 531 532 static struct dce_aux *dce60_aux_engine_create( 533 struct dc_context *ctx, 534 uint32_t inst) 535 { 536 struct aux_engine_dce110 *aux_engine = 537 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 538 539 if (!aux_engine) 540 return NULL; 541 542 dce110_aux_engine_construct(aux_engine, ctx, inst, 543 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 544 &aux_engine_regs[inst], 545 &aux_mask, 546 &aux_shift, 547 ctx->dc->caps.extended_aux_timeout_support); 548 549 return &aux_engine->base; 550 } 551 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 552 553 static const struct dce_i2c_registers i2c_hw_regs[] = { 554 i2c_inst_regs(1), 555 i2c_inst_regs(2), 556 i2c_inst_regs(3), 557 i2c_inst_regs(4), 558 i2c_inst_regs(5), 559 i2c_inst_regs(6), 560 }; 561 562 static const struct dce_i2c_shift i2c_shifts = { 563 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 564 }; 565 566 static const struct dce_i2c_mask i2c_masks = { 567 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 568 }; 569 570 static struct dce_i2c_hw *dce60_i2c_hw_create( 571 struct dc_context *ctx, 572 uint32_t inst) 573 { 574 struct dce_i2c_hw *dce_i2c_hw = 575 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 576 577 if (!dce_i2c_hw) 578 return NULL; 579 580 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 581 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 582 583 return dce_i2c_hw; 584 } 585 586 static struct dce_i2c_sw *dce60_i2c_sw_create( 587 struct dc_context *ctx) 588 { 589 struct dce_i2c_sw *dce_i2c_sw = 590 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 591 592 if (!dce_i2c_sw) 593 return NULL; 594 595 dce_i2c_sw_construct(dce_i2c_sw, ctx); 596 597 return dce_i2c_sw; 598 } 599 static struct stream_encoder *dce60_stream_encoder_create( 600 enum engine_id eng_id, 601 struct dc_context *ctx) 602 { 603 struct dce110_stream_encoder *enc110 = 604 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 605 606 if (!enc110) 607 return NULL; 608 609 if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { 610 dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); 611 return &enc110->base; 612 } 613 614 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 615 &stream_enc_regs[eng_id], 616 &se_shift, &se_mask); 617 return &enc110->base; 618 } 619 620 #define SRII(reg_name, block, id)\ 621 .reg_name[id] = mm ## block ## id ## _ ## reg_name 622 623 static const struct dce_hwseq_registers hwseq_reg = { 624 HWSEQ_DCE6_REG_LIST() 625 }; 626 627 static const struct dce_hwseq_shift hwseq_shift = { 628 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT) 629 }; 630 631 static const struct dce_hwseq_mask hwseq_mask = { 632 HWSEQ_DCE6_MASK_SH_LIST(_MASK) 633 }; 634 635 static struct dce_hwseq *dce60_hwseq_create( 636 struct dc_context *ctx) 637 { 638 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 639 640 if (hws) { 641 hws->ctx = ctx; 642 hws->regs = &hwseq_reg; 643 hws->shifts = &hwseq_shift; 644 hws->masks = &hwseq_mask; 645 } 646 return hws; 647 } 648 649 static const struct resource_create_funcs res_create_funcs = { 650 .read_dce_straps = read_dce_straps, 651 .create_audio = create_audio, 652 .create_stream_encoder = dce60_stream_encoder_create, 653 .create_hwseq = dce60_hwseq_create, 654 }; 655 656 #define mi_inst_regs(id) { \ 657 MI_DCE6_REG_LIST(id), \ 658 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 659 } 660 static const struct dce_mem_input_registers mi_regs[] = { 661 mi_inst_regs(0), 662 mi_inst_regs(1), 663 mi_inst_regs(2), 664 mi_inst_regs(3), 665 mi_inst_regs(4), 666 mi_inst_regs(5), 667 }; 668 669 static const struct dce_mem_input_shift mi_shifts = { 670 MI_DCE6_MASK_SH_LIST(__SHIFT), 671 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 672 }; 673 674 static const struct dce_mem_input_mask mi_masks = { 675 MI_DCE6_MASK_SH_LIST(_MASK), 676 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 677 }; 678 679 static struct mem_input *dce60_mem_input_create( 680 struct dc_context *ctx, 681 uint32_t inst) 682 { 683 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 684 GFP_KERNEL); 685 686 if (!dce_mi) { 687 BREAK_TO_DEBUGGER(); 688 return NULL; 689 } 690 691 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 692 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 693 return &dce_mi->base; 694 } 695 696 static void dce60_transform_destroy(struct transform **xfm) 697 { 698 kfree(TO_DCE_TRANSFORM(*xfm)); 699 *xfm = NULL; 700 } 701 702 static struct transform *dce60_transform_create( 703 struct dc_context *ctx, 704 uint32_t inst) 705 { 706 struct dce_transform *transform = 707 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 708 709 if (!transform) 710 return NULL; 711 712 dce60_transform_construct(transform, ctx, inst, 713 &xfm_regs[inst], &xfm_shift, &xfm_mask); 714 transform->prescaler_on = false; 715 return &transform->base; 716 } 717 718 static const struct encoder_feature_support link_enc_feature = { 719 .max_hdmi_deep_color = COLOR_DEPTH_121212, 720 .max_hdmi_pixel_clock = 297000, 721 .flags.bits.IS_HBR2_CAPABLE = true, 722 .flags.bits.IS_TPS3_CAPABLE = true 723 }; 724 725 static struct link_encoder *dce60_link_encoder_create( 726 struct dc_context *ctx, 727 const struct encoder_init_data *enc_init_data) 728 { 729 struct dce110_link_encoder *enc110 = 730 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 731 int link_regs_id; 732 733 if (!enc110) 734 return NULL; 735 736 if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { 737 dce110_link_encoder_construct(enc110, 738 enc_init_data, 739 &link_enc_feature, 740 &link_enc_regs[ENGINE_ID_DACA], 741 NULL, 742 NULL); 743 return &enc110->base; 744 } 745 746 if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 747 return NULL; 748 749 link_regs_id = 750 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 751 752 dce60_link_encoder_construct(enc110, 753 enc_init_data, 754 &link_enc_feature, 755 &link_enc_regs[link_regs_id], 756 &link_enc_aux_regs[enc_init_data->channel - 1], 757 &link_enc_hpd_regs[enc_init_data->hpd_source]); 758 return &enc110->base; 759 } 760 761 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data) 762 { 763 struct dce_panel_cntl *panel_cntl = 764 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 765 766 if (!panel_cntl) 767 return NULL; 768 769 dce_panel_cntl_construct(panel_cntl, 770 init_data, 771 &panel_cntl_regs[init_data->inst], 772 &panel_cntl_shift, 773 &panel_cntl_mask); 774 775 return &panel_cntl->base; 776 } 777 778 static struct clock_source *dce60_clock_source_create( 779 struct dc_context *ctx, 780 struct dc_bios *bios, 781 enum clock_source_id id, 782 const struct dce110_clk_src_regs *regs, 783 bool dp_clk_src) 784 { 785 struct dce110_clk_src *clk_src = 786 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 787 788 if (!clk_src) 789 return NULL; 790 791 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 792 regs, &cs_shift, &cs_mask)) { 793 clk_src->base.dp_clk_src = dp_clk_src; 794 return &clk_src->base; 795 } 796 797 kfree(clk_src); 798 BREAK_TO_DEBUGGER(); 799 return NULL; 800 } 801 802 static void dce60_clock_source_destroy(struct clock_source **clk_src) 803 { 804 kfree(TO_DCE110_CLK_SRC(*clk_src)); 805 *clk_src = NULL; 806 } 807 808 static struct input_pixel_processor *dce60_ipp_create( 809 struct dc_context *ctx, uint32_t inst) 810 { 811 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 812 813 if (!ipp) { 814 BREAK_TO_DEBUGGER(); 815 return NULL; 816 } 817 818 dce60_ipp_construct(ipp, ctx, inst, 819 &ipp_regs[inst], &ipp_shift, &ipp_mask); 820 return &ipp->base; 821 } 822 823 static void dce60_resource_destruct(struct dce110_resource_pool *pool) 824 { 825 unsigned int i; 826 827 for (i = 0; i < pool->base.pipe_count; i++) { 828 if (pool->base.opps[i] != NULL) 829 dce110_opp_destroy(&pool->base.opps[i]); 830 831 if (pool->base.transforms[i] != NULL) 832 dce60_transform_destroy(&pool->base.transforms[i]); 833 834 if (pool->base.ipps[i] != NULL) 835 dce_ipp_destroy(&pool->base.ipps[i]); 836 837 if (pool->base.mis[i] != NULL) { 838 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 839 pool->base.mis[i] = NULL; 840 } 841 842 if (pool->base.timing_generators[i] != NULL) { 843 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 844 pool->base.timing_generators[i] = NULL; 845 } 846 } 847 848 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 849 if (pool->base.engines[i] != NULL) 850 dce110_engine_destroy(&pool->base.engines[i]); 851 if (pool->base.hw_i2cs[i] != NULL) { 852 kfree(pool->base.hw_i2cs[i]); 853 pool->base.hw_i2cs[i] = NULL; 854 } 855 if (pool->base.sw_i2cs[i] != NULL) { 856 kfree(pool->base.sw_i2cs[i]); 857 pool->base.sw_i2cs[i] = NULL; 858 } 859 } 860 861 for (i = 0; i < pool->base.stream_enc_count; i++) { 862 if (pool->base.stream_enc[i] != NULL) 863 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 864 } 865 866 for (i = 0; i < pool->base.clk_src_count; i++) { 867 if (pool->base.clock_sources[i] != NULL) { 868 dce60_clock_source_destroy(&pool->base.clock_sources[i]); 869 } 870 } 871 872 if (pool->base.abm != NULL) 873 dce_abm_destroy(&pool->base.abm); 874 875 if (pool->base.dmcu != NULL) 876 dce_dmcu_destroy(&pool->base.dmcu); 877 878 if (pool->base.dp_clock_source != NULL) 879 dce60_clock_source_destroy(&pool->base.dp_clock_source); 880 881 for (i = 0; i < pool->base.audio_count; i++) { 882 if (pool->base.audios[i] != NULL) { 883 dce_aud_destroy(&pool->base.audios[i]); 884 } 885 } 886 887 if (pool->base.irqs != NULL) { 888 dal_irq_service_destroy(&pool->base.irqs); 889 } 890 } 891 892 static void dce60_destroy_resource_pool(struct resource_pool **pool) 893 { 894 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 895 896 dce60_resource_destruct(dce110_pool); 897 kfree(dce110_pool); 898 *pool = NULL; 899 } 900 901 static const struct resource_funcs dce60_res_pool_funcs = { 902 .destroy = dce60_destroy_resource_pool, 903 .link_enc_create = dce60_link_encoder_create, 904 .panel_cntl_create = dce60_panel_cntl_create, 905 .validate_bandwidth = dce100_validate_bandwidth, 906 .validate_plane = dce100_validate_plane, 907 .add_stream_to_ctx = dce100_add_stream_to_ctx, 908 .validate_global = dce100_validate_global, 909 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 910 }; 911 912 static bool dce60_construct( 913 uint8_t num_virtual_links, 914 struct dc *dc, 915 struct dce110_resource_pool *pool) 916 { 917 unsigned int i; 918 struct dc_context *ctx = dc->ctx; 919 struct dc_bios *bp; 920 921 ctx->dc_bios->regs = &bios_regs; 922 923 pool->base.res_cap = &res_cap; 924 pool->base.funcs = &dce60_res_pool_funcs; 925 926 927 /************************************************* 928 * Resource + asic cap harcoding * 929 *************************************************/ 930 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 931 pool->base.pipe_count = res_cap.num_timing_generator; 932 pool->base.timing_generator_count = res_cap.num_timing_generator; 933 dc->caps.max_downscale_ratio = 200; 934 dc->caps.i2c_speed_in_khz = 40; 935 dc->caps.max_cursor_size = 64; 936 dc->caps.dual_link_dvi = true; 937 dc->caps.extended_aux_timeout_support = false; 938 939 /************************************************* 940 * Create resources * 941 *************************************************/ 942 943 bp = ctx->dc_bios; 944 945 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 946 pool->base.dp_clock_source = 947 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 948 949 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */ 950 pool->base.clock_sources[0] = 951 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 952 pool->base.clock_sources[1] = 953 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 954 pool->base.clk_src_count = 2; 955 956 } else { 957 pool->base.dp_clock_source = 958 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 959 960 pool->base.clock_sources[0] = 961 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 962 pool->base.clock_sources[1] = 963 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 964 pool->base.clk_src_count = 2; 965 } 966 967 if (pool->base.dp_clock_source == NULL) { 968 dm_error("DC: failed to create dp clock source!\n"); 969 BREAK_TO_DEBUGGER(); 970 goto res_create_fail; 971 } 972 973 for (i = 0; i < pool->base.clk_src_count; i++) { 974 if (pool->base.clock_sources[i] == NULL) { 975 dm_error("DC: failed to create clock sources!\n"); 976 BREAK_TO_DEBUGGER(); 977 goto res_create_fail; 978 } 979 } 980 981 pool->base.dmcu = dce_dmcu_create(ctx, 982 &dmcu_regs, 983 &dmcu_shift, 984 &dmcu_mask); 985 if (pool->base.dmcu == NULL) { 986 dm_error("DC: failed to create dmcu!\n"); 987 BREAK_TO_DEBUGGER(); 988 goto res_create_fail; 989 } 990 991 pool->base.abm = dce_abm_create(ctx, 992 &abm_regs, 993 &abm_shift, 994 &abm_mask); 995 if (pool->base.abm == NULL) { 996 dm_error("DC: failed to create abm!\n"); 997 BREAK_TO_DEBUGGER(); 998 goto res_create_fail; 999 } 1000 1001 { 1002 struct irq_service_init_data init_data; 1003 init_data.ctx = dc->ctx; 1004 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1005 if (!pool->base.irqs) 1006 goto res_create_fail; 1007 } 1008 1009 for (i = 0; i < pool->base.pipe_count; i++) { 1010 pool->base.timing_generators[i] = dce60_timing_generator_create( 1011 ctx, i, &dce60_tg_offsets[i]); 1012 if (pool->base.timing_generators[i] == NULL) { 1013 BREAK_TO_DEBUGGER(); 1014 dm_error("DC: failed to create tg!\n"); 1015 goto res_create_fail; 1016 } 1017 1018 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1019 if (pool->base.mis[i] == NULL) { 1020 BREAK_TO_DEBUGGER(); 1021 dm_error("DC: failed to create memory input!\n"); 1022 goto res_create_fail; 1023 } 1024 1025 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1026 if (pool->base.ipps[i] == NULL) { 1027 BREAK_TO_DEBUGGER(); 1028 dm_error("DC: failed to create input pixel processor!\n"); 1029 goto res_create_fail; 1030 } 1031 1032 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1033 if (pool->base.transforms[i] == NULL) { 1034 BREAK_TO_DEBUGGER(); 1035 dm_error("DC: failed to create transform!\n"); 1036 goto res_create_fail; 1037 } 1038 1039 pool->base.opps[i] = dce60_opp_create(ctx, i); 1040 if (pool->base.opps[i] == NULL) { 1041 BREAK_TO_DEBUGGER(); 1042 dm_error("DC: failed to create output pixel processor!\n"); 1043 goto res_create_fail; 1044 } 1045 } 1046 1047 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1048 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1049 if (pool->base.engines[i] == NULL) { 1050 BREAK_TO_DEBUGGER(); 1051 dm_error( 1052 "DC:failed to create aux engine!!\n"); 1053 goto res_create_fail; 1054 } 1055 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1056 if (pool->base.hw_i2cs[i] == NULL) { 1057 BREAK_TO_DEBUGGER(); 1058 dm_error( 1059 "DC:failed to create i2c engine!!\n"); 1060 goto res_create_fail; 1061 } 1062 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1063 if (pool->base.sw_i2cs[i] == NULL) { 1064 BREAK_TO_DEBUGGER(); 1065 dm_error( 1066 "DC:failed to create sw i2c!!\n"); 1067 goto res_create_fail; 1068 } 1069 } 1070 1071 dc->caps.max_planes = pool->base.pipe_count; 1072 1073 for (i = 0; i < dc->caps.max_planes; ++i) 1074 dc->caps.planes[i] = plane_cap; 1075 1076 dc->caps.disable_dp_clk_share = true; 1077 1078 if (!resource_construct(num_virtual_links, dc, &pool->base, 1079 &res_create_funcs)) 1080 goto res_create_fail; 1081 1082 /* Create hardware sequencer */ 1083 dce60_hw_sequencer_construct(dc); 1084 1085 return true; 1086 1087 res_create_fail: 1088 dce60_resource_destruct(pool); 1089 return false; 1090 } 1091 1092 struct resource_pool *dce60_create_resource_pool( 1093 uint8_t num_virtual_links, 1094 struct dc *dc) 1095 { 1096 struct dce110_resource_pool *pool = 1097 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1098 1099 if (!pool) 1100 return NULL; 1101 1102 if (dce60_construct(num_virtual_links, dc, pool)) 1103 return &pool->base; 1104 1105 kfree(pool); 1106 BREAK_TO_DEBUGGER(); 1107 return NULL; 1108 } 1109 1110 static bool dce61_construct( 1111 uint8_t num_virtual_links, 1112 struct dc *dc, 1113 struct dce110_resource_pool *pool) 1114 { 1115 unsigned int i; 1116 struct dc_context *ctx = dc->ctx; 1117 struct dc_bios *bp; 1118 1119 ctx->dc_bios->regs = &bios_regs; 1120 1121 pool->base.res_cap = &res_cap_61; 1122 pool->base.funcs = &dce60_res_pool_funcs; 1123 1124 1125 /************************************************* 1126 * Resource + asic cap harcoding * 1127 *************************************************/ 1128 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1129 pool->base.pipe_count = res_cap_61.num_timing_generator; 1130 pool->base.timing_generator_count = res_cap_61.num_timing_generator; 1131 dc->caps.max_downscale_ratio = 200; 1132 dc->caps.i2c_speed_in_khz = 40; 1133 dc->caps.max_cursor_size = 64; 1134 dc->caps.is_apu = true; 1135 1136 /************************************************* 1137 * Create resources * 1138 *************************************************/ 1139 1140 bp = ctx->dc_bios; 1141 1142 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1143 pool->base.dp_clock_source = 1144 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1145 1146 pool->base.clock_sources[0] = 1147 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1148 pool->base.clock_sources[1] = 1149 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1150 pool->base.clock_sources[2] = 1151 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1152 pool->base.clk_src_count = 3; 1153 1154 } else { 1155 pool->base.dp_clock_source = 1156 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1157 1158 pool->base.clock_sources[0] = 1159 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1160 pool->base.clock_sources[1] = 1161 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1162 pool->base.clk_src_count = 2; 1163 } 1164 1165 if (pool->base.dp_clock_source == NULL) { 1166 dm_error("DC: failed to create dp clock source!\n"); 1167 BREAK_TO_DEBUGGER(); 1168 goto res_create_fail; 1169 } 1170 1171 for (i = 0; i < pool->base.clk_src_count; i++) { 1172 if (pool->base.clock_sources[i] == NULL) { 1173 dm_error("DC: failed to create clock sources!\n"); 1174 BREAK_TO_DEBUGGER(); 1175 goto res_create_fail; 1176 } 1177 } 1178 1179 pool->base.dmcu = dce_dmcu_create(ctx, 1180 &dmcu_regs, 1181 &dmcu_shift, 1182 &dmcu_mask); 1183 if (pool->base.dmcu == NULL) { 1184 dm_error("DC: failed to create dmcu!\n"); 1185 BREAK_TO_DEBUGGER(); 1186 goto res_create_fail; 1187 } 1188 1189 pool->base.abm = dce_abm_create(ctx, 1190 &abm_regs, 1191 &abm_shift, 1192 &abm_mask); 1193 if (pool->base.abm == NULL) { 1194 dm_error("DC: failed to create abm!\n"); 1195 BREAK_TO_DEBUGGER(); 1196 goto res_create_fail; 1197 } 1198 1199 { 1200 struct irq_service_init_data init_data; 1201 init_data.ctx = dc->ctx; 1202 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1203 if (!pool->base.irqs) 1204 goto res_create_fail; 1205 } 1206 1207 for (i = 0; i < pool->base.pipe_count; i++) { 1208 pool->base.timing_generators[i] = dce60_timing_generator_create( 1209 ctx, i, &dce60_tg_offsets[i]); 1210 if (pool->base.timing_generators[i] == NULL) { 1211 BREAK_TO_DEBUGGER(); 1212 dm_error("DC: failed to create tg!\n"); 1213 goto res_create_fail; 1214 } 1215 1216 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1217 if (pool->base.mis[i] == NULL) { 1218 BREAK_TO_DEBUGGER(); 1219 dm_error("DC: failed to create memory input!\n"); 1220 goto res_create_fail; 1221 } 1222 1223 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1224 if (pool->base.ipps[i] == NULL) { 1225 BREAK_TO_DEBUGGER(); 1226 dm_error("DC: failed to create input pixel processor!\n"); 1227 goto res_create_fail; 1228 } 1229 1230 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1231 if (pool->base.transforms[i] == NULL) { 1232 BREAK_TO_DEBUGGER(); 1233 dm_error("DC: failed to create transform!\n"); 1234 goto res_create_fail; 1235 } 1236 1237 pool->base.opps[i] = dce60_opp_create(ctx, i); 1238 if (pool->base.opps[i] == NULL) { 1239 BREAK_TO_DEBUGGER(); 1240 dm_error("DC: failed to create output pixel processor!\n"); 1241 goto res_create_fail; 1242 } 1243 } 1244 1245 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1246 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1247 if (pool->base.engines[i] == NULL) { 1248 BREAK_TO_DEBUGGER(); 1249 dm_error( 1250 "DC:failed to create aux engine!!\n"); 1251 goto res_create_fail; 1252 } 1253 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1254 if (pool->base.hw_i2cs[i] == NULL) { 1255 BREAK_TO_DEBUGGER(); 1256 dm_error( 1257 "DC:failed to create i2c engine!!\n"); 1258 goto res_create_fail; 1259 } 1260 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1261 if (pool->base.sw_i2cs[i] == NULL) { 1262 BREAK_TO_DEBUGGER(); 1263 dm_error( 1264 "DC:failed to create sw i2c!!\n"); 1265 goto res_create_fail; 1266 } 1267 } 1268 1269 dc->caps.max_planes = pool->base.pipe_count; 1270 1271 for (i = 0; i < dc->caps.max_planes; ++i) 1272 dc->caps.planes[i] = plane_cap; 1273 1274 dc->caps.disable_dp_clk_share = true; 1275 1276 if (!resource_construct(num_virtual_links, dc, &pool->base, 1277 &res_create_funcs)) 1278 goto res_create_fail; 1279 1280 /* Create hardware sequencer */ 1281 dce60_hw_sequencer_construct(dc); 1282 1283 return true; 1284 1285 res_create_fail: 1286 dce60_resource_destruct(pool); 1287 return false; 1288 } 1289 1290 struct resource_pool *dce61_create_resource_pool( 1291 uint8_t num_virtual_links, 1292 struct dc *dc) 1293 { 1294 struct dce110_resource_pool *pool = 1295 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1296 1297 if (!pool) 1298 return NULL; 1299 1300 if (dce61_construct(num_virtual_links, dc, pool)) 1301 return &pool->base; 1302 1303 kfree(pool); 1304 BREAK_TO_DEBUGGER(); 1305 return NULL; 1306 } 1307 1308 static bool dce64_construct( 1309 uint8_t num_virtual_links, 1310 struct dc *dc, 1311 struct dce110_resource_pool *pool) 1312 { 1313 unsigned int i; 1314 struct dc_context *ctx = dc->ctx; 1315 struct dc_bios *bp; 1316 1317 ctx->dc_bios->regs = &bios_regs; 1318 1319 pool->base.res_cap = &res_cap_64; 1320 pool->base.funcs = &dce60_res_pool_funcs; 1321 1322 1323 /************************************************* 1324 * Resource + asic cap harcoding * 1325 *************************************************/ 1326 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1327 pool->base.pipe_count = res_cap_64.num_timing_generator; 1328 pool->base.timing_generator_count = res_cap_64.num_timing_generator; 1329 dc->caps.max_downscale_ratio = 200; 1330 dc->caps.i2c_speed_in_khz = 40; 1331 dc->caps.max_cursor_size = 64; 1332 dc->caps.is_apu = true; 1333 1334 /************************************************* 1335 * Create resources * 1336 *************************************************/ 1337 1338 bp = ctx->dc_bios; 1339 1340 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1341 pool->base.dp_clock_source = 1342 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1343 1344 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */ 1345 pool->base.clock_sources[0] = 1346 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1347 pool->base.clock_sources[1] = 1348 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1349 pool->base.clk_src_count = 2; 1350 1351 } else { 1352 pool->base.dp_clock_source = 1353 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1354 1355 pool->base.clock_sources[0] = 1356 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1357 pool->base.clock_sources[1] = 1358 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1359 pool->base.clk_src_count = 2; 1360 } 1361 1362 if (pool->base.dp_clock_source == NULL) { 1363 dm_error("DC: failed to create dp clock source!\n"); 1364 BREAK_TO_DEBUGGER(); 1365 goto res_create_fail; 1366 } 1367 1368 for (i = 0; i < pool->base.clk_src_count; i++) { 1369 if (pool->base.clock_sources[i] == NULL) { 1370 dm_error("DC: failed to create clock sources!\n"); 1371 BREAK_TO_DEBUGGER(); 1372 goto res_create_fail; 1373 } 1374 } 1375 1376 pool->base.dmcu = dce_dmcu_create(ctx, 1377 &dmcu_regs, 1378 &dmcu_shift, 1379 &dmcu_mask); 1380 if (pool->base.dmcu == NULL) { 1381 dm_error("DC: failed to create dmcu!\n"); 1382 BREAK_TO_DEBUGGER(); 1383 goto res_create_fail; 1384 } 1385 1386 pool->base.abm = dce_abm_create(ctx, 1387 &abm_regs, 1388 &abm_shift, 1389 &abm_mask); 1390 if (pool->base.abm == NULL) { 1391 dm_error("DC: failed to create abm!\n"); 1392 BREAK_TO_DEBUGGER(); 1393 goto res_create_fail; 1394 } 1395 1396 { 1397 struct irq_service_init_data init_data; 1398 init_data.ctx = dc->ctx; 1399 pool->base.irqs = dal_irq_service_dce60_create(&init_data); 1400 if (!pool->base.irqs) 1401 goto res_create_fail; 1402 } 1403 1404 for (i = 0; i < pool->base.pipe_count; i++) { 1405 pool->base.timing_generators[i] = dce60_timing_generator_create( 1406 ctx, i, &dce60_tg_offsets[i]); 1407 if (pool->base.timing_generators[i] == NULL) { 1408 BREAK_TO_DEBUGGER(); 1409 dm_error("DC: failed to create tg!\n"); 1410 goto res_create_fail; 1411 } 1412 1413 pool->base.mis[i] = dce60_mem_input_create(ctx, i); 1414 if (pool->base.mis[i] == NULL) { 1415 BREAK_TO_DEBUGGER(); 1416 dm_error("DC: failed to create memory input!\n"); 1417 goto res_create_fail; 1418 } 1419 1420 pool->base.ipps[i] = dce60_ipp_create(ctx, i); 1421 if (pool->base.ipps[i] == NULL) { 1422 BREAK_TO_DEBUGGER(); 1423 dm_error("DC: failed to create input pixel processor!\n"); 1424 goto res_create_fail; 1425 } 1426 1427 pool->base.transforms[i] = dce60_transform_create(ctx, i); 1428 if (pool->base.transforms[i] == NULL) { 1429 BREAK_TO_DEBUGGER(); 1430 dm_error("DC: failed to create transform!\n"); 1431 goto res_create_fail; 1432 } 1433 1434 pool->base.opps[i] = dce60_opp_create(ctx, i); 1435 if (pool->base.opps[i] == NULL) { 1436 BREAK_TO_DEBUGGER(); 1437 dm_error("DC: failed to create output pixel processor!\n"); 1438 goto res_create_fail; 1439 } 1440 } 1441 1442 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1443 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); 1444 if (pool->base.engines[i] == NULL) { 1445 BREAK_TO_DEBUGGER(); 1446 dm_error( 1447 "DC:failed to create aux engine!!\n"); 1448 goto res_create_fail; 1449 } 1450 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); 1451 if (pool->base.hw_i2cs[i] == NULL) { 1452 BREAK_TO_DEBUGGER(); 1453 dm_error( 1454 "DC:failed to create i2c engine!!\n"); 1455 goto res_create_fail; 1456 } 1457 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); 1458 if (pool->base.sw_i2cs[i] == NULL) { 1459 BREAK_TO_DEBUGGER(); 1460 dm_error( 1461 "DC:failed to create sw i2c!!\n"); 1462 goto res_create_fail; 1463 } 1464 } 1465 1466 dc->caps.max_planes = pool->base.pipe_count; 1467 1468 for (i = 0; i < dc->caps.max_planes; ++i) 1469 dc->caps.planes[i] = plane_cap; 1470 1471 dc->caps.disable_dp_clk_share = true; 1472 1473 if (!resource_construct(num_virtual_links, dc, &pool->base, 1474 &res_create_funcs)) 1475 goto res_create_fail; 1476 1477 /* Create hardware sequencer */ 1478 dce60_hw_sequencer_construct(dc); 1479 1480 return true; 1481 1482 res_create_fail: 1483 dce60_resource_destruct(pool); 1484 return false; 1485 } 1486 1487 struct resource_pool *dce64_create_resource_pool( 1488 uint8_t num_virtual_links, 1489 struct dc *dc) 1490 { 1491 struct dce110_resource_pool *pool = 1492 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1493 1494 if (!pool) 1495 return NULL; 1496 1497 if (dce64_construct(num_virtual_links, dc, pool)) 1498 return &pool->base; 1499 1500 kfree(pool); 1501 BREAK_TO_DEBUGGER(); 1502 return NULL; 1503 } 1504