1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce/dce_11_2_d.h" 30 #include "dce/dce_11_2_sh_mask.h" 31 #include "dce100/dce_clk_mgr.h" 32 #include "dce110/dce110_clk_mgr.h" 33 #include "dce112_clk_mgr.h" 34 #include "dal_asic_id.h" 35 36 /* set register offset */ 37 #define SR(reg_name)\ 38 .reg_name = mm ## reg_name 39 40 /* set register offset with instance */ 41 #define SRI(reg_name, block, id)\ 42 .reg_name = mm ## block ## id ## _ ## reg_name 43 44 static const struct clk_mgr_registers disp_clk_regs = { 45 CLK_COMMON_REG_LIST_DCE_BASE() 46 }; 47 48 static const struct clk_mgr_shift disp_clk_shift = { 49 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 50 }; 51 52 static const struct clk_mgr_mask disp_clk_mask = { 53 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 54 }; 55 56 //TODO: remove use the two broken down functions 57 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) 58 { 59 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 60 struct bp_set_dce_clock_parameters dce_clk_params; 61 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; 62 struct dc *dc = clk_mgr_base->ctx->dc; 63 struct dmcu *dmcu = dc->res_pool->dmcu; 64 int actual_clock = requested_clk_khz; 65 /* Prepare to program display clock*/ 66 memset(&dce_clk_params, 0, sizeof(dce_clk_params)); 67 68 /* Make sure requested clock isn't lower than minimum threshold*/ 69 requested_clk_khz = max(requested_clk_khz, 70 clk_mgr_dce->base.dentist_vco_freq_khz / 62); 71 72 dce_clk_params.target_clock_frequency = requested_clk_khz; 73 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 74 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; 75 76 bp->funcs->set_dce_clock(bp, &dce_clk_params); 77 actual_clock = dce_clk_params.target_clock_frequency; 78 79 /*Program DP ref Clock*/ 80 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ 81 dce_clk_params.target_clock_frequency = 0; 82 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; 83 84 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && 85 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) 86 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = 87 (dce_clk_params.pll_id == 88 CLOCK_SOURCE_COMBO_DISPLAY_PLL0); 89 else 90 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; 91 92 bp->funcs->set_dce_clock(bp, &dce_clk_params); 93 94 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 95 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) 96 dmcu->funcs->set_psr_wait_loop(dmcu, 97 actual_clock / 1000 / 7); 98 } 99 100 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; 101 return actual_clock; 102 } 103 104 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) 105 { 106 struct bp_set_dce_clock_parameters dce_clk_params; 107 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; 108 struct dc *dc = clk_mgr->base.ctx->dc; 109 struct dmcu *dmcu = dc->res_pool->dmcu; 110 int actual_clock = requested_clk_khz; 111 /* Prepare to program display clock*/ 112 memset(&dce_clk_params, 0, sizeof(dce_clk_params)); 113 114 /* Make sure requested clock isn't lower than minimum threshold*/ 115 if (requested_clk_khz > 0) 116 requested_clk_khz = max(requested_clk_khz, 117 clk_mgr->base.dentist_vco_freq_khz / 62); 118 119 dce_clk_params.target_clock_frequency = requested_clk_khz; 120 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 121 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; 122 123 bp->funcs->set_dce_clock(bp, &dce_clk_params); 124 actual_clock = dce_clk_params.target_clock_frequency; 125 126 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 127 if (clk_mgr->dfs_bypass_disp_clk != actual_clock) 128 dmcu->funcs->set_psr_wait_loop(dmcu, 129 actual_clock / 1000 / 7); 130 } 131 132 clk_mgr->dfs_bypass_disp_clk = actual_clock; 133 return actual_clock; 134 135 } 136 137 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) 138 { 139 struct bp_set_dce_clock_parameters dce_clk_params; 140 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; 141 142 memset(&dce_clk_params, 0, sizeof(dce_clk_params)); 143 144 /*Program DP ref Clock*/ 145 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ 146 dce_clk_params.target_clock_frequency = 0; 147 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 148 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; 149 if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) && 150 ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))) 151 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = 152 (dce_clk_params.pll_id == 153 CLOCK_SOURCE_COMBO_DISPLAY_PLL0); 154 else 155 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; 156 157 bp->funcs->set_dce_clock(bp, &dce_clk_params); 158 159 /* Returns the dp_refclk that was set */ 160 return dce_clk_params.target_clock_frequency; 161 } 162 163 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, 164 struct dc_state *context, 165 bool safe_to_lower) 166 { 167 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 168 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; 169 170 /*TODO: W/A for dal3 linux, investigate why this works */ 171 if (!clk_mgr_dce->dfs_bypass_active) 172 patched_disp_clk = patched_disp_clk * 115 / 100; 173 174 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { 175 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk); 176 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; 177 } 178 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); 179 } 180 181 static struct clk_mgr_funcs dce112_funcs = { 182 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, 183 .update_clocks = dce112_update_clocks 184 }; 185 186 void dce112_clk_mgr_construct( 187 struct dc_context *ctx, 188 struct clk_mgr_internal *clk_mgr) 189 { 190 dce_clk_mgr_construct(ctx, clk_mgr); 191 192 clk_mgr->regs = &disp_clk_regs; 193 clk_mgr->clk_mgr_shift = &disp_clk_shift; 194 clk_mgr->clk_mgr_mask = &disp_clk_mask; 195 clk_mgr->base.funcs = &dce112_funcs; 196 } 197