1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include "reg_helper.h" 28 #include "core_types.h" 29 30 #include "dcn31/dcn31_dccg.h" 31 #include "dcn314_dccg.h" 32 #include "dcn20/dcn20_dccg.h" 33 34 #define TO_DCN_DCCG(dccg)\ 35 container_of(dccg, struct dcn_dccg, base) 36 37 #define REG(reg) \ 38 (dccg_dcn->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 43 44 #define CTX \ 45 dccg_dcn->base.ctx 46 #define DC_LOGGER \ 47 dccg->ctx->logger 48 49 static void dccg314_trigger_dio_fifo_resync( 50 struct dccg *dccg) 51 { 52 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 53 uint32_t dispclk_rdivider_value = 0; 54 55 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value); 56 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); 57 } 58 59 static void dccg314_get_pixel_rate_div( 60 struct dccg *dccg, 61 uint32_t otg_inst, 62 uint32_t *k1, 63 uint32_t *k2) 64 { 65 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 66 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; 67 68 *k1 = PIXEL_RATE_DIV_NA; 69 *k2 = PIXEL_RATE_DIV_NA; 70 71 switch (otg_inst) { 72 case 0: 73 REG_GET_2(OTG_PIXEL_RATE_DIV, 74 OTG0_PIXEL_RATE_DIVK1, &val_k1, 75 OTG0_PIXEL_RATE_DIVK2, &val_k2); 76 break; 77 case 1: 78 REG_GET_2(OTG_PIXEL_RATE_DIV, 79 OTG1_PIXEL_RATE_DIVK1, &val_k1, 80 OTG1_PIXEL_RATE_DIVK2, &val_k2); 81 break; 82 case 2: 83 REG_GET_2(OTG_PIXEL_RATE_DIV, 84 OTG2_PIXEL_RATE_DIVK1, &val_k1, 85 OTG2_PIXEL_RATE_DIVK2, &val_k2); 86 break; 87 case 3: 88 REG_GET_2(OTG_PIXEL_RATE_DIV, 89 OTG3_PIXEL_RATE_DIVK1, &val_k1, 90 OTG3_PIXEL_RATE_DIVK2, &val_k2); 91 break; 92 default: 93 BREAK_TO_DEBUGGER(); 94 return; 95 } 96 97 *k1 = val_k1; 98 *k2 = val_k2; 99 } 100 101 static void dccg314_set_pixel_rate_div( 102 struct dccg *dccg, 103 uint32_t otg_inst, 104 enum pixel_rate_div k1, 105 enum pixel_rate_div k2) 106 { 107 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 108 uint32_t cur_k1 = PIXEL_RATE_DIV_NA; 109 uint32_t cur_k2 = PIXEL_RATE_DIV_NA; 110 111 // Don't program 0xF into the register field. Not valid since 112 // K1 / K2 field is only 1 / 2 bits wide 113 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { 114 BREAK_TO_DEBUGGER(); 115 return; 116 } 117 118 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); 119 if (k1 == cur_k1 && k2 == cur_k2) 120 return; 121 122 switch (otg_inst) { 123 case 0: 124 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 125 OTG0_PIXEL_RATE_DIVK1, k1, 126 OTG0_PIXEL_RATE_DIVK2, k2); 127 break; 128 case 1: 129 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 130 OTG1_PIXEL_RATE_DIVK1, k1, 131 OTG1_PIXEL_RATE_DIVK2, k2); 132 break; 133 case 2: 134 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 135 OTG2_PIXEL_RATE_DIVK1, k1, 136 OTG2_PIXEL_RATE_DIVK2, k2); 137 break; 138 case 3: 139 REG_UPDATE_2(OTG_PIXEL_RATE_DIV, 140 OTG3_PIXEL_RATE_DIVK1, k1, 141 OTG3_PIXEL_RATE_DIVK2, k2); 142 break; 143 default: 144 BREAK_TO_DEBUGGER(); 145 return; 146 } 147 } 148 149 static void dccg314_set_dtbclk_p_src( 150 struct dccg *dccg, 151 enum streamclk_source src, 152 uint32_t otg_inst) 153 { 154 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 155 156 uint32_t p_src_sel = 0; /* selects dprefclk */ 157 158 if (src == DTBCLK0) 159 p_src_sel = 2; /* selects dtbclk0 */ 160 161 switch (otg_inst) { 162 case 0: 163 if (src == REFCLK) 164 REG_UPDATE(DTBCLK_P_CNTL, 165 DTBCLK_P0_EN, 0); 166 else 167 REG_UPDATE_2(DTBCLK_P_CNTL, 168 DTBCLK_P0_SRC_SEL, p_src_sel, 169 DTBCLK_P0_EN, 1); 170 break; 171 case 1: 172 if (src == REFCLK) 173 REG_UPDATE(DTBCLK_P_CNTL, 174 DTBCLK_P1_EN, 0); 175 else 176 REG_UPDATE_2(DTBCLK_P_CNTL, 177 DTBCLK_P1_SRC_SEL, p_src_sel, 178 DTBCLK_P1_EN, 1); 179 break; 180 case 2: 181 if (src == REFCLK) 182 REG_UPDATE(DTBCLK_P_CNTL, 183 DTBCLK_P2_EN, 0); 184 else 185 REG_UPDATE_2(DTBCLK_P_CNTL, 186 DTBCLK_P2_SRC_SEL, p_src_sel, 187 DTBCLK_P2_EN, 1); 188 break; 189 case 3: 190 if (src == REFCLK) 191 REG_UPDATE(DTBCLK_P_CNTL, 192 DTBCLK_P3_EN, 0); 193 else 194 REG_UPDATE_2(DTBCLK_P_CNTL, 195 DTBCLK_P3_SRC_SEL, p_src_sel, 196 DTBCLK_P3_EN, 1); 197 break; 198 default: 199 BREAK_TO_DEBUGGER(); 200 return; 201 } 202 203 } 204 205 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 206 static void dccg314_set_dtbclk_dto( 207 struct dccg *dccg, 208 const struct dtbclk_dto_params *params) 209 { 210 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 211 /* DTO Output Rate / Pixel Rate = 1/4 */ 212 int req_dtbclk_khz = params->pixclk_khz / 4; 213 214 if (params->ref_dtbclk_khz && req_dtbclk_khz) { 215 uint32_t modulo, phase; 216 217 // phase / modulo = dtbclk / dtbclk ref 218 modulo = params->ref_dtbclk_khz * 1000; 219 phase = req_dtbclk_khz * 1000; 220 221 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); 222 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); 223 224 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 225 DTBCLK_DTO_ENABLE[params->otg_inst], 1); 226 227 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], 228 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 229 1, 100); 230 231 /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ 232 dccg314_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); 233 234 /* The recommended programming sequence to enable DTBCLK DTO to generate 235 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should 236 * be set only after DTO is enabled 237 */ 238 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 239 PIPE_DTO_SRC_SEL[params->otg_inst], 2); 240 } else { 241 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], 242 DTBCLK_DTO_ENABLE[params->otg_inst], 0, 243 PIPE_DTO_SRC_SEL[params->otg_inst], 1); 244 245 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); 246 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); 247 } 248 } 249 250 void dccg314_set_dpstreamclk( 251 struct dccg *dccg, 252 enum streamclk_source src, 253 int otg_inst, 254 int dp_hpo_inst) 255 { 256 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 257 258 /* set the dtbclk_p source */ 259 dccg314_set_dtbclk_p_src(dccg, src, otg_inst); 260 261 /* enabled to select one of the DTBCLKs for pipe */ 262 switch (dp_hpo_inst) { 263 case 0: 264 REG_UPDATE_2(DPSTREAMCLK_CNTL, 265 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, 266 DPSTREAMCLK0_SRC_SEL, otg_inst); 267 break; 268 case 1: 269 REG_UPDATE_2(DPSTREAMCLK_CNTL, 270 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, 271 DPSTREAMCLK1_SRC_SEL, otg_inst); 272 break; 273 case 2: 274 REG_UPDATE_2(DPSTREAMCLK_CNTL, 275 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, 276 DPSTREAMCLK2_SRC_SEL, otg_inst); 277 break; 278 case 3: 279 REG_UPDATE_2(DPSTREAMCLK_CNTL, 280 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, 281 DPSTREAMCLK3_SRC_SEL, otg_inst); 282 break; 283 default: 284 BREAK_TO_DEBUGGER(); 285 return; 286 } 287 } 288 289 static void dccg314_set_hdmistreamclk( 290 struct dccg *dccg, 291 enum streamclk_source src, 292 uint32_t otg_inst) 293 { 294 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 295 296 /* set the dtbclk_p source */ 297 dccg314_set_dtbclk_p_src(dccg, src, otg_inst); 298 299 if (src == REFCLK) { 300 REG_UPDATE_2(HDMISTREAMCLK_CNTL, 301 HDMISTREAMCLK0_EN, 0, /* SEL_REFCLK */ 302 HDMISTREAMCLK0_DTO_FORCE_DIS, 1); /* DTO_FORCE_BYPASS */ 303 } else { 304 REG_UPDATE_3(HDMISTREAMCLK_CNTL, 305 HDMISTREAMCLK0_EN, 1, /* selects one of the dtbclk_p as per HDMISTREAMCLK0_SRC_SEL */ 306 HDMISTREAMCLK0_SRC_SEL, otg_inst, /* Selects dtbclk_p as source for hdmistreamclk */ 307 HDMISTREAMCLK0_DTO_FORCE_DIS, 1); /* DTO_FORCE_BYPASS */ 308 } 309 } 310 311 static void dccg314_init(struct dccg *dccg) 312 { 313 int otg_inst; 314 315 /* Set HPO stream encoder to use refclk to avoid case where PHY is 316 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which 317 * will cause DCN to hang. 318 */ 319 for (otg_inst = 0; otg_inst < 4; otg_inst++) 320 dccg31_disable_symclk32_se(dccg, otg_inst); 321 322 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 323 for (otg_inst = 0; otg_inst < 2; otg_inst++) 324 dccg31_disable_symclk32_le(dccg, otg_inst); 325 326 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) 327 for (otg_inst = 0; otg_inst < 4; otg_inst++) 328 dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst, 329 otg_inst); 330 331 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 332 for (otg_inst = 0; otg_inst < 5; otg_inst++) 333 dccg31_set_physymclk(dccg, otg_inst, 334 PHYSYMCLK_FORCE_SRC_SYMCLK, false); 335 } 336 337 static void dccg314_set_valid_pixel_rate( 338 struct dccg *dccg, 339 int ref_dtbclk_khz, 340 int otg_inst, 341 int pixclk_khz) 342 { 343 struct dtbclk_dto_params dto_params = {0}; 344 345 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; 346 dto_params.otg_inst = otg_inst; 347 dto_params.pixclk_khz = pixclk_khz; 348 349 dccg314_set_dtbclk_dto(dccg, &dto_params); 350 } 351 352 static void dccg314_dpp_root_clock_control( 353 struct dccg *dccg, 354 unsigned int dpp_inst, 355 bool clock_on) 356 { 357 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 358 359 if (dccg->dpp_clock_gated[dpp_inst] != clock_on) 360 return; 361 362 if (clock_on) { 363 /* turn off the DTO and leave phase/modulo at max */ 364 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0); 365 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 366 DPPCLK0_DTO_PHASE, 0xFF, 367 DPPCLK0_DTO_MODULO, 0xFF); 368 } else { 369 /* turn on the DTO to generate a 0hz clock */ 370 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1); 371 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 372 DPPCLK0_DTO_PHASE, 0, 373 DPPCLK0_DTO_MODULO, 1); 374 } 375 376 dccg->dpp_clock_gated[dpp_inst] = !clock_on; 377 } 378 379 static const struct dccg_funcs dccg314_funcs = { 380 .enable_hdmicharclk = dccg31_enable_hdmicharclk, 381 .disable_hdmicharclk = dccg31_disable_hdmicharclk, 382 .set_hdmistreamclk = dccg314_set_hdmistreamclk, 383 .update_dpp_dto = dccg31_update_dpp_dto, 384 .dpp_root_clock_control = dccg314_dpp_root_clock_control, 385 .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, 386 .dccg_init = dccg314_init, 387 .set_dpstreamclk = dccg314_set_dpstreamclk, 388 .enable_symclk32_se = dccg31_enable_symclk32_se, 389 .disable_symclk32_se = dccg31_disable_symclk32_se, 390 .enable_symclk32_le = dccg31_enable_symclk32_le, 391 .disable_symclk32_le = dccg31_disable_symclk32_le, 392 .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating, 393 .set_physymclk = dccg31_set_physymclk, 394 .set_dtbclk_dto = dccg314_set_dtbclk_dto, 395 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 396 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 397 .otg_add_pixel = dccg31_otg_add_pixel, 398 .otg_drop_pixel = dccg31_otg_drop_pixel, 399 .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, 400 .disable_dsc = dccg31_disable_dscclk, 401 .enable_dsc = dccg31_enable_dscclk, 402 .set_pixel_rate_div = dccg314_set_pixel_rate_div, 403 .get_pixel_rate_div = dccg314_get_pixel_rate_div, 404 .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync, 405 .set_valid_pixel_rate = dccg314_set_valid_pixel_rate, 406 .set_dtbclk_p_src = dccg314_set_dtbclk_p_src, 407 .dccg_read_reg_state = dccg31_read_reg_state, 408 .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ 409 .allow_clock_gating = dccg2_allow_clock_gating, 410 .enable_memory_low_power = dccg2_enable_memory_low_power, 411 .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ 412 }; 413 414 struct dccg *dccg314_create( 415 struct dc_context *ctx, 416 const struct dccg_registers *regs, 417 const struct dccg_shift *dccg_shift, 418 const struct dccg_mask *dccg_mask) 419 { 420 struct dcn_dccg *dccg_dcn = kzalloc_obj(*dccg_dcn); 421 struct dccg *base; 422 423 if (dccg_dcn == NULL) { 424 BREAK_TO_DEBUGGER(); 425 return NULL; 426 } 427 428 base = &dccg_dcn->base; 429 base->ctx = ctx; 430 base->funcs = &dccg314_funcs; 431 432 dccg_dcn->regs = regs; 433 dccg_dcn->dccg_shift = dccg_shift; 434 dccg_dcn->dccg_mask = dccg_mask; 435 436 return &dccg_dcn->base; 437 } 438