1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_3DLUT, 64 PLN_ADDR_TYPE_GRPH_STEREO, 65 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 66 PLN_ADDR_TYPE_RGBEA 67 }; 68 69 struct dc_plane_address { 70 enum dc_plane_addr_type type; 71 bool tmz_surface; 72 union { 73 struct{ 74 PHYSICAL_ADDRESS_LOC addr; 75 PHYSICAL_ADDRESS_LOC cursor_cache_addr; 76 PHYSICAL_ADDRESS_LOC meta_addr; 77 union large_integer dcc_const_color; 78 } grph; 79 80 struct { 81 PHYSICAL_ADDRESS_LOC addr; 82 } lut3d; 83 84 /*stereo*/ 85 struct { 86 PHYSICAL_ADDRESS_LOC left_addr; 87 PHYSICAL_ADDRESS_LOC left_meta_addr; 88 union large_integer left_dcc_const_color; 89 90 PHYSICAL_ADDRESS_LOC right_addr; 91 PHYSICAL_ADDRESS_LOC right_meta_addr; 92 union large_integer right_dcc_const_color; 93 94 PHYSICAL_ADDRESS_LOC left_alpha_addr; 95 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; 96 union large_integer left_alpha_dcc_const_color; 97 98 PHYSICAL_ADDRESS_LOC right_alpha_addr; 99 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; 100 union large_integer right_alpha_dcc_const_color; 101 } grph_stereo; 102 103 /*video progressive*/ 104 struct { 105 PHYSICAL_ADDRESS_LOC luma_addr; 106 PHYSICAL_ADDRESS_LOC luma_meta_addr; 107 union large_integer luma_dcc_const_color; 108 109 PHYSICAL_ADDRESS_LOC chroma_addr; 110 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 111 union large_integer chroma_dcc_const_color; 112 } video_progressive; 113 114 struct { 115 PHYSICAL_ADDRESS_LOC addr; 116 PHYSICAL_ADDRESS_LOC meta_addr; 117 union large_integer dcc_const_color; 118 119 PHYSICAL_ADDRESS_LOC alpha_addr; 120 PHYSICAL_ADDRESS_LOC alpha_meta_addr; 121 union large_integer alpha_dcc_const_color; 122 } rgbea; 123 }; 124 125 union large_integer page_table_base; 126 127 uint8_t vmid; 128 }; 129 130 struct dc_size { 131 int width; 132 int height; 133 }; 134 135 struct rect { 136 int x; 137 int y; 138 int width; 139 int height; 140 }; 141 142 struct plane_size { 143 /* Graphic surface pitch in pixels. 144 * In LINEAR_GENERAL mode, pitch 145 * is 32 pixel aligned. 146 */ 147 int surface_pitch; 148 int chroma_pitch; 149 struct rect surface_size; 150 struct rect chroma_size; 151 }; 152 153 struct dc_plane_dcc_param { 154 bool enable; 155 156 int meta_pitch; 157 bool independent_64b_blks; 158 uint8_t dcc_ind_blk; 159 160 int meta_pitch_c; 161 bool independent_64b_blks_c; 162 uint8_t dcc_ind_blk_c; 163 }; 164 165 /*Displayable pixel format in fb*/ 166 enum surface_pixel_format { 167 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 168 /*TOBE REMOVED paletta 256 colors*/ 169 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 170 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 171 /*16 bpp*/ 172 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 173 /*16 bpp*/ 174 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 175 /*32 bpp*/ 176 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 177 /*32 bpp swaped*/ 178 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 179 180 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 181 /*swaped*/ 182 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 183 /*TOBE REMOVED swaped, XR_BIAS has no differance 184 * for pixel layout than previous and we can 185 * delete this after discusion*/ 186 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 187 /*64 bpp */ 188 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 189 /*swapped*/ 190 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, 191 /*float*/ 192 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 193 /*swaped & float*/ 194 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 195 /*grow graphics here if necessary */ 196 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 197 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 198 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 199 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 200 SURFACE_PIXEL_FORMAT_GRPH_RGBE, 201 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 202 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 203 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 204 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 205 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 206 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 207 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 208 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 209 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 = 210 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 211 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 212 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 213 SURFACE_PIXEL_FORMAT_INVALID 214 215 /*grow 444 video here if necessary */ 216 }; 217 218 219 220 /* Pixel format */ 221 enum pixel_format { 222 /*graph*/ 223 PIXEL_FORMAT_UNINITIALIZED, 224 PIXEL_FORMAT_INDEX8, 225 PIXEL_FORMAT_RGB565, 226 PIXEL_FORMAT_ARGB8888, 227 PIXEL_FORMAT_ARGB2101010, 228 PIXEL_FORMAT_ARGB2101010_XRBIAS, 229 PIXEL_FORMAT_FP16, 230 /*video*/ 231 PIXEL_FORMAT_420BPP8, 232 PIXEL_FORMAT_420BPP10, 233 /*end of pixel format definition*/ 234 PIXEL_FORMAT_INVALID, 235 236 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 237 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 238 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 239 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 240 PIXEL_FORMAT_UNKNOWN 241 }; 242 243 /* 244 * This structure holds a surface address. There could be multiple addresses 245 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 246 * as frame durations and DCC format can also be set. 247 */ 248 #define DC_MAX_DIRTY_RECTS 3 249 struct dc_flip_addrs { 250 struct dc_plane_address address; 251 unsigned long long flip_timestamp_in_us; 252 bool flip_immediate; 253 /* TODO: add flip duration for FreeSync */ 254 bool triplebuffer_flips; 255 unsigned int dirty_rect_count; 256 struct rect dirty_rects[DC_MAX_DIRTY_RECTS]; 257 }; 258 259 enum tile_split_values { 260 DC_DISPLAY_MICRO_TILING = 0x0, 261 DC_THIN_MICRO_TILING = 0x1, 262 DC_DEPTH_MICRO_TILING = 0x2, 263 DC_ROTATED_MICRO_TILING = 0x3, 264 }; 265 266 enum tripleBuffer_enable { 267 DC_TRIPLEBUFFER_DISABLE = 0x0, 268 DC_TRIPLEBUFFER_ENABLE = 0x1, 269 }; 270 enum tile_split_values_new { 271 DC_SURF_TILE_SPLIT_1KB = 0x4, 272 }; 273 274 /* TODO: These values come from hardware spec. We need to readdress this 275 * if they ever change. 276 */ 277 enum array_mode_values { 278 DC_ARRAY_LINEAR_GENERAL = 0, 279 DC_ARRAY_LINEAR_ALLIGNED, 280 DC_ARRAY_1D_TILED_THIN1, 281 DC_ARRAY_1D_TILED_THICK, 282 DC_ARRAY_2D_TILED_THIN1, 283 DC_ARRAY_PRT_TILED_THIN1, 284 DC_ARRAY_PRT_2D_TILED_THIN1, 285 DC_ARRAY_2D_TILED_THICK, 286 DC_ARRAY_2D_TILED_X_THICK, 287 DC_ARRAY_PRT_TILED_THICK, 288 DC_ARRAY_PRT_2D_TILED_THICK, 289 DC_ARRAY_PRT_3D_TILED_THIN1, 290 DC_ARRAY_3D_TILED_THIN1, 291 DC_ARRAY_3D_TILED_THICK, 292 DC_ARRAY_3D_TILED_X_THICK, 293 DC_ARRAY_PRT_3D_TILED_THICK, 294 }; 295 296 enum tile_mode_values { 297 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 298 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 299 }; 300 301 enum swizzle_mode_values { 302 DC_SW_LINEAR = 0, 303 DC_SW_256B_S = 1, 304 DC_SW_256_D = 2, 305 DC_SW_256_R = 3, 306 DC_SW_4KB_S = 5, 307 DC_SW_4KB_D = 6, 308 DC_SW_4KB_R = 7, 309 DC_SW_64KB_S = 9, 310 DC_SW_64KB_D = 10, 311 DC_SW_64KB_R = 11, 312 DC_SW_VAR_S = 13, 313 DC_SW_VAR_D = 14, 314 DC_SW_VAR_R = 15, 315 DC_SW_64KB_S_T = 17, 316 DC_SW_64KB_D_T = 18, 317 DC_SW_4KB_S_X = 21, 318 DC_SW_4KB_D_X = 22, 319 DC_SW_4KB_R_X = 23, 320 DC_SW_64KB_S_X = 25, 321 DC_SW_64KB_D_X = 26, 322 DC_SW_64KB_R_X = 27, 323 DC_SW_VAR_S_X = 29, 324 DC_SW_VAR_D_X = 30, 325 DC_SW_VAR_R_X = 31, 326 DC_SW_MAX = 32, 327 DC_SW_UNKNOWN = DC_SW_MAX 328 }; 329 330 // Definition of swizzle modes with addr3 ASICs 331 enum swizzle_mode_addr3_values { 332 DC_ADDR3_SW_LINEAR = 0, 333 DC_ADDR3_SW_256B_2D = 1, 334 DC_ADDR3_SW_4KB_2D = 2, 335 DC_ADDR3_SW_64KB_2D = 3, 336 DC_ADDR3_SW_256KB_2D = 4, 337 DC_ADDR3_SW_4KB_3D = 5, 338 DC_ADDR3_SW_64KB_3D = 6, 339 DC_ADDR3_SW_256KB_3D = 7, 340 DC_ADDR3_SW_MAX = 8, 341 DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX 342 }; 343 344 enum dc_gfxversion { 345 DcGfxVersion7 = 0, 346 DcGfxVersion8, 347 DcGfxVersion9, 348 DcGfxVersion10, 349 DcGfxVersion11, 350 DcGfxAddr3, 351 DcGfxVersionUnknown 352 }; 353 354 struct dc_tiling_info { 355 unsigned int gfxversion; // Specifies which part of the union to use. Must use DalGfxVersion enum 356 union { 357 struct { 358 /* Specifies the number of memory banks for tiling 359 * purposes. 360 * Only applies to 2D and 3D tiling modes. 361 * POSSIBLE VALUES: 2,4,8,16 362 */ 363 unsigned int num_banks; 364 /* Specifies the number of tiles in the x direction 365 * to be incorporated into the same bank. 366 * Only applies to 2D and 3D tiling modes. 367 * POSSIBLE VALUES: 1,2,4,8 368 */ 369 unsigned int bank_width; 370 unsigned int bank_width_c; 371 /* Specifies the number of tiles in the y direction to 372 * be incorporated into the same bank. 373 * Only applies to 2D and 3D tiling modes. 374 * POSSIBLE VALUES: 1,2,4,8 375 */ 376 unsigned int bank_height; 377 unsigned int bank_height_c; 378 /* Specifies the macro tile aspect ratio. Only applies 379 * to 2D and 3D tiling modes. 380 */ 381 unsigned int tile_aspect; 382 unsigned int tile_aspect_c; 383 /* Specifies the number of bytes that will be stored 384 * contiguously for each tile. 385 * If the tile data requires more storage than this 386 * amount, it is split into multiple slices. 387 * This field must not be larger than 388 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 389 * Only applies to 2D and 3D tiling modes. 390 * For color render targets, TILE_SPLIT >= 256B. 391 */ 392 enum tile_split_values tile_split; 393 enum tile_split_values tile_split_c; 394 /* Specifies the addressing within a tile. 395 * 0x0 - DISPLAY_MICRO_TILING 396 * 0x1 - THIN_MICRO_TILING 397 * 0x2 - DEPTH_MICRO_TILING 398 * 0x3 - ROTATED_MICRO_TILING 399 */ 400 enum tile_mode_values tile_mode; 401 enum tile_mode_values tile_mode_c; 402 /* Specifies the number of pipes and how they are 403 * interleaved in the surface. 404 * Refer to memory addressing document for complete 405 * details and constraints. 406 */ 407 unsigned int pipe_config; 408 /* Specifies the tiling mode of the surface. 409 * THIN tiles use an 8x8x1 tile size. 410 * THICK tiles use an 8x8x4 tile size. 411 * 2D tiling modes rotate banks for successive Z slices 412 * 3D tiling modes rotate pipes and banks for Z slices 413 * Refer to memory addressing document for complete 414 * details and constraints. 415 */ 416 enum array_mode_values array_mode; 417 } gfx8; 418 419 struct { 420 enum swizzle_mode_values swizzle; 421 unsigned int num_pipes; 422 unsigned int max_compressed_frags; 423 unsigned int pipe_interleave; 424 425 unsigned int num_banks; 426 unsigned int num_shader_engines; 427 unsigned int num_rb_per_se; 428 bool shaderEnable; 429 430 bool meta_linear; 431 bool rb_aligned; 432 bool pipe_aligned; 433 unsigned int num_pkrs; 434 } gfx9;/*gfx9, gfx10 and above*/ 435 struct { 436 enum swizzle_mode_addr3_values swizzle; 437 } gfx_addr3;/*gfx with addr3 and above*/ 438 }; 439 }; 440 441 /* Rotation angle */ 442 enum dc_rotation_angle { 443 ROTATION_ANGLE_0 = 0, 444 ROTATION_ANGLE_90, 445 ROTATION_ANGLE_180, 446 ROTATION_ANGLE_270, 447 ROTATION_ANGLE_COUNT 448 }; 449 450 enum dc_scan_direction { 451 SCAN_DIRECTION_UNKNOWN = 0, 452 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 453 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 454 }; 455 456 /** 457 * struct dc_cursor_position: Hardware cursor data. 458 * 459 * This struct keeps the action information related to the cursor that will be 460 * sent and received from our DC core. 461 */ 462 struct dc_cursor_position { 463 /** 464 * @x: It represents the top left abscissa coordinate of the cursor. 465 */ 466 uint32_t x; 467 468 /** 469 * @y: It is the top ordinate of the cursor coordinate. 470 */ 471 uint32_t y; 472 473 /** 474 * @x_hotspot: Define the abscissa point where mouse click happens. 475 */ 476 uint32_t x_hotspot; 477 478 /** 479 * @y_hotspot: Define the ordinate point where mouse click happens. 480 */ 481 uint32_t y_hotspot; 482 483 /** 484 * @enable: This parameter indicates whether hardware cursor should be 485 * enabled. 486 */ 487 bool enable; 488 489 /** 490 * @translate_by_source: Translate cursor x/y by the source rectangle 491 * for each plane. 492 */ 493 bool translate_by_source; 494 }; 495 496 struct dc_cursor_mi_param { 497 unsigned int pixel_clk_khz; 498 unsigned int ref_clk_khz; 499 struct rect viewport; 500 struct rect recout; 501 struct fixed31_32 h_scale_ratio; 502 struct fixed31_32 v_scale_ratio; 503 enum dc_rotation_angle rotation; 504 bool mirror; 505 struct dc_stream_state *stream; 506 }; 507 508 /* IPP related types */ 509 510 enum { 511 GAMMA_RGB_256_ENTRIES = 256, 512 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 513 GAMMA_CS_TFM_1D_ENTRIES = 4096, 514 GAMMA_CUSTOM_ENTRIES = 4096, 515 GAMMA_MAX_ENTRIES = 4096 516 }; 517 518 enum dc_gamma_type { 519 GAMMA_RGB_256 = 1, 520 GAMMA_RGB_FLOAT_1024 = 2, 521 GAMMA_CS_TFM_1D = 3, 522 GAMMA_CUSTOM = 4, 523 }; 524 525 struct dc_csc_transform { 526 uint16_t matrix[12]; 527 bool enable_adjustment; 528 }; 529 530 struct dc_rgb_fixed { 531 struct fixed31_32 red; 532 struct fixed31_32 green; 533 struct fixed31_32 blue; 534 }; 535 536 struct dc_gamma { 537 struct kref refcount; 538 enum dc_gamma_type type; 539 unsigned int num_entries; 540 541 struct dc_gamma_entries { 542 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 543 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 544 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 545 } entries; 546 547 /* private to DC core */ 548 struct dc_context *ctx; 549 550 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 551 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 552 */ 553 bool is_identity; 554 }; 555 556 /* Used by both ipp amd opp functions*/ 557 /* TODO: to be consolidated with enum color_space */ 558 559 /** 560 * enum dc_cursor_color_format - DC cursor programming mode 561 * 562 * This enum is for programming CURSOR_MODE register field. What this register 563 * should be programmed to depends on OS requested cursor shape flags and what 564 * we stored in the cursor surface. 565 */ 566 enum dc_cursor_color_format { 567 CURSOR_MODE_MONO, 568 CURSOR_MODE_COLOR_1BIT_AND, 569 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 570 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 571 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 572 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 573 }; 574 575 /* 576 * This is all the parameters required by DAL in order to update the cursor 577 * attributes, including the new cursor image surface address, size, hotspot 578 * location, color format, etc. 579 */ 580 581 union dc_cursor_attribute_flags { 582 struct { 583 uint32_t ENABLE_MAGNIFICATION:1; 584 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 585 uint32_t HORIZONTAL_MIRROR:1; 586 uint32_t VERTICAL_MIRROR:1; 587 uint32_t INVERT_PIXEL_DATA:1; 588 uint32_t ZERO_EXPANSION:1; 589 uint32_t MIN_MAX_INVERT:1; 590 uint32_t ENABLE_CURSOR_DEGAMMA:1; 591 uint32_t RESERVED:24; 592 } bits; 593 uint32_t value; 594 }; 595 596 struct dc_cursor_attributes { 597 /** 598 * @address: This field represents the framebuffer address associated 599 * with the cursor. It is important to highlight that this address is 600 * divided into a high and low parts. 601 */ 602 PHYSICAL_ADDRESS_LOC address; 603 604 /** 605 * @pitch: Cursor line stride. 606 */ 607 uint32_t pitch; 608 609 /** 610 * @width: Width should correspond to cursor surface width. 611 */ 612 uint32_t width; 613 /** 614 * @heigh: Height should correspond to cursor surface heigh. 615 */ 616 uint32_t height; 617 618 /** 619 * @color_format: DC cursor programming mode. 620 */ 621 enum dc_cursor_color_format color_format; 622 /** 623 * @sdr_white_level: Boosting (SDR) cursor in HDR mode. 624 */ 625 uint32_t sdr_white_level; 626 627 /** 628 * @rotation_angle: In case we support HW Cursor rotation in the future 629 */ 630 enum dc_rotation_angle rotation_angle; 631 632 union dc_cursor_attribute_flags attribute_flags; 633 }; 634 635 struct dpp_cursor_attributes { 636 int bias; 637 int scale; 638 }; 639 640 /* OPP */ 641 642 enum dc_color_space { 643 COLOR_SPACE_UNKNOWN, 644 COLOR_SPACE_SRGB, 645 COLOR_SPACE_XR_RGB, 646 COLOR_SPACE_SRGB_LIMITED, 647 COLOR_SPACE_MSREF_SCRGB, 648 COLOR_SPACE_YCBCR601, 649 COLOR_SPACE_YCBCR709, 650 COLOR_SPACE_XV_YCC_709, 651 COLOR_SPACE_XV_YCC_601, 652 COLOR_SPACE_YCBCR601_LIMITED, 653 COLOR_SPACE_YCBCR709_LIMITED, 654 COLOR_SPACE_2020_RGB_FULLRANGE, 655 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 656 COLOR_SPACE_2020_YCBCR_LIMITED, 657 COLOR_SPACE_2020_YCBCR_FULL, 658 COLOR_SPACE_ADOBERGB, 659 COLOR_SPACE_DCIP3, 660 COLOR_SPACE_DISPLAYNATIVE, 661 COLOR_SPACE_DOLBYVISION, 662 COLOR_SPACE_APPCTRL, 663 COLOR_SPACE_CUSTOMPOINTS, 664 COLOR_SPACE_YCBCR709_BLACK, 665 COLOR_SPACE_2020_YCBCR = COLOR_SPACE_2020_YCBCR_LIMITED, 666 }; 667 668 enum dc_dither_option { 669 DITHER_OPTION_DEFAULT, 670 DITHER_OPTION_DISABLE, 671 DITHER_OPTION_FM6, 672 DITHER_OPTION_FM8, 673 DITHER_OPTION_FM10, 674 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 675 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 676 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 677 DITHER_OPTION_SPATIAL6, 678 DITHER_OPTION_SPATIAL8, 679 DITHER_OPTION_SPATIAL10, 680 DITHER_OPTION_TRUN6, 681 DITHER_OPTION_TRUN8, 682 DITHER_OPTION_TRUN10, 683 DITHER_OPTION_TRUN10_SPATIAL8, 684 DITHER_OPTION_TRUN10_SPATIAL6, 685 DITHER_OPTION_TRUN10_FM8, 686 DITHER_OPTION_TRUN10_FM6, 687 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 688 DITHER_OPTION_SPATIAL10_FM8, 689 DITHER_OPTION_SPATIAL10_FM6, 690 DITHER_OPTION_TRUN8_SPATIAL6, 691 DITHER_OPTION_TRUN8_FM6, 692 DITHER_OPTION_SPATIAL8_FM6, 693 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 694 DITHER_OPTION_INVALID 695 }; 696 697 enum dc_quantization_range { 698 QUANTIZATION_RANGE_UNKNOWN, 699 QUANTIZATION_RANGE_FULL, 700 QUANTIZATION_RANGE_LIMITED 701 }; 702 703 enum dc_dynamic_expansion { 704 DYN_EXPANSION_AUTO, 705 DYN_EXPANSION_DISABLE 706 }; 707 708 /* XFM */ 709 710 /* used in struct dc_plane_state */ 711 struct scaling_taps { 712 uint32_t v_taps; 713 uint32_t h_taps; 714 uint32_t v_taps_c; 715 uint32_t h_taps_c; 716 bool integer_scaling; 717 }; 718 719 enum dc_timing_standard { 720 DC_TIMING_STANDARD_UNDEFINED, 721 DC_TIMING_STANDARD_DMT, 722 DC_TIMING_STANDARD_GTF, 723 DC_TIMING_STANDARD_CVT, 724 DC_TIMING_STANDARD_CVT_RB, 725 DC_TIMING_STANDARD_CEA770, 726 DC_TIMING_STANDARD_CEA861, 727 DC_TIMING_STANDARD_HDMI, 728 DC_TIMING_STANDARD_TV_NTSC, 729 DC_TIMING_STANDARD_TV_NTSC_J, 730 DC_TIMING_STANDARD_TV_PAL, 731 DC_TIMING_STANDARD_TV_PAL_M, 732 DC_TIMING_STANDARD_TV_PAL_CN, 733 DC_TIMING_STANDARD_TV_SECAM, 734 DC_TIMING_STANDARD_EXPLICIT, 735 /*!< For explicit timings from EDID, VBIOS, etc.*/ 736 DC_TIMING_STANDARD_USER_OVERRIDE, 737 /*!< For mode timing override by user*/ 738 DC_TIMING_STANDARD_MAX 739 }; 740 741 enum dc_color_depth { 742 COLOR_DEPTH_UNDEFINED, 743 COLOR_DEPTH_666, 744 COLOR_DEPTH_888, 745 COLOR_DEPTH_101010, 746 COLOR_DEPTH_121212, 747 COLOR_DEPTH_141414, 748 COLOR_DEPTH_161616, 749 COLOR_DEPTH_999, 750 COLOR_DEPTH_111111, 751 COLOR_DEPTH_COUNT 752 }; 753 754 enum dc_pixel_encoding { 755 PIXEL_ENCODING_UNDEFINED, 756 PIXEL_ENCODING_RGB, 757 PIXEL_ENCODING_YCBCR422, 758 PIXEL_ENCODING_YCBCR444, 759 PIXEL_ENCODING_YCBCR420, 760 PIXEL_ENCODING_COUNT 761 }; 762 763 enum dc_aspect_ratio { 764 ASPECT_RATIO_NO_DATA, 765 ASPECT_RATIO_4_3, 766 ASPECT_RATIO_16_9, 767 ASPECT_RATIO_64_27, 768 ASPECT_RATIO_256_135, 769 ASPECT_RATIO_FUTURE 770 }; 771 772 enum scanning_type { 773 SCANNING_TYPE_NODATA = 0, 774 SCANNING_TYPE_OVERSCAN, 775 SCANNING_TYPE_UNDERSCAN, 776 SCANNING_TYPE_FUTURE, 777 SCANNING_TYPE_UNDEFINED 778 }; 779 780 struct dc_crtc_timing_flags { 781 uint32_t INTERLACE :1; 782 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 783 it is positive polarity --reversed with dal1 or video bios define*/ 784 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 785 it is positive polarity --reversed with dal1 or video bios define*/ 786 787 uint32_t HORZ_COUNT_BY_TWO:1; 788 789 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 790 timing can be driven in 3D format only 791 and there is no corresponding 2D timing*/ 792 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 793 (right eye = '1', left eye = '0') */ 794 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 795 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 796 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 797 because corresponding 2D timing also present in the list*/ 798 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 799 and we want to match priority of corresponding 3D timing*/ 800 uint32_t Y_ONLY :1; 801 802 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 803 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 804 805 uint32_t FORCE_HDR :1; 806 807 /* HDMI 2.0 - Support scrambling for TMDS character 808 * rates less than or equal to 340Mcsc */ 809 uint32_t LTE_340MCSC_SCRAMBLE:1; 810 811 uint32_t DSC : 1; /* Use DSC with this timing */ 812 uint32_t VBLANK_SYNCHRONIZABLE: 1; 813 }; 814 815 enum dc_timing_3d_format { 816 TIMING_3D_FORMAT_NONE, 817 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 818 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 819 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 820 /* for active DP-HDMI dongle*/ 821 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 822 TIMING_3D_FORMAT_HW_FRAME_PACKING, 823 TIMING_3D_FORMAT_SW_FRAME_PACKING, 824 TIMING_3D_FORMAT_ROW_INTERLEAVE, 825 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 826 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 827 TIMING_3D_FORMAT_SIDE_BY_SIDE, 828 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 829 TIMING_3D_FORMAT_SBS_SW_PACKED, 830 /* Side-by-side, packed by application/driver into 2D frame*/ 831 TIMING_3D_FORMAT_TB_SW_PACKED, 832 /* Top-and-bottom, packed by application/driver into 2D frame*/ 833 834 TIMING_3D_FORMAT_MAX, 835 }; 836 837 #define DC_DSC_QP_SET_SIZE 15 838 #define DC_DSC_RC_BUF_THRESH_SIZE 14 839 struct dc_dsc_rc_params_override { 840 int32_t rc_model_size; 841 int32_t rc_buf_thresh[DC_DSC_RC_BUF_THRESH_SIZE]; 842 int32_t rc_minqp[DC_DSC_QP_SET_SIZE]; 843 int32_t rc_maxqp[DC_DSC_QP_SET_SIZE]; 844 int32_t rc_offset[DC_DSC_QP_SET_SIZE]; 845 846 int32_t rc_tgt_offset_hi; 847 int32_t rc_tgt_offset_lo; 848 int32_t rc_edge_factor; 849 int32_t rc_quant_incr_limit0; 850 int32_t rc_quant_incr_limit1; 851 852 int32_t initial_fullness_offset; 853 int32_t initial_delay; 854 855 int32_t flatness_min_qp; 856 int32_t flatness_max_qp; 857 int32_t flatness_det_thresh; 858 }; 859 860 struct dc_dsc_config { 861 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 862 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 863 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 864 bool block_pred_enable; /* DSC block prediction enable */ 865 uint32_t linebuf_depth; /* DSC line buffer depth */ 866 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 867 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 868 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 869 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ 870 bool is_dp; /* indicate if DSC is applied based on DP's capability */ 871 uint32_t mst_pbn; /* pbn of display on dsc mst hub */ 872 const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */ 873 }; 874 875 /** 876 * struct dc_crtc_timing - Timing parameters used to configure DCN blocks 877 * 878 * DCN provides multiple signals and parameters that can be used to adjust 879 * timing parameters, this struct aggregate multiple of these values for easy 880 * access. In this struct, fields prefixed with h_* are related to horizontal 881 * timing, and v_* to vertical timing. Keep in mind that when we talk about 882 * vertical timings, the values, in general, are described in the number of 883 * lines; on the other hand, the horizontal values are in pixels. 884 */ 885 struct dc_crtc_timing { 886 /** 887 * @h_total: The total number of pixels from the rising edge of HSync 888 * until the rising edge of the current HSync. 889 */ 890 uint32_t h_total; 891 892 /** 893 * @h_border_left: The black pixels related to the left border 894 */ 895 uint32_t h_border_left; 896 897 /** 898 * @h_addressable: It is the range of pixels displayed horizontally. 899 * For example, if the display resolution is 3840@2160, the horizontal 900 * addressable area is 3840. 901 */ 902 uint32_t h_addressable; 903 904 /** 905 * @h_border_right: The black pixels related to the right border 906 */ 907 uint32_t h_border_right; 908 909 /** 910 * @h_front_porch: Period (in pixels) between HBlank start and the 911 * rising edge of HSync. 912 */ 913 uint32_t h_front_porch; 914 915 /** 916 * @h_sync_width: HSync duration in pixels. 917 */ 918 uint32_t h_sync_width; 919 920 /** 921 * @v_total: It is the total number of lines from the rising edge of 922 * the previous VSync until the rising edge of the current VSync. 923 * 924 * |--------------------------| 925 * +-+ V_TOTAL +-+ 926 * | | | | 927 * VSync ---+ +--------- // -----------+ +--- 928 */ 929 uint32_t v_total; 930 931 /** 932 * @v_border_top: The black border on the top. 933 */ 934 uint32_t v_border_top; 935 936 /** 937 * @v_addressable: It is the range of the scanout at which the 938 * framebuffer is displayed. For example, if the display resolution is 939 * 3840@2160, the addressable area is 2160 lines, or if the resolution 940 * is 1920x1080, the addressable area is 1080 lines. 941 */ 942 uint32_t v_addressable; 943 944 /** 945 * @v_border_bottom: The black border on the bottom. 946 */ 947 uint32_t v_border_bottom; 948 949 /** 950 * @v_front_porch: Period (in lines) between VBlank start and rising 951 * edge of VSync. 952 * +-+ 953 * VSync | | 954 * ----------+ +--------... 955 * +------------------... 956 * VBlank | 957 * --+ 958 * |-------| 959 * v_front_porch 960 */ 961 uint32_t v_front_porch; 962 963 /** 964 * @v_sync_width: VSync signal width in lines. 965 */ 966 uint32_t v_sync_width; 967 968 /** 969 * @pix_clk_100hz: Pipe pixel precision 970 * 971 * This field is used to communicate pixel clocks with 100 Hz accuracy 972 * from dc_crtc_timing to BIOS command table. 973 */ 974 uint32_t pix_clk_100hz; 975 976 uint32_t min_refresh_in_uhz; 977 uint32_t max_refresh_in_uhz; 978 979 uint32_t vic; 980 uint32_t hdmi_vic; 981 uint32_t rid; 982 uint32_t fr_index; 983 uint32_t frl_uncompressed_video_bandwidth_in_kbps; 984 enum dc_timing_3d_format timing_3d_format; 985 enum dc_color_depth display_color_depth; 986 enum dc_pixel_encoding pixel_encoding; 987 enum dc_aspect_ratio aspect_ratio; 988 enum scanning_type scan_type; 989 990 struct dc_crtc_timing_flags flags; 991 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 992 struct dc_dsc_config dsc_cfg; 993 994 /* The number of pixels that HBlank has been expanded by from the original EDID timing. */ 995 uint32_t expanded_hblank; 996 }; 997 998 enum trigger_delay { 999 TRIGGER_DELAY_NEXT_PIXEL = 0, 1000 TRIGGER_DELAY_NEXT_LINE, 1001 }; 1002 1003 enum crtc_event { 1004 CRTC_EVENT_VSYNC_RISING = 0, 1005 CRTC_EVENT_VSYNC_FALLING 1006 }; 1007 1008 struct crtc_trigger_info { 1009 bool enabled; 1010 struct dc_stream_state *event_source; 1011 enum crtc_event event; 1012 enum trigger_delay delay; 1013 }; 1014 1015 struct dc_crtc_timing_adjust { 1016 uint32_t v_total_min; 1017 uint32_t v_total_max; 1018 uint32_t v_total_mid; 1019 uint32_t v_total_mid_frame_num; 1020 uint32_t allow_otg_v_count_halt; 1021 uint8_t timing_adjust_pending; 1022 }; 1023 1024 1025 /* Passed on init */ 1026 enum vram_type { 1027 VIDEO_MEMORY_TYPE_GDDR5 = 2, 1028 VIDEO_MEMORY_TYPE_DDR3 = 3, 1029 VIDEO_MEMORY_TYPE_DDR4 = 4, 1030 VIDEO_MEMORY_TYPE_HBM = 5, 1031 VIDEO_MEMORY_TYPE_GDDR6 = 6, 1032 }; 1033 1034 enum dwb_cnv_out_bpc { 1035 DWB_CNV_OUT_BPC_8BPC = 0, 1036 DWB_CNV_OUT_BPC_10BPC = 1, 1037 }; 1038 1039 enum dwb_output_depth { 1040 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 1041 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 1042 }; 1043 1044 enum dwb_capture_rate { 1045 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 1046 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 1047 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 1048 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 1049 }; 1050 1051 enum dwb_scaler_mode { 1052 dwb_scaler_mode_bypass444 = 0, 1053 dwb_scaler_mode_rgb444 = 1, 1054 dwb_scaler_mode_yuv444 = 2, 1055 dwb_scaler_mode_yuv420 = 3 1056 }; 1057 1058 enum dwb_subsample_position { 1059 DWB_INTERSTITIAL_SUBSAMPLING = 0, 1060 DWB_COSITED_SUBSAMPLING = 1 1061 }; 1062 1063 enum dwb_stereo_eye_select { 1064 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 1065 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 1066 }; 1067 1068 enum dwb_stereo_type { 1069 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 1070 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 1071 }; 1072 1073 enum dwb_out_format { 1074 DWB_OUT_FORMAT_32BPP_ARGB = 0, 1075 DWB_OUT_FORMAT_32BPP_RGBA = 1, 1076 DWB_OUT_FORMAT_64BPP_ARGB = 2, 1077 DWB_OUT_FORMAT_64BPP_RGBA = 3 1078 }; 1079 1080 enum dwb_out_denorm { 1081 DWB_OUT_DENORM_10BPC = 0, 1082 DWB_OUT_DENORM_8BPC = 1, 1083 DWB_OUT_DENORM_BYPASS = 2 1084 }; 1085 1086 enum cm_gamut_remap_select { 1087 CM_GAMUT_REMAP_MODE_BYPASS = 0, 1088 CM_GAMUT_REMAP_MODE_RAMA_COEFF, 1089 CM_GAMUT_REMAP_MODE_RAMB_COEFF, 1090 CM_GAMUT_REMAP_MODE_RESERVED 1091 }; 1092 1093 enum cm_gamut_coef_format { 1094 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, 1095 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 1096 }; 1097 1098 enum mpcc_gamut_remap_mode_select { 1099 MPCC_GAMUT_REMAP_MODE_SELECT_0 = 0, 1100 MPCC_GAMUT_REMAP_MODE_SELECT_1, 1101 MPCC_GAMUT_REMAP_MODE_SELECT_2 1102 }; 1103 1104 enum mpcc_gamut_remap_id { 1105 MPCC_OGAM_GAMUT_REMAP, 1106 MPCC_MCM_FIRST_GAMUT_REMAP, 1107 MPCC_MCM_SECOND_GAMUT_REMAP 1108 }; 1109 1110 enum cursor_matrix_mode { 1111 CUR_MATRIX_BYPASS = 0, 1112 CUR_MATRIX_SET_A, 1113 CUR_MATRIX_SET_B 1114 }; 1115 1116 struct mcif_warmup_params { 1117 union large_integer start_address; 1118 unsigned int address_increment; 1119 unsigned int region_size; 1120 unsigned int p_vmid; 1121 }; 1122 1123 #define MCIF_BUF_COUNT 4 1124 1125 struct mcif_buf_params { 1126 unsigned long long luma_address[MCIF_BUF_COUNT]; 1127 unsigned long long chroma_address[MCIF_BUF_COUNT]; 1128 unsigned int luma_pitch; 1129 unsigned int chroma_pitch; 1130 unsigned int warmup_pitch; 1131 unsigned int swlock; 1132 unsigned int p_vmid; 1133 }; 1134 1135 1136 #define MAX_TG_COLOR_VALUE 0x3FF 1137 struct tg_color { 1138 /* Maximum 10 bits color value */ 1139 uint16_t color_r_cr; 1140 uint16_t color_g_y; 1141 uint16_t color_b_cb; 1142 }; 1143 1144 enum symclk_state { 1145 SYMCLK_OFF_TX_OFF, 1146 SYMCLK_ON_TX_ON, 1147 SYMCLK_ON_TX_OFF, 1148 }; 1149 1150 struct phy_state { 1151 struct { 1152 uint8_t otg : 1; 1153 uint8_t reserved : 7; 1154 } symclk_ref_cnts; 1155 enum symclk_state symclk_state; 1156 }; 1157 1158 #endif /* DC_HW_TYPES_H */ 1159 1160