xref: /linux/drivers/net/ethernet/mellanox/mlx5/core/lib/aso.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3 
4 #ifndef __MLX5_LIB_ASO_H__
5 #define __MLX5_LIB_ASO_H__
6 
7 #include <linux/mlx5/qp.h>
8 #include "mlx5_core.h"
9 
10 #define MLX5_ASO_WQEBBS \
11 	(DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_BB))
12 #define MLX5_ASO_WQEBBS_DATA \
13 	(DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe_data), MLX5_SEND_WQE_BB))
14 #define ASO_CTRL_READ_EN BIT(0)
15 #define MLX5_WQE_CTRL_WQE_OPC_MOD_SHIFT 24
16 #define MLX5_MACSEC_ASO_DS_CNT (DIV_ROUND_UP(sizeof(struct mlx5_aso_wqe), MLX5_SEND_WQE_DS))
17 
18 #define ASO_CTRL_READ_EN BIT(0)
19 struct mlx5_wqe_aso_ctrl_seg {
20 	__be32  va_h;
21 	__be32  va_l; /* include read_enable */
22 	__be32  l_key;
23 	u8      data_mask_mode;
24 	u8      condition_1_0_operand;
25 	u8      condition_1_0_offset;
26 	u8      data_offset_condition_operand;
27 	__be32  condition_0_data;
28 	__be32  condition_0_mask;
29 	__be32  condition_1_data;
30 	__be32  condition_1_mask;
31 	__be64  bitwise_data;
32 	__be64  data_mask;
33 };
34 
35 struct mlx5_wqe_aso_data_seg {
36 	__be32  bytewise_data[16];
37 };
38 
39 struct mlx5_aso_wqe {
40 	struct mlx5_wqe_ctrl_seg      ctrl;
41 	struct mlx5_wqe_aso_ctrl_seg  aso_ctrl;
42 };
43 
44 struct mlx5_aso_wqe_data {
45 	struct mlx5_wqe_ctrl_seg      ctrl;
46 	struct mlx5_wqe_aso_ctrl_seg  aso_ctrl;
47 	struct mlx5_wqe_aso_data_seg  aso_data;
48 };
49 
50 enum {
51 	MLX5_ASO_LOGICAL_AND,
52 	MLX5_ASO_LOGICAL_OR,
53 };
54 
55 enum {
56 	MLX5_ASO_ALWAYS_FALSE,
57 	MLX5_ASO_ALWAYS_TRUE,
58 	MLX5_ASO_EQUAL,
59 	MLX5_ASO_NOT_EQUAL,
60 	MLX5_ASO_GREATER_OR_EQUAL,
61 	MLX5_ASO_LESSER_OR_EQUAL,
62 	MLX5_ASO_LESSER,
63 	MLX5_ASO_GREATER,
64 	MLX5_ASO_CYCLIC_GREATER,
65 	MLX5_ASO_CYCLIC_LESSER,
66 };
67 
68 enum {
69 	MLX5_ASO_DATA_MASK_MODE_BITWISE_64BIT,
70 	MLX5_ASO_DATA_MASK_MODE_BYTEWISE_64BYTE,
71 	MLX5_ASO_DATA_MASK_MODE_CALCULATED_64BYTE,
72 };
73 
74 enum {
75 	MLX5_ACCESS_ASO_OPC_MOD_IPSEC = 0x0,
76 	MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2,
77 	MLX5_ACCESS_ASO_OPC_MOD_MACSEC = 0x5,
78 };
79 
80 struct mlx5_aso;
81 
82 struct mlx5_aso_wqe *mlx5_aso_get_wqe(struct mlx5_aso *aso);
83 void mlx5_aso_build_wqe(struct mlx5_aso *aso, u8 ds_cnt,
84 			struct mlx5_aso_wqe *aso_wqe,
85 			u32 obj_id, u32 opc_mode);
86 void mlx5_aso_post_wqe(struct mlx5_aso *aso, bool with_data,
87 		       struct mlx5_wqe_ctrl_seg *doorbell_cseg);
88 int mlx5_aso_poll_cq(struct mlx5_aso *aso, bool with_data);
89 
90 struct mlx5_aso *mlx5_aso_create(struct mlx5_core_dev *mdev, u32 pdn);
91 void mlx5_aso_destroy(struct mlx5_aso *aso);
92 #endif /* __MLX5_LIB_ASO_H__ */
93