xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		i2c0 = &i2c0;
15		serial0 = &scif1;
16		serial1 = &scif3;
17		serial3 = &scif0;
18		mmc1 = &sdhi1;
19	};
20
21	chosen {
22		bootargs = "ignore_loglevel";
23		stdout-path = "serial3:115200n8";
24	};
25
26	keys {
27		compatible = "gpio-keys";
28
29		key-1 {
30			interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
31			linux,code = <KEY_1>;
32			label = "USER_SW1";
33			wakeup-source;
34			debounce-interval = <20>;
35		};
36
37		key-2 {
38			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
39			linux,code = <KEY_2>;
40			label = "USER_SW2";
41			wakeup-source;
42			debounce-interval = <20>;
43		};
44
45		key-3 {
46			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
47			linux,code = <KEY_3>;
48			label = "USER_SW3";
49			wakeup-source;
50			debounce-interval = <20>;
51		};
52	};
53
54	snd_rzg3s: sound {
55		compatible = "simple-audio-card";
56		simple-audio-card,format = "i2s";
57		simple-audio-card,bitclock-master = <&cpu_dai>;
58		simple-audio-card,frame-master = <&cpu_dai>;
59		simple-audio-card,mclk-fs = <256>;
60
61		cpu_dai: simple-audio-card,cpu {
62			sound-dai = <&ssi3>;
63		};
64
65		codec_dai: simple-audio-card,codec {
66			sound-dai = <&da7212>;
67			clocks = <&versa3 1>;
68		};
69	};
70
71	vcc_sdhi1: regulator-vcc-sdhi1 {
72		compatible = "regulator-fixed";
73		regulator-name = "SDHI1 Vcc";
74		regulator-min-microvolt = <3300000>;
75		regulator-max-microvolt = <3300000>;
76		gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
77		enable-active-high;
78	};
79
80	vccq_sdhi1: regulator-vccq-sdhi1 {
81		compatible = "regulator-gpio";
82		regulator-name = "SDHI1 VccQ";
83		regulator-min-microvolt = <1800000>;
84		regulator-max-microvolt = <3300000>;
85		gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
86		gpios-states = <1>;
87		states = <3300000 1>, <1800000 0>;
88	};
89};
90
91&audio_clk2 {
92	clock-frequency = <12288000>;
93};
94
95&ehci0 {
96	dr_mode = "otg";
97	status = "okay";
98};
99
100&ehci1 {
101	status = "okay";
102};
103
104&hsusb {
105	dr_mode = "otg";
106	status = "okay";
107};
108
109&i2c0 {
110	status = "okay";
111
112	clock-frequency = <1000000>;
113
114	da7212: codec@1a {
115		compatible = "dlg,da7212";
116		reg = <0x1a>;
117
118		clocks = <&versa3 1>;
119		clock-names = "mclk";
120
121		#sound-dai-cells = <0>;
122
123		dlg,micbias1-lvl = <2500>;
124		dlg,micbias2-lvl = <2500>;
125		dlg,dmic-data-sel = "lrise_rfall";
126		dlg,dmic-samplephase = "between_clkedge";
127		dlg,dmic-clkrate = <3000000>;
128
129		VDDA-supply = <&reg_1p8v>;
130		VDDSP-supply = <&reg_3p3v>;
131		VDDMIC-supply = <&reg_3p3v>;
132		VDDIO-supply = <&reg_1p8v>;
133	};
134};
135
136&i2c1 {
137	status = "okay";
138
139	clock-frequency = <400000>;
140
141	power-monitor@44 {
142		compatible = "renesas,isl28022";
143		reg = <0x44>;
144		shunt-resistor-micro-ohms = <8000>;
145		renesas,average-samples = <32>;
146	};
147};
148
149&ohci0 {
150	dr_mode = "otg";
151	status = "okay";
152};
153
154&ohci1 {
155	status = "okay";
156};
157
158&phyrst {
159	status = "okay";
160};
161
162&pinctrl {
163	audio_clock_pins: audio-clock {
164		pins = "AUDIO_CLK1", "AUDIO_CLK2";
165		input-enable;
166	};
167
168	key-1-gpio-hog {
169		gpio-hog;
170		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
171		input;
172		line-name = "key-1-gpio-irq";
173	};
174
175	key-2-gpio-hog {
176		gpio-hog;
177		gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
178		input;
179		line-name = "key-2-gpio-irq";
180	};
181
182	key-3-gpio-hog {
183		gpio-hog;
184		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
185		input;
186		line-name = "key-3-gpio-irq";
187	};
188
189	scif0_pins: scif0 {
190		pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
191			 <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
192	};
193
194	scif3_pins: scif3 {
195		pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
196			 <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
197	};
198
199	sdhi1_pins: sd1 {
200		data {
201			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
202			power-source = <3300>;
203		};
204
205		ctrl {
206			pins = "SD1_CLK", "SD1_CMD";
207			power-source = <3300>;
208		};
209
210		cd {
211			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
212		};
213	};
214
215	sdhi1_pins_uhs: sd1-uhs {
216		data {
217			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
218			power-source = <1800>;
219		};
220
221		ctrl {
222			pins = "SD1_CLK", "SD1_CMD";
223			power-source = <1800>;
224		};
225
226		cd {
227			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
228		};
229	};
230
231	ssi3_pins: ssi3 {
232		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
233			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
234			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
235			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
236	};
237
238	usb0_pins: usb0 {
239		peri {
240			pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
241				 <RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */
242		};
243
244		otg {
245			pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
246			bias-pull-up;
247		};
248	};
249
250	usb1_pins: usb1 {
251		pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
252			 <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
253	};
254};
255
256&scif0 {
257	pinctrl-names = "default";
258	pinctrl-0 = <&scif0_pins>;
259	status = "okay";
260};
261
262&scif3 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&scif3_pins>;
265	status = "okay";
266};
267
268&sdhi1 {
269	pinctrl-0 = <&sdhi1_pins>;
270	pinctrl-1 = <&sdhi1_pins_uhs>;
271	pinctrl-names = "default", "state_uhs";
272	vmmc-supply = <&vcc_sdhi1>;
273	vqmmc-supply = <&vccq_sdhi1>;
274	bus-width = <4>;
275	sd-uhs-sdr50;
276	sd-uhs-sdr104;
277	max-frequency = <125000000>;
278	status = "okay";
279};
280
281&ssi3 {
282	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
283		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
284		 <&versa3 2>, <&audio_clk2>;
285	pinctrl-names = "default";
286	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
287	status = "okay";
288};
289
290&usb2_phy0 {
291	pinctrl-0 = <&usb0_pins>;
292	pinctrl-names = "default";
293	vbus-supply = <&usb0_vbus_otg>;
294	status = "okay";
295};
296
297&usb2_phy1 {
298	pinctrl-0 = <&usb1_pins>;
299	pinctrl-names = "default";
300	status = "okay";
301};
302