xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi (revision 2f24482304ebd32c5aa374f31465b9941a860b92) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		i2c0 = &i2c0;
15		serial0 = &scif1;
16		serial1 = &scif3;
17		serial3 = &scif0;
18		mmc1 = &sdhi1;
19	};
20
21	chosen {
22		bootargs = "ignore_loglevel";
23		stdout-path = "serial3:115200n8";
24	};
25
26	keys {
27		compatible = "gpio-keys";
28
29		key-1 {
30			interrupts-extended = <&pinctrl RZG2L_GPIO(18, 0) IRQ_TYPE_EDGE_FALLING>;
31			linux,code = <KEY_1>;
32			label = "USER_SW1";
33			wakeup-source;
34			debounce-interval = <20>;
35		};
36
37		key-2 {
38			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 1) IRQ_TYPE_EDGE_FALLING>;
39			linux,code = <KEY_2>;
40			label = "USER_SW2";
41			wakeup-source;
42			debounce-interval = <20>;
43		};
44
45		key-3 {
46			interrupts-extended = <&pinctrl RZG2L_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
47			linux,code = <KEY_3>;
48			label = "USER_SW3";
49			wakeup-source;
50			debounce-interval = <20>;
51		};
52	};
53
54	snd_rzg3s: sound {
55		compatible = "simple-audio-card";
56		simple-audio-card,format = "i2s";
57		simple-audio-card,bitclock-master = <&cpu_dai>;
58		simple-audio-card,frame-master = <&cpu_dai>;
59		simple-audio-card,mclk-fs = <256>;
60
61		cpu_dai: simple-audio-card,cpu {
62			sound-dai = <&ssi3>;
63		};
64
65		codec_dai: simple-audio-card,codec {
66			sound-dai = <&da7212>;
67			clocks = <&versa3 1>;
68		};
69	};
70
71	vcc_sdhi1: regulator-vcc-sdhi1 {
72		compatible = "regulator-fixed";
73		regulator-name = "SDHI1 Vcc";
74		regulator-min-microvolt = <3300000>;
75		regulator-max-microvolt = <3300000>;
76		gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
77		enable-active-high;
78	};
79
80	vccq_sdhi1: regulator-vccq-sdhi1 {
81		compatible = "regulator-gpio";
82		regulator-name = "SDHI1 VccQ";
83		regulator-min-microvolt = <1800000>;
84		regulator-max-microvolt = <3300000>;
85		gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
86		gpios-states = <1>;
87		states = <3300000 1>, <1800000 0>;
88	};
89};
90
91&audio_clk2 {
92	clock-frequency = <12288000>;
93};
94
95&i2c0 {
96	status = "okay";
97
98	clock-frequency = <1000000>;
99
100	da7212: codec@1a {
101		compatible = "dlg,da7212";
102		reg = <0x1a>;
103
104		clocks = <&versa3 1>;
105		clock-names = "mclk";
106
107		#sound-dai-cells = <0>;
108
109		dlg,micbias1-lvl = <2500>;
110		dlg,micbias2-lvl = <2500>;
111		dlg,dmic-data-sel = "lrise_rfall";
112		dlg,dmic-samplephase = "between_clkedge";
113		dlg,dmic-clkrate = <3000000>;
114
115		VDDA-supply = <&reg_1p8v>;
116		VDDSP-supply = <&reg_3p3v>;
117		VDDMIC-supply = <&reg_3p3v>;
118		VDDIO-supply = <&reg_1p8v>;
119	};
120};
121
122&i2c1 {
123	status = "okay";
124
125	clock-frequency = <400000>;
126
127	power-monitor@44 {
128		compatible = "renesas,isl28022";
129		reg = <0x44>;
130		shunt-resistor-micro-ohms = <8000>;
131		renesas,average-samples = <32>;
132	};
133};
134
135&pinctrl {
136	audio_clock_pins: audio-clock {
137		pins = "AUDIO_CLK1", "AUDIO_CLK2";
138		input-enable;
139	};
140
141	key-1-gpio-hog {
142		gpio-hog;
143		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
144		input;
145		line-name = "key-1-gpio-irq";
146	};
147
148	key-2-gpio-hog {
149		gpio-hog;
150		gpios = <RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
151		input;
152		line-name = "key-2-gpio-irq";
153	};
154
155	key-3-gpio-hog {
156		gpio-hog;
157		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
158		input;
159		line-name = "key-3-gpio-irq";
160	};
161
162	scif0_pins: scif0 {
163		pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
164			 <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
165	};
166
167	scif3_pins: scif3 {
168		pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
169			 <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
170	};
171
172	sdhi1_pins: sd1 {
173		data {
174			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
175			power-source = <3300>;
176		};
177
178		ctrl {
179			pins = "SD1_CLK", "SD1_CMD";
180			power-source = <3300>;
181		};
182
183		cd {
184			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
185		};
186	};
187
188	sdhi1_pins_uhs: sd1-uhs {
189		data {
190			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
191			power-source = <1800>;
192		};
193
194		ctrl {
195			pins = "SD1_CLK", "SD1_CMD";
196			power-source = <1800>;
197		};
198
199		cd {
200			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
201		};
202	};
203
204	ssi3_pins: ssi3 {
205		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
206			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
207			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
208			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
209	};
210};
211
212&scif0 {
213	pinctrl-names = "default";
214	pinctrl-0 = <&scif0_pins>;
215	status = "okay";
216};
217
218&scif3 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&scif3_pins>;
221	status = "okay";
222};
223
224&sdhi1 {
225	pinctrl-0 = <&sdhi1_pins>;
226	pinctrl-1 = <&sdhi1_pins_uhs>;
227	pinctrl-names = "default", "state_uhs";
228	vmmc-supply = <&vcc_sdhi1>;
229	vqmmc-supply = <&vccq_sdhi1>;
230	bus-width = <4>;
231	sd-uhs-sdr50;
232	sd-uhs-sdr104;
233	max-frequency = <125000000>;
234	status = "okay";
235};
236
237&ssi3 {
238	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
239		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
240		 <&versa3 2>, <&audio_clk2>;
241	pinctrl-names = "default";
242	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
243	status = "okay";
244};
245