1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DEVICE_TYPES_H_ 7 #define _XE_DEVICE_TYPES_H_ 8 9 #include <linux/pci.h> 10 11 #include <drm/drm_device.h> 12 #include <drm/drm_file.h> 13 #include <drm/ttm/ttm_device.h> 14 15 #include "xe_devcoredump_types.h" 16 #include "xe_heci_gsc.h" 17 #include "xe_lmtt_types.h" 18 #include "xe_memirq_types.h" 19 #include "xe_oa_types.h" 20 #include "xe_platform_types.h" 21 #include "xe_pt_types.h" 22 #include "xe_sriov_types.h" 23 #include "xe_step_types.h" 24 25 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 26 #define TEST_VM_OPS_ERROR 27 #endif 28 29 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 30 #include "soc/intel_pch.h" 31 #include "intel_display_core.h" 32 #include "intel_display_device.h" 33 #endif 34 35 struct xe_ggtt; 36 struct xe_pat_ops; 37 38 #define XE_BO_INVALID_OFFSET LONG_MAX 39 40 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) 41 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100) 42 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) 43 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) 44 #define IS_DGFX(xe) ((xe)->info.is_dgfx) 45 46 #define XE_VRAM_FLAGS_NEED64K BIT(0) 47 48 #define XE_GT0 0 49 #define XE_GT1 1 50 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1) 51 52 #define XE_MAX_ASID (BIT(20)) 53 54 #define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step) \ 55 ((_xe)->info.platform == (_platform) && \ 56 (_xe)->info.step.graphics >= (min_step) && \ 57 (_xe)->info.step.graphics < (max_step)) 58 #define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step) \ 59 ((_xe)->info.platform == (_platform) && \ 60 (_xe)->info.subplatform == (sub) && \ 61 (_xe)->info.step.graphics >= (min_step) && \ 62 (_xe)->info.step.graphics < (max_step)) 63 64 #define tile_to_xe(tile__) \ 65 _Generic(tile__, \ 66 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ 67 struct xe_tile * : (tile__)->xe) 68 69 /** 70 * struct xe_mem_region - memory region structure 71 * This is used to describe a memory region in xe 72 * device, such as HBM memory or CXL extension memory. 73 */ 74 struct xe_mem_region { 75 /** @io_start: IO start address of this VRAM instance */ 76 resource_size_t io_start; 77 /** 78 * @io_size: IO size of this VRAM instance 79 * 80 * This represents how much of this VRAM we can access 81 * via the CPU through the VRAM BAR. This can be smaller 82 * than @usable_size, in which case only part of VRAM is CPU 83 * accessible (typically the first 256M). This 84 * configuration is known as small-bar. 85 */ 86 resource_size_t io_size; 87 /** @dpa_base: This memory regions's DPA (device physical address) base */ 88 resource_size_t dpa_base; 89 /** 90 * @usable_size: usable size of VRAM 91 * 92 * Usable size of VRAM excluding reserved portions 93 * (e.g stolen mem) 94 */ 95 resource_size_t usable_size; 96 /** 97 * @actual_physical_size: Actual VRAM size 98 * 99 * Actual VRAM size including reserved portions 100 * (e.g stolen mem) 101 */ 102 resource_size_t actual_physical_size; 103 /** @mapping: pointer to VRAM mappable space */ 104 void __iomem *mapping; 105 }; 106 107 /** 108 * struct xe_mmio - register mmio structure 109 * 110 * Represents an MMIO region that the CPU may use to access registers. A 111 * region may share its IO map with other regions (e.g., all GTs within a 112 * tile share the same map with their parent tile, but represent different 113 * subregions of the overall IO space). 114 */ 115 struct xe_mmio { 116 /** @tile: Backpointer to tile, used for tracing */ 117 struct xe_tile *tile; 118 119 /** @regs: Map used to access registers. */ 120 void __iomem *regs; 121 122 /** 123 * @sriov_vf_gt: Backpointer to GT. 124 * 125 * This pointer is only set for GT MMIO regions and only when running 126 * as an SRIOV VF structure 127 */ 128 struct xe_gt *sriov_vf_gt; 129 130 /** 131 * @regs_size: Length of the register region within the map. 132 * 133 * The size of the iomap set in *regs is generally larger than the 134 * register mmio space since it includes unused regions and/or 135 * non-register regions such as the GGTT PTEs. 136 */ 137 size_t regs_size; 138 139 /** @adj_limit: adjust MMIO address if address is below this value */ 140 u32 adj_limit; 141 142 /** @adj_offset: offset to add to MMIO address when adjusting */ 143 u32 adj_offset; 144 }; 145 146 /** 147 * struct xe_tile - hardware tile structure 148 * 149 * From a driver perspective, a "tile" is effectively a complete GPU, containing 150 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. 151 * 152 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI 153 * device and designate one "root" tile as being responsible for external PCI 154 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each 155 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated 156 * with each tile similarly. Device-wide interrupts can be enabled/disabled 157 * at the root tile, and the MSTR_TILE_INTR register will report which tiles 158 * have interrupts that need servicing. 159 */ 160 struct xe_tile { 161 /** @xe: Backpointer to tile's PCI device */ 162 struct xe_device *xe; 163 164 /** @id: ID of the tile */ 165 u8 id; 166 167 /** 168 * @primary_gt: Primary GT 169 */ 170 struct xe_gt *primary_gt; 171 172 /** 173 * @media_gt: Media GT 174 * 175 * Only present on devices with media version >= 13. 176 */ 177 struct xe_gt *media_gt; 178 179 /** 180 * @mmio: MMIO info for a tile. 181 * 182 * Each tile has its own 16MB space in BAR0, laid out as: 183 * * 0-4MB: registers 184 * * 4MB-8MB: reserved 185 * * 8MB-16MB: global GTT 186 */ 187 struct xe_mmio mmio; 188 189 /** 190 * @mmio_ext: MMIO-extension info for a tile. 191 * 192 * Each tile has its own additional 256MB (28-bit) MMIO-extension space. 193 */ 194 struct xe_mmio mmio_ext; 195 196 /** @mem: memory management info for tile */ 197 struct { 198 /** 199 * @mem.vram: VRAM info for tile. 200 * 201 * Although VRAM is associated with a specific tile, it can 202 * still be accessed by all tiles' GTs. 203 */ 204 struct xe_mem_region vram; 205 206 /** @mem.vram_mgr: VRAM TTM manager */ 207 struct xe_ttm_vram_mgr *vram_mgr; 208 209 /** @mem.ggtt: Global graphics translation table */ 210 struct xe_ggtt *ggtt; 211 212 /** 213 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated. 214 * 215 * Media GT shares a pool with its primary GT. 216 */ 217 struct xe_sa_manager *kernel_bb_pool; 218 } mem; 219 220 /** @sriov: tile level virtualization data */ 221 union { 222 struct { 223 /** @sriov.pf.lmtt: Local Memory Translation Table. */ 224 struct xe_lmtt lmtt; 225 } pf; 226 struct { 227 /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */ 228 struct xe_ggtt_node *ggtt_balloon[2]; 229 } vf; 230 } sriov; 231 232 /** @memirq: Memory Based Interrupts. */ 233 struct xe_memirq memirq; 234 235 /** @pcode: tile's PCODE */ 236 struct { 237 /** @pcode.lock: protecting tile's PCODE mailbox data */ 238 struct mutex lock; 239 } pcode; 240 241 /** @migrate: Migration helper for vram blits and clearing */ 242 struct xe_migrate *migrate; 243 244 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */ 245 struct kobject *sysfs; 246 }; 247 248 /** 249 * struct xe_device - Top level struct of XE device 250 */ 251 struct xe_device { 252 /** @drm: drm device */ 253 struct drm_device drm; 254 255 /** @devcoredump: device coredump */ 256 struct xe_devcoredump devcoredump; 257 258 /** @info: device info */ 259 struct intel_device_info { 260 /** @info.platform_name: platform name */ 261 const char *platform_name; 262 /** @info.graphics_name: graphics IP name */ 263 const char *graphics_name; 264 /** @info.media_name: media IP name */ 265 const char *media_name; 266 /** @info.tile_mmio_ext_size: size of MMIO extension space, per-tile */ 267 u32 tile_mmio_ext_size; 268 /** @info.graphics_verx100: graphics IP version */ 269 u32 graphics_verx100; 270 /** @info.media_verx100: media IP version */ 271 u32 media_verx100; 272 /** @info.mem_region_mask: mask of valid memory regions */ 273 u32 mem_region_mask; 274 /** @info.platform: XE platform enum */ 275 enum xe_platform platform; 276 /** @info.subplatform: XE subplatform enum */ 277 enum xe_subplatform subplatform; 278 /** @info.devid: device ID */ 279 u16 devid; 280 /** @info.revid: device revision */ 281 u8 revid; 282 /** @info.step: stepping information for each IP */ 283 struct xe_step_info step; 284 /** @info.dma_mask_size: DMA address bits */ 285 u8 dma_mask_size; 286 /** @info.vram_flags: Vram flags */ 287 u8 vram_flags; 288 /** @info.tile_count: Number of tiles */ 289 u8 tile_count; 290 /** @info.gt_count: Total number of GTs for entire device */ 291 u8 gt_count; 292 /** @info.vm_max_level: Max VM level */ 293 u8 vm_max_level; 294 /** @info.va_bits: Maximum bits of a virtual address */ 295 u8 va_bits; 296 297 /* 298 * Keep all flags below alphabetically sorted 299 */ 300 301 /** @info.force_execlist: Forced execlist submission */ 302 u8 force_execlist:1; 303 /** @info.has_asid: Has address space ID */ 304 u8 has_asid:1; 305 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ 306 u8 has_atomic_enable_pte_bit:1; 307 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 308 u8 has_device_atomics_on_smem:1; 309 /** @info.has_flat_ccs: Whether flat CCS metadata is used */ 310 u8 has_flat_ccs:1; 311 /** @info.has_heci_cscfi: device has heci cscfi */ 312 u8 has_heci_cscfi:1; 313 /** @info.has_heci_gscfi: device has heci gscfi */ 314 u8 has_heci_gscfi:1; 315 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 316 u8 has_llc:1; 317 /** @info.has_mmio_ext: Device has extra MMIO address range */ 318 u8 has_mmio_ext:1; 319 /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */ 320 u8 has_range_tlb_invalidation:1; 321 /** @info.has_sriov: Supports SR-IOV */ 322 u8 has_sriov:1; 323 /** @info.has_usm: Device has unified shared memory support */ 324 u8 has_usm:1; 325 /** @info.is_dgfx: is discrete device */ 326 u8 is_dgfx:1; 327 /** 328 * @info.probe_display: Probe display hardware. If set to 329 * false, the driver will behave as if there is no display 330 * hardware present and will not try to read/write to it in any 331 * way. The display hardware, if it exists, will not be 332 * exposed to userspace and will be left untouched in whatever 333 * state the firmware or bootloader left it in. 334 */ 335 u8 probe_display:1; 336 /** @info.skip_guc_pc: Skip GuC based PM feature init */ 337 u8 skip_guc_pc:1; 338 /** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */ 339 u8 skip_mtcfg:1; 340 /** @info.skip_pcode: skip access to PCODE uC */ 341 u8 skip_pcode:1; 342 } info; 343 344 /** @irq: device interrupt state */ 345 struct { 346 /** @irq.lock: lock for processing irq's on this device */ 347 spinlock_t lock; 348 349 /** @irq.enabled: interrupts enabled on this device */ 350 atomic_t enabled; 351 352 /** @irq.msix: irq info for platforms that support MSI-X */ 353 struct { 354 /** @irq.msix.nvec: number of MSI-X interrupts */ 355 u16 nvec; 356 /** @irq.msix.indexes: used to allocate MSI-X indexes */ 357 struct xarray indexes; 358 } msix; 359 } irq; 360 361 /** @ttm: ttm device */ 362 struct ttm_device ttm; 363 364 /** @mmio: mmio info for device */ 365 struct { 366 /** @mmio.size: size of MMIO space for device */ 367 size_t size; 368 /** @mmio.regs: pointer to MMIO space for device */ 369 void __iomem *regs; 370 } mmio; 371 372 /** @mem: memory info for device */ 373 struct { 374 /** @mem.vram: VRAM info for device */ 375 struct xe_mem_region vram; 376 /** @mem.sys_mgr: system TTM manager */ 377 struct ttm_resource_manager sys_mgr; 378 } mem; 379 380 /** @sriov: device level virtualization data */ 381 struct { 382 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */ 383 enum xe_sriov_mode __mode; 384 385 /** @sriov.pf: PF specific data */ 386 struct xe_device_pf pf; 387 /** @sriov.vf: VF specific data */ 388 struct xe_device_vf vf; 389 390 /** @sriov.wq: workqueue used by the virtualization workers */ 391 struct workqueue_struct *wq; 392 } sriov; 393 394 /** @usm: unified memory state */ 395 struct { 396 /** @usm.asid: convert a ASID to VM */ 397 struct xarray asid_to_vm; 398 /** @usm.next_asid: next ASID, used to cyclical alloc asids */ 399 u32 next_asid; 400 /** @usm.lock: protects UM state */ 401 struct rw_semaphore lock; 402 } usm; 403 404 /** @pinned: pinned BO state */ 405 struct { 406 /** @pinned.lock: protected pinned BO list state */ 407 spinlock_t lock; 408 /** @pinned.kernel_bo_present: pinned kernel BO that are present */ 409 struct list_head kernel_bo_present; 410 /** @pinned.evicted: pinned BO that have been evicted */ 411 struct list_head evicted; 412 /** @pinned.external_vram: pinned external BO in vram*/ 413 struct list_head external_vram; 414 } pinned; 415 416 /** @ufence_wq: user fence wait queue */ 417 wait_queue_head_t ufence_wq; 418 419 /** @preempt_fence_wq: used to serialize preempt fences */ 420 struct workqueue_struct *preempt_fence_wq; 421 422 /** @ordered_wq: used to serialize compute mode resume */ 423 struct workqueue_struct *ordered_wq; 424 425 /** @unordered_wq: used to serialize unordered work, mostly display */ 426 struct workqueue_struct *unordered_wq; 427 428 /** @destroy_wq: used to serialize user destroy work, like queue */ 429 struct workqueue_struct *destroy_wq; 430 431 /** @tiles: device tiles */ 432 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; 433 434 /** 435 * @mem_access: keep track of memory access in the device, possibly 436 * triggering additional actions when they occur. 437 */ 438 struct { 439 /** 440 * @mem_access.vram_userfault: Encapsulate vram_userfault 441 * related stuff 442 */ 443 struct { 444 /** 445 * @mem_access.vram_userfault.lock: Protects access to 446 * @vram_usefault.list Using mutex instead of spinlock 447 * as lock is applied to entire list operation which 448 * may sleep 449 */ 450 struct mutex lock; 451 452 /** 453 * @mem_access.vram_userfault.list: Keep list of userfaulted 454 * vram bo, which require to release their mmap mappings 455 * at runtime suspend path 456 */ 457 struct list_head list; 458 } vram_userfault; 459 } mem_access; 460 461 /** 462 * @pat: Encapsulate PAT related stuff 463 */ 464 struct { 465 /** @pat.ops: Internal operations to abstract platforms */ 466 const struct xe_pat_ops *ops; 467 /** @pat.table: PAT table to program in the HW */ 468 const struct xe_pat_table_entry *table; 469 /** @pat.n_entries: Number of PAT entries */ 470 int n_entries; 471 u32 idx[__XE_CACHE_LEVEL_COUNT]; 472 } pat; 473 474 /** @d3cold: Encapsulate d3cold related stuff */ 475 struct { 476 /** @d3cold.capable: Indicates if root port is d3cold capable */ 477 bool capable; 478 479 /** @d3cold.allowed: Indicates if d3cold is a valid device state */ 480 bool allowed; 481 482 /** 483 * @d3cold.vram_threshold: 484 * 485 * This represents the permissible threshold(in megabytes) 486 * for vram save/restore. d3cold will be disallowed, 487 * when vram_usages is above or equals the threshold value 488 * to avoid the vram save/restore latency. 489 * Default threshold value is 300mb. 490 */ 491 u32 vram_threshold; 492 /** @d3cold.lock: protect vram_threshold */ 493 struct mutex lock; 494 } d3cold; 495 496 /** @pmt: Support the PMT driver callback interface */ 497 struct { 498 /** @pmt.lock: protect access for telemetry data */ 499 struct mutex lock; 500 } pmt; 501 502 /** 503 * @pm_callback_task: Track the active task that is running in either 504 * the runtime_suspend or runtime_resume callbacks. 505 */ 506 struct task_struct *pm_callback_task; 507 508 /** @hwmon: hwmon subsystem integration */ 509 struct xe_hwmon *hwmon; 510 511 /** @heci_gsc: graphics security controller */ 512 struct xe_heci_gsc heci_gsc; 513 514 /** @oa: oa observation subsystem */ 515 struct xe_oa oa; 516 517 /** @needs_flr_on_fini: requests function-reset on fini */ 518 bool needs_flr_on_fini; 519 520 /** @wedged: Struct to control Wedged States and mode */ 521 struct { 522 /** @wedged.flag: Xe device faced a critical error and is now blocked. */ 523 atomic_t flag; 524 /** @wedged.mode: Mode controlled by kernel parameter and debugfs */ 525 int mode; 526 } wedged; 527 528 #ifdef TEST_VM_OPS_ERROR 529 /** 530 * @vm_inject_error_position: inject errors at different places in VM 531 * bind IOCTL based on this value 532 */ 533 u8 vm_inject_error_position; 534 #endif 535 536 /* private: */ 537 538 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 539 /* 540 * Any fields below this point are the ones used by display. 541 * They are temporarily added here so xe_device can be desguised as 542 * drm_i915_private during build. After cleanup these should go away, 543 * migrating to the right sub-structs 544 */ 545 struct intel_display display; 546 enum intel_pch pch_type; 547 u16 pch_id; 548 549 struct dram_info { 550 bool wm_lv_0_adjust_needed; 551 u8 num_channels; 552 bool symmetric_memory; 553 enum intel_dram_type { 554 INTEL_DRAM_UNKNOWN, 555 INTEL_DRAM_DDR3, 556 INTEL_DRAM_DDR4, 557 INTEL_DRAM_LPDDR3, 558 INTEL_DRAM_LPDDR4, 559 INTEL_DRAM_DDR5, 560 INTEL_DRAM_LPDDR5, 561 INTEL_DRAM_GDDR, 562 } type; 563 u8 num_qgv_points; 564 u8 num_psf_gv_points; 565 } dram_info; 566 567 /* 568 * edram size in MB. 569 * Cannot be determined by PCIID. You must always read a register. 570 */ 571 u32 edram_size_mb; 572 573 /* To shut up runtime pm macros.. */ 574 struct xe_runtime_pm {} runtime_pm; 575 576 /* only to allow build, not used functionally */ 577 u32 irq_mask; 578 579 struct intel_uncore { 580 spinlock_t lock; 581 } uncore; 582 583 /* only to allow build, not used functionally */ 584 struct { 585 unsigned int hpll_freq; 586 unsigned int czclk_freq; 587 unsigned int fsb_freq, mem_freq, is_ddr3; 588 }; 589 590 void *pxp; 591 #endif 592 }; 593 594 /** 595 * struct xe_file - file handle for XE driver 596 */ 597 struct xe_file { 598 /** @xe: xe DEVICE **/ 599 struct xe_device *xe; 600 601 /** @drm: base DRM file */ 602 struct drm_file *drm; 603 604 /** @vm: VM state for file */ 605 struct { 606 /** @vm.xe: xarray to store VMs */ 607 struct xarray xa; 608 /** 609 * @vm.lock: Protects VM lookup + reference and removal from 610 * file xarray. Not an intended to be an outer lock which does 611 * thing while being held. 612 */ 613 struct mutex lock; 614 } vm; 615 616 /** @exec_queue: Submission exec queue state for file */ 617 struct { 618 /** @exec_queue.xa: xarray to store exece queues */ 619 struct xarray xa; 620 /** 621 * @exec_queue.lock: Protects exec queue lookup + reference and 622 * removal from file xarray. Not intended to be an outer lock 623 * which does things while being held. 624 */ 625 struct mutex lock; 626 /** 627 * @exec_queue.pending_removal: items pending to be removed to 628 * synchronize GPU state update with ongoing query. 629 */ 630 atomic_t pending_removal; 631 } exec_queue; 632 633 /** @run_ticks: hw engine class run time in ticks for this drm client */ 634 u64 run_ticks[XE_ENGINE_CLASS_MAX]; 635 636 /** @client: drm client */ 637 struct xe_drm_client *client; 638 639 /** 640 * @process_name: process name for file handle, used to safely output 641 * during error situations where xe file can outlive process 642 */ 643 char *process_name; 644 645 /** 646 * @pid: pid for file handle, used to safely output uring error 647 * situations where xe file can outlive process 648 */ 649 pid_t pid; 650 651 /** @refcount: ref count of this xe file */ 652 struct kref refcount; 653 }; 654 655 #endif 656