1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Nicera D3-323-AA PIR sensor.
4 *
5 * Copyright (C) 2025 Axis Communications AB
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/cleanup.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/types.h>
21
22 #include <linux/iio/events.h>
23 #include <linux/iio/iio.h>
24
25 /*
26 * Register bitmap.
27 * For some reason the first bit is denoted as F37 in the datasheet, the second
28 * as F38 and so on. Note the gap between F60 and F64.
29 */
30 #define D3323AA_REG_BIT_SLAVEA1 0 /* F37. */
31 #define D3323AA_REG_BIT_SLAVEA2 1 /* F38. */
32 #define D3323AA_REG_BIT_SLAVEA3 2 /* F39. */
33 #define D3323AA_REG_BIT_SLAVEA4 3 /* F40. */
34 #define D3323AA_REG_BIT_SLAVEA5 4 /* F41. */
35 #define D3323AA_REG_BIT_SLAVEA6 5 /* F42. */
36 #define D3323AA_REG_BIT_SLAVEA7 6 /* F43. */
37 #define D3323AA_REG_BIT_SLAVEA8 7 /* F44. */
38 #define D3323AA_REG_BIT_SLAVEA9 8 /* F45. */
39 #define D3323AA_REG_BIT_SLAVEA10 9 /* F46. */
40 #define D3323AA_REG_BIT_DETLVLABS0 10 /* F47. */
41 #define D3323AA_REG_BIT_DETLVLABS1 11 /* F48. */
42 #define D3323AA_REG_BIT_DETLVLABS2 12 /* F49. */
43 #define D3323AA_REG_BIT_DETLVLABS3 13 /* F50. */
44 #define D3323AA_REG_BIT_DETLVLABS4 14 /* F51. */
45 #define D3323AA_REG_BIT_DETLVLABS5 15 /* F52. */
46 #define D3323AA_REG_BIT_DETLVLABS6 16 /* F53. */
47 #define D3323AA_REG_BIT_DETLVLABS7 17 /* F54. */
48 #define D3323AA_REG_BIT_DSLP 18 /* F55. */
49 #define D3323AA_REG_BIT_FSTEP0 19 /* F56. */
50 #define D3323AA_REG_BIT_FSTEP1 20 /* F57. */
51 #define D3323AA_REG_BIT_FILSEL0 21 /* F58. */
52 #define D3323AA_REG_BIT_FILSEL1 22 /* F59. */
53 #define D3323AA_REG_BIT_FILSEL2 23 /* F60. */
54 #define D3323AA_REG_BIT_FDSET 24 /* F64. */
55 #define D3323AA_REG_BIT_F65 25
56 #define D3323AA_REG_BIT_F87 (D3323AA_REG_BIT_F65 + (87 - 65))
57
58 #define D3323AA_REG_NR_BITS (D3323AA_REG_BIT_F87 - D3323AA_REG_BIT_SLAVEA1 + 1)
59 #define D3323AA_THRESH_REG_NR_BITS \
60 (D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 + 1)
61 #define D3323AA_FILTER_TYPE_NR_BITS \
62 (D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1)
63 #define D3323AA_FILTER_GAIN_REG_NR_BITS \
64 (D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1)
65
66 #define D3323AA_THRESH_DEFAULT_VAL 56
67 #define D3323AA_FILTER_GAIN_DEFAULT_IDX 1
68 #define D3323AA_LP_FILTER_FREQ_DEFAULT_IDX 1
69
70 /*
71 * The pattern is 0b01101, but store it reversed (0b10110) due to writing from
72 * LSB on the wire (c.f. d3323aa_write_settings()).
73 */
74 #define D3323AA_SETTING_END_PATTERN 0x16
75 #define D3323AA_SETTING_END_PATTERN_NR_BITS 5
76
77 /*
78 * Device should be ready for configuration after this many milliseconds.
79 * Datasheet mentions "approx. 1.2 s". Measurements show around 1.23 s,
80 * therefore add 100 ms of slack.
81 */
82 #define D3323AA_RESET_TIMEOUT (1200 + 100)
83
84 /*
85 * The configuration of the device (write and read) should be done within this
86 * many milliseconds.
87 */
88 #define D3323AA_CONFIG_TIMEOUT 1400
89
90 /* Number of IRQs needed for configuration stage after reset. */
91 #define D3323AA_IRQ_RESET_COUNT 2
92
93 /*
94 * High-pass filter cutoff frequency for the band-pass filter. There is a
95 * corresponding low-pass cutoff frequency for each of the filter types
96 * (denoted A, B, C and D in the datasheet). The index in this array matches
97 * that corresponding value in d3323aa_lp_filter_freq.
98 * Note that this represents a fractional value (e.g. the first value
99 * corresponds to 40 / 100 = 0.4 Hz).
100 */
101 static const int d3323aa_hp_filter_freq[][2] = {
102 { 40, 100 },
103 { 30, 100 },
104 { 30, 100 },
105 { 1, 100 },
106 };
107
108 /*
109 * Low-pass filter cutoff frequency for the band-pass filter. There is a
110 * corresponding high-pass cutoff frequency for each of the filter types
111 * (denoted A, B, C and D in the datasheet). The index in this array matches
112 * that corresponding value in d3323aa_hp_filter_freq.
113 * Note that this represents a fractional value (e.g. the first value
114 * corresponds to 27 / 10 = 2.7 Hz).
115 */
116 static const int d3323aa_lp_filter_freq[][2] = {
117 { 27, 10 },
118 { 15, 10 },
119 { 5, 1 },
120 { 100, 1 },
121 };
122
123 /*
124 * Register bitmap values for filter types (denoted A, B, C and D in the
125 * datasheet). The index in this array matches the corresponding value in
126 * d3323aa_lp_filter_freq (which in turn matches d3323aa_hp_filter_freq). For
127 * example, the first value 7 corresponds to 2.7 Hz low-pass and 0.4 Hz
128 * high-pass cutoff frequency.
129 */
130 static const int d3323aa_lp_filter_regval[] = {
131 7,
132 0,
133 1,
134 2,
135 };
136
137 /*
138 * This is denoted as "step" in datasheet and corresponds to the gain at peak
139 * for the band-pass filter. The index in this array is the corresponding index
140 * in d3323aa_filter_gain_regval for the register bitmap value.
141 */
142 static const int d3323aa_filter_gain[] = { 1, 2, 3 };
143
144 /*
145 * Register bitmap values for the filter gain. The index in this array is the
146 * corresponding index in d3323aa_filter_gain for the gain value.
147 */
148 static const u8 d3323aa_filter_gain_regval[] = { 1, 3, 0 };
149
150 struct d3323aa_data {
151 struct completion reset_completion;
152 /*
153 * Since the setup process always requires a complete write of _all_
154 * the state variables, we need to synchronize them with a lock.
155 */
156 struct mutex statevar_lock;
157
158 struct device *dev;
159
160 /* Supply voltage. */
161 struct regulator *regulator_vdd;
162 /* Input clock or output detection signal (Vout). */
163 struct gpio_desc *gpiod_clkin_detectout;
164 /* Input (setting) or output data. */
165 struct gpio_desc *gpiod_data;
166
167 /*
168 * We only need the low-pass cutoff frequency to unambiguously choose
169 * the type of band-pass filter. For example, both filter type B and C
170 * have 0.3 Hz as high-pass cutoff frequency (see
171 * d3323aa_hp_filter_freq).
172 */
173 size_t lp_filter_freq_idx;
174 size_t filter_gain_idx;
175 u8 detect_thresh;
176 u8 irq_reset_count;
177
178 /* Indicator for operational mode (configuring or detecting). */
179 bool detecting;
180 };
181
d3323aa_read_settings(struct iio_dev * indio_dev,unsigned long * regbitmap)182 static int d3323aa_read_settings(struct iio_dev *indio_dev,
183 unsigned long *regbitmap)
184 {
185 struct d3323aa_data *data = iio_priv(indio_dev);
186 size_t i;
187 int ret;
188
189 /* Bit bang the clock and data pins. */
190 ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0);
191 if (ret)
192 return ret;
193
194 ret = gpiod_direction_input(data->gpiod_data);
195 if (ret)
196 return ret;
197
198 dev_dbg(data->dev, "Reading settings...\n");
199
200 for (i = 0; i < D3323AA_REG_NR_BITS; ++i) {
201 /* Clock frequency needs to be 1 kHz. */
202 gpiod_set_value(data->gpiod_clkin_detectout, 1);
203 udelay(500);
204
205 /* The data seems to change when clock signal is high. */
206 if (gpiod_get_value(data->gpiod_data))
207 set_bit(i, regbitmap);
208
209 gpiod_set_value(data->gpiod_clkin_detectout, 0);
210 udelay(500);
211 }
212
213 /* The first bit (F37) is just dummy data. Discard it. */
214 clear_bit(0, regbitmap);
215
216 /* Datasheet says to wait 30 ms after reading the settings. */
217 msleep(30);
218
219 return 0;
220 }
221
d3323aa_write_settings(struct iio_dev * indio_dev,unsigned long * written_regbitmap)222 static int d3323aa_write_settings(struct iio_dev *indio_dev,
223 unsigned long *written_regbitmap)
224 {
225 #define REGBITMAP_LEN \
226 (D3323AA_REG_NR_BITS + D3323AA_SETTING_END_PATTERN_NR_BITS)
227 DECLARE_BITMAP(regbitmap, REGBITMAP_LEN);
228 struct d3323aa_data *data = iio_priv(indio_dev);
229 size_t i;
230 int ret;
231
232 /* Build the register bitmap. */
233 bitmap_zero(regbitmap, REGBITMAP_LEN);
234 bitmap_write(regbitmap, data->detect_thresh, D3323AA_REG_BIT_DETLVLABS0,
235 D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 +
236 1);
237 bitmap_write(regbitmap,
238 d3323aa_filter_gain_regval[data->filter_gain_idx],
239 D3323AA_REG_BIT_FSTEP0,
240 D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1);
241 bitmap_write(regbitmap,
242 d3323aa_lp_filter_regval[data->lp_filter_freq_idx],
243 D3323AA_REG_BIT_FILSEL0,
244 D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1);
245 /* Compulsory end pattern. */
246 bitmap_write(regbitmap, D3323AA_SETTING_END_PATTERN,
247 D3323AA_REG_NR_BITS, D3323AA_SETTING_END_PATTERN_NR_BITS);
248
249 /* Bit bang the clock and data pins. */
250 ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0);
251 if (ret)
252 return ret;
253
254 ret = gpiod_direction_output(data->gpiod_data, 0);
255 if (ret)
256 return ret;
257
258 dev_dbg(data->dev, "Writing settings...\n");
259
260 /* First bit (F37) is not used when writing the register bitmap. */
261 for (i = 1; i < REGBITMAP_LEN; ++i) {
262 gpiod_set_value(data->gpiod_data, test_bit(i, regbitmap));
263
264 /* Clock frequency needs to be 1 kHz. */
265 gpiod_set_value(data->gpiod_clkin_detectout, 1);
266 udelay(500);
267 gpiod_set_value(data->gpiod_clkin_detectout, 0);
268 udelay(500);
269 }
270
271 /* Datasheet says to wait 30 ms after writing the settings. */
272 msleep(30);
273
274 bitmap_copy(written_regbitmap, regbitmap, D3323AA_REG_NR_BITS);
275
276 return 0;
277 }
278
d3323aa_irq_handler(int irq,void * dev_id)279 static irqreturn_t d3323aa_irq_handler(int irq, void *dev_id)
280 {
281 struct iio_dev *indio_dev = dev_id;
282 struct d3323aa_data *data = iio_priv(indio_dev);
283 enum iio_event_direction dir;
284 int val;
285
286 val = gpiod_get_value(data->gpiod_clkin_detectout);
287 if (val < 0) {
288 dev_err_ratelimited(data->dev,
289 "Could not read from GPIO vout-clk (%d)\n",
290 val);
291 return IRQ_HANDLED;
292 }
293
294 if (!data->detecting) {
295 /* Reset interrupt counting falling edges. */
296 if (!val && ++data->irq_reset_count == D3323AA_IRQ_RESET_COUNT)
297 complete(&data->reset_completion);
298
299 return IRQ_HANDLED;
300 }
301
302 /* Detection interrupt. */
303 dir = val ? IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
304 iio_push_event(indio_dev,
305 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
306 IIO_EV_TYPE_THRESH, dir),
307 iio_get_time_ns(indio_dev));
308
309 return IRQ_HANDLED;
310 }
311
d3323aa_reset(struct iio_dev * indio_dev)312 static int d3323aa_reset(struct iio_dev *indio_dev)
313 {
314 struct d3323aa_data *data = iio_priv(indio_dev);
315 long time;
316 int ret;
317
318 /* During probe() the regulator may already be disabled. */
319 if (regulator_is_enabled(data->regulator_vdd)) {
320 ret = regulator_disable(data->regulator_vdd);
321 if (ret)
322 return ret;
323 }
324
325 /*
326 * Datasheet says VDD needs to be low at least for 30 ms. Let's add a
327 * couple more to allow VDD to completely discharge as well.
328 */
329 fsleep((30 + 5) * USEC_PER_MSEC);
330
331 /*
332 * When later enabling VDD, the device will signal with
333 * D3323AA_IRQ_RESET_COUNT falling edges on Vout/CLK that it is now
334 * ready for configuration. Datasheet says that this should happen
335 * within D3323AA_RESET_TIMEOUT ms. Count these two edges within that
336 * timeout.
337 */
338 data->irq_reset_count = 0;
339 reinit_completion(&data->reset_completion);
340 data->detecting = false;
341
342 ret = gpiod_direction_input(data->gpiod_clkin_detectout);
343 if (ret)
344 return ret;
345
346 dev_dbg(data->dev, "Resetting...\n");
347
348 ret = regulator_enable(data->regulator_vdd);
349 if (ret)
350 return ret;
351
352 /*
353 * Wait for VDD to completely charge up. Measurements have shown that
354 * Vout/CLK signal slowly ramps up during this period. Thus, the digital
355 * signal will have bogus values. It is therefore necessary to wait
356 * before we can count the "real" falling edges.
357 */
358 fsleep(2000);
359
360 time = wait_for_completion_killable_timeout(
361 &data->reset_completion,
362 msecs_to_jiffies(D3323AA_RESET_TIMEOUT));
363 if (time == 0) {
364 return -ETIMEDOUT;
365 } else if (time < 0) {
366 /* Got interrupted. */
367 return time;
368 }
369
370 dev_dbg(data->dev, "Reset completed\n");
371
372 return 0;
373 }
374
d3323aa_setup(struct iio_dev * indio_dev,size_t lp_filter_freq_idx,size_t filter_gain_idx,u8 detect_thresh)375 static int d3323aa_setup(struct iio_dev *indio_dev, size_t lp_filter_freq_idx,
376 size_t filter_gain_idx, u8 detect_thresh)
377 {
378 DECLARE_BITMAP(write_regbitmap, D3323AA_REG_NR_BITS);
379 DECLARE_BITMAP(read_regbitmap, D3323AA_REG_NR_BITS);
380 struct d3323aa_data *data = iio_priv(indio_dev);
381 unsigned long start_time;
382 int ret;
383
384 ret = d3323aa_reset(indio_dev);
385 if (ret) {
386 if (ret != -ERESTARTSYS)
387 dev_err(data->dev, "Could not reset device (%d)\n",
388 ret);
389
390 return ret;
391 }
392
393 /*
394 * Datasheet says to wait 10 us before setting the configuration.
395 * Moreover, the total configuration should be done within
396 * D3323AA_CONFIG_TIMEOUT ms. Clock it.
397 */
398 fsleep(10);
399 start_time = jiffies;
400
401 ret = d3323aa_write_settings(indio_dev, write_regbitmap);
402 if (ret) {
403 dev_err(data->dev, "Could not write settings (%d)\n", ret);
404 return ret;
405 }
406
407 ret = d3323aa_read_settings(indio_dev, read_regbitmap);
408 if (ret) {
409 dev_err(data->dev, "Could not read settings (%d)\n", ret);
410 return ret;
411 }
412
413 if (time_is_before_jiffies(start_time +
414 msecs_to_jiffies(D3323AA_CONFIG_TIMEOUT))) {
415 dev_err(data->dev, "Could not set up configuration in time\n");
416 return -EAGAIN;
417 }
418
419 /* Check if settings were set successfully. */
420 if (!bitmap_equal(write_regbitmap, read_regbitmap,
421 D3323AA_REG_NR_BITS)) {
422 dev_err(data->dev, "Settings data mismatch\n");
423 return -EIO;
424 }
425
426 /* Now in operational mode. */
427 ret = gpiod_direction_input(data->gpiod_clkin_detectout);
428 if (ret) {
429 dev_err(data->dev,
430 "Could not set GPIO vout-clk as input (%d)\n", ret);
431 return ret;
432 }
433
434 ret = gpiod_direction_input(data->gpiod_data);
435 if (ret) {
436 dev_err(data->dev, "Could not set GPIO data as input (%d)\n",
437 ret);
438 return ret;
439 }
440
441 data->lp_filter_freq_idx = lp_filter_freq_idx;
442 data->filter_gain_idx = filter_gain_idx;
443 data->detect_thresh = detect_thresh;
444 data->detecting = true;
445
446 dev_dbg(data->dev, "Setup done\n");
447
448 return 0;
449 }
450
d3323aa_set_lp_filter_freq(struct iio_dev * indio_dev,const int val,int val2)451 static int d3323aa_set_lp_filter_freq(struct iio_dev *indio_dev, const int val,
452 int val2)
453 {
454 struct d3323aa_data *data = iio_priv(indio_dev);
455 size_t idx;
456
457 /* Truncate fractional part to one digit. */
458 val2 /= 100000;
459
460 for (idx = 0; idx < ARRAY_SIZE(d3323aa_lp_filter_freq); ++idx) {
461 int integer = d3323aa_lp_filter_freq[idx][0] /
462 d3323aa_lp_filter_freq[idx][1];
463 int fract = d3323aa_lp_filter_freq[idx][0] %
464 d3323aa_lp_filter_freq[idx][1];
465
466 if (val == integer && val2 == fract)
467 break;
468 }
469
470 if (idx == ARRAY_SIZE(d3323aa_lp_filter_freq))
471 return -EINVAL;
472
473 return d3323aa_setup(indio_dev, idx, data->filter_gain_idx,
474 data->detect_thresh);
475 }
476
d3323aa_set_hp_filter_freq(struct iio_dev * indio_dev,const int val,int val2)477 static int d3323aa_set_hp_filter_freq(struct iio_dev *indio_dev, const int val,
478 int val2)
479 {
480 struct d3323aa_data *data = iio_priv(indio_dev);
481 size_t idx;
482
483 /* Truncate fractional part to two digits. */
484 val2 /= 10000;
485
486 for (idx = 0; idx < ARRAY_SIZE(d3323aa_hp_filter_freq); ++idx) {
487 int integer = d3323aa_hp_filter_freq[idx][0] /
488 d3323aa_hp_filter_freq[idx][1];
489 int fract = d3323aa_hp_filter_freq[idx][0] %
490 d3323aa_hp_filter_freq[idx][1];
491
492 if (val == integer && val2 == fract)
493 break;
494 }
495
496 if (idx == ARRAY_SIZE(d3323aa_hp_filter_freq))
497 return -EINVAL;
498
499 if (idx == data->lp_filter_freq_idx) {
500 /* Corresponding filter frequency already set. */
501 return 0;
502 }
503
504 if (idx == 1 && data->lp_filter_freq_idx == 2) {
505 /*
506 * The low-pass cutoff frequency is the only way to
507 * unambiguously choose the type of band-pass filter. For
508 * example, both filter type B (index 1) and C (index 2) have
509 * 0.3 Hz as high-pass cutoff frequency (see
510 * d3323aa_hp_filter_freq). Therefore, if one of these are
511 * requested _and_ the corresponding low-pass filter frequency
512 * is already set, we can't know which filter type is the wanted
513 * one. The low-pass filter frequency is the decider (i.e. in
514 * this case index 2).
515 */
516 return 0;
517 }
518
519 return d3323aa_setup(indio_dev, idx, data->filter_gain_idx,
520 data->detect_thresh);
521 }
522
d3323aa_set_filter_gain(struct iio_dev * indio_dev,const int val)523 static int d3323aa_set_filter_gain(struct iio_dev *indio_dev, const int val)
524 {
525 struct d3323aa_data *data = iio_priv(indio_dev);
526 size_t idx;
527
528 for (idx = 0; idx < ARRAY_SIZE(d3323aa_filter_gain); ++idx) {
529 if (d3323aa_filter_gain[idx] == val)
530 break;
531 }
532
533 if (idx == ARRAY_SIZE(d3323aa_filter_gain))
534 return -EINVAL;
535
536 return d3323aa_setup(indio_dev, data->lp_filter_freq_idx, idx,
537 data->detect_thresh);
538 }
539
d3323aa_set_threshold(struct iio_dev * indio_dev,const int val)540 static int d3323aa_set_threshold(struct iio_dev *indio_dev, const int val)
541 {
542 struct d3323aa_data *data = iio_priv(indio_dev);
543
544 if (val > ((1 << D3323AA_THRESH_REG_NR_BITS) - 1))
545 return -EINVAL;
546
547 return d3323aa_setup(indio_dev, data->lp_filter_freq_idx,
548 data->filter_gain_idx, val);
549 }
550
d3323aa_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)551 static int d3323aa_read_avail(struct iio_dev *indio_dev,
552 struct iio_chan_spec const *chan,
553 const int **vals, int *type, int *length,
554 long mask)
555 {
556 switch (mask) {
557 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
558 *vals = (int *)d3323aa_hp_filter_freq;
559 *type = IIO_VAL_FRACTIONAL;
560 *length = 2 * ARRAY_SIZE(d3323aa_hp_filter_freq);
561 return IIO_AVAIL_LIST;
562 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
563 *vals = (int *)d3323aa_lp_filter_freq;
564 *type = IIO_VAL_FRACTIONAL;
565 *length = 2 * ARRAY_SIZE(d3323aa_lp_filter_freq);
566 return IIO_AVAIL_LIST;
567 case IIO_CHAN_INFO_HARDWAREGAIN:
568 *vals = (int *)d3323aa_filter_gain;
569 *type = IIO_VAL_INT;
570 *length = ARRAY_SIZE(d3323aa_filter_gain);
571 return IIO_AVAIL_LIST;
572 default:
573 return -EINVAL;
574 }
575 }
576
d3323aa_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)577 static int d3323aa_read_raw(struct iio_dev *indio_dev,
578 struct iio_chan_spec const *chan, int *val,
579 int *val2, long mask)
580 {
581 struct d3323aa_data *data = iio_priv(indio_dev);
582
583 guard(mutex)(&data->statevar_lock);
584
585 switch (mask) {
586 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
587 *val = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][0];
588 *val2 = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][1];
589 return IIO_VAL_FRACTIONAL;
590 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
591 *val = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][0];
592 *val2 = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][1];
593 return IIO_VAL_FRACTIONAL;
594 case IIO_CHAN_INFO_HARDWAREGAIN:
595 *val = d3323aa_filter_gain[data->filter_gain_idx];
596 return IIO_VAL_INT;
597 default:
598 return -EINVAL;
599 }
600 }
601
d3323aa_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)602 static int d3323aa_write_raw(struct iio_dev *indio_dev,
603 struct iio_chan_spec const *chan, int val,
604 int val2, long mask)
605 {
606 struct d3323aa_data *data = iio_priv(indio_dev);
607
608 guard(mutex)(&data->statevar_lock);
609
610 switch (mask) {
611 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
612 return d3323aa_set_hp_filter_freq(indio_dev, val, val2);
613 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
614 return d3323aa_set_lp_filter_freq(indio_dev, val, val2);
615 case IIO_CHAN_INFO_HARDWAREGAIN:
616 return d3323aa_set_filter_gain(indio_dev, val);
617 default:
618 return -EINVAL;
619 }
620 }
621
d3323aa_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)622 static int d3323aa_read_event(struct iio_dev *indio_dev,
623 const struct iio_chan_spec *chan,
624 enum iio_event_type type,
625 enum iio_event_direction dir,
626 enum iio_event_info info, int *val, int *val2)
627 {
628 struct d3323aa_data *data = iio_priv(indio_dev);
629
630 guard(mutex)(&data->statevar_lock);
631
632 switch (info) {
633 case IIO_EV_INFO_VALUE:
634 *val = data->detect_thresh;
635 return IIO_VAL_INT;
636 default:
637 return -EINVAL;
638 }
639 }
640
d3323aa_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)641 static int d3323aa_write_event(struct iio_dev *indio_dev,
642 const struct iio_chan_spec *chan,
643 enum iio_event_type type,
644 enum iio_event_direction dir,
645 enum iio_event_info info, int val, int val2)
646 {
647 struct d3323aa_data *data = iio_priv(indio_dev);
648
649 guard(mutex)(&data->statevar_lock);
650
651 switch (info) {
652 case IIO_EV_INFO_VALUE:
653 return d3323aa_set_threshold(indio_dev, val);
654 default:
655 return -EINVAL;
656 }
657 }
658
659 static const struct iio_info d3323aa_info = {
660 .read_avail = d3323aa_read_avail,
661 .read_raw = d3323aa_read_raw,
662 .write_raw = d3323aa_write_raw,
663 .read_event_value = d3323aa_read_event,
664 .write_event_value = d3323aa_write_event,
665 };
666
667 static const struct iio_event_spec d3323aa_event_spec[] = {
668 {
669 .type = IIO_EV_TYPE_THRESH,
670 .dir = IIO_EV_DIR_RISING,
671 .mask_separate = BIT(IIO_EV_INFO_VALUE),
672 },
673 {
674 .type = IIO_EV_TYPE_THRESH,
675 .dir = IIO_EV_DIR_FALLING,
676 .mask_separate = BIT(IIO_EV_INFO_VALUE),
677 },
678 };
679
680 static const struct iio_chan_spec d3323aa_channels[] = {
681 {
682 .type = IIO_PROXIMITY,
683 .info_mask_separate =
684 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) |
685 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
686 BIT(IIO_CHAN_INFO_HARDWAREGAIN),
687 .info_mask_separate_available =
688 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) |
689 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
690 BIT(IIO_CHAN_INFO_HARDWAREGAIN),
691 .event_spec = d3323aa_event_spec,
692 .num_event_specs = ARRAY_SIZE(d3323aa_event_spec),
693 },
694 };
695
d3323aa_disable_regulator(void * indata)696 static void d3323aa_disable_regulator(void *indata)
697 {
698 struct d3323aa_data *data = indata;
699 int ret;
700
701 /*
702 * During probe() the regulator may be disabled. It is enabled during
703 * device setup (in d3323aa_reset(), where it is also briefly disabled).
704 * The check is therefore needed in order to have balanced
705 * regulator_enable/disable() calls.
706 */
707 if (!regulator_is_enabled(data->regulator_vdd))
708 return;
709
710 ret = regulator_disable(data->regulator_vdd);
711 if (ret)
712 dev_err(data->dev, "Could not disable regulator (%d)\n", ret);
713 }
714
d3323aa_probe(struct platform_device * pdev)715 static int d3323aa_probe(struct platform_device *pdev)
716 {
717 struct device *dev = &pdev->dev;
718 struct d3323aa_data *data;
719 struct iio_dev *indio_dev;
720 int ret;
721
722 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
723 if (!indio_dev)
724 return -ENOMEM;
725
726 data = iio_priv(indio_dev);
727 data->dev = dev;
728
729 init_completion(&data->reset_completion);
730
731 ret = devm_mutex_init(dev, &data->statevar_lock);
732 if (ret)
733 return dev_err_probe(dev, ret, "Could not initialize mutex\n");
734
735 data->regulator_vdd = devm_regulator_get_exclusive(dev, "vdd");
736 if (IS_ERR(data->regulator_vdd))
737 return dev_err_probe(dev, PTR_ERR(data->regulator_vdd),
738 "Could not get regulator\n");
739
740 /*
741 * The regulator will be enabled for the first time during the
742 * device setup below (in d3323aa_reset()). However parameter changes
743 * from userspace can require a temporary disable of the regulator.
744 * To avoid complex handling of state, use a callback that will disable
745 * the regulator if it happens to be enabled at time of devm unwind.
746 */
747 ret = devm_add_action_or_reset(dev, d3323aa_disable_regulator, data);
748 if (ret)
749 return ret;
750
751 data->gpiod_clkin_detectout =
752 devm_gpiod_get(dev, "vout-clk", GPIOD_OUT_LOW);
753 if (IS_ERR(data->gpiod_clkin_detectout))
754 return dev_err_probe(dev, PTR_ERR(data->gpiod_clkin_detectout),
755 "Could not get GPIO vout-clk\n");
756
757 data->gpiod_data = devm_gpiod_get(dev, "data", GPIOD_OUT_LOW);
758 if (IS_ERR(data->gpiod_data))
759 return dev_err_probe(dev, PTR_ERR(data->gpiod_data),
760 "Could not get GPIO data\n");
761
762 ret = gpiod_to_irq(data->gpiod_clkin_detectout);
763 if (ret < 0)
764 return dev_err_probe(dev, ret, "Could not get IRQ\n");
765
766 /*
767 * Device signals with a rising or falling detection signal when the
768 * proximity data is above or below the threshold, respectively.
769 */
770 ret = devm_request_irq(dev, ret, d3323aa_irq_handler,
771 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
772 dev_name(dev), indio_dev);
773 if (ret)
774 return ret;
775
776 ret = d3323aa_setup(indio_dev, D3323AA_LP_FILTER_FREQ_DEFAULT_IDX,
777 D3323AA_FILTER_GAIN_DEFAULT_IDX,
778 D3323AA_THRESH_DEFAULT_VAL);
779 if (ret)
780 return ret;
781
782 indio_dev->info = &d3323aa_info;
783 indio_dev->name = "d3323aa";
784 indio_dev->channels = d3323aa_channels;
785 indio_dev->num_channels = ARRAY_SIZE(d3323aa_channels);
786
787 ret = devm_iio_device_register(dev, indio_dev);
788 if (ret)
789 return dev_err_probe(dev, ret,
790 "Could not register iio device\n");
791
792 return 0;
793 }
794
795 static const struct of_device_id d3323aa_of_match[] = {
796 {
797 .compatible = "nicera,d3323aa",
798 },
799 { }
800 };
801 MODULE_DEVICE_TABLE(of, d3323aa_of_match);
802
803 static struct platform_driver d3323aa_driver = {
804 .probe = d3323aa_probe,
805 .driver = {
806 .name = "d3323aa",
807 .of_match_table = d3323aa_of_match,
808 },
809 };
810 module_platform_driver(d3323aa_driver);
811
812 MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>");
813 MODULE_DESCRIPTION("Nicera D3-323-AA PIR sensor driver");
814 MODULE_LICENSE("GPL");
815