1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
3
4 #include "igc.h"
5
6 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/pci.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
14 #include <net/xdp_sock_drv.h>
15
16 #define INCVALUE_MASK 0x7fffffff
17 #define ISGN 0x80000000
18
19 #define IGC_PTP_TX_TIMEOUT (HZ * 15)
20
21 #define IGC_PTM_STAT_SLEEP 2
22 #define IGC_PTM_STAT_TIMEOUT 100
23
24 /* SYSTIM read access for I225 */
igc_ptp_read(struct igc_adapter * adapter,struct timespec64 * ts)25 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
26 {
27 struct igc_hw *hw = &adapter->hw;
28 u32 sec, nsec;
29
30 /* The timestamp is latched when SYSTIML is read. */
31 nsec = rd32(IGC_SYSTIML);
32 sec = rd32(IGC_SYSTIMH);
33
34 ts->tv_sec = sec;
35 ts->tv_nsec = nsec;
36 }
37
igc_ptp_write_i225(struct igc_adapter * adapter,const struct timespec64 * ts)38 static void igc_ptp_write_i225(struct igc_adapter *adapter,
39 const struct timespec64 *ts)
40 {
41 struct igc_hw *hw = &adapter->hw;
42
43 wr32(IGC_SYSTIML, ts->tv_nsec);
44 wr32(IGC_SYSTIMH, ts->tv_sec);
45 }
46
igc_ptp_adjfine_i225(struct ptp_clock_info * ptp,long scaled_ppm)47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
48 {
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
50 ptp_caps);
51 struct igc_hw *hw = &igc->hw;
52 int neg_adj = 0;
53 u64 rate;
54 u32 inca;
55
56 if (scaled_ppm < 0) {
57 neg_adj = 1;
58 scaled_ppm = -scaled_ppm;
59 }
60 rate = scaled_ppm;
61 rate <<= 14;
62 rate = div_u64(rate, 78125);
63
64 inca = rate & INCVALUE_MASK;
65 if (neg_adj)
66 inca |= ISGN;
67
68 wr32(IGC_TIMINCA, inca);
69
70 return 0;
71 }
72
igc_ptp_adjtime_i225(struct ptp_clock_info * ptp,s64 delta)73 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
74 {
75 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
76 ptp_caps);
77 struct timespec64 now, then = ns_to_timespec64(delta);
78 unsigned long flags;
79
80 spin_lock_irqsave(&igc->tmreg_lock, flags);
81
82 igc_ptp_read(igc, &now);
83 now = timespec64_add(now, then);
84 igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
85
86 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
87
88 return 0;
89 }
90
igc_ptp_gettimex64_i225(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)91 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
92 struct timespec64 *ts,
93 struct ptp_system_timestamp *sts)
94 {
95 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
96 ptp_caps);
97 struct igc_hw *hw = &igc->hw;
98 unsigned long flags;
99
100 spin_lock_irqsave(&igc->tmreg_lock, flags);
101
102 ptp_read_system_prets(sts);
103 ts->tv_nsec = rd32(IGC_SYSTIML);
104 ts->tv_sec = rd32(IGC_SYSTIMH);
105 ptp_read_system_postts(sts);
106
107 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
108
109 return 0;
110 }
111
igc_ptp_settime_i225(struct ptp_clock_info * ptp,const struct timespec64 * ts)112 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
113 const struct timespec64 *ts)
114 {
115 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
116 ptp_caps);
117 unsigned long flags;
118
119 spin_lock_irqsave(&igc->tmreg_lock, flags);
120
121 igc_ptp_write_i225(igc, ts);
122
123 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
124
125 return 0;
126 }
127
igc_pin_direction(int pin,int input,u32 * ctrl,u32 * ctrl_ext)128 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
129 {
130 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
131 static const u32 mask[IGC_N_SDP] = {
132 IGC_CTRL_SDP0_DIR,
133 IGC_CTRL_SDP1_DIR,
134 IGC_CTRL_EXT_SDP2_DIR,
135 IGC_CTRL_EXT_SDP3_DIR,
136 };
137
138 if (input)
139 *ptr &= ~mask[pin];
140 else
141 *ptr |= mask[pin];
142 }
143
igc_pin_perout(struct igc_adapter * igc,int chan,int pin,int freq)144 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
145 {
146 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
147 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
148 };
149 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
150 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
151 };
152 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
153 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
154 };
155 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
156 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
157 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
158 };
159 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
160 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
161 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
162 };
163 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
164 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
165 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
166 };
167 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
168 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
169 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
170 };
171 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
172 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
173 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
174 };
175 struct igc_hw *hw = &igc->hw;
176 u32 ctrl, ctrl_ext, tssdp = 0;
177
178 ctrl = rd32(IGC_CTRL);
179 ctrl_ext = rd32(IGC_CTRL_EXT);
180 tssdp = rd32(IGC_TSSDP);
181
182 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
183
184 /* Make sure this pin is not enabled as an input. */
185 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
186 tssdp &= ~IGC_AUX0_TS_SDP_EN;
187
188 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
189 tssdp &= ~IGC_AUX1_TS_SDP_EN;
190
191 tssdp &= ~igc_ts_sdp_sel_clr[pin];
192 if (freq) {
193 if (chan == 1)
194 tssdp |= igc_ts_sdp_sel_fc1[pin];
195 else
196 tssdp |= igc_ts_sdp_sel_fc0[pin];
197 } else {
198 if (chan == 1)
199 tssdp |= igc_ts_sdp_sel_tt1[pin];
200 else
201 tssdp |= igc_ts_sdp_sel_tt0[pin];
202 }
203 tssdp |= igc_ts_sdp_en[pin];
204
205 wr32(IGC_TSSDP, tssdp);
206 wr32(IGC_CTRL, ctrl);
207 wr32(IGC_CTRL_EXT, ctrl_ext);
208 }
209
igc_pin_extts(struct igc_adapter * igc,int chan,int pin)210 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
211 {
212 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
213 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
214 };
215 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
216 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
217 };
218 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
219 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
220 };
221 struct igc_hw *hw = &igc->hw;
222 u32 ctrl, ctrl_ext, tssdp = 0;
223
224 ctrl = rd32(IGC_CTRL);
225 ctrl_ext = rd32(IGC_CTRL_EXT);
226 tssdp = rd32(IGC_TSSDP);
227
228 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
229
230 /* Make sure this pin is not enabled as an output. */
231 tssdp &= ~igc_ts_sdp_en[pin];
232
233 if (chan == 1) {
234 tssdp &= ~IGC_AUX1_SEL_SDP3;
235 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
236 } else {
237 tssdp &= ~IGC_AUX0_SEL_SDP3;
238 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
239 }
240
241 wr32(IGC_TSSDP, tssdp);
242 wr32(IGC_CTRL, ctrl);
243 wr32(IGC_CTRL_EXT, ctrl_ext);
244 }
245
igc_ptp_feature_enable_i225(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)246 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
247 struct ptp_clock_request *rq, int on)
248 {
249 struct igc_adapter *igc =
250 container_of(ptp, struct igc_adapter, ptp_caps);
251 struct igc_hw *hw = &igc->hw;
252 unsigned long flags;
253 struct timespec64 ts;
254 int use_freq = 0, pin = -1;
255 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
256 s64 ns;
257
258 switch (rq->type) {
259 case PTP_CLK_REQ_EXTTS:
260 /* Reject requests failing to enable both edges. */
261 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
262 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
263 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
264 return -EOPNOTSUPP;
265
266 if (on) {
267 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
268 rq->extts.index);
269 if (pin < 0)
270 return -EBUSY;
271 }
272 if (rq->extts.index == 1) {
273 tsauxc_mask = IGC_TSAUXC_EN_TS1;
274 tsim_mask = IGC_TSICR_AUTT1;
275 } else {
276 tsauxc_mask = IGC_TSAUXC_EN_TS0;
277 tsim_mask = IGC_TSICR_AUTT0;
278 }
279 spin_lock_irqsave(&igc->tmreg_lock, flags);
280 tsauxc = rd32(IGC_TSAUXC);
281 tsim = rd32(IGC_TSIM);
282 if (on) {
283 igc_pin_extts(igc, rq->extts.index, pin);
284 tsauxc |= tsauxc_mask;
285 tsim |= tsim_mask;
286 } else {
287 tsauxc &= ~tsauxc_mask;
288 tsim &= ~tsim_mask;
289 }
290 wr32(IGC_TSAUXC, tsauxc);
291 wr32(IGC_TSIM, tsim);
292 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
293 return 0;
294
295 case PTP_CLK_REQ_PEROUT:
296 if (on) {
297 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
298 rq->perout.index);
299 if (pin < 0)
300 return -EBUSY;
301 }
302 ts.tv_sec = rq->perout.period.sec;
303 ts.tv_nsec = rq->perout.period.nsec;
304 ns = timespec64_to_ns(&ts);
305 ns = ns >> 1;
306 if (on && (ns <= 70000000LL || ns == 125000000LL ||
307 ns == 250000000LL || ns == 500000000LL)) {
308 if (ns < 8LL)
309 return -EINVAL;
310 use_freq = 1;
311 }
312 ts = ns_to_timespec64(ns);
313 if (rq->perout.index == 1) {
314 if (use_freq) {
315 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
316 tsim_mask = 0;
317 } else {
318 tsauxc_mask = IGC_TSAUXC_EN_TT1;
319 tsim_mask = IGC_TSICR_TT1;
320 }
321 trgttiml = IGC_TRGTTIML1;
322 trgttimh = IGC_TRGTTIMH1;
323 freqout = IGC_FREQOUT1;
324 } else {
325 if (use_freq) {
326 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
327 tsim_mask = 0;
328 } else {
329 tsauxc_mask = IGC_TSAUXC_EN_TT0;
330 tsim_mask = IGC_TSICR_TT0;
331 }
332 trgttiml = IGC_TRGTTIML0;
333 trgttimh = IGC_TRGTTIMH0;
334 freqout = IGC_FREQOUT0;
335 }
336 spin_lock_irqsave(&igc->tmreg_lock, flags);
337 tsauxc = rd32(IGC_TSAUXC);
338 tsim = rd32(IGC_TSIM);
339 if (rq->perout.index == 1) {
340 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
341 IGC_TSAUXC_ST1);
342 tsim &= ~IGC_TSICR_TT1;
343 } else {
344 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
345 IGC_TSAUXC_ST0);
346 tsim &= ~IGC_TSICR_TT0;
347 }
348 if (on) {
349 struct timespec64 safe_start;
350 int i = rq->perout.index;
351
352 igc_pin_perout(igc, i, pin, use_freq);
353 igc_ptp_read(igc, &safe_start);
354
355 /* PPS output start time is triggered by Target time(TT)
356 * register. Programming any past time value into TT
357 * register will cause PPS to never start. Need to make
358 * sure we program the TT register a time ahead in
359 * future. There isn't a stringent need to fire PPS out
360 * right away. Adding +2 seconds should take care of
361 * corner cases. Let's say if the SYSTIML is close to
362 * wrap up and the timer keeps ticking as we program the
363 * register, adding +2seconds is safe bet.
364 */
365 safe_start.tv_sec += 2;
366
367 if (rq->perout.start.sec < safe_start.tv_sec)
368 igc->perout[i].start.tv_sec = safe_start.tv_sec;
369 else
370 igc->perout[i].start.tv_sec = rq->perout.start.sec;
371 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
372 igc->perout[i].period.tv_sec = ts.tv_sec;
373 igc->perout[i].period.tv_nsec = ts.tv_nsec;
374 wr32(trgttimh, (u32)igc->perout[i].start.tv_sec);
375 /* For now, always select timer 0 as source. */
376 wr32(trgttiml, (u32)(igc->perout[i].start.tv_nsec |
377 IGC_TT_IO_TIMER_SEL_SYSTIM0));
378 if (use_freq)
379 wr32(freqout, ns);
380 tsauxc |= tsauxc_mask;
381 tsim |= tsim_mask;
382 }
383 wr32(IGC_TSAUXC, tsauxc);
384 wr32(IGC_TSIM, tsim);
385 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
386 return 0;
387
388 case PTP_CLK_REQ_PPS:
389 spin_lock_irqsave(&igc->tmreg_lock, flags);
390 tsim = rd32(IGC_TSIM);
391 if (on)
392 tsim |= IGC_TSICR_SYS_WRAP;
393 else
394 tsim &= ~IGC_TSICR_SYS_WRAP;
395 igc->pps_sys_wrap_on = on;
396 wr32(IGC_TSIM, tsim);
397 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
398 return 0;
399
400 default:
401 break;
402 }
403
404 return -EOPNOTSUPP;
405 }
406
igc_ptp_verify_pin(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)407 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
408 enum ptp_pin_function func, unsigned int chan)
409 {
410 switch (func) {
411 case PTP_PF_NONE:
412 case PTP_PF_EXTTS:
413 case PTP_PF_PEROUT:
414 break;
415 case PTP_PF_PHYSYNC:
416 return -1;
417 }
418 return 0;
419 }
420
421 /**
422 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
423 * @adapter: board private structure
424 * @hwtstamps: timestamp structure to update
425 * @systim: unsigned 64bit system time value
426 *
427 * We need to convert the system time value stored in the RX/TXSTMP registers
428 * into a hwtstamp which can be used by the upper level timestamping functions.
429 *
430 * Returns 0 on success.
431 **/
igc_ptp_systim_to_hwtstamp(struct igc_adapter * adapter,struct skb_shared_hwtstamps * hwtstamps,u64 systim)432 static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
433 struct skb_shared_hwtstamps *hwtstamps,
434 u64 systim)
435 {
436 switch (adapter->hw.mac.type) {
437 case igc_i225:
438 memset(hwtstamps, 0, sizeof(*hwtstamps));
439 /* Upper 32 bits contain s, lower 32 bits contain ns. */
440 hwtstamps->hwtstamp = ktime_set(systim >> 32,
441 systim & 0xFFFFFFFF);
442 break;
443 default:
444 return -EINVAL;
445 }
446 return 0;
447 }
448
449 /**
450 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
451 * @adapter: Pointer to adapter the packet buffer belongs to
452 * @buf: Pointer to start of timestamp in HW format (2 32-bit words)
453 *
454 * This function retrieves and converts the timestamp stored at @buf
455 * to ktime_t, adjusting for hardware latencies.
456 *
457 * Returns timestamp value.
458 */
igc_ptp_rx_pktstamp(struct igc_adapter * adapter,__le32 * buf)459 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
460 {
461 ktime_t timestamp;
462 u32 secs, nsecs;
463 int adjust;
464
465 nsecs = le32_to_cpu(buf[0]);
466 secs = le32_to_cpu(buf[1]);
467
468 timestamp = ktime_set(secs, nsecs);
469
470 /* Adjust timestamp for the RX latency based on link speed */
471 switch (adapter->link_speed) {
472 case SPEED_10:
473 adjust = IGC_I225_RX_LATENCY_10;
474 break;
475 case SPEED_100:
476 adjust = IGC_I225_RX_LATENCY_100;
477 break;
478 case SPEED_1000:
479 adjust = IGC_I225_RX_LATENCY_1000;
480 break;
481 case SPEED_2500:
482 adjust = IGC_I225_RX_LATENCY_2500;
483 break;
484 default:
485 adjust = 0;
486 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
487 break;
488 }
489
490 return ktime_sub_ns(timestamp, adjust);
491 }
492
igc_ptp_disable_rx_timestamp(struct igc_adapter * adapter)493 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
494 {
495 struct igc_hw *hw = &adapter->hw;
496 u32 val;
497 int i;
498
499 wr32(IGC_TSYNCRXCTL, 0);
500
501 for (i = 0; i < adapter->num_rx_queues; i++) {
502 val = rd32(IGC_SRRCTL(i));
503 val &= ~IGC_SRRCTL_TIMESTAMP;
504 wr32(IGC_SRRCTL(i), val);
505 }
506
507 val = rd32(IGC_RXPBS);
508 val &= ~IGC_RXPBS_CFG_TS_EN;
509 wr32(IGC_RXPBS, val);
510 }
511
igc_ptp_enable_rx_timestamp(struct igc_adapter * adapter)512 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
513 {
514 struct igc_hw *hw = &adapter->hw;
515 u32 val;
516 int i;
517
518 val = rd32(IGC_RXPBS);
519 val |= IGC_RXPBS_CFG_TS_EN;
520 wr32(IGC_RXPBS, val);
521
522 for (i = 0; i < adapter->num_rx_queues; i++) {
523 val = rd32(IGC_SRRCTL(i));
524 /* Enable retrieving timestamps from timer 0, the
525 * "adjustable clock" and timer 1 the "free running
526 * clock".
527 */
528 val |= IGC_SRRCTL_TIMER1SEL(1) | IGC_SRRCTL_TIMER0SEL(0) |
529 IGC_SRRCTL_TIMESTAMP;
530 wr32(IGC_SRRCTL(i), val);
531 }
532
533 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
534 IGC_TSYNCRXCTL_RXSYNSIG;
535 wr32(IGC_TSYNCRXCTL, val);
536 }
537
igc_ptp_free_tx_buffer(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp)538 static void igc_ptp_free_tx_buffer(struct igc_adapter *adapter,
539 struct igc_tx_timestamp_request *tstamp)
540 {
541 if (tstamp->buffer_type == IGC_TX_BUFFER_TYPE_XSK) {
542 /* Release the transmit completion */
543 tstamp->xsk_tx_buffer->xsk_pending_ts = false;
544
545 /* Note: tstamp->skb and tstamp->xsk_tx_buffer are in union.
546 * By setting tstamp->xsk_tx_buffer to NULL, tstamp->skb will
547 * become NULL as well.
548 */
549 tstamp->xsk_tx_buffer = NULL;
550 tstamp->buffer_type = 0;
551
552 /* Trigger txrx interrupt for transmit completion */
553 igc_xsk_wakeup(adapter->netdev, tstamp->xsk_queue_index,
554 XDP_WAKEUP_TX);
555
556 return;
557 }
558
559 dev_kfree_skb_any(tstamp->skb);
560 tstamp->skb = NULL;
561 }
562
igc_ptp_clear_tx_tstamp(struct igc_adapter * adapter)563 static void igc_ptp_clear_tx_tstamp(struct igc_adapter *adapter)
564 {
565 unsigned long flags;
566 int i;
567
568 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
569
570 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
571 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
572
573 if (tstamp->skb)
574 igc_ptp_free_tx_buffer(adapter, tstamp);
575 }
576
577 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
578 }
579
igc_ptp_disable_tx_timestamp(struct igc_adapter * adapter)580 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
581 {
582 struct igc_hw *hw = &adapter->hw;
583 int i;
584
585 /* Clear the flags first to avoid new packets to be enqueued
586 * for TX timestamping.
587 */
588 for (i = 0; i < adapter->num_tx_queues; i++) {
589 struct igc_ring *tx_ring = adapter->tx_ring[i];
590
591 clear_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
592 }
593
594 /* Now we can clean the pending TX timestamp requests. */
595 igc_ptp_clear_tx_tstamp(adapter);
596
597 wr32(IGC_TSYNCTXCTL, 0);
598 }
599
igc_ptp_enable_tx_timestamp(struct igc_adapter * adapter)600 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
601 {
602 struct igc_hw *hw = &adapter->hw;
603 int i;
604
605 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
606
607 /* Read TXSTMP registers to discard any timestamp previously stored. */
608 rd32(IGC_TXSTMPL);
609 rd32(IGC_TXSTMPH);
610
611 /* The hardware is ready to accept TX timestamp requests,
612 * notify the transmit path.
613 */
614 for (i = 0; i < adapter->num_tx_queues; i++) {
615 struct igc_ring *tx_ring = adapter->tx_ring[i];
616
617 set_bit(IGC_RING_FLAG_TX_HWTSTAMP, &tx_ring->flags);
618 }
619
620 }
621
622 /**
623 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
624 * @adapter: networking device structure
625 * @config: hwtstamp configuration
626 *
627 * Return: 0 in case of success, negative errno code otherwise.
628 */
igc_ptp_set_timestamp_mode(struct igc_adapter * adapter,struct kernel_hwtstamp_config * config)629 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
630 struct kernel_hwtstamp_config *config)
631 {
632 switch (config->tx_type) {
633 case HWTSTAMP_TX_OFF:
634 igc_ptp_disable_tx_timestamp(adapter);
635 break;
636 case HWTSTAMP_TX_ON:
637 igc_ptp_enable_tx_timestamp(adapter);
638 break;
639 default:
640 return -ERANGE;
641 }
642
643 switch (config->rx_filter) {
644 case HWTSTAMP_FILTER_NONE:
645 igc_ptp_disable_rx_timestamp(adapter);
646 break;
647 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
648 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
649 case HWTSTAMP_FILTER_PTP_V2_EVENT:
650 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
651 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
652 case HWTSTAMP_FILTER_PTP_V2_SYNC:
653 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
654 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
655 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
656 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
657 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
658 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
659 case HWTSTAMP_FILTER_NTP_ALL:
660 case HWTSTAMP_FILTER_ALL:
661 igc_ptp_enable_rx_timestamp(adapter);
662 config->rx_filter = HWTSTAMP_FILTER_ALL;
663 break;
664 default:
665 return -ERANGE;
666 }
667
668 return 0;
669 }
670
671 /* Requires adapter->ptp_tx_lock held by caller. */
igc_ptp_tx_timeout(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp)672 static void igc_ptp_tx_timeout(struct igc_adapter *adapter,
673 struct igc_tx_timestamp_request *tstamp)
674 {
675 if (tstamp->skb)
676 igc_ptp_free_tx_buffer(adapter, tstamp);
677
678 adapter->tx_hwtstamp_timeouts++;
679
680 netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
681 }
682
igc_ptp_tx_hang(struct igc_adapter * adapter)683 void igc_ptp_tx_hang(struct igc_adapter *adapter)
684 {
685 struct igc_tx_timestamp_request *tstamp;
686 struct igc_hw *hw = &adapter->hw;
687 unsigned long flags;
688 bool found = false;
689 int i;
690
691 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
692
693 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
694 tstamp = &adapter->tx_tstamp[i];
695
696 if (!tstamp->skb)
697 continue;
698
699 if (time_is_after_jiffies(tstamp->start + IGC_PTP_TX_TIMEOUT))
700 continue;
701
702 igc_ptp_tx_timeout(adapter, tstamp);
703 found = true;
704 }
705
706 if (found) {
707 /* Reading the high register of the first set of timestamp registers
708 * clears all the equivalent bits in the TSYNCTXCTL register.
709 */
710 rd32(IGC_TXSTMPH_0);
711 }
712
713 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
714 }
715
igc_ptp_tx_reg_to_stamp(struct igc_adapter * adapter,struct igc_tx_timestamp_request * tstamp,u64 regval)716 static void igc_ptp_tx_reg_to_stamp(struct igc_adapter *adapter,
717 struct igc_tx_timestamp_request *tstamp, u64 regval)
718 {
719 struct skb_shared_hwtstamps shhwtstamps;
720 struct sk_buff *skb;
721 int adjust = 0;
722
723 skb = tstamp->skb;
724 if (!skb)
725 return;
726
727 if (igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval))
728 return;
729
730 switch (adapter->link_speed) {
731 case SPEED_10:
732 adjust = IGC_I225_TX_LATENCY_10;
733 break;
734 case SPEED_100:
735 adjust = IGC_I225_TX_LATENCY_100;
736 break;
737 case SPEED_1000:
738 adjust = IGC_I225_TX_LATENCY_1000;
739 break;
740 case SPEED_2500:
741 adjust = IGC_I225_TX_LATENCY_2500;
742 break;
743 }
744
745 shhwtstamps.hwtstamp =
746 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
747
748 /* Copy the tx hardware timestamp into xdp metadata or skb */
749 if (tstamp->buffer_type == IGC_TX_BUFFER_TYPE_XSK) {
750 struct xsk_buff_pool *xsk_pool;
751
752 xsk_pool = adapter->tx_ring[tstamp->xsk_queue_index]->xsk_pool;
753 if (xsk_pool && xp_tx_metadata_enabled(xsk_pool)) {
754 xsk_tx_metadata_complete(&tstamp->xsk_meta,
755 &igc_xsk_tx_metadata_ops,
756 &shhwtstamps.hwtstamp);
757 }
758 } else {
759 skb_tstamp_tx(skb, &shhwtstamps);
760 }
761
762 igc_ptp_free_tx_buffer(adapter, tstamp);
763 }
764
765 /**
766 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
767 * @adapter: Board private structure
768 *
769 * Check against the ready mask for which of the timestamp register
770 * sets are ready to be retrieved, then retrieve that and notify the
771 * rest of the stack.
772 *
773 * Context: Expects adapter->ptp_tx_lock to be held by caller.
774 */
igc_ptp_tx_hwtstamp(struct igc_adapter * adapter)775 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
776 {
777 struct igc_hw *hw = &adapter->hw;
778 u32 txstmpl_old;
779 u64 regval;
780 u32 mask;
781 int i;
782
783 /* Establish baseline of TXSTMPL_0 before checking TXTT_0.
784 * This baseline is used to detect if a new timestamp arrives in
785 * register 0 during the hardware bug workaround below.
786 */
787 txstmpl_old = rd32(IGC_TXSTMPL);
788
789 mask = rd32(IGC_TSYNCTXCTL) & IGC_TSYNCTXCTL_TXTT_ANY;
790 if (mask & IGC_TSYNCTXCTL_TXTT_0) {
791 regval = rd32(IGC_TXSTMPL);
792 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
793 } else {
794 /* TXTT_0 not set - register 0 has no new timestamp initially.
795 *
796 * Hardware bug: Future timestamp interrupts won't fire unless
797 * TXSTMPH_0 is read, even if the timestamp was captured in
798 * registers 1-3.
799 *
800 * Workaround: Read TXSTMPH_0 here to enable future interrupts.
801 * However, this read clears TXTT_0. If a timestamp arrives in
802 * register 0 after checking TXTT_0 but before this read, it
803 * would be lost.
804 *
805 * To detect this race: We saved a baseline read of TXSTMPL_0
806 * before TXTT_0 check. After performing the workaround read of
807 * TXSTMPH_0, we read TXSTMPL_0 again. Since consecutive
808 * timestamps never share the same nanosecond value, a change
809 * between the baseline and new TXSTMPL_0 indicates a timestamp
810 * arrived during the race window. If so, read the complete
811 * timestamp.
812 */
813 u32 txstmpl_new;
814
815 rd32(IGC_TXSTMPH);
816 txstmpl_new = rd32(IGC_TXSTMPL);
817
818 if (txstmpl_old == txstmpl_new)
819 goto done;
820
821 regval = txstmpl_new;
822 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
823 }
824
825 igc_ptp_tx_reg_to_stamp(adapter, &adapter->tx_tstamp[0], regval);
826
827 done:
828 /* Now that the problematic first register was handled, we can
829 * retrieve the timestamps from the other registers
830 * (starting from '1') with less complications.
831 */
832 for (i = 1; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
833 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
834
835 if (!(tstamp->mask & mask))
836 continue;
837
838 regval = rd32(tstamp->regl);
839 regval |= (u64)rd32(tstamp->regh) << 32;
840
841 igc_ptp_tx_reg_to_stamp(adapter, tstamp, regval);
842 }
843 }
844
845 /**
846 * igc_ptp_tx_tstamp_event
847 * @adapter: board private structure
848 *
849 * Called when a TX timestamp interrupt happens to retrieve the
850 * timestamp and send it up to the socket.
851 */
igc_ptp_tx_tstamp_event(struct igc_adapter * adapter)852 void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter)
853 {
854 unsigned long flags;
855
856 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
857
858 igc_ptp_tx_hwtstamp(adapter);
859
860 spin_unlock_irqrestore(&adapter->ptp_tx_lock, flags);
861 }
862
863 /**
864 * igc_ptp_hwtstamp_set - set hardware time stamping config
865 * @netdev: network interface device structure
866 * @config: timestamping configuration structure
867 * @extack: netlink extended ack structure for error reporting
868 *
869 **/
igc_ptp_hwtstamp_set(struct net_device * netdev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)870 int igc_ptp_hwtstamp_set(struct net_device *netdev,
871 struct kernel_hwtstamp_config *config,
872 struct netlink_ext_ack *extack)
873 {
874 struct igc_adapter *adapter = netdev_priv(netdev);
875 int err;
876
877 err = igc_ptp_set_timestamp_mode(adapter, config);
878 if (err)
879 return err;
880
881 /* save these settings for future reference */
882 adapter->tstamp_config = *config;
883
884 return 0;
885 }
886
887 /**
888 * igc_ptp_hwtstamp_get - get hardware time stamping config
889 * @netdev: network interface device structure
890 * @config: timestamping configuration structure
891 *
892 * Get the hwtstamp_config settings to return to the user. Rather than attempt
893 * to deconstruct the settings from the registers, just return a shadow copy
894 * of the last known settings.
895 **/
igc_ptp_hwtstamp_get(struct net_device * netdev,struct kernel_hwtstamp_config * config)896 int igc_ptp_hwtstamp_get(struct net_device *netdev,
897 struct kernel_hwtstamp_config *config)
898 {
899 struct igc_adapter *adapter = netdev_priv(netdev);
900
901 *config = adapter->tstamp_config;
902
903 return 0;
904 }
905
906 /* The two conditions below must be met for cross timestamping via
907 * PCIe PTM:
908 *
909 * 1. We have an way to convert the timestamps in the PTM messages
910 * to something related to the system clocks (right now, only
911 * X86 systems with support for the Always Running Timer allow that);
912 *
913 * 2. We have PTM enabled in the path from the device to the PCIe root port.
914 */
igc_is_crosststamp_supported(struct igc_adapter * adapter)915 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
916 {
917 if (!IS_ENABLED(CONFIG_X86_TSC))
918 return false;
919
920 /* FIXME: it was noticed that enabling support for PCIe PTM in
921 * some i225-V models could cause lockups when bringing the
922 * interface up/down. There should be no downsides to
923 * disabling crosstimestamping support for i225-V, as it
924 * doesn't have any PTP support. That way we gain some time
925 * while root causing the issue.
926 */
927 if (adapter->pdev->device == IGC_DEV_ID_I225_V)
928 return false;
929
930 return pcie_ptm_enabled(adapter->pdev);
931 }
932
igc_device_tstamp_to_system(u64 tstamp)933 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
934 {
935 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
936 return (struct system_counterval_t) {
937 .cs_id = CSID_X86_ART,
938 .cycles = tstamp,
939 .use_nsecs = true,
940 };
941 #else
942 return (struct system_counterval_t) { };
943 #endif
944 }
945
igc_ptm_log_error(struct igc_adapter * adapter,u32 ptm_stat)946 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
947 {
948 struct net_device *netdev = adapter->netdev;
949
950 switch (ptm_stat) {
951 case IGC_PTM_STAT_RET_ERR:
952 netdev_err(netdev, "PTM Error: Root port timeout\n");
953 break;
954 case IGC_PTM_STAT_BAD_PTM_RES:
955 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
956 break;
957 case IGC_PTM_STAT_T4M1_OVFL:
958 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
959 break;
960 case IGC_PTM_STAT_ADJUST_1ST:
961 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
962 break;
963 case IGC_PTM_STAT_ADJUST_CYC:
964 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
965 break;
966 default:
967 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
968 break;
969 }
970 }
971
972 /* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_trigger() */
igc_ptm_trigger(struct igc_hw * hw)973 static void igc_ptm_trigger(struct igc_hw *hw)
974 {
975 u32 ctrl;
976
977 /* To "manually" start the PTM cycle we need to set the
978 * trigger (TRIG) bit
979 */
980 ctrl = rd32(IGC_PTM_CTRL);
981 ctrl |= IGC_PTM_CTRL_TRIG;
982 wr32(IGC_PTM_CTRL, ctrl);
983 /* Perform flush after write to CTRL register otherwise
984 * transaction may not start
985 */
986 wrfl();
987 }
988
989 /* The PTM lock: adapter->ptm_lock must be held when calling igc_ptm_reset() */
igc_ptm_reset(struct igc_hw * hw)990 static void igc_ptm_reset(struct igc_hw *hw)
991 {
992 u32 ctrl;
993
994 ctrl = rd32(IGC_PTM_CTRL);
995 ctrl &= ~IGC_PTM_CTRL_TRIG;
996 wr32(IGC_PTM_CTRL, ctrl);
997 /* Write to clear all status */
998 wr32(IGC_PTM_STAT, IGC_PTM_STAT_ALL);
999 }
1000
igc_phc_get_syncdevicetime(ktime_t * device,struct system_counterval_t * system,void * ctx)1001 static int igc_phc_get_syncdevicetime(ktime_t *device,
1002 struct system_counterval_t *system,
1003 void *ctx)
1004 {
1005 struct igc_adapter *adapter = ctx;
1006 struct igc_hw *hw = &adapter->hw;
1007 u32 stat, t2_curr_h, t2_curr_l;
1008 int err, count = 100;
1009 ktime_t t1, t2_curr;
1010
1011 /* Doing this in a loop because in the event of a
1012 * badly timed (ha!) system clock adjustment, we may
1013 * get PTM errors from the PCI root, but these errors
1014 * are transitory. Repeating the process returns valid
1015 * data eventually.
1016 */
1017 do {
1018 /* Get a snapshot of system clocks to use as historic value. */
1019 ktime_get_snapshot(&adapter->snapshot);
1020
1021 igc_ptm_trigger(hw);
1022
1023 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
1024 stat, IGC_PTM_STAT_SLEEP,
1025 IGC_PTM_STAT_TIMEOUT);
1026 igc_ptm_reset(hw);
1027
1028 if (err < 0) {
1029 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
1030 return err;
1031 }
1032
1033 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
1034 break;
1035
1036 igc_ptm_log_error(adapter, stat);
1037 } while (--count);
1038
1039 if (!count) {
1040 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
1041 return -ETIMEDOUT;
1042 }
1043
1044 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
1045
1046 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
1047 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
1048
1049 /* FIXME: When the register that tells the endianness of the
1050 * PTM registers are implemented, check them here and add the
1051 * appropriate conversion.
1052 */
1053 t2_curr_h = swab32(t2_curr_h);
1054
1055 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
1056
1057 *device = t1;
1058 *system = igc_device_tstamp_to_system(t2_curr);
1059
1060 return 0;
1061 }
1062
igc_ptp_getcrosststamp(struct ptp_clock_info * ptp,struct system_device_crosststamp * cts)1063 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
1064 struct system_device_crosststamp *cts)
1065 {
1066 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
1067 ptp_caps);
1068 int ret;
1069
1070 /* This blocks until any in progress PTM transactions complete */
1071 mutex_lock(&adapter->ptm_lock);
1072
1073 ret = get_device_system_crosststamp(igc_phc_get_syncdevicetime,
1074 adapter, &adapter->snapshot, cts);
1075 mutex_unlock(&adapter->ptm_lock);
1076
1077 return ret;
1078 }
1079
igc_ptp_getcyclesx64(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1080 static int igc_ptp_getcyclesx64(struct ptp_clock_info *ptp,
1081 struct timespec64 *ts,
1082 struct ptp_system_timestamp *sts)
1083 {
1084 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, ptp_caps);
1085 struct igc_hw *hw = &igc->hw;
1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&igc->free_timer_lock, flags);
1089
1090 ptp_read_system_prets(sts);
1091 ts->tv_nsec = rd32(IGC_SYSTIML_1);
1092 ts->tv_sec = rd32(IGC_SYSTIMH_1);
1093 ptp_read_system_postts(sts);
1094
1095 spin_unlock_irqrestore(&igc->free_timer_lock, flags);
1096
1097 return 0;
1098 }
1099
1100 /**
1101 * igc_ptp_init - Initialize PTP functionality
1102 * @adapter: Board private structure
1103 *
1104 * This function is called at device probe to initialize the PTP
1105 * functionality.
1106 */
igc_ptp_init(struct igc_adapter * adapter)1107 void igc_ptp_init(struct igc_adapter *adapter)
1108 {
1109 struct net_device *netdev = adapter->netdev;
1110 struct igc_tx_timestamp_request *tstamp;
1111 struct igc_hw *hw = &adapter->hw;
1112 int i;
1113
1114 tstamp = &adapter->tx_tstamp[0];
1115 tstamp->mask = IGC_TSYNCTXCTL_TXTT_0;
1116 tstamp->regl = IGC_TXSTMPL_0;
1117 tstamp->regh = IGC_TXSTMPH_0;
1118 tstamp->flags = 0;
1119
1120 tstamp = &adapter->tx_tstamp[1];
1121 tstamp->mask = IGC_TSYNCTXCTL_TXTT_1;
1122 tstamp->regl = IGC_TXSTMPL_1;
1123 tstamp->regh = IGC_TXSTMPH_1;
1124 tstamp->flags = IGC_TX_FLAGS_TSTAMP_1;
1125
1126 tstamp = &adapter->tx_tstamp[2];
1127 tstamp->mask = IGC_TSYNCTXCTL_TXTT_2;
1128 tstamp->regl = IGC_TXSTMPL_2;
1129 tstamp->regh = IGC_TXSTMPH_2;
1130 tstamp->flags = IGC_TX_FLAGS_TSTAMP_2;
1131
1132 tstamp = &adapter->tx_tstamp[3];
1133 tstamp->mask = IGC_TSYNCTXCTL_TXTT_3;
1134 tstamp->regl = IGC_TXSTMPL_3;
1135 tstamp->regh = IGC_TXSTMPH_3;
1136 tstamp->flags = IGC_TX_FLAGS_TSTAMP_3;
1137
1138 switch (hw->mac.type) {
1139 case igc_i225:
1140 for (i = 0; i < IGC_N_SDP; i++) {
1141 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1142
1143 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1144 ppd->index = i;
1145 ppd->func = PTP_PF_NONE;
1146 }
1147 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1148 adapter->ptp_caps.owner = THIS_MODULE;
1149 adapter->ptp_caps.max_adj = 62499999;
1150 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
1151 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
1152 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
1153 adapter->ptp_caps.getcyclesx64 = igc_ptp_getcyclesx64;
1154 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
1155 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
1156 adapter->ptp_caps.pps = 1;
1157 adapter->ptp_caps.pin_config = adapter->sdp_config;
1158 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
1159 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
1160 adapter->ptp_caps.supported_extts_flags = PTP_RISING_EDGE |
1161 PTP_FALLING_EDGE |
1162 PTP_STRICT_FLAGS;
1163 adapter->ptp_caps.n_pins = IGC_N_SDP;
1164 adapter->ptp_caps.verify = igc_ptp_verify_pin;
1165
1166 if (!igc_is_crosststamp_supported(adapter))
1167 break;
1168
1169 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
1170 break;
1171 default:
1172 adapter->ptp_clock = NULL;
1173 return;
1174 }
1175
1176 spin_lock_init(&adapter->ptp_tx_lock);
1177 spin_lock_init(&adapter->free_timer_lock);
1178 spin_lock_init(&adapter->tmreg_lock);
1179 mutex_init(&adapter->ptm_lock);
1180
1181 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1182 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1183
1184 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
1185 adapter->ptp_reset_start = ktime_get();
1186
1187 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1188 &adapter->pdev->dev);
1189 if (IS_ERR(adapter->ptp_clock)) {
1190 adapter->ptp_clock = NULL;
1191 netdev_err(netdev, "ptp_clock_register failed\n");
1192 mutex_destroy(&adapter->ptm_lock);
1193 } else if (adapter->ptp_clock) {
1194 netdev_info(netdev, "PHC added\n");
1195 adapter->ptp_flags |= IGC_PTP_ENABLED;
1196 }
1197 }
1198
igc_ptp_time_save(struct igc_adapter * adapter)1199 static void igc_ptp_time_save(struct igc_adapter *adapter)
1200 {
1201 igc_ptp_read(adapter, &adapter->prev_ptp_time);
1202 adapter->ptp_reset_start = ktime_get();
1203 }
1204
igc_ptp_time_restore(struct igc_adapter * adapter)1205 static void igc_ptp_time_restore(struct igc_adapter *adapter)
1206 {
1207 struct timespec64 ts = adapter->prev_ptp_time;
1208 ktime_t delta;
1209
1210 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
1211
1212 timespec64_add_ns(&ts, ktime_to_ns(delta));
1213
1214 igc_ptp_write_i225(adapter, &ts);
1215 }
1216
igc_ptm_stop(struct igc_adapter * adapter)1217 static void igc_ptm_stop(struct igc_adapter *adapter)
1218 {
1219 struct igc_hw *hw = &adapter->hw;
1220 u32 ctrl;
1221
1222 mutex_lock(&adapter->ptm_lock);
1223 ctrl = rd32(IGC_PTM_CTRL);
1224 ctrl &= ~IGC_PTM_CTRL_EN;
1225
1226 wr32(IGC_PTM_CTRL, ctrl);
1227 mutex_unlock(&adapter->ptm_lock);
1228 }
1229
1230 /**
1231 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1232 * @adapter: Board private structure
1233 *
1234 * This function stops the overflow check work and PTP Tx timestamp work, and
1235 * will prepare the device for OS suspend.
1236 */
igc_ptp_suspend(struct igc_adapter * adapter)1237 void igc_ptp_suspend(struct igc_adapter *adapter)
1238 {
1239 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1240 return;
1241
1242 igc_ptp_clear_tx_tstamp(adapter);
1243
1244 if (pci_device_is_present(adapter->pdev)) {
1245 igc_ptp_time_save(adapter);
1246 igc_ptm_stop(adapter);
1247 }
1248 }
1249
1250 /**
1251 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1252 * @adapter: Board private structure.
1253 *
1254 * This function stops the PTP support and cancels the delayed work.
1255 **/
igc_ptp_stop(struct igc_adapter * adapter)1256 void igc_ptp_stop(struct igc_adapter *adapter)
1257 {
1258 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1259 return;
1260
1261 igc_ptp_suspend(adapter);
1262
1263 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1264 if (adapter->ptp_clock) {
1265 ptp_clock_unregister(adapter->ptp_clock);
1266 netdev_info(adapter->netdev, "PHC removed\n");
1267 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1268 }
1269 mutex_destroy(&adapter->ptm_lock);
1270 }
1271
1272 /**
1273 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1274 * @adapter: Board private structure.
1275 *
1276 * This function handles the reset work required to re-enable the PTP device.
1277 **/
igc_ptp_reset(struct igc_adapter * adapter)1278 void igc_ptp_reset(struct igc_adapter *adapter)
1279 {
1280 struct igc_hw *hw = &adapter->hw;
1281 u32 cycle_ctrl, ctrl, stat;
1282 unsigned long flags;
1283 u32 timadj;
1284
1285 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1286 return;
1287
1288 /* reset the tstamp_config */
1289 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1290
1291 mutex_lock(&adapter->ptm_lock);
1292
1293 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1294
1295 switch (adapter->hw.mac.type) {
1296 case igc_i225:
1297 timadj = rd32(IGC_TIMADJ);
1298 timadj |= IGC_TIMADJ_ADJUST_METH;
1299 wr32(IGC_TIMADJ, timadj);
1300
1301 wr32(IGC_TSAUXC, 0x0);
1302 wr32(IGC_TSSDP, 0x0);
1303 wr32(IGC_TSIM,
1304 IGC_TSICR_INTERRUPTS |
1305 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1306 wr32(IGC_IMS, IGC_IMS_TS);
1307
1308 if (!igc_is_crosststamp_supported(adapter))
1309 break;
1310
1311 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1312 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1313
1314 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1315
1316 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1317
1318 ctrl = IGC_PTM_CTRL_EN |
1319 IGC_PTM_CTRL_START_NOW |
1320 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1321 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT);
1322
1323 wr32(IGC_PTM_CTRL, ctrl);
1324
1325 /* Force the first cycle to run. */
1326 igc_ptm_trigger(hw);
1327
1328 if (readx_poll_timeout_atomic(rd32, IGC_PTM_STAT, stat,
1329 stat, IGC_PTM_STAT_SLEEP,
1330 IGC_PTM_STAT_TIMEOUT))
1331 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
1332
1333 igc_ptm_reset(hw);
1334 break;
1335 default:
1336 /* No work to do. */
1337 goto out;
1338 }
1339
1340 /* Re-initialize the timer. */
1341 if (hw->mac.type == igc_i225) {
1342 igc_ptp_time_restore(adapter);
1343 } else {
1344 timecounter_init(&adapter->tc, &adapter->cc,
1345 ktime_to_ns(ktime_get_real()));
1346 }
1347 out:
1348 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1349
1350 mutex_unlock(&adapter->ptm_lock);
1351
1352 wrfl();
1353 }
1354