1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the Conexant CX25821 PCIe bridge
4 *
5 * Copyright (C) 2009 Conexant Systems Inc.
6 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8 */
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/i2c.h>
13 #include <linux/slab.h>
14 #include "cx25821.h"
15 #include "cx25821-sram.h"
16 #include "cx25821-video.h"
17
18 MODULE_DESCRIPTION("Driver for Athena cards");
19 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
20 MODULE_LICENSE("GPL");
21
22 static unsigned int debug;
23 module_param(debug, int, 0644);
24 MODULE_PARM_DESC(debug, "enable debug messages");
25
26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
27 module_param_array(card, int, NULL, 0444);
28 MODULE_PARM_DESC(card, "card type");
29
30 const struct sram_channel cx25821_sram_channels[] = {
31 [SRAM_CH00] = {
32 .i = SRAM_CH00,
33 .name = "VID A",
34 .cmds_start = VID_A_DOWN_CMDS,
35 .ctrl_start = VID_A_IQ,
36 .cdt = VID_A_CDT,
37 .fifo_start = VID_A_DOWN_CLUSTER_1,
38 .fifo_size = (VID_CLUSTER_SIZE << 2),
39 .ptr1_reg = DMA1_PTR1,
40 .ptr2_reg = DMA1_PTR2,
41 .cnt1_reg = DMA1_CNT1,
42 .cnt2_reg = DMA1_CNT2,
43 .int_msk = VID_A_INT_MSK,
44 .int_stat = VID_A_INT_STAT,
45 .int_mstat = VID_A_INT_MSTAT,
46 .dma_ctl = VID_DST_A_DMA_CTL,
47 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
48 .gpcnt = VID_DST_A_GPCNT,
49 .vip_ctl = VID_DST_A_VIP_CTL,
50 .pix_frmt = VID_DST_A_PIX_FRMT,
51 },
52
53 [SRAM_CH01] = {
54 .i = SRAM_CH01,
55 .name = "VID B",
56 .cmds_start = VID_B_DOWN_CMDS,
57 .ctrl_start = VID_B_IQ,
58 .cdt = VID_B_CDT,
59 .fifo_start = VID_B_DOWN_CLUSTER_1,
60 .fifo_size = (VID_CLUSTER_SIZE << 2),
61 .ptr1_reg = DMA2_PTR1,
62 .ptr2_reg = DMA2_PTR2,
63 .cnt1_reg = DMA2_CNT1,
64 .cnt2_reg = DMA2_CNT2,
65 .int_msk = VID_B_INT_MSK,
66 .int_stat = VID_B_INT_STAT,
67 .int_mstat = VID_B_INT_MSTAT,
68 .dma_ctl = VID_DST_B_DMA_CTL,
69 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
70 .gpcnt = VID_DST_B_GPCNT,
71 .vip_ctl = VID_DST_B_VIP_CTL,
72 .pix_frmt = VID_DST_B_PIX_FRMT,
73 },
74
75 [SRAM_CH02] = {
76 .i = SRAM_CH02,
77 .name = "VID C",
78 .cmds_start = VID_C_DOWN_CMDS,
79 .ctrl_start = VID_C_IQ,
80 .cdt = VID_C_CDT,
81 .fifo_start = VID_C_DOWN_CLUSTER_1,
82 .fifo_size = (VID_CLUSTER_SIZE << 2),
83 .ptr1_reg = DMA3_PTR1,
84 .ptr2_reg = DMA3_PTR2,
85 .cnt1_reg = DMA3_CNT1,
86 .cnt2_reg = DMA3_CNT2,
87 .int_msk = VID_C_INT_MSK,
88 .int_stat = VID_C_INT_STAT,
89 .int_mstat = VID_C_INT_MSTAT,
90 .dma_ctl = VID_DST_C_DMA_CTL,
91 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
92 .gpcnt = VID_DST_C_GPCNT,
93 .vip_ctl = VID_DST_C_VIP_CTL,
94 .pix_frmt = VID_DST_C_PIX_FRMT,
95 },
96
97 [SRAM_CH03] = {
98 .i = SRAM_CH03,
99 .name = "VID D",
100 .cmds_start = VID_D_DOWN_CMDS,
101 .ctrl_start = VID_D_IQ,
102 .cdt = VID_D_CDT,
103 .fifo_start = VID_D_DOWN_CLUSTER_1,
104 .fifo_size = (VID_CLUSTER_SIZE << 2),
105 .ptr1_reg = DMA4_PTR1,
106 .ptr2_reg = DMA4_PTR2,
107 .cnt1_reg = DMA4_CNT1,
108 .cnt2_reg = DMA4_CNT2,
109 .int_msk = VID_D_INT_MSK,
110 .int_stat = VID_D_INT_STAT,
111 .int_mstat = VID_D_INT_MSTAT,
112 .dma_ctl = VID_DST_D_DMA_CTL,
113 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
114 .gpcnt = VID_DST_D_GPCNT,
115 .vip_ctl = VID_DST_D_VIP_CTL,
116 .pix_frmt = VID_DST_D_PIX_FRMT,
117 },
118
119 [SRAM_CH04] = {
120 .i = SRAM_CH04,
121 .name = "VID E",
122 .cmds_start = VID_E_DOWN_CMDS,
123 .ctrl_start = VID_E_IQ,
124 .cdt = VID_E_CDT,
125 .fifo_start = VID_E_DOWN_CLUSTER_1,
126 .fifo_size = (VID_CLUSTER_SIZE << 2),
127 .ptr1_reg = DMA5_PTR1,
128 .ptr2_reg = DMA5_PTR2,
129 .cnt1_reg = DMA5_CNT1,
130 .cnt2_reg = DMA5_CNT2,
131 .int_msk = VID_E_INT_MSK,
132 .int_stat = VID_E_INT_STAT,
133 .int_mstat = VID_E_INT_MSTAT,
134 .dma_ctl = VID_DST_E_DMA_CTL,
135 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
136 .gpcnt = VID_DST_E_GPCNT,
137 .vip_ctl = VID_DST_E_VIP_CTL,
138 .pix_frmt = VID_DST_E_PIX_FRMT,
139 },
140
141 [SRAM_CH05] = {
142 .i = SRAM_CH05,
143 .name = "VID F",
144 .cmds_start = VID_F_DOWN_CMDS,
145 .ctrl_start = VID_F_IQ,
146 .cdt = VID_F_CDT,
147 .fifo_start = VID_F_DOWN_CLUSTER_1,
148 .fifo_size = (VID_CLUSTER_SIZE << 2),
149 .ptr1_reg = DMA6_PTR1,
150 .ptr2_reg = DMA6_PTR2,
151 .cnt1_reg = DMA6_CNT1,
152 .cnt2_reg = DMA6_CNT2,
153 .int_msk = VID_F_INT_MSK,
154 .int_stat = VID_F_INT_STAT,
155 .int_mstat = VID_F_INT_MSTAT,
156 .dma_ctl = VID_DST_F_DMA_CTL,
157 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
158 .gpcnt = VID_DST_F_GPCNT,
159 .vip_ctl = VID_DST_F_VIP_CTL,
160 .pix_frmt = VID_DST_F_PIX_FRMT,
161 },
162
163 [SRAM_CH06] = {
164 .i = SRAM_CH06,
165 .name = "VID G",
166 .cmds_start = VID_G_DOWN_CMDS,
167 .ctrl_start = VID_G_IQ,
168 .cdt = VID_G_CDT,
169 .fifo_start = VID_G_DOWN_CLUSTER_1,
170 .fifo_size = (VID_CLUSTER_SIZE << 2),
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 .int_msk = VID_G_INT_MSK,
176 .int_stat = VID_G_INT_STAT,
177 .int_mstat = VID_G_INT_MSTAT,
178 .dma_ctl = VID_DST_G_DMA_CTL,
179 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
180 .gpcnt = VID_DST_G_GPCNT,
181 .vip_ctl = VID_DST_G_VIP_CTL,
182 .pix_frmt = VID_DST_G_PIX_FRMT,
183 },
184
185 [SRAM_CH07] = {
186 .i = SRAM_CH07,
187 .name = "VID H",
188 .cmds_start = VID_H_DOWN_CMDS,
189 .ctrl_start = VID_H_IQ,
190 .cdt = VID_H_CDT,
191 .fifo_start = VID_H_DOWN_CLUSTER_1,
192 .fifo_size = (VID_CLUSTER_SIZE << 2),
193 .ptr1_reg = DMA8_PTR1,
194 .ptr2_reg = DMA8_PTR2,
195 .cnt1_reg = DMA8_CNT1,
196 .cnt2_reg = DMA8_CNT2,
197 .int_msk = VID_H_INT_MSK,
198 .int_stat = VID_H_INT_STAT,
199 .int_mstat = VID_H_INT_MSTAT,
200 .dma_ctl = VID_DST_H_DMA_CTL,
201 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
202 .gpcnt = VID_DST_H_GPCNT,
203 .vip_ctl = VID_DST_H_VIP_CTL,
204 .pix_frmt = VID_DST_H_PIX_FRMT,
205 },
206
207 [SRAM_CH08] = {
208 .name = "audio from",
209 .cmds_start = AUD_A_DOWN_CMDS,
210 .ctrl_start = AUD_A_IQ,
211 .cdt = AUD_A_CDT,
212 .fifo_start = AUD_A_DOWN_CLUSTER_1,
213 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
214 .ptr1_reg = DMA17_PTR1,
215 .ptr2_reg = DMA17_PTR2,
216 .cnt1_reg = DMA17_CNT1,
217 .cnt2_reg = DMA17_CNT2,
218 },
219
220 [SRAM_CH09] = {
221 .i = SRAM_CH09,
222 .name = "VID Upstream I",
223 .cmds_start = VID_I_UP_CMDS,
224 .ctrl_start = VID_I_IQ,
225 .cdt = VID_I_CDT,
226 .fifo_start = VID_I_UP_CLUSTER_1,
227 .fifo_size = (VID_CLUSTER_SIZE << 2),
228 .ptr1_reg = DMA15_PTR1,
229 .ptr2_reg = DMA15_PTR2,
230 .cnt1_reg = DMA15_CNT1,
231 .cnt2_reg = DMA15_CNT2,
232 .int_msk = VID_I_INT_MSK,
233 .int_stat = VID_I_INT_STAT,
234 .int_mstat = VID_I_INT_MSTAT,
235 .dma_ctl = VID_SRC_I_DMA_CTL,
236 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
237 .gpcnt = VID_SRC_I_GPCNT,
238
239 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
240 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
241 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
242 .vid_cdt_size = VID_SRC_I_CDT_SZ,
243 .irq_bit = 8,
244 },
245
246 [SRAM_CH10] = {
247 .i = SRAM_CH10,
248 .name = "VID Upstream J",
249 .cmds_start = VID_J_UP_CMDS,
250 .ctrl_start = VID_J_IQ,
251 .cdt = VID_J_CDT,
252 .fifo_start = VID_J_UP_CLUSTER_1,
253 .fifo_size = (VID_CLUSTER_SIZE << 2),
254 .ptr1_reg = DMA16_PTR1,
255 .ptr2_reg = DMA16_PTR2,
256 .cnt1_reg = DMA16_CNT1,
257 .cnt2_reg = DMA16_CNT2,
258 .int_msk = VID_J_INT_MSK,
259 .int_stat = VID_J_INT_STAT,
260 .int_mstat = VID_J_INT_MSTAT,
261 .dma_ctl = VID_SRC_J_DMA_CTL,
262 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
263 .gpcnt = VID_SRC_J_GPCNT,
264
265 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
266 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
267 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
268 .vid_cdt_size = VID_SRC_J_CDT_SZ,
269 .irq_bit = 9,
270 },
271
272 [SRAM_CH11] = {
273 .i = SRAM_CH11,
274 .name = "Audio Upstream Channel B",
275 .cmds_start = AUD_B_UP_CMDS,
276 .ctrl_start = AUD_B_IQ,
277 .cdt = AUD_B_CDT,
278 .fifo_start = AUD_B_UP_CLUSTER_1,
279 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
280 .ptr1_reg = DMA22_PTR1,
281 .ptr2_reg = DMA22_PTR2,
282 .cnt1_reg = DMA22_CNT1,
283 .cnt2_reg = DMA22_CNT2,
284 .int_msk = AUD_B_INT_MSK,
285 .int_stat = AUD_B_INT_STAT,
286 .int_mstat = AUD_B_INT_MSTAT,
287 .dma_ctl = AUD_INT_DMA_CTL,
288 .gpcnt_ctl = AUD_B_GPCNT_CTL,
289 .gpcnt = AUD_B_GPCNT,
290 .aud_length = AUD_B_LNGTH,
291 .aud_cfg = AUD_B_CFG,
292 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
293 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
294 .irq_bit = 11,
295 },
296 };
297 EXPORT_SYMBOL(cx25821_sram_channels);
298
cx25821_risc_decode(u32 risc)299 static int cx25821_risc_decode(u32 risc)
300 {
301 static const char * const instr[16] = {
302 [RISC_SYNC >> 28] = "sync",
303 [RISC_WRITE >> 28] = "write",
304 [RISC_WRITEC >> 28] = "writec",
305 [RISC_READ >> 28] = "read",
306 [RISC_READC >> 28] = "readc",
307 [RISC_JUMP >> 28] = "jump",
308 [RISC_SKIP >> 28] = "skip",
309 [RISC_WRITERM >> 28] = "writerm",
310 [RISC_WRITECM >> 28] = "writecm",
311 [RISC_WRITECR >> 28] = "writecr",
312 };
313 static const int incr[16] = {
314 [RISC_WRITE >> 28] = 3,
315 [RISC_JUMP >> 28] = 3,
316 [RISC_SKIP >> 28] = 1,
317 [RISC_SYNC >> 28] = 1,
318 [RISC_WRITERM >> 28] = 3,
319 [RISC_WRITECM >> 28] = 3,
320 [RISC_WRITECR >> 28] = 4,
321 };
322 static const char * const bits[] = {
323 "12", "13", "14", "resync",
324 "cnt0", "cnt1", "18", "19",
325 "20", "21", "22", "23",
326 "irq1", "irq2", "eol", "sol",
327 };
328 int i;
329
330 pr_cont("0x%08x [ %s",
331 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
333 if (risc & (1 << (i + 12)))
334 pr_cont(" %s", bits[i]);
335 }
336 pr_cont(" count=%d ]\n", risc & 0xfff);
337 return incr[risc >> 28] ? incr[risc >> 28] : 1;
338 }
339
cx25821_registers_init(struct cx25821_dev * dev)340 static void cx25821_registers_init(struct cx25821_dev *dev)
341 {
342 u32 tmp;
343
344 /* enable RUN_RISC in Pecos */
345 cx_write(DEV_CNTRL2, 0x20);
346
347 /* Set the master PCI interrupt masks to enable video, audio, MBIF,
348 * and GPIO interrupts
349 * I2C interrupt masking is handled by the I2C objects themselves. */
350 cx_write(PCI_INT_MSK, 0x2001FFFF);
351
352 tmp = cx_read(RDR_TLCTL0);
353 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */
354 cx_write(RDR_TLCTL0, tmp);
355
356 /* PLL-A setting for the Audio Master Clock */
357 cx_write(PLL_A_INT_FRAC, 0x9807A58B);
358
359 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
360 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
361
362 /* clear reset bit [31] */
363 tmp = cx_read(PLL_A_INT_FRAC);
364 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
365
366 /* PLL-B setting for Mobilygen Host Bus Interface */
367 cx_write(PLL_B_INT_FRAC, 0x9883A86F);
368
369 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
370 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
371
372 /* clear reset bit [31] */
373 tmp = cx_read(PLL_B_INT_FRAC);
374 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
375
376 /* PLL-C setting for video upstream channel */
377 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
378
379 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
380 cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
381
382 /* clear reset bit [31] */
383 tmp = cx_read(PLL_C_INT_FRAC);
384 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
385
386 /* PLL-D setting for audio upstream channel */
387 cx_write(PLL_D_INT_FRAC, 0x98757F5B);
388
389 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
390 cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
391
392 /* clear reset bit [31] */
393 tmp = cx_read(PLL_D_INT_FRAC);
394 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
395
396 /* This selects the PLL C clock source for the video upstream channel
397 * I and J */
398 tmp = cx_read(VID_CH_CLK_SEL);
399 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
400
401 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
402 * channel A-C
403 * select 656/VIP DST for downstream Channel A - C */
404 tmp = cx_read(VID_CH_MODE_SEL);
405 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
406 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
407
408 /* enables 656 port I and J as output */
409 tmp = cx_read(CLK_RST);
410 /* use external ALT_PLL_REF pin as its reference clock instead */
411 tmp |= FLD_USE_ALT_PLL_REF;
412 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
413
414 msleep(100);
415 }
416
cx25821_sram_channel_setup(struct cx25821_dev * dev,const struct sram_channel * ch,unsigned int bpl,u32 risc)417 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
418 const struct sram_channel *ch,
419 unsigned int bpl, u32 risc)
420 {
421 unsigned int i, lines;
422 u32 cdt;
423
424 if (ch->cmds_start == 0) {
425 cx_write(ch->ptr1_reg, 0);
426 cx_write(ch->ptr2_reg, 0);
427 cx_write(ch->cnt2_reg, 0);
428 cx_write(ch->cnt1_reg, 0);
429 return 0;
430 }
431
432 bpl = (bpl + 7) & ~7; /* alignment */
433 cdt = ch->cdt;
434 lines = ch->fifo_size / bpl;
435
436 if (lines > 4)
437 lines = 4;
438
439 BUG_ON(lines < 2);
440
441 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
442 cx_write(8 + 4, 8);
443 cx_write(8 + 8, 0);
444
445 /* write CDT */
446 for (i = 0; i < lines; i++) {
447 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
448 cx_write(cdt + 16 * i + 4, 0);
449 cx_write(cdt + 16 * i + 8, 0);
450 cx_write(cdt + 16 * i + 12, 0);
451 }
452
453 /* init the first cdt buffer */
454 for (i = 0; i < 128; i++)
455 cx_write(ch->fifo_start + 4 * i, i);
456
457 /* write CMDS */
458 if (ch->jumponly)
459 cx_write(ch->cmds_start + 0, 8);
460 else
461 cx_write(ch->cmds_start + 0, risc);
462
463 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
464 cx_write(ch->cmds_start + 8, cdt);
465 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
466 cx_write(ch->cmds_start + 16, ch->ctrl_start);
467
468 if (ch->jumponly)
469 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
470 else
471 cx_write(ch->cmds_start + 20, 64 >> 2);
472
473 for (i = 24; i < 80; i += 4)
474 cx_write(ch->cmds_start + i, 0);
475
476 /* fill registers */
477 cx_write(ch->ptr1_reg, ch->fifo_start);
478 cx_write(ch->ptr2_reg, cdt);
479 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
480 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
481
482 return 0;
483 }
484
cx25821_sram_channel_setup_audio(struct cx25821_dev * dev,const struct sram_channel * ch,unsigned int bpl,u32 risc)485 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
486 const struct sram_channel *ch,
487 unsigned int bpl, u32 risc)
488 {
489 unsigned int i, lines;
490 u32 cdt;
491
492 if (ch->cmds_start == 0) {
493 cx_write(ch->ptr1_reg, 0);
494 cx_write(ch->ptr2_reg, 0);
495 cx_write(ch->cnt2_reg, 0);
496 cx_write(ch->cnt1_reg, 0);
497 return 0;
498 }
499
500 bpl = (bpl + 7) & ~7; /* alignment */
501 cdt = ch->cdt;
502 lines = ch->fifo_size / bpl;
503
504 if (lines > 3)
505 lines = 3; /* for AUDIO */
506
507 BUG_ON(lines < 2);
508
509 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
510 cx_write(8 + 4, 8);
511 cx_write(8 + 8, 0);
512
513 /* write CDT */
514 for (i = 0; i < lines; i++) {
515 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
516 cx_write(cdt + 16 * i + 4, 0);
517 cx_write(cdt + 16 * i + 8, 0);
518 cx_write(cdt + 16 * i + 12, 0);
519 }
520
521 /* write CMDS */
522 if (ch->jumponly)
523 cx_write(ch->cmds_start + 0, 8);
524 else
525 cx_write(ch->cmds_start + 0, risc);
526
527 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
528 cx_write(ch->cmds_start + 8, cdt);
529 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
530 cx_write(ch->cmds_start + 16, ch->ctrl_start);
531
532 /* IQ size */
533 if (ch->jumponly)
534 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
535 else
536 cx_write(ch->cmds_start + 20, 64 >> 2);
537
538 /* zero out */
539 for (i = 24; i < 80; i += 4)
540 cx_write(ch->cmds_start + i, 0);
541
542 /* fill registers */
543 cx_write(ch->ptr1_reg, ch->fifo_start);
544 cx_write(ch->ptr2_reg, cdt);
545 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
546 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
547
548 return 0;
549 }
550 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
551
cx25821_sram_channel_dump(struct cx25821_dev * dev,const struct sram_channel * ch)552 void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch)
553 {
554 static char *name[] = {
555 "init risc lo",
556 "init risc hi",
557 "cdt base",
558 "cdt size",
559 "iq base",
560 "iq size",
561 "risc pc lo",
562 "risc pc hi",
563 "iq wr ptr",
564 "iq rd ptr",
565 "cdt current",
566 "pci target lo",
567 "pci target hi",
568 "line / byte",
569 };
570 u32 risc;
571 unsigned int i, j, n;
572
573 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
574 for (i = 0; i < ARRAY_SIZE(name); i++)
575 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n",
576 i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
577
578 j = i * 4;
579 for (i = 0; i < 4;) {
580 risc = cx_read(ch->cmds_start + 4 * (i + 14));
581 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
582 i += cx25821_risc_decode(risc);
583 }
584
585 for (i = 0; i < (64 >> 2); i += n) {
586 risc = cx_read(ch->ctrl_start + 4 * i);
587 /* No consideration for bits 63-32 */
588
589 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
590 i * 4, ch->ctrl_start + 4 * i, i);
591 n = cx25821_risc_decode(risc);
592 for (j = 1; j < n; j++) {
593 risc = cx_read(ch->ctrl_start + 4 * (i + j));
594 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
595 4 * (i + j), i + j, risc, j);
596 }
597 }
598
599 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
600 ch->fifo_start, ch->fifo_start + ch->fifo_size);
601 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
602 ch->ctrl_start, ch->ctrl_start + 6 * 16);
603 pr_warn(" : ptr1_reg: 0x%08x\n",
604 cx_read(ch->ptr1_reg));
605 pr_warn(" : ptr2_reg: 0x%08x\n",
606 cx_read(ch->ptr2_reg));
607 pr_warn(" : cnt1_reg: 0x%08x\n",
608 cx_read(ch->cnt1_reg));
609 pr_warn(" : cnt2_reg: 0x%08x\n",
610 cx_read(ch->cnt2_reg));
611 }
612
cx25821_sram_channel_dump_audio(struct cx25821_dev * dev,const struct sram_channel * ch)613 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
614 const struct sram_channel *ch)
615 {
616 static const char * const name[] = {
617 "init risc lo",
618 "init risc hi",
619 "cdt base",
620 "cdt size",
621 "iq base",
622 "iq size",
623 "risc pc lo",
624 "risc pc hi",
625 "iq wr ptr",
626 "iq rd ptr",
627 "cdt current",
628 "pci target lo",
629 "pci target hi",
630 "line / byte",
631 };
632
633 u32 risc, value, tmp;
634 unsigned int i, j, n;
635
636 pr_info("\n%s: %s - dma Audio channel status dump\n",
637 dev->name, ch->name);
638
639 for (i = 0; i < ARRAY_SIZE(name); i++)
640 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n",
641 dev->name, i * 4, name[i],
642 cx_read(ch->cmds_start + 4 * i));
643
644 j = i * 4;
645 for (i = 0; i < 4;) {
646 risc = cx_read(ch->cmds_start + 4 * (i + 14));
647 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
648 i += cx25821_risc_decode(risc);
649 }
650
651 for (i = 0; i < (64 >> 2); i += n) {
652 risc = cx_read(ch->ctrl_start + 4 * i);
653 /* No consideration for bits 63-32 */
654
655 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
656 i * 4, ch->ctrl_start + 4 * i, i);
657 n = cx25821_risc_decode(risc);
658
659 for (j = 1; j < n; j++) {
660 risc = cx_read(ch->ctrl_start + 4 * (i + j));
661 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
662 4 * (i + j), i + j, risc, j);
663 }
664 }
665
666 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
667 ch->fifo_start, ch->fifo_start + ch->fifo_size);
668 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
669 ch->ctrl_start, ch->ctrl_start + 6 * 16);
670 pr_warn(" : ptr1_reg: 0x%08x\n",
671 cx_read(ch->ptr1_reg));
672 pr_warn(" : ptr2_reg: 0x%08x\n",
673 cx_read(ch->ptr2_reg));
674 pr_warn(" : cnt1_reg: 0x%08x\n",
675 cx_read(ch->cnt1_reg));
676 pr_warn(" : cnt2_reg: 0x%08x\n",
677 cx_read(ch->cnt2_reg));
678
679 for (i = 0; i < 4; i++) {
680 risc = cx_read(ch->cmds_start + 56 + (i * 4));
681 pr_warn("instruction %d = 0x%x\n", i, risc);
682 }
683
684 /* read data from the first cdt buffer */
685 risc = cx_read(AUD_A_CDT);
686 pr_warn("\nread cdt loc=0x%x\n", risc);
687 for (i = 0; i < 8; i++) {
688 n = cx_read(risc + i * 4);
689 pr_cont("0x%x ", n);
690 }
691 pr_cont("\n\n");
692
693 value = cx_read(CLK_RST);
694 CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
695
696 value = cx_read(PLL_A_POST_STAT_BIST);
697 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
698 value = cx_read(PLL_A_INT_FRAC);
699 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
700
701 value = cx_read(PLL_B_POST_STAT_BIST);
702 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
703 value = cx_read(PLL_B_INT_FRAC);
704 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
705
706 value = cx_read(PLL_C_POST_STAT_BIST);
707 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
708 value = cx_read(PLL_C_INT_FRAC);
709 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
710
711 value = cx_read(PLL_D_POST_STAT_BIST);
712 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
713 value = cx_read(PLL_D_INT_FRAC);
714 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
715
716 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
717 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
718 }
719 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
720
cx25821_shutdown(struct cx25821_dev * dev)721 static void cx25821_shutdown(struct cx25821_dev *dev)
722 {
723 int i;
724
725 /* disable RISC controller */
726 cx_write(DEV_CNTRL2, 0);
727
728 /* Disable Video A/B activity */
729 for (i = 0; i < VID_CHANNEL_NUM; i++) {
730 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
731 cx_write(dev->channels[i].sram_channels->int_msk, 0);
732 }
733
734 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
735 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
736 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
737 cx_write(dev->channels[i].sram_channels->int_msk, 0);
738 }
739
740 /* Disable Audio activity */
741 cx_write(AUD_INT_DMA_CTL, 0);
742
743 /* Disable Serial port */
744 cx_write(UART_CTL, 0);
745
746 /* Disable Interrupts */
747 cx_write(PCI_INT_MSK, 0);
748 cx_write(AUD_A_INT_MSK, 0);
749 }
750
cx25821_set_pixel_format(struct cx25821_dev * dev,int channel_select,u32 format)751 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
752 u32 format)
753 {
754 if (channel_select <= 7 && channel_select >= 0) {
755 cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
756 format);
757 }
758 dev->channels[channel_select].pixel_formats = format;
759 }
760
cx25821_set_vip_mode(struct cx25821_dev * dev,const struct sram_channel * ch)761 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
762 const struct sram_channel *ch)
763 {
764 cx_write(ch->pix_frmt, PIXEL_FRMT_422);
765 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
766 }
767
cx25821_initialize(struct cx25821_dev * dev)768 static void cx25821_initialize(struct cx25821_dev *dev)
769 {
770 int i;
771
772 dprintk(1, "%s()\n", __func__);
773
774 cx25821_shutdown(dev);
775 cx_write(PCI_INT_STAT, 0xffffffff);
776
777 for (i = 0; i < VID_CHANNEL_NUM; i++)
778 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
779
780 cx_write(AUD_A_INT_STAT, 0xffffffff);
781 cx_write(AUD_B_INT_STAT, 0xffffffff);
782 cx_write(AUD_C_INT_STAT, 0xffffffff);
783 cx_write(AUD_D_INT_STAT, 0xffffffff);
784 cx_write(AUD_E_INT_STAT, 0xffffffff);
785
786 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
787 cx_write(PAD_CTRL, 0x12); /* for I2C */
788 cx25821_registers_init(dev); /* init Pecos registers */
789 msleep(100);
790
791 for (i = 0; i < VID_CHANNEL_NUM; i++) {
792 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
793 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
794 1440, 0);
795 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
796 dev->channels[i].use_cif_resolution = 0;
797 }
798
799 /* Probably only affect Downstream */
800 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
801 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
802 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
803 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
804 }
805
806 cx25821_sram_channel_setup_audio(dev,
807 dev->channels[SRAM_CH08].sram_channels, 128, 0);
808
809 cx25821_gpio_init(dev);
810 }
811
cx25821_get_resources(struct cx25821_dev * dev)812 static int cx25821_get_resources(struct cx25821_dev *dev)
813 {
814 if (request_mem_region(pci_resource_start(dev->pci, 0),
815 pci_resource_len(dev->pci, 0), dev->name))
816 return 0;
817
818 pr_err("%s: can't get MMIO memory @ 0x%llx\n",
819 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
820
821 return -EBUSY;
822 }
823
cx25821_dev_checkrevision(struct cx25821_dev * dev)824 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
825 {
826 dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
827
828 pr_info("Hardware revision = 0x%02x\n", dev->hwrevision);
829 }
830
cx25821_iounmap(struct cx25821_dev * dev)831 static void cx25821_iounmap(struct cx25821_dev *dev)
832 {
833 if (dev == NULL)
834 return;
835
836 /* Releasing IO memory */
837 if (dev->lmmio != NULL) {
838 iounmap(dev->lmmio);
839 dev->lmmio = NULL;
840 }
841 }
842
cx25821_dev_setup(struct cx25821_dev * dev)843 static int cx25821_dev_setup(struct cx25821_dev *dev)
844 {
845 static unsigned int cx25821_devcount;
846 int i;
847
848 mutex_init(&dev->lock);
849
850 dev->nr = ++cx25821_devcount;
851 sprintf(dev->name, "cx25821[%d]", dev->nr);
852
853 if (dev->nr >= ARRAY_SIZE(card)) {
854 CX25821_INFO("dev->nr >= %zd", ARRAY_SIZE(card));
855 return -ENODEV;
856 }
857 if (dev->pci->device != 0x8210) {
858 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
859 __func__, dev->pci->device);
860 return -ENODEV;
861 }
862 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
863
864 /* Apply a sensible clock frequency for the PCIe bridge */
865 dev->clk_freq = 28000000;
866 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) {
867 dev->channels[i].dev = dev;
868 dev->channels[i].id = i;
869 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
870 }
871
872 /* board config */
873 dev->board = 1; /* card[dev->nr]; */
874 dev->_max_num_decoders = MAX_DECODERS;
875
876 dev->pci_bus = dev->pci->bus->number;
877 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
878 dev->pci_irqmask = 0x001f00;
879
880 /* External Master 1 Bus */
881 dev->i2c_bus[0].nr = 0;
882 dev->i2c_bus[0].dev = dev;
883 dev->i2c_bus[0].reg_stat = I2C1_STAT;
884 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
885 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
886 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
887 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
888 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
889
890 if (cx25821_get_resources(dev) < 0) {
891 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
892 dev->name, dev->pci->subsystem_vendor,
893 dev->pci->subsystem_device);
894
895 cx25821_devcount--;
896 return -EBUSY;
897 }
898
899 /* PCIe stuff */
900 dev->base_io_addr = pci_resource_start(dev->pci, 0);
901
902 if (!dev->base_io_addr) {
903 CX25821_ERR("No PCI Memory resources, exiting!\n");
904 return -ENODEV;
905 }
906
907 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
908
909 if (!dev->lmmio) {
910 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
911 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
912 cx25821_iounmap(dev);
913 return -ENOMEM;
914 }
915
916 dev->bmmio = (u8 __iomem *) dev->lmmio;
917
918 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
919 dev->name, dev->pci->subsystem_vendor,
920 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
921 dev->board, card[dev->nr] == dev->board ?
922 "insmod option" : "autodetected");
923
924 /* init hardware */
925 cx25821_initialize(dev);
926
927 cx25821_i2c_register(&dev->i2c_bus[0]);
928 /* cx25821_i2c_register(&dev->i2c_bus[1]);
929 * cx25821_i2c_register(&dev->i2c_bus[2]); */
930
931 if (medusa_video_init(dev) < 0)
932 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
933
934 cx25821_video_register(dev);
935
936 cx25821_dev_checkrevision(dev);
937 return 0;
938 }
939
cx25821_dev_unregister(struct cx25821_dev * dev)940 void cx25821_dev_unregister(struct cx25821_dev *dev)
941 {
942 int i;
943
944 if (!dev->base_io_addr)
945 return;
946
947 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
948
949 for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; i++) {
950 if (i == SRAM_CH08) /* audio channel */
951 continue;
952 /*
953 * TODO: enable when video output is properly
954 * supported.
955 if (i == SRAM_CH09 || i == SRAM_CH10)
956 cx25821_free_mem_upstream(&dev->channels[i]);
957 */
958 cx25821_video_unregister(dev, i);
959 }
960
961 cx25821_i2c_unregister(&dev->i2c_bus[0]);
962 cx25821_iounmap(dev);
963 }
964 EXPORT_SYMBOL(cx25821_dev_unregister);
965
cx25821_riscmem_alloc(struct pci_dev * pci,struct cx25821_riscmem * risc,unsigned int size)966 int cx25821_riscmem_alloc(struct pci_dev *pci,
967 struct cx25821_riscmem *risc,
968 unsigned int size)
969 {
970 __le32 *cpu;
971 dma_addr_t dma = 0;
972
973 if (risc->cpu && risc->size < size) {
974 dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma);
975 risc->cpu = NULL;
976 }
977 if (NULL == risc->cpu) {
978 cpu = dma_alloc_coherent(&pci->dev, size, &dma, GFP_KERNEL);
979 if (NULL == cpu)
980 return -ENOMEM;
981 risc->cpu = cpu;
982 risc->dma = dma;
983 risc->size = size;
984 }
985 return 0;
986 }
987 EXPORT_SYMBOL(cx25821_riscmem_alloc);
988
cx25821_risc_field(__le32 * rp,struct scatterlist * sglist,unsigned int offset,u32 sync_line,unsigned int bpl,unsigned int padding,unsigned int lines,bool jump)989 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
990 unsigned int offset, u32 sync_line,
991 unsigned int bpl, unsigned int padding,
992 unsigned int lines, bool jump)
993 {
994 struct scatterlist *sg;
995 unsigned int line, todo;
996
997 if (jump) {
998 *(rp++) = cpu_to_le32(RISC_JUMP);
999 *(rp++) = cpu_to_le32(0);
1000 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1001 }
1002
1003 /* sync instruction */
1004 if (sync_line != NO_SYNC_LINE)
1005 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1006
1007 /* scan lines */
1008 sg = sglist;
1009 for (line = 0; line < lines; line++) {
1010 while (offset && offset >= sg_dma_len(sg)) {
1011 offset -= sg_dma_len(sg);
1012 sg = sg_next(sg);
1013 }
1014 if (bpl <= sg_dma_len(sg) - offset) {
1015 /* fits into current chunk */
1016 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
1017 bpl);
1018 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1019 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1020 offset += bpl;
1021 } else {
1022 /* scanline needs to be split */
1023 todo = bpl;
1024 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1025 (sg_dma_len(sg) - offset));
1026 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1027 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1028 todo -= (sg_dma_len(sg) - offset);
1029 offset = 0;
1030 sg = sg_next(sg);
1031 while (todo > sg_dma_len(sg)) {
1032 *(rp++) = cpu_to_le32(RISC_WRITE |
1033 sg_dma_len(sg));
1034 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1035 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1036 todo -= sg_dma_len(sg);
1037 sg = sg_next(sg);
1038 }
1039 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1040 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1041 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1042 offset += todo;
1043 }
1044
1045 offset += padding;
1046 }
1047
1048 return rp;
1049 }
1050
cx25821_risc_buffer(struct pci_dev * pci,struct cx25821_riscmem * risc,struct scatterlist * sglist,unsigned int top_offset,unsigned int bottom_offset,unsigned int bpl,unsigned int padding,unsigned int lines)1051 int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
1052 struct scatterlist *sglist, unsigned int top_offset,
1053 unsigned int bottom_offset, unsigned int bpl,
1054 unsigned int padding, unsigned int lines)
1055 {
1056 u32 instructions;
1057 u32 fields;
1058 __le32 *rp;
1059 int rc;
1060
1061 fields = 0;
1062 if (UNSET != top_offset)
1063 fields++;
1064 if (UNSET != bottom_offset)
1065 fields++;
1066
1067 /* estimate risc mem: worst case is one write per page border +
1068 one write per scan line + syncs + jump (all 3 dwords). Padding
1069 can cause next bpl to start close to a page border. First DMA
1070 region may be smaller than PAGE_SIZE */
1071 /* write and jump need and extra dword */
1072 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
1073 lines);
1074 instructions += 5;
1075 rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1076
1077 if (rc < 0)
1078 return rc;
1079
1080 /* write risc instructions */
1081 rp = risc->cpu;
1082
1083 if (UNSET != top_offset) {
1084 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1085 lines, true);
1086 }
1087
1088 if (UNSET != bottom_offset) {
1089 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1090 padding, lines, UNSET == top_offset);
1091 }
1092
1093 /* save pointer to jmp instruction address */
1094 risc->jmp = rp;
1095 BUG_ON((risc->jmp - risc->cpu + 3) * sizeof(*risc->cpu) > risc->size);
1096
1097 return 0;
1098 }
1099
cx25821_risc_field_audio(__le32 * rp,struct scatterlist * sglist,unsigned int offset,u32 sync_line,unsigned int bpl,unsigned int padding,unsigned int lines,unsigned int lpi)1100 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1101 unsigned int offset, u32 sync_line,
1102 unsigned int bpl, unsigned int padding,
1103 unsigned int lines, unsigned int lpi)
1104 {
1105 struct scatterlist *sg;
1106 unsigned int line, todo, sol;
1107
1108 /* sync instruction */
1109 if (sync_line != NO_SYNC_LINE)
1110 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1111
1112 /* scan lines */
1113 sg = sglist;
1114 for (line = 0; line < lines; line++) {
1115 while (offset && offset >= sg_dma_len(sg)) {
1116 offset -= sg_dma_len(sg);
1117 sg = sg_next(sg);
1118 }
1119
1120 if (lpi && line > 0 && !(line % lpi))
1121 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1122 else
1123 sol = RISC_SOL;
1124
1125 if (bpl <= sg_dma_len(sg) - offset) {
1126 /* fits into current chunk */
1127 *(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
1128 bpl);
1129 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1130 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1131 offset += bpl;
1132 } else {
1133 /* scanline needs to be split */
1134 todo = bpl;
1135 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1136 (sg_dma_len(sg) - offset));
1137 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1138 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1139 todo -= (sg_dma_len(sg) - offset);
1140 offset = 0;
1141 sg = sg_next(sg);
1142 while (todo > sg_dma_len(sg)) {
1143 *(rp++) = cpu_to_le32(RISC_WRITE |
1144 sg_dma_len(sg));
1145 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1146 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1147 todo -= sg_dma_len(sg);
1148 sg = sg_next(sg);
1149 }
1150 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1151 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1152 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1153 offset += todo;
1154 }
1155 offset += padding;
1156 }
1157
1158 return rp;
1159 }
1160
cx25821_risc_databuffer_audio(struct pci_dev * pci,struct cx25821_riscmem * risc,struct scatterlist * sglist,unsigned int bpl,unsigned int lines,unsigned int lpi)1161 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1162 struct cx25821_riscmem *risc,
1163 struct scatterlist *sglist,
1164 unsigned int bpl,
1165 unsigned int lines, unsigned int lpi)
1166 {
1167 u32 instructions;
1168 __le32 *rp;
1169 int rc;
1170
1171 /* estimate risc mem: worst case is one write per page border +
1172 one write per scan line + syncs + jump (all 2 dwords). Here
1173 there is no padding and no sync. First DMA region may be smaller
1174 than PAGE_SIZE */
1175 /* Jump and write need an extra dword */
1176 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1177 instructions += 1;
1178
1179 rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1180 if (rc < 0)
1181 return rc;
1182
1183 /* write risc instructions */
1184 rp = risc->cpu;
1185 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1186 lines, lpi);
1187
1188 /* save pointer to jmp instruction address */
1189 risc->jmp = rp;
1190 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1191 return 0;
1192 }
1193 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1194
cx25821_free_buffer(struct cx25821_dev * dev,struct cx25821_buffer * buf)1195 void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf)
1196 {
1197 if (WARN_ON(buf->risc.size == 0))
1198 return;
1199 dma_free_coherent(&dev->pci->dev, buf->risc.size, buf->risc.cpu,
1200 buf->risc.dma);
1201 memset(&buf->risc, 0, sizeof(buf->risc));
1202 }
1203
cx25821_irq(int irq,void * dev_id)1204 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1205 {
1206 struct cx25821_dev *dev = dev_id;
1207 u32 pci_status;
1208 u32 vid_status;
1209 int i, handled = 0;
1210 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1211
1212 pci_status = cx_read(PCI_INT_STAT);
1213
1214 if (pci_status == 0)
1215 goto out;
1216
1217 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1218 if (pci_status & mask[i]) {
1219 vid_status = cx_read(dev->channels[i].
1220 sram_channels->int_stat);
1221
1222 if (vid_status)
1223 handled += cx25821_video_irq(dev, i,
1224 vid_status);
1225
1226 cx_write(PCI_INT_STAT, mask[i]);
1227 }
1228 }
1229
1230 out:
1231 return IRQ_RETVAL(handled);
1232 }
1233
cx25821_print_irqbits(char * name,char * tag,char ** strings,int len,u32 bits,u32 mask)1234 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1235 int len, u32 bits, u32 mask)
1236 {
1237 unsigned int i;
1238
1239 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1240
1241 for (i = 0; i < len; i++) {
1242 if (!(bits & (1 << i)))
1243 continue;
1244 if (strings[i])
1245 pr_cont(" %s", strings[i]);
1246 else
1247 pr_cont(" %d", i);
1248 if (!(mask & (1 << i)))
1249 continue;
1250 pr_cont("*");
1251 }
1252 pr_cont("\n");
1253 }
1254 EXPORT_SYMBOL(cx25821_print_irqbits);
1255
cx25821_dev_get(struct pci_dev * pci)1256 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1257 {
1258 struct cx25821_dev *dev = pci_get_drvdata(pci);
1259 return dev;
1260 }
1261 EXPORT_SYMBOL(cx25821_dev_get);
1262
cx25821_initdev(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)1263 static int cx25821_initdev(struct pci_dev *pci_dev,
1264 const struct pci_device_id *pci_id)
1265 {
1266 struct cx25821_dev *dev;
1267 int err = 0;
1268
1269 dev = kzalloc_obj(*dev);
1270 if (NULL == dev)
1271 return -ENOMEM;
1272
1273 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1274 if (err < 0)
1275 goto fail_free;
1276
1277 /* pci init */
1278 dev->pci = pci_dev;
1279 if (pci_enable_device(pci_dev)) {
1280 err = -EIO;
1281
1282 pr_info("pci enable failed!\n");
1283
1284 goto fail_unregister_device;
1285 }
1286
1287 err = cx25821_dev_setup(dev);
1288 if (err)
1289 goto fail_unregister_pci;
1290
1291 /* print pci info */
1292 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1293 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1294 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1295 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1296 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1297
1298 pci_set_master(pci_dev);
1299 err = dma_set_mask(&pci_dev->dev, 0xffffffff);
1300 if (err) {
1301 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1302 err = -EIO;
1303 goto fail_irq;
1304 }
1305
1306 err = request_irq(pci_dev->irq, cx25821_irq,
1307 IRQF_SHARED, dev->name, dev);
1308
1309 if (err < 0) {
1310 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1311 goto fail_irq;
1312 }
1313
1314 return 0;
1315
1316 fail_irq:
1317 pr_info("cx25821_initdev() can't get IRQ !\n");
1318 cx25821_dev_unregister(dev);
1319
1320 fail_unregister_pci:
1321 pci_disable_device(pci_dev);
1322 fail_unregister_device:
1323 v4l2_device_unregister(&dev->v4l2_dev);
1324
1325 fail_free:
1326 kfree(dev);
1327 return err;
1328 }
1329
cx25821_finidev(struct pci_dev * pci_dev)1330 static void cx25821_finidev(struct pci_dev *pci_dev)
1331 {
1332 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1333 struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1334
1335 cx25821_shutdown(dev);
1336
1337 /* unregister stuff */
1338 if (pci_dev->irq)
1339 free_irq(pci_dev->irq, dev);
1340 pci_disable_device(pci_dev);
1341
1342 cx25821_dev_unregister(dev);
1343 v4l2_device_unregister(v4l2_dev);
1344 kfree(dev);
1345 }
1346
1347 static const struct pci_device_id cx25821_pci_tbl[] = {
1348 {
1349 /* CX25821 Athena */
1350 .vendor = 0x14f1,
1351 .device = 0x8210,
1352 .subvendor = 0x14f1,
1353 .subdevice = 0x0920,
1354 }, {
1355 /* CX25821 No Brand */
1356 .vendor = 0x14f1,
1357 .device = 0x8210,
1358 .subvendor = 0x0000,
1359 .subdevice = 0x0000,
1360 }, {
1361 /* --- end of list --- */
1362 }
1363 };
1364
1365 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1366
1367 static struct pci_driver cx25821_pci_driver = {
1368 .name = "cx25821",
1369 .id_table = cx25821_pci_tbl,
1370 .probe = cx25821_initdev,
1371 .remove = cx25821_finidev,
1372 };
1373
cx25821_init(void)1374 static int __init cx25821_init(void)
1375 {
1376 pr_info("driver loaded\n");
1377 return pci_register_driver(&cx25821_pci_driver);
1378 }
1379
cx25821_fini(void)1380 static void __exit cx25821_fini(void)
1381 {
1382 pci_unregister_driver(&cx25821_pci_driver);
1383 }
1384
1385 module_init(cx25821_init);
1386 module_exit(cx25821_fini);
1387