xref: /linux/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h (revision a976c2951d8f376112361830aa7762beff83a205)
1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2017 Cavium, Inc.
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_PCIERCX_DEFS_H__
29 #define __CVMX_PCIERCX_DEFS_H__
30 
31 #include <uapi/asm/bitfield.h>
32 
33 #define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
34 #define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
35 #define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
36 #define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
37 #define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
38 #define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
39 #define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
40 #define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
41 #define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
42 #define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
43 #define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
44 #define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
45 #define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
46 #define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
47 #define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
48 #define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
49 #define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
50 #define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
51 #define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
52 #define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
53 
54 union cvmx_pciercx_cfg001 {
55 	uint32_t u32;
56 	struct cvmx_pciercx_cfg001_s {
57 		__BITFIELD_FIELD(uint32_t dpe:1,
58 		__BITFIELD_FIELD(uint32_t sse:1,
59 		__BITFIELD_FIELD(uint32_t rma:1,
60 		__BITFIELD_FIELD(uint32_t rta:1,
61 		__BITFIELD_FIELD(uint32_t sta:1,
62 		__BITFIELD_FIELD(uint32_t devt:2,
63 		__BITFIELD_FIELD(uint32_t mdpe:1,
64 		__BITFIELD_FIELD(uint32_t fbb:1,
65 		__BITFIELD_FIELD(uint32_t reserved_22_22:1,
66 		__BITFIELD_FIELD(uint32_t m66:1,
67 		__BITFIELD_FIELD(uint32_t cl:1,
68 		__BITFIELD_FIELD(uint32_t i_stat:1,
69 		__BITFIELD_FIELD(uint32_t reserved_11_18:8,
70 		__BITFIELD_FIELD(uint32_t i_dis:1,
71 		__BITFIELD_FIELD(uint32_t fbbe:1,
72 		__BITFIELD_FIELD(uint32_t see:1,
73 		__BITFIELD_FIELD(uint32_t ids_wcc:1,
74 		__BITFIELD_FIELD(uint32_t per:1,
75 		__BITFIELD_FIELD(uint32_t vps:1,
76 		__BITFIELD_FIELD(uint32_t mwice:1,
77 		__BITFIELD_FIELD(uint32_t scse:1,
78 		__BITFIELD_FIELD(uint32_t me:1,
79 		__BITFIELD_FIELD(uint32_t msae:1,
80 		__BITFIELD_FIELD(uint32_t isae:1,
81 		;))))))))))))))))))))))))
82 	} s;
83 };
84 
85 union cvmx_pciercx_cfg006 {
86 	uint32_t u32;
87 	struct cvmx_pciercx_cfg006_s {
88 		__BITFIELD_FIELD(uint32_t slt:8,
89 		__BITFIELD_FIELD(uint32_t subbnum:8,
90 		__BITFIELD_FIELD(uint32_t sbnum:8,
91 		__BITFIELD_FIELD(uint32_t pbnum:8,
92 		;))))
93 	} s;
94 };
95 
96 union cvmx_pciercx_cfg008 {
97 	uint32_t u32;
98 	struct cvmx_pciercx_cfg008_s {
99 		__BITFIELD_FIELD(uint32_t ml_addr:12,
100 		__BITFIELD_FIELD(uint32_t reserved_16_19:4,
101 		__BITFIELD_FIELD(uint32_t mb_addr:12,
102 		__BITFIELD_FIELD(uint32_t reserved_0_3:4,
103 		;))))
104 	} s;
105 };
106 
107 union cvmx_pciercx_cfg009 {
108 	uint32_t u32;
109 	struct cvmx_pciercx_cfg009_s {
110 		__BITFIELD_FIELD(uint32_t lmem_limit:12,
111 		__BITFIELD_FIELD(uint32_t reserved_17_19:3,
112 		__BITFIELD_FIELD(uint32_t mem64b:1,
113 		__BITFIELD_FIELD(uint32_t lmem_base:12,
114 		__BITFIELD_FIELD(uint32_t reserved_1_3:3,
115 		__BITFIELD_FIELD(uint32_t mem64a:1,
116 		;))))))
117 	} s;
118 };
119 
120 union cvmx_pciercx_cfg010 {
121 	uint32_t u32;
122 	struct cvmx_pciercx_cfg010_s {
123 		uint32_t umem_base;
124 	} s;
125 };
126 
127 union cvmx_pciercx_cfg011 {
128 	uint32_t u32;
129 	struct cvmx_pciercx_cfg011_s {
130 		uint32_t umem_limit;
131 	} s;
132 };
133 
134 union cvmx_pciercx_cfg030 {
135 	uint32_t u32;
136 	struct cvmx_pciercx_cfg030_s {
137 		__BITFIELD_FIELD(uint32_t reserved_22_31:10,
138 		__BITFIELD_FIELD(uint32_t tp:1,
139 		__BITFIELD_FIELD(uint32_t ap_d:1,
140 		__BITFIELD_FIELD(uint32_t ur_d:1,
141 		__BITFIELD_FIELD(uint32_t fe_d:1,
142 		__BITFIELD_FIELD(uint32_t nfe_d:1,
143 		__BITFIELD_FIELD(uint32_t ce_d:1,
144 		__BITFIELD_FIELD(uint32_t reserved_15_15:1,
145 		__BITFIELD_FIELD(uint32_t mrrs:3,
146 		__BITFIELD_FIELD(uint32_t ns_en:1,
147 		__BITFIELD_FIELD(uint32_t ap_en:1,
148 		__BITFIELD_FIELD(uint32_t pf_en:1,
149 		__BITFIELD_FIELD(uint32_t etf_en:1,
150 		__BITFIELD_FIELD(uint32_t mps:3,
151 		__BITFIELD_FIELD(uint32_t ro_en:1,
152 		__BITFIELD_FIELD(uint32_t ur_en:1,
153 		__BITFIELD_FIELD(uint32_t fe_en:1,
154 		__BITFIELD_FIELD(uint32_t nfe_en:1,
155 		__BITFIELD_FIELD(uint32_t ce_en:1,
156 		;)))))))))))))))))))
157 	} s;
158 };
159 
160 union cvmx_pciercx_cfg031 {
161 	uint32_t u32;
162 	struct cvmx_pciercx_cfg031_s {
163 		__BITFIELD_FIELD(uint32_t pnum:8,
164 		__BITFIELD_FIELD(uint32_t reserved_23_23:1,
165 		__BITFIELD_FIELD(uint32_t aspm:1,
166 		__BITFIELD_FIELD(uint32_t lbnc:1,
167 		__BITFIELD_FIELD(uint32_t dllarc:1,
168 		__BITFIELD_FIELD(uint32_t sderc:1,
169 		__BITFIELD_FIELD(uint32_t cpm:1,
170 		__BITFIELD_FIELD(uint32_t l1el:3,
171 		__BITFIELD_FIELD(uint32_t l0el:3,
172 		__BITFIELD_FIELD(uint32_t aslpms:2,
173 		__BITFIELD_FIELD(uint32_t mlw:6,
174 		__BITFIELD_FIELD(uint32_t mls:4,
175 		;))))))))))))
176 	} s;
177 };
178 
179 union cvmx_pciercx_cfg032 {
180 	uint32_t u32;
181 	struct cvmx_pciercx_cfg032_s {
182 		__BITFIELD_FIELD(uint32_t lab:1,
183 		__BITFIELD_FIELD(uint32_t lbm:1,
184 		__BITFIELD_FIELD(uint32_t dlla:1,
185 		__BITFIELD_FIELD(uint32_t scc:1,
186 		__BITFIELD_FIELD(uint32_t lt:1,
187 		__BITFIELD_FIELD(uint32_t reserved_26_26:1,
188 		__BITFIELD_FIELD(uint32_t nlw:6,
189 		__BITFIELD_FIELD(uint32_t ls:4,
190 		__BITFIELD_FIELD(uint32_t reserved_12_15:4,
191 		__BITFIELD_FIELD(uint32_t lab_int_enb:1,
192 		__BITFIELD_FIELD(uint32_t lbm_int_enb:1,
193 		__BITFIELD_FIELD(uint32_t hawd:1,
194 		__BITFIELD_FIELD(uint32_t ecpm:1,
195 		__BITFIELD_FIELD(uint32_t es:1,
196 		__BITFIELD_FIELD(uint32_t ccc:1,
197 		__BITFIELD_FIELD(uint32_t rl:1,
198 		__BITFIELD_FIELD(uint32_t ld:1,
199 		__BITFIELD_FIELD(uint32_t rcb:1,
200 		__BITFIELD_FIELD(uint32_t reserved_2_2:1,
201 		__BITFIELD_FIELD(uint32_t aslpc:2,
202 		;))))))))))))))))))))
203 	} s;
204 };
205 
206 union cvmx_pciercx_cfg034 {
207 	uint32_t u32;
208 	struct cvmx_pciercx_cfg034_s {
209 		__BITFIELD_FIELD(uint32_t reserved_25_31:7,
210 		__BITFIELD_FIELD(uint32_t dlls_c:1,
211 		__BITFIELD_FIELD(uint32_t emis:1,
212 		__BITFIELD_FIELD(uint32_t pds:1,
213 		__BITFIELD_FIELD(uint32_t mrlss:1,
214 		__BITFIELD_FIELD(uint32_t ccint_d:1,
215 		__BITFIELD_FIELD(uint32_t pd_c:1,
216 		__BITFIELD_FIELD(uint32_t mrls_c:1,
217 		__BITFIELD_FIELD(uint32_t pf_d:1,
218 		__BITFIELD_FIELD(uint32_t abp_d:1,
219 		__BITFIELD_FIELD(uint32_t reserved_13_15:3,
220 		__BITFIELD_FIELD(uint32_t dlls_en:1,
221 		__BITFIELD_FIELD(uint32_t emic:1,
222 		__BITFIELD_FIELD(uint32_t pcc:1,
223 		__BITFIELD_FIELD(uint32_t pic:1,
224 		__BITFIELD_FIELD(uint32_t aic:1,
225 		__BITFIELD_FIELD(uint32_t hpint_en:1,
226 		__BITFIELD_FIELD(uint32_t ccint_en:1,
227 		__BITFIELD_FIELD(uint32_t pd_en:1,
228 		__BITFIELD_FIELD(uint32_t mrls_en:1,
229 		__BITFIELD_FIELD(uint32_t pf_en:1,
230 		__BITFIELD_FIELD(uint32_t abp_en:1,
231 		;))))))))))))))))))))))
232 	} s;
233 };
234 
235 union cvmx_pciercx_cfg035 {
236 	uint32_t u32;
237 	struct cvmx_pciercx_cfg035_s {
238 		__BITFIELD_FIELD(uint32_t reserved_17_31:15,
239 		__BITFIELD_FIELD(uint32_t crssv:1,
240 		__BITFIELD_FIELD(uint32_t reserved_5_15:11,
241 		__BITFIELD_FIELD(uint32_t crssve:1,
242 		__BITFIELD_FIELD(uint32_t pmeie:1,
243 		__BITFIELD_FIELD(uint32_t sefee:1,
244 		__BITFIELD_FIELD(uint32_t senfee:1,
245 		__BITFIELD_FIELD(uint32_t secee:1,
246 		;))))))))
247 	} s;
248 };
249 
250 union cvmx_pciercx_cfg040 {
251 	uint32_t u32;
252 	struct cvmx_pciercx_cfg040_s {
253 		__BITFIELD_FIELD(uint32_t reserved_22_31:10,
254 		__BITFIELD_FIELD(uint32_t ler:1,
255 		__BITFIELD_FIELD(uint32_t ep3s:1,
256 		__BITFIELD_FIELD(uint32_t ep2s:1,
257 		__BITFIELD_FIELD(uint32_t ep1s:1,
258 		__BITFIELD_FIELD(uint32_t eqc:1,
259 		__BITFIELD_FIELD(uint32_t cdl:1,
260 		__BITFIELD_FIELD(uint32_t cde:4,
261 		__BITFIELD_FIELD(uint32_t csos:1,
262 		__BITFIELD_FIELD(uint32_t emc:1,
263 		__BITFIELD_FIELD(uint32_t tm:3,
264 		__BITFIELD_FIELD(uint32_t sde:1,
265 		__BITFIELD_FIELD(uint32_t hasd:1,
266 		__BITFIELD_FIELD(uint32_t ec:1,
267 		__BITFIELD_FIELD(uint32_t tls:4,
268 		;)))))))))))))))
269 	} s;
270 };
271 
272 union cvmx_pciercx_cfg070 {
273 	uint32_t u32;
274 	struct cvmx_pciercx_cfg070_s {
275 		__BITFIELD_FIELD(uint32_t reserved_12_31:20,
276 		__BITFIELD_FIELD(uint32_t tplp:1,
277 		__BITFIELD_FIELD(uint32_t reserved_9_10:2,
278 		__BITFIELD_FIELD(uint32_t ce:1,
279 		__BITFIELD_FIELD(uint32_t cc:1,
280 		__BITFIELD_FIELD(uint32_t ge:1,
281 		__BITFIELD_FIELD(uint32_t gc:1,
282 		__BITFIELD_FIELD(uint32_t fep:5,
283 		;))))))))
284 	} s;
285 };
286 
287 union cvmx_pciercx_cfg075 {
288 	uint32_t u32;
289 	struct cvmx_pciercx_cfg075_s {
290 		__BITFIELD_FIELD(uint32_t reserved_3_31:29,
291 		__BITFIELD_FIELD(uint32_t fere:1,
292 		__BITFIELD_FIELD(uint32_t nfere:1,
293 		__BITFIELD_FIELD(uint32_t cere:1,
294 		;))))
295 	} s;
296 };
297 
298 union cvmx_pciercx_cfg448 {
299 	uint32_t u32;
300 	struct cvmx_pciercx_cfg448_s {
301 		__BITFIELD_FIELD(uint32_t rtl:16,
302 		__BITFIELD_FIELD(uint32_t rtltl:16,
303 		;))
304 	} s;
305 };
306 
307 union cvmx_pciercx_cfg452 {
308 	uint32_t u32;
309 	struct cvmx_pciercx_cfg452_s {
310 		__BITFIELD_FIELD(uint32_t reserved_26_31:6,
311 		__BITFIELD_FIELD(uint32_t eccrc:1,
312 		__BITFIELD_FIELD(uint32_t reserved_22_24:3,
313 		__BITFIELD_FIELD(uint32_t lme:6,
314 		__BITFIELD_FIELD(uint32_t reserved_12_15:4,
315 		__BITFIELD_FIELD(uint32_t link_rate:4,
316 		__BITFIELD_FIELD(uint32_t flm:1,
317 		__BITFIELD_FIELD(uint32_t reserved_6_6:1,
318 		__BITFIELD_FIELD(uint32_t dllle:1,
319 		__BITFIELD_FIELD(uint32_t reserved_4_4:1,
320 		__BITFIELD_FIELD(uint32_t ra:1,
321 		__BITFIELD_FIELD(uint32_t le:1,
322 		__BITFIELD_FIELD(uint32_t sd:1,
323 		__BITFIELD_FIELD(uint32_t omr:1,
324 		;))))))))))))))
325 	} s;
326 };
327 
328 union cvmx_pciercx_cfg455 {
329 	uint32_t u32;
330 	struct cvmx_pciercx_cfg455_s {
331 		__BITFIELD_FIELD(uint32_t m_cfg0_filt:1,
332 		__BITFIELD_FIELD(uint32_t m_io_filt:1,
333 		__BITFIELD_FIELD(uint32_t msg_ctrl:1,
334 		__BITFIELD_FIELD(uint32_t m_cpl_ecrc_filt:1,
335 		__BITFIELD_FIELD(uint32_t m_ecrc_filt:1,
336 		__BITFIELD_FIELD(uint32_t m_cpl_len_err:1,
337 		__BITFIELD_FIELD(uint32_t m_cpl_attr_err:1,
338 		__BITFIELD_FIELD(uint32_t m_cpl_tc_err:1,
339 		__BITFIELD_FIELD(uint32_t m_cpl_fun_err:1,
340 		__BITFIELD_FIELD(uint32_t m_cpl_rid_err:1,
341 		__BITFIELD_FIELD(uint32_t m_cpl_tag_err:1,
342 		__BITFIELD_FIELD(uint32_t m_lk_filt:1,
343 		__BITFIELD_FIELD(uint32_t m_cfg1_filt:1,
344 		__BITFIELD_FIELD(uint32_t m_bar_match:1,
345 		__BITFIELD_FIELD(uint32_t m_pois_filt:1,
346 		__BITFIELD_FIELD(uint32_t m_fun:1,
347 		__BITFIELD_FIELD(uint32_t dfcwt:1,
348 		__BITFIELD_FIELD(uint32_t reserved_11_14:4,
349 		__BITFIELD_FIELD(uint32_t skpiv:11,
350 		;)))))))))))))))))))
351 	} s;
352 };
353 
354 union cvmx_pciercx_cfg515 {
355 	uint32_t u32;
356 	struct cvmx_pciercx_cfg515_s {
357 		__BITFIELD_FIELD(uint32_t reserved_21_31:11,
358 		__BITFIELD_FIELD(uint32_t s_d_e:1,
359 		__BITFIELD_FIELD(uint32_t ctcrb:1,
360 		__BITFIELD_FIELD(uint32_t cpyts:1,
361 		__BITFIELD_FIELD(uint32_t dsc:1,
362 		__BITFIELD_FIELD(uint32_t le:9,
363 		__BITFIELD_FIELD(uint32_t n_fts:8,
364 		;)))))))
365 	} s;
366 };
367 
368 #endif
369