xref: /linux/arch/mips/include/asm/octeon/cvmx-dpi-defs.h (revision 597473720f4dc69749542bfcfed4a927a43d935e)
1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_DPI_DEFS_H__
29 #define __CVMX_DPI_DEFS_H__
30 
31 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)58 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
59 {
60 	switch (cvmx_get_octeon_family()) {
61 	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62 		return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63 	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64 	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65 	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66 
67 		if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68 			return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
69 
70 		if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71 			return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72 		return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73 	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 		return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
75 	}
76 	return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
77 }
78 
79 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
80 
81 union cvmx_dpi_bist_status {
82 	uint64_t u64;
83 	struct cvmx_dpi_bist_status_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 		uint64_t reserved_47_63:17;
86 		uint64_t bist:47;
87 #else
88 		uint64_t bist:47;
89 		uint64_t reserved_47_63:17;
90 #endif
91 	} s;
92 	struct cvmx_dpi_bist_status_cn63xx {
93 #ifdef __BIG_ENDIAN_BITFIELD
94 		uint64_t reserved_45_63:19;
95 		uint64_t bist:45;
96 #else
97 		uint64_t bist:45;
98 		uint64_t reserved_45_63:19;
99 #endif
100 	} cn63xx;
101 	struct cvmx_dpi_bist_status_cn63xxp1 {
102 #ifdef __BIG_ENDIAN_BITFIELD
103 		uint64_t reserved_37_63:27;
104 		uint64_t bist:37;
105 #else
106 		uint64_t bist:37;
107 		uint64_t reserved_37_63:27;
108 #endif
109 	} cn63xxp1;
110 };
111 
112 union cvmx_dpi_ctl {
113 	uint64_t u64;
114 	struct cvmx_dpi_ctl_s {
115 #ifdef __BIG_ENDIAN_BITFIELD
116 		uint64_t reserved_2_63:62;
117 		uint64_t clk:1;
118 		uint64_t en:1;
119 #else
120 		uint64_t en:1;
121 		uint64_t clk:1;
122 		uint64_t reserved_2_63:62;
123 #endif
124 	} s;
125 	struct cvmx_dpi_ctl_cn61xx {
126 #ifdef __BIG_ENDIAN_BITFIELD
127 		uint64_t reserved_1_63:63;
128 		uint64_t en:1;
129 #else
130 		uint64_t en:1;
131 		uint64_t reserved_1_63:63;
132 #endif
133 	} cn61xx;
134 };
135 
136 union cvmx_dpi_dmax_counts {
137 	uint64_t u64;
138 	struct cvmx_dpi_dmax_counts_s {
139 #ifdef __BIG_ENDIAN_BITFIELD
140 		uint64_t reserved_39_63:25;
141 		uint64_t fcnt:7;
142 		uint64_t dbell:32;
143 #else
144 		uint64_t dbell:32;
145 		uint64_t fcnt:7;
146 		uint64_t reserved_39_63:25;
147 #endif
148 	} s;
149 };
150 
151 union cvmx_dpi_dmax_dbell {
152 	uint64_t u64;
153 	struct cvmx_dpi_dmax_dbell_s {
154 #ifdef __BIG_ENDIAN_BITFIELD
155 		uint64_t reserved_16_63:48;
156 		uint64_t dbell:16;
157 #else
158 		uint64_t dbell:16;
159 		uint64_t reserved_16_63:48;
160 #endif
161 	} s;
162 };
163 
164 union cvmx_dpi_dmax_err_rsp_status {
165 	uint64_t u64;
166 	struct cvmx_dpi_dmax_err_rsp_status_s {
167 #ifdef __BIG_ENDIAN_BITFIELD
168 		uint64_t reserved_6_63:58;
169 		uint64_t status:6;
170 #else
171 		uint64_t status:6;
172 		uint64_t reserved_6_63:58;
173 #endif
174 	} s;
175 };
176 
177 union cvmx_dpi_dmax_ibuff_saddr {
178 	uint64_t u64;
179 	struct cvmx_dpi_dmax_ibuff_saddr_s {
180 #ifdef __BIG_ENDIAN_BITFIELD
181 		uint64_t reserved_62_63:2;
182 		uint64_t csize:14;
183 		uint64_t reserved_41_47:7;
184 		uint64_t idle:1;
185 		uint64_t saddr:33;
186 		uint64_t reserved_0_6:7;
187 #else
188 		uint64_t reserved_0_6:7;
189 		uint64_t saddr:33;
190 		uint64_t idle:1;
191 		uint64_t reserved_41_47:7;
192 		uint64_t csize:14;
193 		uint64_t reserved_62_63:2;
194 #endif
195 	} s;
196 	struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 		uint64_t reserved_62_63:2;
199 		uint64_t csize:14;
200 		uint64_t reserved_41_47:7;
201 		uint64_t idle:1;
202 		uint64_t reserved_36_39:4;
203 		uint64_t saddr:29;
204 		uint64_t reserved_0_6:7;
205 #else
206 		uint64_t reserved_0_6:7;
207 		uint64_t saddr:29;
208 		uint64_t reserved_36_39:4;
209 		uint64_t idle:1;
210 		uint64_t reserved_41_47:7;
211 		uint64_t csize:14;
212 		uint64_t reserved_62_63:2;
213 #endif
214 	} cn61xx;
215 };
216 
217 union cvmx_dpi_dmax_iflight {
218 	uint64_t u64;
219 	struct cvmx_dpi_dmax_iflight_s {
220 #ifdef __BIG_ENDIAN_BITFIELD
221 		uint64_t reserved_3_63:61;
222 		uint64_t cnt:3;
223 #else
224 		uint64_t cnt:3;
225 		uint64_t reserved_3_63:61;
226 #endif
227 	} s;
228 };
229 
230 union cvmx_dpi_dmax_naddr {
231 	uint64_t u64;
232 	struct cvmx_dpi_dmax_naddr_s {
233 #ifdef __BIG_ENDIAN_BITFIELD
234 		uint64_t reserved_40_63:24;
235 		uint64_t addr:40;
236 #else
237 		uint64_t addr:40;
238 		uint64_t reserved_40_63:24;
239 #endif
240 	} s;
241 	struct cvmx_dpi_dmax_naddr_cn61xx {
242 #ifdef __BIG_ENDIAN_BITFIELD
243 		uint64_t reserved_36_63:28;
244 		uint64_t addr:36;
245 #else
246 		uint64_t addr:36;
247 		uint64_t reserved_36_63:28;
248 #endif
249 	} cn61xx;
250 };
251 
252 union cvmx_dpi_dmax_reqbnk0 {
253 	uint64_t u64;
254 	struct cvmx_dpi_dmax_reqbnk0_s {
255 #ifdef __BIG_ENDIAN_BITFIELD
256 		uint64_t state:64;
257 #else
258 		uint64_t state:64;
259 #endif
260 	} s;
261 };
262 
263 union cvmx_dpi_dmax_reqbnk1 {
264 	uint64_t u64;
265 	struct cvmx_dpi_dmax_reqbnk1_s {
266 #ifdef __BIG_ENDIAN_BITFIELD
267 		uint64_t state:64;
268 #else
269 		uint64_t state:64;
270 #endif
271 	} s;
272 };
273 
274 union cvmx_dpi_dma_control {
275 	uint64_t u64;
276 	struct cvmx_dpi_dma_control_s {
277 #ifdef __BIG_ENDIAN_BITFIELD
278 		uint64_t reserved_62_63:2;
279 		uint64_t dici_mode:1;
280 		uint64_t pkt_en1:1;
281 		uint64_t ffp_dis:1;
282 		uint64_t commit_mode:1;
283 		uint64_t pkt_hp:1;
284 		uint64_t pkt_en:1;
285 		uint64_t reserved_54_55:2;
286 		uint64_t dma_enb:6;
287 		uint64_t reserved_34_47:14;
288 		uint64_t b0_lend:1;
289 		uint64_t dwb_denb:1;
290 		uint64_t dwb_ichk:9;
291 		uint64_t fpa_que:3;
292 		uint64_t o_add1:1;
293 		uint64_t o_ro:1;
294 		uint64_t o_ns:1;
295 		uint64_t o_es:2;
296 		uint64_t o_mode:1;
297 		uint64_t reserved_0_13:14;
298 #else
299 		uint64_t reserved_0_13:14;
300 		uint64_t o_mode:1;
301 		uint64_t o_es:2;
302 		uint64_t o_ns:1;
303 		uint64_t o_ro:1;
304 		uint64_t o_add1:1;
305 		uint64_t fpa_que:3;
306 		uint64_t dwb_ichk:9;
307 		uint64_t dwb_denb:1;
308 		uint64_t b0_lend:1;
309 		uint64_t reserved_34_47:14;
310 		uint64_t dma_enb:6;
311 		uint64_t reserved_54_55:2;
312 		uint64_t pkt_en:1;
313 		uint64_t pkt_hp:1;
314 		uint64_t commit_mode:1;
315 		uint64_t ffp_dis:1;
316 		uint64_t pkt_en1:1;
317 		uint64_t dici_mode:1;
318 		uint64_t reserved_62_63:2;
319 #endif
320 	} s;
321 	struct cvmx_dpi_dma_control_cn63xx {
322 #ifdef __BIG_ENDIAN_BITFIELD
323 		uint64_t reserved_61_63:3;
324 		uint64_t pkt_en1:1;
325 		uint64_t ffp_dis:1;
326 		uint64_t commit_mode:1;
327 		uint64_t pkt_hp:1;
328 		uint64_t pkt_en:1;
329 		uint64_t reserved_54_55:2;
330 		uint64_t dma_enb:6;
331 		uint64_t reserved_34_47:14;
332 		uint64_t b0_lend:1;
333 		uint64_t dwb_denb:1;
334 		uint64_t dwb_ichk:9;
335 		uint64_t fpa_que:3;
336 		uint64_t o_add1:1;
337 		uint64_t o_ro:1;
338 		uint64_t o_ns:1;
339 		uint64_t o_es:2;
340 		uint64_t o_mode:1;
341 		uint64_t reserved_0_13:14;
342 #else
343 		uint64_t reserved_0_13:14;
344 		uint64_t o_mode:1;
345 		uint64_t o_es:2;
346 		uint64_t o_ns:1;
347 		uint64_t o_ro:1;
348 		uint64_t o_add1:1;
349 		uint64_t fpa_que:3;
350 		uint64_t dwb_ichk:9;
351 		uint64_t dwb_denb:1;
352 		uint64_t b0_lend:1;
353 		uint64_t reserved_34_47:14;
354 		uint64_t dma_enb:6;
355 		uint64_t reserved_54_55:2;
356 		uint64_t pkt_en:1;
357 		uint64_t pkt_hp:1;
358 		uint64_t commit_mode:1;
359 		uint64_t ffp_dis:1;
360 		uint64_t pkt_en1:1;
361 		uint64_t reserved_61_63:3;
362 #endif
363 	} cn63xx;
364 	struct cvmx_dpi_dma_control_cn63xxp1 {
365 #ifdef __BIG_ENDIAN_BITFIELD
366 		uint64_t reserved_59_63:5;
367 		uint64_t commit_mode:1;
368 		uint64_t pkt_hp:1;
369 		uint64_t pkt_en:1;
370 		uint64_t reserved_54_55:2;
371 		uint64_t dma_enb:6;
372 		uint64_t reserved_34_47:14;
373 		uint64_t b0_lend:1;
374 		uint64_t dwb_denb:1;
375 		uint64_t dwb_ichk:9;
376 		uint64_t fpa_que:3;
377 		uint64_t o_add1:1;
378 		uint64_t o_ro:1;
379 		uint64_t o_ns:1;
380 		uint64_t o_es:2;
381 		uint64_t o_mode:1;
382 		uint64_t reserved_0_13:14;
383 #else
384 		uint64_t reserved_0_13:14;
385 		uint64_t o_mode:1;
386 		uint64_t o_es:2;
387 		uint64_t o_ns:1;
388 		uint64_t o_ro:1;
389 		uint64_t o_add1:1;
390 		uint64_t fpa_que:3;
391 		uint64_t dwb_ichk:9;
392 		uint64_t dwb_denb:1;
393 		uint64_t b0_lend:1;
394 		uint64_t reserved_34_47:14;
395 		uint64_t dma_enb:6;
396 		uint64_t reserved_54_55:2;
397 		uint64_t pkt_en:1;
398 		uint64_t pkt_hp:1;
399 		uint64_t commit_mode:1;
400 		uint64_t reserved_59_63:5;
401 #endif
402 	} cn63xxp1;
403 };
404 
405 union cvmx_dpi_dma_engx_en {
406 	uint64_t u64;
407 	struct cvmx_dpi_dma_engx_en_s {
408 #ifdef __BIG_ENDIAN_BITFIELD
409 		uint64_t reserved_8_63:56;
410 		uint64_t qen:8;
411 #else
412 		uint64_t qen:8;
413 		uint64_t reserved_8_63:56;
414 #endif
415 	} s;
416 };
417 
418 union cvmx_dpi_dma_ppx_cnt {
419 	uint64_t u64;
420 	struct cvmx_dpi_dma_ppx_cnt_s {
421 #ifdef __BIG_ENDIAN_BITFIELD
422 		uint64_t reserved_16_63:48;
423 		uint64_t cnt:16;
424 #else
425 		uint64_t cnt:16;
426 		uint64_t reserved_16_63:48;
427 #endif
428 	} s;
429 };
430 
431 union cvmx_dpi_engx_buf {
432 	uint64_t u64;
433 	struct cvmx_dpi_engx_buf_s {
434 #ifdef __BIG_ENDIAN_BITFIELD
435 		uint64_t reserved_37_63:27;
436 		uint64_t compblks:5;
437 		uint64_t reserved_9_31:23;
438 		uint64_t base:5;
439 		uint64_t blks:4;
440 #else
441 		uint64_t blks:4;
442 		uint64_t base:5;
443 		uint64_t reserved_9_31:23;
444 		uint64_t compblks:5;
445 		uint64_t reserved_37_63:27;
446 #endif
447 	} s;
448 	struct cvmx_dpi_engx_buf_cn63xx {
449 #ifdef __BIG_ENDIAN_BITFIELD
450 		uint64_t reserved_8_63:56;
451 		uint64_t base:4;
452 		uint64_t blks:4;
453 #else
454 		uint64_t blks:4;
455 		uint64_t base:4;
456 		uint64_t reserved_8_63:56;
457 #endif
458 	} cn63xx;
459 };
460 
461 union cvmx_dpi_info_reg {
462 	uint64_t u64;
463 	struct cvmx_dpi_info_reg_s {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 		uint64_t reserved_8_63:56;
466 		uint64_t ffp:4;
467 		uint64_t reserved_2_3:2;
468 		uint64_t ncb:1;
469 		uint64_t rsl:1;
470 #else
471 		uint64_t rsl:1;
472 		uint64_t ncb:1;
473 		uint64_t reserved_2_3:2;
474 		uint64_t ffp:4;
475 		uint64_t reserved_8_63:56;
476 #endif
477 	} s;
478 	struct cvmx_dpi_info_reg_cn63xxp1 {
479 #ifdef __BIG_ENDIAN_BITFIELD
480 		uint64_t reserved_2_63:62;
481 		uint64_t ncb:1;
482 		uint64_t rsl:1;
483 #else
484 		uint64_t rsl:1;
485 		uint64_t ncb:1;
486 		uint64_t reserved_2_63:62;
487 #endif
488 	} cn63xxp1;
489 };
490 
491 union cvmx_dpi_int_en {
492 	uint64_t u64;
493 	struct cvmx_dpi_int_en_s {
494 #ifdef __BIG_ENDIAN_BITFIELD
495 		uint64_t reserved_28_63:36;
496 		uint64_t sprt3_rst:1;
497 		uint64_t sprt2_rst:1;
498 		uint64_t sprt1_rst:1;
499 		uint64_t sprt0_rst:1;
500 		uint64_t reserved_23_23:1;
501 		uint64_t req_badfil:1;
502 		uint64_t req_inull:1;
503 		uint64_t req_anull:1;
504 		uint64_t req_undflw:1;
505 		uint64_t req_ovrflw:1;
506 		uint64_t req_badlen:1;
507 		uint64_t req_badadr:1;
508 		uint64_t dmadbo:8;
509 		uint64_t reserved_2_7:6;
510 		uint64_t nfovr:1;
511 		uint64_t nderr:1;
512 #else
513 		uint64_t nderr:1;
514 		uint64_t nfovr:1;
515 		uint64_t reserved_2_7:6;
516 		uint64_t dmadbo:8;
517 		uint64_t req_badadr:1;
518 		uint64_t req_badlen:1;
519 		uint64_t req_ovrflw:1;
520 		uint64_t req_undflw:1;
521 		uint64_t req_anull:1;
522 		uint64_t req_inull:1;
523 		uint64_t req_badfil:1;
524 		uint64_t reserved_23_23:1;
525 		uint64_t sprt0_rst:1;
526 		uint64_t sprt1_rst:1;
527 		uint64_t sprt2_rst:1;
528 		uint64_t sprt3_rst:1;
529 		uint64_t reserved_28_63:36;
530 #endif
531 	} s;
532 	struct cvmx_dpi_int_en_cn63xx {
533 #ifdef __BIG_ENDIAN_BITFIELD
534 		uint64_t reserved_26_63:38;
535 		uint64_t sprt1_rst:1;
536 		uint64_t sprt0_rst:1;
537 		uint64_t reserved_23_23:1;
538 		uint64_t req_badfil:1;
539 		uint64_t req_inull:1;
540 		uint64_t req_anull:1;
541 		uint64_t req_undflw:1;
542 		uint64_t req_ovrflw:1;
543 		uint64_t req_badlen:1;
544 		uint64_t req_badadr:1;
545 		uint64_t dmadbo:8;
546 		uint64_t reserved_2_7:6;
547 		uint64_t nfovr:1;
548 		uint64_t nderr:1;
549 #else
550 		uint64_t nderr:1;
551 		uint64_t nfovr:1;
552 		uint64_t reserved_2_7:6;
553 		uint64_t dmadbo:8;
554 		uint64_t req_badadr:1;
555 		uint64_t req_badlen:1;
556 		uint64_t req_ovrflw:1;
557 		uint64_t req_undflw:1;
558 		uint64_t req_anull:1;
559 		uint64_t req_inull:1;
560 		uint64_t req_badfil:1;
561 		uint64_t reserved_23_23:1;
562 		uint64_t sprt0_rst:1;
563 		uint64_t sprt1_rst:1;
564 		uint64_t reserved_26_63:38;
565 #endif
566 	} cn63xx;
567 };
568 
569 union cvmx_dpi_int_reg {
570 	uint64_t u64;
571 	struct cvmx_dpi_int_reg_s {
572 #ifdef __BIG_ENDIAN_BITFIELD
573 		uint64_t reserved_28_63:36;
574 		uint64_t sprt3_rst:1;
575 		uint64_t sprt2_rst:1;
576 		uint64_t sprt1_rst:1;
577 		uint64_t sprt0_rst:1;
578 		uint64_t reserved_23_23:1;
579 		uint64_t req_badfil:1;
580 		uint64_t req_inull:1;
581 		uint64_t req_anull:1;
582 		uint64_t req_undflw:1;
583 		uint64_t req_ovrflw:1;
584 		uint64_t req_badlen:1;
585 		uint64_t req_badadr:1;
586 		uint64_t dmadbo:8;
587 		uint64_t reserved_2_7:6;
588 		uint64_t nfovr:1;
589 		uint64_t nderr:1;
590 #else
591 		uint64_t nderr:1;
592 		uint64_t nfovr:1;
593 		uint64_t reserved_2_7:6;
594 		uint64_t dmadbo:8;
595 		uint64_t req_badadr:1;
596 		uint64_t req_badlen:1;
597 		uint64_t req_ovrflw:1;
598 		uint64_t req_undflw:1;
599 		uint64_t req_anull:1;
600 		uint64_t req_inull:1;
601 		uint64_t req_badfil:1;
602 		uint64_t reserved_23_23:1;
603 		uint64_t sprt0_rst:1;
604 		uint64_t sprt1_rst:1;
605 		uint64_t sprt2_rst:1;
606 		uint64_t sprt3_rst:1;
607 		uint64_t reserved_28_63:36;
608 #endif
609 	} s;
610 	struct cvmx_dpi_int_reg_cn63xx {
611 #ifdef __BIG_ENDIAN_BITFIELD
612 		uint64_t reserved_26_63:38;
613 		uint64_t sprt1_rst:1;
614 		uint64_t sprt0_rst:1;
615 		uint64_t reserved_23_23:1;
616 		uint64_t req_badfil:1;
617 		uint64_t req_inull:1;
618 		uint64_t req_anull:1;
619 		uint64_t req_undflw:1;
620 		uint64_t req_ovrflw:1;
621 		uint64_t req_badlen:1;
622 		uint64_t req_badadr:1;
623 		uint64_t dmadbo:8;
624 		uint64_t reserved_2_7:6;
625 		uint64_t nfovr:1;
626 		uint64_t nderr:1;
627 #else
628 		uint64_t nderr:1;
629 		uint64_t nfovr:1;
630 		uint64_t reserved_2_7:6;
631 		uint64_t dmadbo:8;
632 		uint64_t req_badadr:1;
633 		uint64_t req_badlen:1;
634 		uint64_t req_ovrflw:1;
635 		uint64_t req_undflw:1;
636 		uint64_t req_anull:1;
637 		uint64_t req_inull:1;
638 		uint64_t req_badfil:1;
639 		uint64_t reserved_23_23:1;
640 		uint64_t sprt0_rst:1;
641 		uint64_t sprt1_rst:1;
642 		uint64_t reserved_26_63:38;
643 #endif
644 	} cn63xx;
645 };
646 
647 union cvmx_dpi_ncbx_cfg {
648 	uint64_t u64;
649 	struct cvmx_dpi_ncbx_cfg_s {
650 #ifdef __BIG_ENDIAN_BITFIELD
651 		uint64_t reserved_6_63:58;
652 		uint64_t molr:6;
653 #else
654 		uint64_t molr:6;
655 		uint64_t reserved_6_63:58;
656 #endif
657 	} s;
658 };
659 
660 union cvmx_dpi_pint_info {
661 	uint64_t u64;
662 	struct cvmx_dpi_pint_info_s {
663 #ifdef __BIG_ENDIAN_BITFIELD
664 		uint64_t reserved_14_63:50;
665 		uint64_t iinfo:6;
666 		uint64_t reserved_6_7:2;
667 		uint64_t sinfo:6;
668 #else
669 		uint64_t sinfo:6;
670 		uint64_t reserved_6_7:2;
671 		uint64_t iinfo:6;
672 		uint64_t reserved_14_63:50;
673 #endif
674 	} s;
675 };
676 
677 union cvmx_dpi_pkt_err_rsp {
678 	uint64_t u64;
679 	struct cvmx_dpi_pkt_err_rsp_s {
680 #ifdef __BIG_ENDIAN_BITFIELD
681 		uint64_t reserved_1_63:63;
682 		uint64_t pkterr:1;
683 #else
684 		uint64_t pkterr:1;
685 		uint64_t reserved_1_63:63;
686 #endif
687 	} s;
688 };
689 
690 union cvmx_dpi_req_err_rsp {
691 	uint64_t u64;
692 	struct cvmx_dpi_req_err_rsp_s {
693 #ifdef __BIG_ENDIAN_BITFIELD
694 		uint64_t reserved_8_63:56;
695 		uint64_t qerr:8;
696 #else
697 		uint64_t qerr:8;
698 		uint64_t reserved_8_63:56;
699 #endif
700 	} s;
701 };
702 
703 union cvmx_dpi_req_err_rsp_en {
704 	uint64_t u64;
705 	struct cvmx_dpi_req_err_rsp_en_s {
706 #ifdef __BIG_ENDIAN_BITFIELD
707 		uint64_t reserved_8_63:56;
708 		uint64_t en:8;
709 #else
710 		uint64_t en:8;
711 		uint64_t reserved_8_63:56;
712 #endif
713 	} s;
714 };
715 
716 union cvmx_dpi_req_err_rst {
717 	uint64_t u64;
718 	struct cvmx_dpi_req_err_rst_s {
719 #ifdef __BIG_ENDIAN_BITFIELD
720 		uint64_t reserved_8_63:56;
721 		uint64_t qerr:8;
722 #else
723 		uint64_t qerr:8;
724 		uint64_t reserved_8_63:56;
725 #endif
726 	} s;
727 };
728 
729 union cvmx_dpi_req_err_rst_en {
730 	uint64_t u64;
731 	struct cvmx_dpi_req_err_rst_en_s {
732 #ifdef __BIG_ENDIAN_BITFIELD
733 		uint64_t reserved_8_63:56;
734 		uint64_t en:8;
735 #else
736 		uint64_t en:8;
737 		uint64_t reserved_8_63:56;
738 #endif
739 	} s;
740 };
741 
742 union cvmx_dpi_req_err_skip_comp {
743 	uint64_t u64;
744 	struct cvmx_dpi_req_err_skip_comp_s {
745 #ifdef __BIG_ENDIAN_BITFIELD
746 		uint64_t reserved_24_63:40;
747 		uint64_t en_rst:8;
748 		uint64_t reserved_8_15:8;
749 		uint64_t en_rsp:8;
750 #else
751 		uint64_t en_rsp:8;
752 		uint64_t reserved_8_15:8;
753 		uint64_t en_rst:8;
754 		uint64_t reserved_24_63:40;
755 #endif
756 	} s;
757 };
758 
759 union cvmx_dpi_req_gbl_en {
760 	uint64_t u64;
761 	struct cvmx_dpi_req_gbl_en_s {
762 #ifdef __BIG_ENDIAN_BITFIELD
763 		uint64_t reserved_8_63:56;
764 		uint64_t qen:8;
765 #else
766 		uint64_t qen:8;
767 		uint64_t reserved_8_63:56;
768 #endif
769 	} s;
770 };
771 
772 union cvmx_dpi_sli_prtx_cfg {
773 	uint64_t u64;
774 	struct cvmx_dpi_sli_prtx_cfg_s {
775 #ifdef __BIG_ENDIAN_BITFIELD
776 		uint64_t reserved_25_63:39;
777 		uint64_t halt:1;
778 		uint64_t qlm_cfg:4;
779 		uint64_t reserved_17_19:3;
780 		uint64_t rd_mode:1;
781 		uint64_t reserved_14_15:2;
782 		uint64_t molr:6;
783 		uint64_t mps_lim:1;
784 		uint64_t reserved_5_6:2;
785 		uint64_t mps:1;
786 		uint64_t mrrs_lim:1;
787 		uint64_t reserved_2_2:1;
788 		uint64_t mrrs:2;
789 #else
790 		uint64_t mrrs:2;
791 		uint64_t reserved_2_2:1;
792 		uint64_t mrrs_lim:1;
793 		uint64_t mps:1;
794 		uint64_t reserved_5_6:2;
795 		uint64_t mps_lim:1;
796 		uint64_t molr:6;
797 		uint64_t reserved_14_15:2;
798 		uint64_t rd_mode:1;
799 		uint64_t reserved_17_19:3;
800 		uint64_t qlm_cfg:4;
801 		uint64_t halt:1;
802 		uint64_t reserved_25_63:39;
803 #endif
804 	} s;
805 	struct cvmx_dpi_sli_prtx_cfg_cn63xx {
806 #ifdef __BIG_ENDIAN_BITFIELD
807 		uint64_t reserved_25_63:39;
808 		uint64_t halt:1;
809 		uint64_t reserved_21_23:3;
810 		uint64_t qlm_cfg:1;
811 		uint64_t reserved_17_19:3;
812 		uint64_t rd_mode:1;
813 		uint64_t reserved_14_15:2;
814 		uint64_t molr:6;
815 		uint64_t mps_lim:1;
816 		uint64_t reserved_5_6:2;
817 		uint64_t mps:1;
818 		uint64_t mrrs_lim:1;
819 		uint64_t reserved_2_2:1;
820 		uint64_t mrrs:2;
821 #else
822 		uint64_t mrrs:2;
823 		uint64_t reserved_2_2:1;
824 		uint64_t mrrs_lim:1;
825 		uint64_t mps:1;
826 		uint64_t reserved_5_6:2;
827 		uint64_t mps_lim:1;
828 		uint64_t molr:6;
829 		uint64_t reserved_14_15:2;
830 		uint64_t rd_mode:1;
831 		uint64_t reserved_17_19:3;
832 		uint64_t qlm_cfg:1;
833 		uint64_t reserved_21_23:3;
834 		uint64_t halt:1;
835 		uint64_t reserved_25_63:39;
836 #endif
837 	} cn63xx;
838 };
839 
840 union cvmx_dpi_sli_prtx_err {
841 	uint64_t u64;
842 	struct cvmx_dpi_sli_prtx_err_s {
843 #ifdef __BIG_ENDIAN_BITFIELD
844 		uint64_t addr:61;
845 		uint64_t reserved_0_2:3;
846 #else
847 		uint64_t reserved_0_2:3;
848 		uint64_t addr:61;
849 #endif
850 	} s;
851 };
852 
853 union cvmx_dpi_sli_prtx_err_info {
854 	uint64_t u64;
855 	struct cvmx_dpi_sli_prtx_err_info_s {
856 #ifdef __BIG_ENDIAN_BITFIELD
857 		uint64_t reserved_9_63:55;
858 		uint64_t lock:1;
859 		uint64_t reserved_5_7:3;
860 		uint64_t type:1;
861 		uint64_t reserved_3_3:1;
862 		uint64_t reqq:3;
863 #else
864 		uint64_t reqq:3;
865 		uint64_t reserved_3_3:1;
866 		uint64_t type:1;
867 		uint64_t reserved_5_7:3;
868 		uint64_t lock:1;
869 		uint64_t reserved_9_63:55;
870 #endif
871 	} s;
872 };
873 
874 #endif
875