1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35 #include "opp.h"
36 #include "dsc.h"
37 #include "dchubbub.h"
38 #include "dccg.h"
39 #include "abm.h"
40 #include "dcn10/dcn10_hubbub.h"
41 #include "dce/dmub_hw_lock_mgr.h"
42
43 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
44 #define MAX_NUM_MCACHE 8
45
46 /* used as index in array of black_color_format */
47 enum black_color_format {
48 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
49 BLACK_COLOR_FORMAT_RGB_LIMITED,
50 BLACK_COLOR_FORMAT_YUV_TV,
51 BLACK_COLOR_FORMAT_YUV_CV,
52 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
53 BLACK_COLOR_FORMAT_DEBUG,
54 };
55
56 enum dc_color_space_type {
57 COLOR_SPACE_RGB_TYPE,
58 COLOR_SPACE_RGB_LIMITED_TYPE,
59 COLOR_SPACE_YCBCR601_TYPE,
60 COLOR_SPACE_YCBCR709_TYPE,
61 COLOR_SPACE_YCBCR2020_TYPE,
62 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
63 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
64 COLOR_SPACE_YCBCR709_BLACK_TYPE,
65 };
66
67 static const struct tg_color black_color_format[] = {
68 /* BlackColorFormat_RGB_FullRange */
69 {0, 0, 0},
70 /* BlackColorFormat_RGB_Limited */
71 {0x40, 0x40, 0x40},
72 /* BlackColorFormat_YUV_TV */
73 {0x200, 0x40, 0x200},
74 /* BlackColorFormat_YUV_CV */
75 {0x1f4, 0x40, 0x1f4},
76 /* BlackColorFormat_YUV_SuperAA */
77 {0x1a2, 0x20, 0x1a2},
78 /* visual confirm debug */
79 {0xff, 0xff, 0},
80 };
81
82 struct out_csc_color_matrix_type {
83 enum dc_color_space_type color_space_type;
84 uint16_t regval[12];
85 };
86
87 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
88 { COLOR_SPACE_RGB_TYPE,
89 { 0x2000, 0, 0, 0,
90 0, 0x2000, 0, 0,
91 0, 0, 0x2000, 0} },
92 { COLOR_SPACE_RGB_LIMITED_TYPE,
93 { 0x1B67, 0, 0, 0x201,
94 0, 0x1B67, 0, 0x201,
95 0, 0, 0x1B67, 0x201} },
96 { COLOR_SPACE_YCBCR601_TYPE,
97 { 0xE04, 0xF444, 0xFDB9, 0x1004,
98 0x831, 0x1016, 0x320, 0x201,
99 0xFB45, 0xF6B7, 0xE04, 0x1004} },
100 { COLOR_SPACE_YCBCR709_TYPE,
101 { 0xE04, 0xF345, 0xFEB7, 0x1004,
102 0x5D3, 0x1399, 0x1FA, 0x201,
103 0xFCCA, 0xF533, 0xE04, 0x1004} },
104 /* TODO: correct values below */
105 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
106 { 0xE00, 0xF447, 0xFDB9, 0x1000,
107 0x991, 0x12C9, 0x3A6, 0x200,
108 0xFB47, 0xF6B9, 0xE00, 0x1000} },
109 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
110 { 0xE00, 0xF349, 0xFEB7, 0x1000,
111 0x6CE, 0x16E3, 0x24F, 0x200,
112 0xFCCB, 0xF535, 0xE00, 0x1000} },
113 { COLOR_SPACE_YCBCR2020_TYPE,
114 { 0x1000, 0xF149, 0xFEB7, 0x1004,
115 0x0868, 0x15B2, 0x01E6, 0x201,
116 0xFB88, 0xF478, 0x1000, 0x1004} },
117 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
118 { 0x0000, 0x0000, 0x0000, 0x1000,
119 0x0000, 0x0000, 0x0000, 0x0200,
120 0x0000, 0x0000, 0x0000, 0x1000} },
121 };
122
is_rgb_type(enum dc_color_space color_space)123 static bool is_rgb_type(
124 enum dc_color_space color_space)
125 {
126 bool ret = false;
127
128 if (color_space == COLOR_SPACE_SRGB ||
129 color_space == COLOR_SPACE_XR_RGB ||
130 color_space == COLOR_SPACE_MSREF_SCRGB ||
131 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
132 color_space == COLOR_SPACE_ADOBERGB ||
133 color_space == COLOR_SPACE_DCIP3 ||
134 color_space == COLOR_SPACE_DOLBYVISION)
135 ret = true;
136 return ret;
137 }
138
is_rgb_limited_type(enum dc_color_space color_space)139 static bool is_rgb_limited_type(
140 enum dc_color_space color_space)
141 {
142 bool ret = false;
143
144 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
145 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
146 ret = true;
147 return ret;
148 }
149
is_ycbcr601_type(enum dc_color_space color_space)150 static bool is_ycbcr601_type(
151 enum dc_color_space color_space)
152 {
153 bool ret = false;
154
155 if (color_space == COLOR_SPACE_YCBCR601 ||
156 color_space == COLOR_SPACE_XV_YCC_601)
157 ret = true;
158 return ret;
159 }
160
is_ycbcr601_limited_type(enum dc_color_space color_space)161 static bool is_ycbcr601_limited_type(
162 enum dc_color_space color_space)
163 {
164 bool ret = false;
165
166 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
167 ret = true;
168 return ret;
169 }
170
is_ycbcr709_type(enum dc_color_space color_space)171 static bool is_ycbcr709_type(
172 enum dc_color_space color_space)
173 {
174 bool ret = false;
175
176 if (color_space == COLOR_SPACE_YCBCR709 ||
177 color_space == COLOR_SPACE_XV_YCC_709)
178 ret = true;
179 return ret;
180 }
181
is_ycbcr2020_type(enum dc_color_space color_space)182 static bool is_ycbcr2020_type(
183 enum dc_color_space color_space)
184 {
185 bool ret = false;
186
187 if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL)
188 ret = true;
189 return ret;
190 }
191
is_ycbcr709_limited_type(enum dc_color_space color_space)192 static bool is_ycbcr709_limited_type(
193 enum dc_color_space color_space)
194 {
195 bool ret = false;
196
197 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
198 ret = true;
199 return ret;
200 }
201
get_color_space_type(enum dc_color_space color_space)202 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
203 {
204 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
205
206 if (is_rgb_type(color_space))
207 type = COLOR_SPACE_RGB_TYPE;
208 else if (is_rgb_limited_type(color_space))
209 type = COLOR_SPACE_RGB_LIMITED_TYPE;
210 else if (is_ycbcr601_type(color_space))
211 type = COLOR_SPACE_YCBCR601_TYPE;
212 else if (is_ycbcr709_type(color_space))
213 type = COLOR_SPACE_YCBCR709_TYPE;
214 else if (is_ycbcr601_limited_type(color_space))
215 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
216 else if (is_ycbcr709_limited_type(color_space))
217 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
218 else if (is_ycbcr2020_type(color_space))
219 type = COLOR_SPACE_YCBCR2020_TYPE;
220 else if (color_space == COLOR_SPACE_YCBCR709)
221 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
222 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
223 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
224 return type;
225 }
226
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)227 const uint16_t *find_color_matrix(enum dc_color_space color_space,
228 uint32_t *array_size)
229 {
230 int i;
231 enum dc_color_space_type type;
232 const uint16_t *val = NULL;
233 int arr_size = NUM_ELEMENTS(output_csc_matrix);
234
235 type = get_color_space_type(color_space);
236 for (i = 0; i < arr_size; i++)
237 if (output_csc_matrix[i].color_space_type == type) {
238 val = output_csc_matrix[i].regval;
239 *array_size = 12;
240 break;
241 }
242
243 return val;
244 }
245
246
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)247 void color_space_to_black_color(
248 const struct dc *dc,
249 enum dc_color_space colorspace,
250 struct tg_color *black_color)
251 {
252 switch (colorspace) {
253 case COLOR_SPACE_YCBCR601:
254 case COLOR_SPACE_YCBCR709:
255 case COLOR_SPACE_YCBCR709_BLACK:
256 case COLOR_SPACE_YCBCR601_LIMITED:
257 case COLOR_SPACE_YCBCR709_LIMITED:
258 case COLOR_SPACE_2020_YCBCR_LIMITED:
259 case COLOR_SPACE_2020_YCBCR_FULL:
260 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
261 break;
262
263 case COLOR_SPACE_SRGB_LIMITED:
264 *black_color =
265 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
266 break;
267
268 /*
269 * Remove default and add case for all color space
270 * so when we forget to add new color space
271 * compiler will give a warning
272 */
273 case COLOR_SPACE_UNKNOWN:
274 case COLOR_SPACE_SRGB:
275 case COLOR_SPACE_XR_RGB:
276 case COLOR_SPACE_MSREF_SCRGB:
277 case COLOR_SPACE_XV_YCC_709:
278 case COLOR_SPACE_XV_YCC_601:
279 case COLOR_SPACE_2020_RGB_FULLRANGE:
280 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
281 case COLOR_SPACE_ADOBERGB:
282 case COLOR_SPACE_DCIP3:
283 case COLOR_SPACE_DISPLAYNATIVE:
284 case COLOR_SPACE_DOLBYVISION:
285 case COLOR_SPACE_APPCTRL:
286 case COLOR_SPACE_CUSTOMPOINTS:
287 /* fefault is sRGB black (full range). */
288 *black_color =
289 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
290 /* default is sRGB black 0. */
291 break;
292 }
293 }
294
hwss_wait_for_blank_complete(struct timing_generator * tg)295 bool hwss_wait_for_blank_complete(
296 struct timing_generator *tg)
297 {
298 int counter;
299
300 /* Not applicable if the pipe is not primary, save 300ms of boot time */
301 if (!tg->funcs->is_blanked)
302 return true;
303 for (counter = 0; counter < 100; counter++) {
304 if (tg->funcs->is_blanked(tg))
305 break;
306
307 msleep(1);
308 }
309
310 if (counter == 100) {
311 dm_error("DC: failed to blank crtc!\n");
312 return false;
313 }
314
315 return true;
316 }
317
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)318 void get_mpctree_visual_confirm_color(
319 struct pipe_ctx *pipe_ctx,
320 struct tg_color *color)
321 {
322 const struct tg_color pipe_colors[6] = {
323 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
324 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
325 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
326 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
327 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
328 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
329 };
330
331 struct pipe_ctx *top_pipe = pipe_ctx;
332
333 while (top_pipe->top_pipe)
334 top_pipe = top_pipe->top_pipe;
335
336 *color = pipe_colors[top_pipe->pipe_idx];
337 }
338
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)339 void get_surface_visual_confirm_color(
340 const struct pipe_ctx *pipe_ctx,
341 struct tg_color *color)
342 {
343 uint32_t color_value = MAX_TG_COLOR_VALUE;
344
345 switch (pipe_ctx->plane_res.scl_data.format) {
346 case PIXEL_FORMAT_ARGB8888:
347 /* set border color to red */
348 color->color_r_cr = color_value;
349 if (pipe_ctx->plane_state->layer_index > 0) {
350 /* set border color to pink */
351 color->color_b_cb = color_value;
352 color->color_g_y = color_value * 0.5;
353 }
354 break;
355
356 case PIXEL_FORMAT_ARGB2101010:
357 /* set border color to blue */
358 color->color_b_cb = color_value;
359 if (pipe_ctx->plane_state->layer_index > 0) {
360 /* set border color to cyan */
361 color->color_g_y = color_value;
362 }
363 break;
364 case PIXEL_FORMAT_420BPP8:
365 /* set border color to green */
366 color->color_g_y = color_value;
367 break;
368 case PIXEL_FORMAT_420BPP10:
369 /* set border color to yellow */
370 color->color_g_y = color_value;
371 color->color_r_cr = color_value;
372 break;
373 case PIXEL_FORMAT_FP16:
374 /* set border color to white */
375 color->color_r_cr = color_value;
376 color->color_b_cb = color_value;
377 color->color_g_y = color_value;
378 if (pipe_ctx->plane_state->layer_index > 0) {
379 /* set border color to orange */
380 color->color_g_y = 0.22 * color_value;
381 color->color_b_cb = 0;
382 }
383 break;
384 default:
385 break;
386 }
387 }
388
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)389 void get_hdr_visual_confirm_color(
390 struct pipe_ctx *pipe_ctx,
391 struct tg_color *color)
392 {
393 uint32_t color_value = MAX_TG_COLOR_VALUE;
394 bool is_sdr = false;
395
396 /* Determine the overscan color based on the top-most (desktop) plane's context */
397 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
398
399 while (top_pipe_ctx->top_pipe != NULL)
400 top_pipe_ctx = top_pipe_ctx->top_pipe;
401
402 switch (top_pipe_ctx->plane_res.scl_data.format) {
403 case PIXEL_FORMAT_ARGB2101010:
404 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
405 /* HDR10, ARGB2101010 - set border color to red */
406 color->color_r_cr = color_value;
407 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
408 /* FreeSync 2 ARGB2101010 - set border color to pink */
409 color->color_r_cr = color_value;
410 color->color_b_cb = color_value;
411 } else
412 is_sdr = true;
413 break;
414 case PIXEL_FORMAT_FP16:
415 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
416 /* HDR10, FP16 - set border color to blue */
417 color->color_b_cb = color_value;
418 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
419 /* FreeSync 2 HDR - set border color to green */
420 color->color_g_y = color_value;
421 } else
422 is_sdr = true;
423 break;
424 default:
425 is_sdr = true;
426 break;
427 }
428
429 if (is_sdr) {
430 /* SDR - set border color to Gray */
431 color->color_r_cr = color_value/2;
432 color->color_b_cb = color_value/2;
433 color->color_g_y = color_value/2;
434 }
435 }
436
437 /* Visual Confirm color definition for Smart Mux */
get_smartmux_visual_confirm_color(struct dc * dc,struct tg_color * color)438 void get_smartmux_visual_confirm_color(
439 struct dc *dc,
440 struct tg_color *color)
441 {
442 uint32_t color_value = MAX_TG_COLOR_VALUE;
443
444 const struct tg_color sm_ver_colors[5] = {
445 {0, 0, 0}, /* SMUX_MUXCONTROL_UNSUPPORTED - Black */
446 {0, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_v10 - Green */
447 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_v15 - Cyan */
448 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* SMUX_MUXCONTROL_MDM - Yellow */
449 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* SMUX_MUXCONTROL_vUNKNOWN - Magenta*/
450 };
451
452 if (dc->caps.is_apu) {
453 /* APU driving the eDP */
454 *color = sm_ver_colors[dc->config.smart_mux_version];
455 } else {
456 /* dGPU driving the eDP - red */
457 color->color_r_cr = color_value;
458 color->color_g_y = 0;
459 color->color_b_cb = 0;
460 }
461 }
462
463 /* Visual Confirm color definition for VABC */
get_vabc_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)464 void get_vabc_visual_confirm_color(
465 struct pipe_ctx *pipe_ctx,
466 struct tg_color *color)
467 {
468 uint32_t color_value = MAX_TG_COLOR_VALUE;
469 struct dc_link *edp_link = NULL;
470
471 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {
472 if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)
473 edp_link = pipe_ctx->stream->link;
474 }
475
476 if (edp_link) {
477 switch (edp_link->backlight_control_type) {
478 case BACKLIGHT_CONTROL_PWM:
479 color->color_r_cr = color_value;
480 color->color_g_y = 0;
481 color->color_b_cb = 0;
482 break;
483 case BACKLIGHT_CONTROL_AMD_AUX:
484 color->color_r_cr = 0;
485 color->color_g_y = color_value;
486 color->color_b_cb = 0;
487 break;
488 case BACKLIGHT_CONTROL_VESA_AUX:
489 color->color_r_cr = 0;
490 color->color_g_y = 0;
491 color->color_b_cb = color_value;
492 break;
493 }
494 } else {
495 color->color_r_cr = 0;
496 color->color_g_y = 0;
497 color->color_b_cb = 0;
498 }
499 }
500
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)501 void get_subvp_visual_confirm_color(
502 struct pipe_ctx *pipe_ctx,
503 struct tg_color *color)
504 {
505 uint32_t color_value = MAX_TG_COLOR_VALUE;
506 if (pipe_ctx) {
507 switch (pipe_ctx->p_state_type) {
508 case P_STATE_SUB_VP:
509 color->color_r_cr = color_value;
510 color->color_g_y = 0;
511 color->color_b_cb = 0;
512 break;
513 case P_STATE_DRR_SUB_VP:
514 color->color_r_cr = 0;
515 color->color_g_y = color_value;
516 color->color_b_cb = 0;
517 break;
518 case P_STATE_V_BLANK_SUB_VP:
519 color->color_r_cr = 0;
520 color->color_g_y = 0;
521 color->color_b_cb = color_value;
522 break;
523 default:
524 break;
525 }
526 }
527 }
528
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)529 void get_mclk_switch_visual_confirm_color(
530 struct pipe_ctx *pipe_ctx,
531 struct tg_color *color)
532 {
533 uint32_t color_value = MAX_TG_COLOR_VALUE;
534
535 if (pipe_ctx) {
536 switch (pipe_ctx->p_state_type) {
537 case P_STATE_V_BLANK:
538 color->color_r_cr = color_value;
539 color->color_g_y = color_value;
540 color->color_b_cb = 0;
541 break;
542 case P_STATE_FPO:
543 color->color_r_cr = 0;
544 color->color_g_y = color_value;
545 color->color_b_cb = color_value;
546 break;
547 case P_STATE_V_ACTIVE:
548 color->color_r_cr = color_value;
549 color->color_g_y = 0;
550 color->color_b_cb = color_value;
551 break;
552 case P_STATE_SUB_VP:
553 color->color_r_cr = color_value;
554 color->color_g_y = 0;
555 color->color_b_cb = 0;
556 break;
557 case P_STATE_DRR_SUB_VP:
558 color->color_r_cr = 0;
559 color->color_g_y = color_value;
560 color->color_b_cb = 0;
561 break;
562 case P_STATE_V_BLANK_SUB_VP:
563 color->color_r_cr = 0;
564 color->color_g_y = 0;
565 color->color_b_cb = color_value;
566 break;
567 default:
568 break;
569 }
570 }
571 }
572
get_cursor_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)573 void get_cursor_visual_confirm_color(
574 struct pipe_ctx *pipe_ctx,
575 struct tg_color *color)
576 {
577 uint32_t color_value = MAX_TG_COLOR_VALUE;
578
579 if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
580 color->color_r_cr = color_value;
581 color->color_g_y = 0;
582 color->color_b_cb = 0;
583 } else {
584 color->color_r_cr = 0;
585 color->color_g_y = 0;
586 color->color_b_cb = color_value;
587 }
588 }
589
get_dcc_visual_confirm_color(struct dc * dc,struct pipe_ctx * pipe_ctx,struct tg_color * color)590 void get_dcc_visual_confirm_color(
591 struct dc *dc,
592 struct pipe_ctx *pipe_ctx,
593 struct tg_color *color)
594 {
595 const uint32_t MCACHE_ID_UNASSIGNED = 0xF;
596
597 if (!pipe_ctx->plane_state->dcc.enable) {
598 color->color_r_cr = 0; /* black - DCC disabled */
599 color->color_g_y = 0;
600 color->color_b_cb = 0;
601 return;
602 }
603
604 if (dc->ctx->dce_version < DCN_VERSION_4_01) {
605 color->color_r_cr = MAX_TG_COLOR_VALUE; /* red - DCC enabled */
606 color->color_g_y = 0;
607 color->color_b_cb = 0;
608 return;
609 }
610
611 uint32_t first_id = pipe_ctx->mcache_regs.main.p0.mcache_id_first;
612 uint32_t second_id = pipe_ctx->mcache_regs.main.p0.mcache_id_second;
613
614 if (first_id != MCACHE_ID_UNASSIGNED && second_id != MCACHE_ID_UNASSIGNED && first_id != second_id) {
615 color->color_r_cr = MAX_TG_COLOR_VALUE/2; /* grey - 2 mcache */
616 color->color_g_y = MAX_TG_COLOR_VALUE/2;
617 color->color_b_cb = MAX_TG_COLOR_VALUE/2;
618 }
619
620 else if (first_id != MCACHE_ID_UNASSIGNED || second_id != MCACHE_ID_UNASSIGNED) {
621 const struct tg_color id_colors[MAX_NUM_MCACHE] = {
622 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
623 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
624 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
625 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
626 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
627 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* white */
628 {MAX_TG_COLOR_VALUE/2, 0, 0}, /* dark red */
629 {0, MAX_TG_COLOR_VALUE/2, 0}, /* dark green */
630 };
631
632 uint32_t assigned_id = (first_id != MCACHE_ID_UNASSIGNED) ? first_id : second_id;
633 *color = id_colors[assigned_id];
634 }
635 }
636
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)637 void set_p_state_switch_method(
638 struct dc *dc,
639 struct dc_state *context,
640 struct pipe_ctx *pipe_ctx)
641 {
642 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
643 bool enable_subvp;
644
645 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
646 return;
647
648 pipe_ctx->p_state_type = P_STATE_UNKNOWN;
649 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
650 dm_dram_clock_change_unsupported) {
651 /* MCLK switching is supported */
652 if (!pipe_ctx->has_vactive_margin) {
653 /* In Vblank - yellow */
654 pipe_ctx->p_state_type = P_STATE_V_BLANK;
655
656 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
657 /* FPO + Vblank - cyan */
658 pipe_ctx->p_state_type = P_STATE_FPO;
659 }
660 } else {
661 /* In Vactive - pink */
662 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
663 }
664
665 /* SubVP */
666 enable_subvp = false;
667
668 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
669 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
670
671 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
672 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
673 /* SubVP enable - red */
674 pipe_ctx->p_state_type = P_STATE_SUB_VP;
675 enable_subvp = true;
676
677 if (pipe_ctx->stream == pipe->stream)
678 return;
679 break;
680 }
681 }
682
683 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
684 if (pipe_ctx->stream->allow_freesync == 1) {
685 /* SubVP enable and DRR on - green */
686 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
687 } else {
688 /* SubVP enable and No DRR - blue */
689 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
690 }
691 }
692 }
693 }
694
set_drr_and_clear_adjust_pending(struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream,struct drr_params * params)695 void set_drr_and_clear_adjust_pending(
696 struct pipe_ctx *pipe_ctx,
697 struct dc_stream_state *stream,
698 struct drr_params *params)
699 {
700 /* params can be null.*/
701 if (pipe_ctx && pipe_ctx->stream_res.tg &&
702 pipe_ctx->stream_res.tg->funcs->set_drr)
703 pipe_ctx->stream_res.tg->funcs->set_drr(
704 pipe_ctx->stream_res.tg, params);
705
706 if (stream)
707 stream->adjust.timing_adjust_pending = false;
708 }
709
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)710 void get_fams2_visual_confirm_color(
711 struct dc *dc,
712 struct dc_state *context,
713 struct pipe_ctx *pipe_ctx,
714 struct tg_color *color)
715 {
716 uint32_t color_value = MAX_TG_COLOR_VALUE;
717
718 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
719 return;
720
721 /* driver only handles visual confirm when FAMS2 is disabled */
722 if (!dc_state_is_fams2_in_use(dc, context)) {
723 /* when FAMS2 is disabled, all pipes are grey */
724 color->color_g_y = color_value / 2;
725 color->color_b_cb = color_value / 2;
726 color->color_r_cr = color_value / 2;
727 }
728 }
729
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)730 void hwss_build_fast_sequence(struct dc *dc,
731 struct dc_dmub_cmd *dc_dmub_cmd,
732 unsigned int dmub_cmd_count,
733 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
734 unsigned int *num_steps,
735 struct pipe_ctx *pipe_ctx,
736 struct dc_stream_status *stream_status,
737 struct dc_state *context)
738 {
739 struct dc_plane_state *plane = pipe_ctx->plane_state;
740 struct dc_stream_state *stream = pipe_ctx->stream;
741 struct dce_hwseq *hws = dc->hwseq;
742 struct pipe_ctx *current_pipe = NULL;
743 struct pipe_ctx *current_mpc_pipe = NULL;
744 bool is_dmub_lock_required = false;
745 unsigned int i = 0;
746
747 *num_steps = 0; // Initialize to 0
748
749 if (!plane || !stream)
750 return;
751
752 if (dc->hwss.wait_for_dcc_meta_propagation) {
753 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
754 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
755 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
756 (*num_steps)++;
757 }
758 if (dc->hwss.subvp_pipe_control_lock_fast) {
759 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
760 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
761 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
762 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
763 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
764 (*num_steps)++;
765 }
766 if (dc->hwss.dmub_hw_control_lock_fast) {
767 is_dmub_lock_required = dc_state_is_fams2_in_use(dc, context) ||
768 dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link);
769
770 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
771 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;
772 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
773 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
774 (*num_steps)++;
775 }
776 if (dc->hwss.pipe_control_lock) {
777 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
778 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
779 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
780 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
781 (*num_steps)++;
782 }
783
784 for (i = 0; i < dmub_cmd_count; i++) {
785 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
786 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
787 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
788 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
789 (*num_steps)++;
790 }
791
792 current_pipe = pipe_ctx;
793 while (current_pipe) {
794 current_mpc_pipe = current_pipe;
795 while (current_mpc_pipe) {
796 if (current_mpc_pipe->plane_state) {
797 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
798 block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;
799 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
800 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
801 (*num_steps)++;
802 }
803 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
804 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
805 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
806 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
807 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
808 (*num_steps)++;
809 }
810 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
811 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
812 stream_status->mall_stream_config.type == SUBVP_MAIN) {
813 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
814 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
815 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
816 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
817 (*num_steps)++;
818 }
819
820 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
821 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
822 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
823 (*num_steps)++;
824 }
825
826 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
827 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
828 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
829 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
830 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
831 (*num_steps)++;
832 }
833
834 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
835 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
836 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
837 (*num_steps)++;
838 }
839 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
840 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
841 block_sequence[*num_steps].func = DPP_SETUP_DPP;
842 (*num_steps)++;
843 }
844 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
845 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
846 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
847 (*num_steps)++;
848 }
849 }
850 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
851 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
852 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
853 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
854 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
855 (*num_steps)++;
856 }
857 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE &&
858 dc->hwss.update_visual_confirm_color) {
859 block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;
860 block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;
861 block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
862 block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
863 (*num_steps)++;
864 }
865 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
866 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
867 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
868 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
869 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
870 (*num_steps)++;
871
872 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
873 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
874 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
875 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
876 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
877 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
878 (*num_steps)++;
879 } else {
880 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
881 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
882 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
883 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
884 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
885 (*num_steps)++;
886 }
887 }
888 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
889 }
890 current_pipe = current_pipe->next_odm_pipe;
891 }
892
893 if (dc->hwss.pipe_control_lock) {
894 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
895 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
896 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
897 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
898 (*num_steps)++;
899 }
900 if (dc->hwss.subvp_pipe_control_lock_fast) {
901 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
902 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
903 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
904 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
905 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
906 (*num_steps)++;
907 }
908 if (dc->hwss.dmub_hw_control_lock_fast) {
909 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
910 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;
911 block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
912 block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
913 (*num_steps)++;
914 }
915
916 current_pipe = pipe_ctx;
917 while (current_pipe) {
918 current_mpc_pipe = current_pipe;
919
920 while (current_mpc_pipe) {
921 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
922 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
923 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
924 !current_mpc_pipe->plane_state->skip_manual_trigger) {
925 if (dc->hwss.program_cursor_offload_now) {
926 block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;
927 block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;
928 block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW;
929 (*num_steps)++;
930 }
931
932 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
933 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
934 (*num_steps)++;
935 }
936 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
937 }
938 current_pipe = current_pipe->next_odm_pipe;
939 }
940 }
941
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],int num_steps)942 void hwss_execute_sequence(struct dc *dc,
943 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
944 int num_steps)
945 {
946 unsigned int i;
947 union block_sequence_params *params;
948 struct dce_hwseq *hws = dc->hwseq;
949
950 for (i = 0; i < num_steps; i++) {
951 params = &(block_sequence[i].params);
952 switch (block_sequence[i].func) {
953
954 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
955 dc->hwss.subvp_pipe_control_lock_fast(params);
956 break;
957 case OPTC_PIPE_CONTROL_LOCK:
958 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
959 params->pipe_control_lock_params.pipe_ctx,
960 params->pipe_control_lock_params.lock);
961 break;
962 case HUBP_SET_FLIP_CONTROL_GSL:
963 params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl(
964 params->set_flip_control_gsl_params.hubp,
965 params->set_flip_control_gsl_params.flip_immediate);
966 break;
967 case HUBP_PROGRAM_TRIPLEBUFFER:
968 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
969 params->program_triplebuffer_params.pipe_ctx,
970 params->program_triplebuffer_params.enableTripleBuffer);
971 break;
972 case HUBP_UPDATE_PLANE_ADDR:
973 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
974 params->update_plane_addr_params.pipe_ctx);
975 break;
976 case DPP_SET_INPUT_TRANSFER_FUNC:
977 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
978 params->set_input_transfer_func_params.pipe_ctx,
979 params->set_input_transfer_func_params.plane_state);
980 break;
981 case DPP_PROGRAM_GAMUT_REMAP:
982 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
983 break;
984 case DPP_SETUP_DPP:
985 hwss_setup_dpp(params);
986 break;
987 case DPP_PROGRAM_BIAS_AND_SCALE:
988 hwss_program_bias_and_scale(params);
989 break;
990 case OPTC_PROGRAM_MANUAL_TRIGGER:
991 hwss_program_manual_trigger(params);
992 break;
993 case DPP_SET_OUTPUT_TRANSFER_FUNC:
994 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
995 params->set_output_transfer_func_params.pipe_ctx,
996 params->set_output_transfer_func_params.stream);
997 break;
998 case MPC_UPDATE_VISUAL_CONFIRM:
999 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
1000 params->update_visual_confirm_params.pipe_ctx,
1001 params->update_visual_confirm_params.mpcc_id);
1002 break;
1003 case MPC_POWER_ON_MPC_MEM_PWR:
1004 hwss_power_on_mpc_mem_pwr(params);
1005 break;
1006 case MPC_SET_OUTPUT_CSC:
1007 hwss_set_output_csc(params);
1008 break;
1009 case MPC_SET_OCSC_DEFAULT:
1010 hwss_set_ocsc_default(params);
1011 break;
1012 case DMUB_SEND_DMCUB_CMD:
1013 hwss_send_dmcub_cmd(params);
1014 break;
1015 case DMUB_SUBVP_SAVE_SURF_ADDR:
1016 hwss_subvp_save_surf_addr(params);
1017 break;
1018 case HUBP_WAIT_FOR_DCC_META_PROP:
1019 dc->hwss.wait_for_dcc_meta_propagation(
1020 params->wait_for_dcc_meta_propagation_params.dc,
1021 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
1022 break;
1023 case DMUB_HW_CONTROL_LOCK_FAST:
1024 dc->hwss.dmub_hw_control_lock_fast(params);
1025 break;
1026 case HUBP_PROGRAM_SURFACE_CONFIG:
1027 hwss_program_surface_config(params);
1028 break;
1029 case HUBP_PROGRAM_MCACHE_ID:
1030 hwss_program_mcache_id_and_split_coordinate(params);
1031 break;
1032 case PROGRAM_CURSOR_UPDATE_NOW:
1033 dc->hwss.program_cursor_offload_now(
1034 params->program_cursor_update_now_params.dc,
1035 params->program_cursor_update_now_params.pipe_ctx);
1036 break;
1037 case HUBP_WAIT_PIPE_READ_START:
1038 params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start(
1039 params->hubp_wait_pipe_read_start_params.hubp);
1040 break;
1041 case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM:
1042 dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx);
1043 break;
1044 case HWS_UPDATE_PHANTOM_VP_POSITION:
1045 dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc,
1046 params->update_phantom_vp_position_params.context,
1047 params->update_phantom_vp_position_params.pipe_ctx);
1048 break;
1049 case OPTC_SET_ODM_COMBINE:
1050 hwss_set_odm_combine(params);
1051 break;
1052 case OPTC_SET_ODM_BYPASS:
1053 hwss_set_odm_bypass(params);
1054 break;
1055 case OPP_PIPE_CLOCK_CONTROL:
1056 hwss_opp_pipe_clock_control(params);
1057 break;
1058 case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL:
1059 hwss_opp_program_left_edge_extra_pixel(params);
1060 break;
1061 case DCCG_SET_DTO_DSCCLK:
1062 hwss_dccg_set_dto_dscclk(params);
1063 break;
1064 case DSC_SET_CONFIG:
1065 hwss_dsc_set_config(params);
1066 break;
1067 case DSC_ENABLE:
1068 hwss_dsc_enable(params);
1069 break;
1070 case TG_SET_DSC_CONFIG:
1071 hwss_tg_set_dsc_config(params);
1072 break;
1073 case DSC_DISCONNECT:
1074 hwss_dsc_disconnect(params);
1075 break;
1076 case DSC_READ_STATE:
1077 hwss_dsc_read_state(params);
1078 break;
1079 case DSC_CALCULATE_AND_SET_CONFIG:
1080 hwss_dsc_calculate_and_set_config(params);
1081 break;
1082 case DSC_ENABLE_WITH_OPP:
1083 hwss_dsc_enable_with_opp(params);
1084 break;
1085 case TG_PROGRAM_GLOBAL_SYNC:
1086 hwss_tg_program_global_sync(params);
1087 break;
1088 case TG_WAIT_FOR_STATE:
1089 hwss_tg_wait_for_state(params);
1090 break;
1091 case TG_SET_VTG_PARAMS:
1092 hwss_tg_set_vtg_params(params);
1093 break;
1094 case TG_SETUP_VERTICAL_INTERRUPT2:
1095 hwss_tg_setup_vertical_interrupt2(params);
1096 break;
1097 case DPP_SET_HDR_MULTIPLIER:
1098 hwss_dpp_set_hdr_multiplier(params);
1099 break;
1100 case HUBP_PROGRAM_DET_SIZE:
1101 hwss_program_det_size(params);
1102 break;
1103 case HUBP_PROGRAM_DET_SEGMENTS:
1104 hwss_program_det_segments(params);
1105 break;
1106 case OPP_SET_DYN_EXPANSION:
1107 hwss_opp_set_dyn_expansion(params);
1108 break;
1109 case OPP_PROGRAM_FMT:
1110 hwss_opp_program_fmt(params);
1111 break;
1112 case OPP_PROGRAM_BIT_DEPTH_REDUCTION:
1113 hwss_opp_program_bit_depth_reduction(params);
1114 break;
1115 case OPP_SET_DISP_PATTERN_GENERATOR:
1116 hwss_opp_set_disp_pattern_generator(params);
1117 break;
1118 case ABM_SET_PIPE:
1119 hwss_set_abm_pipe(params);
1120 break;
1121 case ABM_SET_LEVEL:
1122 hwss_set_abm_level(params);
1123 break;
1124 case ABM_SET_IMMEDIATE_DISABLE:
1125 hwss_set_abm_immediate_disable(params);
1126 break;
1127 case MPC_REMOVE_MPCC:
1128 hwss_mpc_remove_mpcc(params);
1129 break;
1130 case OPP_SET_MPCC_DISCONNECT_PENDING:
1131 hwss_opp_set_mpcc_disconnect_pending(params);
1132 break;
1133 case DC_SET_OPTIMIZED_REQUIRED:
1134 hwss_dc_set_optimized_required(params);
1135 break;
1136 case HUBP_DISCONNECT:
1137 hwss_hubp_disconnect(params);
1138 break;
1139 case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL:
1140 hwss_hubbub_force_pstate_change_control(params);
1141 break;
1142 case TG_ENABLE_CRTC:
1143 hwss_tg_enable_crtc(params);
1144 break;
1145 case TG_SET_GSL:
1146 hwss_tg_set_gsl(params);
1147 break;
1148 case TG_SET_GSL_SOURCE_SELECT:
1149 hwss_tg_set_gsl_source_select(params);
1150 break;
1151 case HUBP_WAIT_FLIP_PENDING:
1152 hwss_hubp_wait_flip_pending(params);
1153 break;
1154 case TG_WAIT_DOUBLE_BUFFER_PENDING:
1155 hwss_tg_wait_double_buffer_pending(params);
1156 break;
1157 case UPDATE_FORCE_PSTATE:
1158 hwss_update_force_pstate(params);
1159 break;
1160 case HUBBUB_APPLY_DEDCN21_147_WA:
1161 hwss_hubbub_apply_dedcn21_147_wa(params);
1162 break;
1163 case HUBBUB_ALLOW_SELF_REFRESH_CONTROL:
1164 hwss_hubbub_allow_self_refresh_control(params);
1165 break;
1166 case TG_GET_FRAME_COUNT:
1167 hwss_tg_get_frame_count(params);
1168 break;
1169 case MPC_SET_DWB_MUX:
1170 hwss_mpc_set_dwb_mux(params);
1171 break;
1172 case MPC_DISABLE_DWB_MUX:
1173 hwss_mpc_disable_dwb_mux(params);
1174 break;
1175 case MCIF_WB_CONFIG_BUF:
1176 hwss_mcif_wb_config_buf(params);
1177 break;
1178 case MCIF_WB_CONFIG_ARB:
1179 hwss_mcif_wb_config_arb(params);
1180 break;
1181 case MCIF_WB_ENABLE:
1182 hwss_mcif_wb_enable(params);
1183 break;
1184 case MCIF_WB_DISABLE:
1185 hwss_mcif_wb_disable(params);
1186 break;
1187 case DWBC_ENABLE:
1188 hwss_dwbc_enable(params);
1189 break;
1190 case DWBC_DISABLE:
1191 hwss_dwbc_disable(params);
1192 break;
1193 case DWBC_UPDATE:
1194 hwss_dwbc_update(params);
1195 break;
1196 case HUBP_UPDATE_MALL_SEL:
1197 hwss_hubp_update_mall_sel(params);
1198 break;
1199 case HUBP_PREPARE_SUBVP_BUFFERING:
1200 hwss_hubp_prepare_subvp_buffering(params);
1201 break;
1202 case HUBP_SET_BLANK_EN:
1203 hwss_hubp_set_blank_en(params);
1204 break;
1205 case HUBP_DISABLE_CONTROL:
1206 hwss_hubp_disable_control(params);
1207 break;
1208 case HUBBUB_SOFT_RESET:
1209 hwss_hubbub_soft_reset(params);
1210 break;
1211 case HUBP_CLK_CNTL:
1212 hwss_hubp_clk_cntl(params);
1213 break;
1214 case HUBP_INIT:
1215 hwss_hubp_init(params);
1216 break;
1217 case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS:
1218 hwss_hubp_set_vm_system_aperture_settings(params);
1219 break;
1220 case HUBP_SET_FLIP_INT:
1221 hwss_hubp_set_flip_int(params);
1222 break;
1223 case DPP_DPPCLK_CONTROL:
1224 hwss_dpp_dppclk_control(params);
1225 break;
1226 case DISABLE_PHANTOM_CRTC:
1227 hwss_disable_phantom_crtc(params);
1228 break;
1229 case DSC_PG_STATUS:
1230 hwss_dsc_pg_status(params);
1231 break;
1232 case DSC_WAIT_DISCONNECT_PENDING_CLEAR:
1233 hwss_dsc_wait_disconnect_pending_clear(params);
1234 break;
1235 case DSC_DISABLE:
1236 hwss_dsc_disable(params);
1237 break;
1238 case DCCG_SET_REF_DSCCLK:
1239 hwss_dccg_set_ref_dscclk(params);
1240 break;
1241 case DPP_PG_CONTROL:
1242 hwss_dpp_pg_control(params);
1243 break;
1244 case HUBP_PG_CONTROL:
1245 hwss_hubp_pg_control(params);
1246 break;
1247 case HUBP_RESET:
1248 hwss_hubp_reset(params);
1249 break;
1250 case DPP_RESET:
1251 hwss_dpp_reset(params);
1252 break;
1253 case DPP_ROOT_CLOCK_CONTROL:
1254 hwss_dpp_root_clock_control(params);
1255 break;
1256 case DC_IP_REQUEST_CNTL:
1257 hwss_dc_ip_request_cntl(params);
1258 break;
1259 case DCCG_UPDATE_DPP_DTO:
1260 hwss_dccg_update_dpp_dto(params);
1261 break;
1262 case HUBP_VTG_SEL:
1263 hwss_hubp_vtg_sel(params);
1264 break;
1265 case HUBP_SETUP2:
1266 hwss_hubp_setup2(params);
1267 break;
1268 case HUBP_SETUP:
1269 hwss_hubp_setup(params);
1270 break;
1271 case HUBP_SET_UNBOUNDED_REQUESTING:
1272 hwss_hubp_set_unbounded_requesting(params);
1273 break;
1274 case HUBP_SETUP_INTERDEPENDENT2:
1275 hwss_hubp_setup_interdependent2(params);
1276 break;
1277 case HUBP_SETUP_INTERDEPENDENT:
1278 hwss_hubp_setup_interdependent(params);
1279 break;
1280 case DPP_SET_CURSOR_MATRIX:
1281 hwss_dpp_set_cursor_matrix(params);
1282 break;
1283 case MPC_UPDATE_BLENDING:
1284 hwss_mpc_update_blending(params);
1285 break;
1286 case MPC_ASSERT_IDLE_MPCC:
1287 hwss_mpc_assert_idle_mpcc(params);
1288 break;
1289 case MPC_INSERT_PLANE:
1290 hwss_mpc_insert_plane(params);
1291 break;
1292 case DPP_SET_SCALER:
1293 hwss_dpp_set_scaler(params);
1294 break;
1295 case HUBP_MEM_PROGRAM_VIEWPORT:
1296 hwss_hubp_mem_program_viewport(params);
1297 break;
1298 case ABORT_CURSOR_OFFLOAD_UPDATE:
1299 hwss_abort_cursor_offload_update(params);
1300 break;
1301 case SET_CURSOR_ATTRIBUTE:
1302 hwss_set_cursor_attribute(params);
1303 break;
1304 case SET_CURSOR_POSITION:
1305 hwss_set_cursor_position(params);
1306 break;
1307 case SET_CURSOR_SDR_WHITE_LEVEL:
1308 hwss_set_cursor_sdr_white_level(params);
1309 break;
1310 case PROGRAM_OUTPUT_CSC:
1311 hwss_program_output_csc(params);
1312 break;
1313 case HUBP_SET_BLANK:
1314 hwss_hubp_set_blank(params);
1315 break;
1316 case PHANTOM_HUBP_POST_ENABLE:
1317 hwss_phantom_hubp_post_enable(params);
1318 break;
1319 default:
1320 ASSERT(false);
1321 break;
1322 }
1323 }
1324 }
1325
1326 /*
1327 * Helper function to add OPTC pipe control lock to block sequence
1328 */
hwss_add_optc_pipe_control_lock(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,bool lock)1329 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,
1330 struct dc *dc,
1331 struct pipe_ctx *pipe_ctx,
1332 bool lock)
1333 {
1334 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1335 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc;
1336 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
1337 seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock;
1338 seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK;
1339 (*seq_state->num_steps)++;
1340 }
1341 }
1342
1343 /*
1344 * Helper function to add HUBP set flip control GSL to block sequence
1345 */
hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state * seq_state,struct hubp * hubp,bool flip_immediate)1346 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,
1347 struct hubp *hubp,
1348 bool flip_immediate)
1349 {
1350 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1351 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp;
1352 seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate;
1353 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
1354 (*seq_state->num_steps)++;
1355 }
1356 }
1357
1358 /*
1359 * Helper function to add HUBP program triplebuffer to block sequence
1360 */
hwss_add_hubp_program_triplebuffer(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,bool enableTripleBuffer)1361 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,
1362 struct dc *dc,
1363 struct pipe_ctx *pipe_ctx,
1364 bool enableTripleBuffer)
1365 {
1366 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1367 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc;
1368 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx;
1369 seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer;
1370 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
1371 (*seq_state->num_steps)++;
1372 }
1373 }
1374
1375 /*
1376 * Helper function to add HUBP update plane address to block sequence
1377 */
hwss_add_hubp_update_plane_addr(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)1378 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,
1379 struct dc *dc,
1380 struct pipe_ctx *pipe_ctx)
1381 {
1382 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1383 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc;
1384 seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx;
1385 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR;
1386 (*seq_state->num_steps)++;
1387 }
1388 }
1389
1390 /*
1391 * Helper function to add DPP set input transfer function to block sequence
1392 */
hwss_add_dpp_set_input_transfer_func(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_plane_state * plane_state)1393 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,
1394 struct dc *dc,
1395 struct pipe_ctx *pipe_ctx,
1396 struct dc_plane_state *plane_state)
1397 {
1398 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1399 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc;
1400 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx;
1401 seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state;
1402 seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
1403 (*seq_state->num_steps)++;
1404 }
1405 }
1406
1407 /*
1408 * Helper function to add DPP program gamut remap to block sequence
1409 */
hwss_add_dpp_program_gamut_remap(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1410 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,
1411 struct pipe_ctx *pipe_ctx)
1412 {
1413 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1414 seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx;
1415 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
1416 (*seq_state->num_steps)++;
1417 }
1418 }
1419
1420 /*
1421 * Helper function to add DPP program bias and scale to block sequence
1422 */
hwss_add_dpp_program_bias_and_scale(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1423 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)
1424 {
1425 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1426 seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx;
1427 seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
1428 (*seq_state->num_steps)++;
1429 }
1430 }
1431
1432 /*
1433 * Helper function to add OPTC program manual trigger to block sequence
1434 */
hwss_add_optc_program_manual_trigger(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1435 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,
1436 struct pipe_ctx *pipe_ctx)
1437 {
1438 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1439 seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx;
1440 seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
1441 (*seq_state->num_steps)++;
1442 }
1443 }
1444
1445 /*
1446 * Helper function to add DPP set output transfer function to block sequence
1447 */
hwss_add_dpp_set_output_transfer_func(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)1448 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,
1449 struct dc *dc,
1450 struct pipe_ctx *pipe_ctx,
1451 struct dc_stream_state *stream)
1452 {
1453 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1454 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc;
1455 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;
1456 seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream;
1457 seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
1458 (*seq_state->num_steps)++;
1459 }
1460 }
1461
1462 /*
1463 * Helper function to add MPC update visual confirm to block sequence
1464 */
hwss_add_mpc_update_visual_confirm(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,int mpcc_id)1465 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,
1466 struct dc *dc,
1467 struct pipe_ctx *pipe_ctx,
1468 int mpcc_id)
1469 {
1470 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1471 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc;
1472 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx;
1473 seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id;
1474 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
1475 (*seq_state->num_steps)++;
1476 }
1477 }
1478
1479 /*
1480 * Helper function to add MPC power on MPC mem PWR to block sequence
1481 */
hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state * seq_state,struct mpc * mpc,int mpcc_id,bool power_on)1482 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,
1483 struct mpc *mpc,
1484 int mpcc_id,
1485 bool power_on)
1486 {
1487 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1488 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc;
1489 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id;
1490 seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on;
1491 seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
1492 (*seq_state->num_steps)++;
1493 }
1494 }
1495
1496 /*
1497 * Helper function to add MPC set output CSC to block sequence
1498 */
hwss_add_mpc_set_output_csc(struct block_sequence_state * seq_state,struct mpc * mpc,int opp_id,const uint16_t * regval,enum mpc_output_csc_mode ocsc_mode)1499 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,
1500 struct mpc *mpc,
1501 int opp_id,
1502 const uint16_t *regval,
1503 enum mpc_output_csc_mode ocsc_mode)
1504 {
1505 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1506 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc;
1507 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id;
1508 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval;
1509 seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode;
1510 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC;
1511 (*seq_state->num_steps)++;
1512 }
1513 }
1514
1515 /*
1516 * Helper function to add MPC set OCSC default to block sequence
1517 */
hwss_add_mpc_set_ocsc_default(struct block_sequence_state * seq_state,struct mpc * mpc,int opp_id,enum dc_color_space colorspace,enum mpc_output_csc_mode ocsc_mode)1518 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,
1519 struct mpc *mpc,
1520 int opp_id,
1521 enum dc_color_space colorspace,
1522 enum mpc_output_csc_mode ocsc_mode)
1523 {
1524 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1525 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc;
1526 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id;
1527 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace;
1528 seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode;
1529 seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT;
1530 (*seq_state->num_steps)++;
1531 }
1532 }
1533
1534 /*
1535 * Helper function to add DMUB send DMCUB command to block sequence
1536 */
hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state * seq_state,struct dc_context * ctx,union dmub_rb_cmd * cmd,enum dm_dmub_wait_type wait_type)1537 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,
1538 struct dc_context *ctx,
1539 union dmub_rb_cmd *cmd,
1540 enum dm_dmub_wait_type wait_type)
1541 {
1542 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1543 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx;
1544 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd;
1545 seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type;
1546 seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD;
1547 (*seq_state->num_steps)++;
1548 }
1549 }
1550
1551 /*
1552 * Helper function to add DMUB SubVP save surface address to block sequence
1553 */
hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state * seq_state,struct dc_dmub_srv * dc_dmub_srv,struct dc_plane_address * addr,uint8_t subvp_index)1554 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,
1555 struct dc_dmub_srv *dc_dmub_srv,
1556 struct dc_plane_address *addr,
1557 uint8_t subvp_index)
1558 {
1559 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1560 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv;
1561 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr;
1562 seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index;
1563 seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
1564 (*seq_state->num_steps)++;
1565 }
1566 }
1567
1568 /*
1569 * Helper function to add HUBP wait for DCC meta propagation to block sequence
1570 */
hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * top_pipe_to_program)1571 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,
1572 struct dc *dc,
1573 struct pipe_ctx *top_pipe_to_program)
1574 {
1575 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1576 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
1577 seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program;
1578 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
1579 (*seq_state->num_steps)++;
1580 }
1581 }
1582
1583 /*
1584 * Helper function to add HUBP wait pipe read start to block sequence
1585 */
hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state * seq_state,struct hubp * hubp)1586 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,
1587 struct hubp *hubp)
1588 {
1589 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1590 seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;
1591 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START;
1592 (*seq_state->num_steps)++;
1593 }
1594 }
1595
1596 /*
1597 * Helper function to add HWS apply update flags for phantom to block sequence
1598 */
hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)1599 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,
1600 struct pipe_ctx *pipe_ctx)
1601 {
1602 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1603 seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx;
1604 seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM;
1605 (*seq_state->num_steps)++;
1606 }
1607 }
1608
1609 /*
1610 * Helper function to add HWS update phantom VP position to block sequence
1611 */
hwss_add_hws_update_phantom_vp_position(struct block_sequence_state * seq_state,struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1612 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,
1613 struct dc *dc,
1614 struct dc_state *context,
1615 struct pipe_ctx *pipe_ctx)
1616 {
1617 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1618 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc;
1619 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context;
1620 seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx;
1621 seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION;
1622 (*seq_state->num_steps)++;
1623 }
1624 }
1625
1626 /*
1627 * Helper function to add OPTC set ODM combine to block sequence
1628 */
hwss_add_optc_set_odm_combine(struct block_sequence_state * seq_state,struct timing_generator * tg,int opp_inst[MAX_PIPES],int opp_head_count,int odm_slice_width,int last_odm_slice_width)1629 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,
1630 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count,
1631 int odm_slice_width, int last_odm_slice_width)
1632 {
1633 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1634 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg;
1635 memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES);
1636 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count;
1637 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width;
1638 seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width;
1639 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE;
1640 (*seq_state->num_steps)++;
1641 }
1642 }
1643
1644 /*
1645 * Helper function to add OPTC set ODM bypass to block sequence
1646 */
hwss_add_optc_set_odm_bypass(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dc_crtc_timing * timing)1647 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,
1648 struct timing_generator *tg, struct dc_crtc_timing *timing)
1649 {
1650 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1651 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg;
1652 seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing;
1653 seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS;
1654 (*seq_state->num_steps)++;
1655 }
1656 }
1657
hwss_send_dmcub_cmd(union block_sequence_params * params)1658 void hwss_send_dmcub_cmd(union block_sequence_params *params)
1659 {
1660 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
1661 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
1662 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
1663
1664 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
1665 }
1666
1667 /*
1668 * Helper function to add TG program global sync to block sequence
1669 */
hwss_add_tg_program_global_sync(struct block_sequence_state * seq_state,struct timing_generator * tg,int vready_offset,unsigned int vstartup_lines,unsigned int vupdate_offset_pixels,unsigned int vupdate_vupdate_width_pixels,unsigned int pstate_keepout_start_lines)1670 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,
1671 struct timing_generator *tg,
1672 int vready_offset,
1673 unsigned int vstartup_lines,
1674 unsigned int vupdate_offset_pixels,
1675 unsigned int vupdate_vupdate_width_pixels,
1676 unsigned int pstate_keepout_start_lines)
1677 {
1678 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1679 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg;
1680 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset;
1681 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines;
1682 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels;
1683 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels;
1684 seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines;
1685 seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC;
1686 (*seq_state->num_steps)++;
1687 }
1688 }
1689
1690 /*
1691 * Helper function to add TG wait for state to block sequence
1692 */
hwss_add_tg_wait_for_state(struct block_sequence_state * seq_state,struct timing_generator * tg,enum crtc_state state)1693 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,
1694 struct timing_generator *tg,
1695 enum crtc_state state)
1696 {
1697 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1698 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg;
1699 seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state;
1700 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE;
1701 (*seq_state->num_steps)++;
1702 }
1703 }
1704
1705 /*
1706 * Helper function to add TG set VTG params to block sequence
1707 */
hwss_add_tg_set_vtg_params(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dc_crtc_timing * dc_crtc_timing,bool program_fp2)1708 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,
1709 struct timing_generator *tg,
1710 struct dc_crtc_timing *dc_crtc_timing,
1711 bool program_fp2)
1712 {
1713 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1714 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg;
1715 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing;
1716 seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2;
1717 seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS;
1718 (*seq_state->num_steps)++;
1719 }
1720 }
1721
1722 /*
1723 * Helper function to add TG setup vertical interrupt2 to block sequence
1724 */
hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state * seq_state,struct timing_generator * tg,int start_line)1725 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,
1726 struct timing_generator *tg, int start_line)
1727 {
1728 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1729 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg;
1730 seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line;
1731 seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2;
1732 (*seq_state->num_steps)++;
1733 }
1734 }
1735
1736 /*
1737 * Helper function to add DPP set HDR multiplier to block sequence
1738 */
hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state * seq_state,struct dpp * dpp,uint32_t hw_mult)1739 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,
1740 struct dpp *dpp, uint32_t hw_mult)
1741 {
1742 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1743 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;
1744 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult;
1745 seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER;
1746 (*seq_state->num_steps)++;
1747 }
1748 }
1749
1750 /*
1751 * Helper function to add HUBP program DET size to block sequence
1752 */
hwss_add_hubp_program_det_size(struct block_sequence_state * seq_state,struct hubbub * hubbub,unsigned int hubp_inst,unsigned int det_buffer_size_kb)1753 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,
1754 struct hubbub *hubbub,
1755 unsigned int hubp_inst,
1756 unsigned int det_buffer_size_kb)
1757 {
1758 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1759 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub;
1760 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst;
1761 seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb;
1762 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE;
1763 (*seq_state->num_steps)++;
1764 }
1765 }
1766
hwss_add_hubp_program_mcache_id(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_hubp_pipe_mcache_regs * mcache_regs)1767 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,
1768 struct hubp *hubp,
1769 struct dml2_hubp_pipe_mcache_regs *mcache_regs)
1770 {
1771 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1772 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;
1773 seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs;
1774 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID;
1775 (*seq_state->num_steps)++;
1776 }
1777 }
1778
hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state * seq_state,struct hubbub * hubbub,bool enable,bool wait)1779 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,
1780 struct hubbub *hubbub,
1781 bool enable,
1782 bool wait)
1783 {
1784 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1785 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub;
1786 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable;
1787 seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait;
1788 seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL;
1789 (*seq_state->num_steps)++;
1790 }
1791 }
1792
1793 /*
1794 * Helper function to add HUBP program DET segments to block sequence
1795 */
hwss_add_hubp_program_det_segments(struct block_sequence_state * seq_state,struct hubbub * hubbub,unsigned int hubp_inst,unsigned int det_size)1796 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,
1797 struct hubbub *hubbub,
1798 unsigned int hubp_inst,
1799 unsigned int det_size)
1800 {
1801 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1802 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub;
1803 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst;
1804 seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size;
1805 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS;
1806 (*seq_state->num_steps)++;
1807 }
1808 }
1809
1810 /*
1811 * Helper function to add OPP set dynamic expansion to block sequence
1812 */
hwss_add_opp_set_dyn_expansion(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum dc_color_space color_space,enum dc_color_depth color_depth,enum signal_type signal)1813 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,
1814 struct output_pixel_processor *opp,
1815 enum dc_color_space color_space,
1816 enum dc_color_depth color_depth,
1817 enum signal_type signal)
1818 {
1819 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1820 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp;
1821 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space;
1822 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth;
1823 seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal;
1824 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION;
1825 (*seq_state->num_steps)++;
1826 }
1827 }
1828
1829 /*
1830 * Helper function to add OPP program FMT to block sequence
1831 */
hwss_add_opp_program_fmt(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,struct bit_depth_reduction_params * fmt_bit_depth,struct clamping_and_pixel_encoding_params * clamping)1832 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,
1833 struct output_pixel_processor *opp,
1834 struct bit_depth_reduction_params *fmt_bit_depth,
1835 struct clamping_and_pixel_encoding_params *clamping)
1836 {
1837 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1838 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp;
1839 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth;
1840 seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping;
1841 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT;
1842 (*seq_state->num_steps)++;
1843 }
1844 }
1845
hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum dc_pixel_encoding pixel_encoding,bool is_otg_master)1846 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,
1847 struct output_pixel_processor *opp,
1848 enum dc_pixel_encoding pixel_encoding,
1849 bool is_otg_master)
1850 {
1851 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1852 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL;
1853 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp;
1854 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding;
1855 seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master;
1856 (*seq_state->num_steps)++;
1857 }
1858 }
1859
1860 /*
1861 * Helper function to add ABM set pipe to block sequence
1862 */
hwss_add_abm_set_pipe(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)1863 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,
1864 struct dc *dc,
1865 struct pipe_ctx *pipe_ctx)
1866 {
1867 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1868 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc;
1869 seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx;
1870 seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE;
1871 (*seq_state->num_steps)++;
1872 }
1873 }
1874
1875 /*
1876 * Helper function to add ABM set level to block sequence
1877 */
hwss_add_abm_set_level(struct block_sequence_state * seq_state,struct abm * abm,uint32_t abm_level)1878 void hwss_add_abm_set_level(struct block_sequence_state *seq_state,
1879 struct abm *abm,
1880 uint32_t abm_level)
1881 {
1882 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1883 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm;
1884 seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level;
1885 seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL;
1886 (*seq_state->num_steps)++;
1887 }
1888 }
1889
1890 /*
1891 * Helper function to add TG enable CRTC to block sequence
1892 */
hwss_add_tg_enable_crtc(struct block_sequence_state * seq_state,struct timing_generator * tg)1893 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,
1894 struct timing_generator *tg)
1895 {
1896 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1897 seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg;
1898 seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC;
1899 (*seq_state->num_steps)++;
1900 }
1901 }
1902
1903 /*
1904 * Helper function to add HUBP wait flip pending to block sequence
1905 */
hwss_add_hubp_wait_flip_pending(struct block_sequence_state * seq_state,struct hubp * hubp,unsigned int timeout_us,unsigned int polling_interval_us)1906 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,
1907 struct hubp *hubp,
1908 unsigned int timeout_us,
1909 unsigned int polling_interval_us)
1910 {
1911 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1912 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;
1913 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us;
1914 seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us;
1915 seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING;
1916 (*seq_state->num_steps)++;
1917 }
1918 }
1919
1920 /*
1921 * Helper function to add TG wait double buffer pending to block sequence
1922 */
hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state * seq_state,struct timing_generator * tg,unsigned int timeout_us,unsigned int polling_interval_us)1923 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,
1924 struct timing_generator *tg,
1925 unsigned int timeout_us,
1926 unsigned int polling_interval_us)
1927 {
1928 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
1929 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg;
1930 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us;
1931 seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us;
1932 seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING;
1933 (*seq_state->num_steps)++;
1934 }
1935 }
1936
hwss_program_manual_trigger(union block_sequence_params * params)1937 void hwss_program_manual_trigger(union block_sequence_params *params)
1938 {
1939 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
1940
1941 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
1942 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
1943 }
1944
hwss_setup_dpp(union block_sequence_params * params)1945 void hwss_setup_dpp(union block_sequence_params *params)
1946 {
1947 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
1948 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1949 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1950
1951 if (!plane_state)
1952 return;
1953
1954 if (dpp && dpp->funcs->dpp_setup) {
1955 // program the input csc
1956 dpp->funcs->dpp_setup(dpp,
1957 plane_state->format,
1958 EXPANSION_MODE_ZERO,
1959 plane_state->input_csc_color_matrix,
1960 plane_state->color_space,
1961 NULL);
1962 }
1963 }
1964
hwss_program_bias_and_scale(union block_sequence_params * params)1965 void hwss_program_bias_and_scale(union block_sequence_params *params)
1966 {
1967 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
1968 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1969 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1970 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
1971
1972 //TODO :for CNVC set scale and bias registers if necessary
1973 if (dpp->funcs->dpp_program_bias_and_scale)
1974 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1975 }
1976
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)1977 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
1978 {
1979 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
1980 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
1981 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
1982
1983 if (mpc->funcs->power_on_mpc_mem_pwr)
1984 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
1985 }
1986
hwss_set_output_csc(union block_sequence_params * params)1987 void hwss_set_output_csc(union block_sequence_params *params)
1988 {
1989 struct mpc *mpc = params->set_output_csc_params.mpc;
1990 int opp_id = params->set_output_csc_params.opp_id;
1991 const uint16_t *matrix = params->set_output_csc_params.regval;
1992 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
1993
1994 if (mpc->funcs->set_output_csc != NULL)
1995 mpc->funcs->set_output_csc(mpc,
1996 opp_id,
1997 matrix,
1998 ocsc_mode);
1999 }
2000
hwss_set_ocsc_default(union block_sequence_params * params)2001 void hwss_set_ocsc_default(union block_sequence_params *params)
2002 {
2003 struct mpc *mpc = params->set_ocsc_default_params.mpc;
2004 int opp_id = params->set_ocsc_default_params.opp_id;
2005 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
2006 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
2007
2008 if (mpc->funcs->set_ocsc_default != NULL)
2009 mpc->funcs->set_ocsc_default(mpc,
2010 opp_id,
2011 colorspace,
2012 ocsc_mode);
2013 }
2014
hwss_subvp_save_surf_addr(union block_sequence_params * params)2015 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
2016 {
2017 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
2018 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
2019 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
2020
2021 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
2022 }
2023
hwss_program_surface_config(union block_sequence_params * params)2024 void hwss_program_surface_config(union block_sequence_params *params)
2025 {
2026 struct hubp *hubp = params->program_surface_config_params.hubp;
2027 enum surface_pixel_format format = params->program_surface_config_params.format;
2028 struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info;
2029 struct plane_size size = params->program_surface_config_params.plane_size;
2030 enum dc_rotation_angle rotation = params->program_surface_config_params.rotation;
2031 struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc;
2032 bool horizontal_mirror = params->program_surface_config_params.horizontal_mirror;
2033 int compat_level = params->program_surface_config_params.compat_level;
2034
2035 hubp->funcs->hubp_program_surface_config(
2036 hubp,
2037 format,
2038 tiling_info,
2039 &size,
2040 rotation,
2041 dcc,
2042 horizontal_mirror,
2043 compat_level);
2044
2045 hubp->power_gated = false;
2046 }
2047
hwss_program_mcache_id_and_split_coordinate(union block_sequence_params * params)2048 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params)
2049 {
2050 struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp;
2051 struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs;
2052
2053 hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);
2054
2055 }
2056
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)2057 void get_surface_tile_visual_confirm_color(
2058 struct pipe_ctx *pipe_ctx,
2059 struct tg_color *color)
2060 {
2061 uint32_t color_value = MAX_TG_COLOR_VALUE;
2062 /* Determine the overscan color based on the bottom-most plane's context */
2063 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
2064
2065 while (bottom_pipe_ctx->bottom_pipe != NULL)
2066 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
2067
2068 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
2069 case DC_SW_LINEAR:
2070 /* LINEAR Surface - set border color to red */
2071 color->color_r_cr = color_value;
2072 break;
2073 default:
2074 break;
2075 }
2076 }
2077
2078 /**
2079 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
2080 * pattern updates
2081 *
2082 * @dc: [in] dc reference
2083 * @context: [in] hardware context in use
2084 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)2085 void hwss_wait_for_all_blank_complete(struct dc *dc,
2086 struct dc_state *context)
2087 {
2088 struct pipe_ctx *opp_head;
2089 struct dce_hwseq *hws = dc->hwseq;
2090 int i;
2091
2092 if (!hws->funcs.wait_for_blank_complete)
2093 return;
2094
2095 for (i = 0; i < MAX_PIPES; i++) {
2096 opp_head = &context->res_ctx.pipe_ctx[i];
2097
2098 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
2099 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
2100 continue;
2101
2102 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
2103 }
2104 }
2105
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)2106 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
2107 {
2108 struct pipe_ctx *otg_master;
2109 struct timing_generator *tg;
2110 int i;
2111
2112 for (i = 0; i < MAX_PIPES; i++) {
2113 otg_master = &context->res_ctx.pipe_ctx[i];
2114 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
2115 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
2116 continue;
2117 tg = otg_master->stream_res.tg;
2118 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
2119 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
2120 if (tg->funcs->wait_otg_disable)
2121 tg->funcs->wait_otg_disable(tg);
2122 }
2123
2124 /* ODM update may require to reprogram blank pattern for each OPP */
2125 hwss_wait_for_all_blank_complete(dc, context);
2126 }
2127
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)2128 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
2129 {
2130 int i;
2131
2132 for (i = 0; i < MAX_PIPES; i++) {
2133 int count = 0;
2134 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2135
2136 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
2137 continue;
2138
2139 /* Timeout 100 ms */
2140 while (count < 100000) {
2141 /* Must set to false to start with, due to OR in update function */
2142 pipe->plane_state->status.is_flip_pending = false;
2143 dc->hwss.update_pending_status(pipe);
2144 if (!pipe->plane_state->status.is_flip_pending)
2145 break;
2146 udelay(1);
2147 count++;
2148 }
2149 ASSERT(!pipe->plane_state->status.is_flip_pending);
2150 }
2151 }
2152
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)2153 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
2154 {
2155 /*
2156 * This function calls HWSS to wait for any potentially double buffered
2157 * operations to complete. It should be invoked as a pre-amble prior
2158 * to full update programming before asserting any HW locks.
2159 */
2160 int pipe_idx;
2161 int opp_inst;
2162 int opp_count = dc->res_pool->res_cap->num_opp;
2163 struct hubp *hubp;
2164 int mpcc_inst;
2165 const struct pipe_ctx *pipe_ctx;
2166
2167 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
2168 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
2169
2170 if (!pipe_ctx->stream)
2171 continue;
2172
2173 /* For full update we must wait for all double buffer updates, not just DRR updates. This
2174 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes,
2175 * as non-OTG Master pipes share the same OTG as
2176 */
2177 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {
2178 dc->hwss.wait_for_all_pending_updates(pipe_ctx);
2179 }
2180
2181 hubp = pipe_ctx->plane_res.hubp;
2182 if (!hubp)
2183 continue;
2184
2185 mpcc_inst = hubp->inst;
2186 // MPCC inst is equal to pipe index in practice
2187 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
2188 if ((dc->res_pool->opps[opp_inst] != NULL) &&
2189 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
2190 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
2191 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
2192 break;
2193 }
2194 }
2195 }
2196 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
2197 }
2198
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)2199 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
2200 {
2201 /* wait for outstanding updates */
2202 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
2203
2204 /* perform outstanding post update programming */
2205 if (dc->hwss.program_outstanding_updates)
2206 dc->hwss.program_outstanding_updates(dc, dc_context);
2207 }
2208
hwss_set_odm_combine(union block_sequence_params * params)2209 void hwss_set_odm_combine(union block_sequence_params *params)
2210 {
2211 struct timing_generator *tg = params->set_odm_combine_params.tg;
2212 int *opp_inst = params->set_odm_combine_params.opp_inst;
2213 int opp_head_count = params->set_odm_combine_params.opp_head_count;
2214 int odm_slice_width = params->set_odm_combine_params.odm_slice_width;
2215 int last_odm_slice_width = params->set_odm_combine_params.last_odm_slice_width;
2216
2217 if (tg && tg->funcs->set_odm_combine)
2218 tg->funcs->set_odm_combine(tg, opp_inst, opp_head_count,
2219 odm_slice_width, last_odm_slice_width);
2220 }
2221
hwss_set_odm_bypass(union block_sequence_params * params)2222 void hwss_set_odm_bypass(union block_sequence_params *params)
2223 {
2224 struct timing_generator *tg = params->set_odm_bypass_params.tg;
2225 const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing;
2226
2227 if (tg && tg->funcs->set_odm_bypass)
2228 tg->funcs->set_odm_bypass(tg, timing);
2229 }
2230
hwss_opp_pipe_clock_control(union block_sequence_params * params)2231 void hwss_opp_pipe_clock_control(union block_sequence_params *params)
2232 {
2233 struct output_pixel_processor *opp = params->opp_pipe_clock_control_params.opp;
2234 bool enable = params->opp_pipe_clock_control_params.enable;
2235
2236 if (opp && opp->funcs->opp_pipe_clock_control)
2237 opp->funcs->opp_pipe_clock_control(opp, enable);
2238 }
2239
hwss_opp_program_left_edge_extra_pixel(union block_sequence_params * params)2240 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params)
2241 {
2242 struct output_pixel_processor *opp = params->opp_program_left_edge_extra_pixel_params.opp;
2243 enum dc_pixel_encoding pixel_encoding = params->opp_program_left_edge_extra_pixel_params.pixel_encoding;
2244 bool is_otg_master = params->opp_program_left_edge_extra_pixel_params.is_otg_master;
2245
2246 if (opp && opp->funcs->opp_program_left_edge_extra_pixel)
2247 opp->funcs->opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master);
2248 }
2249
hwss_dccg_set_dto_dscclk(union block_sequence_params * params)2250 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params)
2251 {
2252 struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg;
2253 int inst = params->dccg_set_dto_dscclk_params.inst;
2254 int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h;
2255
2256 if (dccg && dccg->funcs->set_dto_dscclk)
2257 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h);
2258 }
2259
hwss_dsc_set_config(union block_sequence_params * params)2260 void hwss_dsc_set_config(union block_sequence_params *params)
2261 {
2262 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc;
2263 struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg;
2264 struct dsc_optc_config *dsc_optc_cfg = params->dsc_set_config_params.dsc_optc_cfg;
2265
2266 if (dsc && dsc->funcs->dsc_set_config)
2267 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg);
2268 }
2269
hwss_dsc_enable(union block_sequence_params * params)2270 void hwss_dsc_enable(union block_sequence_params *params)
2271 {
2272 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc;
2273 int opp_inst = params->dsc_enable_params.opp_inst;
2274
2275 if (dsc && dsc->funcs->dsc_enable)
2276 dsc->funcs->dsc_enable(dsc, opp_inst);
2277 }
2278
hwss_tg_set_dsc_config(union block_sequence_params * params)2279 void hwss_tg_set_dsc_config(union block_sequence_params *params)
2280 {
2281 struct timing_generator *tg = params->tg_set_dsc_config_params.tg;
2282 enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED;
2283 uint32_t bytes_per_pixel = 0;
2284 uint32_t slice_width = 0;
2285
2286 if (params->tg_set_dsc_config_params.enable) {
2287 struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg;
2288
2289 if (dsc_optc_cfg) {
2290 bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel;
2291 slice_width = dsc_optc_cfg->slice_width;
2292 optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ?
2293 OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
2294 }
2295 }
2296
2297 if (tg && tg->funcs->set_dsc_config)
2298 tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width);
2299 }
2300
hwss_dsc_disconnect(union block_sequence_params * params)2301 void hwss_dsc_disconnect(union block_sequence_params *params)
2302 {
2303 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc;
2304
2305 if (dsc && dsc->funcs->dsc_disconnect)
2306 dsc->funcs->dsc_disconnect(dsc);
2307 }
2308
hwss_dsc_read_state(union block_sequence_params * params)2309 void hwss_dsc_read_state(union block_sequence_params *params)
2310 {
2311 struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc;
2312 struct dcn_dsc_state *dsc_state = params->dsc_read_state_params.dsc_state;
2313
2314 if (dsc && dsc->funcs->dsc_read_state)
2315 dsc->funcs->dsc_read_state(dsc, dsc_state);
2316 }
2317
hwss_dsc_calculate_and_set_config(union block_sequence_params * params)2318 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params)
2319 {
2320 struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx;
2321 struct pipe_ctx *top_pipe = pipe_ctx;
2322 bool enable = params->dsc_calculate_and_set_config_params.enable;
2323 int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt;
2324
2325 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
2326 struct dc_stream_state *stream = pipe_ctx->stream;
2327
2328 if (!dsc || !enable)
2329 return;
2330
2331 /* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */
2332 struct dsc_config dsc_cfg;
2333
2334 while (top_pipe->prev_odm_pipe)
2335 top_pipe = top_pipe->prev_odm_pipe;
2336
2337 dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding +
2338 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
2339 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
2340 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2341 dsc_cfg.color_depth = stream->timing.display_color_depth;
2342 dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false;
2343 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2344 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2345 dsc_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding;
2346
2347 /* Set DSC configuration */
2348 if (dsc->funcs->dsc_set_config)
2349 dsc->funcs->dsc_set_config(dsc, &dsc_cfg,
2350 ¶ms->dsc_calculate_and_set_config_params.dsc_optc_cfg);
2351 }
2352
hwss_dsc_enable_with_opp(union block_sequence_params * params)2353 void hwss_dsc_enable_with_opp(union block_sequence_params *params)
2354 {
2355 struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx;
2356 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
2357
2358 if (dsc && dsc->funcs->dsc_enable)
2359 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
2360 }
2361
hwss_tg_program_global_sync(union block_sequence_params * params)2362 void hwss_tg_program_global_sync(union block_sequence_params *params)
2363 {
2364 struct timing_generator *tg = params->tg_program_global_sync_params.tg;
2365 int vready_offset = params->tg_program_global_sync_params.vready_offset;
2366 unsigned int vstartup_lines = params->tg_program_global_sync_params.vstartup_lines;
2367 unsigned int vupdate_offset_pixels = params->tg_program_global_sync_params.vupdate_offset_pixels;
2368 unsigned int vupdate_vupdate_width_pixels = params->tg_program_global_sync_params.vupdate_vupdate_width_pixels;
2369 unsigned int pstate_keepout_start_lines = params->tg_program_global_sync_params.pstate_keepout_start_lines;
2370
2371 if (tg->funcs->program_global_sync) {
2372 tg->funcs->program_global_sync(tg, vready_offset, vstartup_lines,
2373 vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines);
2374 }
2375 }
2376
hwss_tg_wait_for_state(union block_sequence_params * params)2377 void hwss_tg_wait_for_state(union block_sequence_params *params)
2378 {
2379 struct timing_generator *tg = params->tg_wait_for_state_params.tg;
2380 enum crtc_state state = params->tg_wait_for_state_params.state;
2381
2382 if (tg->funcs->wait_for_state)
2383 tg->funcs->wait_for_state(tg, state);
2384 }
2385
hwss_tg_set_vtg_params(union block_sequence_params * params)2386 void hwss_tg_set_vtg_params(union block_sequence_params *params)
2387 {
2388 struct timing_generator *tg = params->tg_set_vtg_params_params.tg;
2389 struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing;
2390 bool program_fp2 = params->tg_set_vtg_params_params.program_fp2;
2391
2392 if (tg->funcs->set_vtg_params)
2393 tg->funcs->set_vtg_params(tg, timing, program_fp2);
2394 }
2395
hwss_tg_setup_vertical_interrupt2(union block_sequence_params * params)2396 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params)
2397 {
2398 struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg;
2399 int start_line = params->tg_setup_vertical_interrupt2_params.start_line;
2400
2401 if (tg->funcs->setup_vertical_interrupt2)
2402 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2403 }
2404
hwss_dpp_set_hdr_multiplier(union block_sequence_params * params)2405 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params)
2406 {
2407 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp;
2408 uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult;
2409
2410 if (dpp->funcs->dpp_set_hdr_multiplier)
2411 dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult);
2412 }
2413
hwss_program_det_size(union block_sequence_params * params)2414 void hwss_program_det_size(union block_sequence_params *params)
2415 {
2416 struct hubbub *hubbub = params->program_det_size_params.hubbub;
2417 unsigned int hubp_inst = params->program_det_size_params.hubp_inst;
2418 unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb;
2419
2420 if (hubbub->funcs->program_det_size)
2421 hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb);
2422 }
2423
hwss_program_det_segments(union block_sequence_params * params)2424 void hwss_program_det_segments(union block_sequence_params *params)
2425 {
2426 struct hubbub *hubbub = params->program_det_segments_params.hubbub;
2427 unsigned int hubp_inst = params->program_det_segments_params.hubp_inst;
2428 unsigned int det_size = params->program_det_segments_params.det_size;
2429
2430 if (hubbub->funcs->program_det_segments)
2431 hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size);
2432 }
2433
hwss_opp_set_dyn_expansion(union block_sequence_params * params)2434 void hwss_opp_set_dyn_expansion(union block_sequence_params *params)
2435 {
2436 struct output_pixel_processor *opp = params->opp_set_dyn_expansion_params.opp;
2437 enum dc_color_space color_space = params->opp_set_dyn_expansion_params.color_space;
2438 enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth;
2439 enum signal_type signal = params->opp_set_dyn_expansion_params.signal;
2440
2441 if (opp->funcs->opp_set_dyn_expansion)
2442 opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal);
2443 }
2444
hwss_opp_program_fmt(union block_sequence_params * params)2445 void hwss_opp_program_fmt(union block_sequence_params *params)
2446 {
2447 struct output_pixel_processor *opp = params->opp_program_fmt_params.opp;
2448 struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth;
2449 struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping;
2450
2451 if (opp->funcs->opp_program_fmt)
2452 opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping);
2453 }
2454
hwss_opp_program_bit_depth_reduction(union block_sequence_params * params)2455 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params)
2456 {
2457 struct output_pixel_processor *opp = params->opp_program_bit_depth_reduction_params.opp;
2458 bool use_default_params = params->opp_program_bit_depth_reduction_params.use_default_params;
2459 struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx;
2460 struct bit_depth_reduction_params bit_depth_params;
2461
2462 if (use_default_params)
2463 memset(&bit_depth_params, 0, sizeof(bit_depth_params));
2464 else
2465 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params);
2466
2467 if (opp->funcs->opp_program_bit_depth_reduction)
2468 opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params);
2469 }
2470
hwss_opp_set_disp_pattern_generator(union block_sequence_params * params)2471 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params)
2472 {
2473 struct output_pixel_processor *opp = params->opp_set_disp_pattern_generator_params.opp;
2474 enum controller_dp_test_pattern test_pattern = params->opp_set_disp_pattern_generator_params.test_pattern;
2475 enum controller_dp_color_space color_space = params->opp_set_disp_pattern_generator_params.color_space;
2476 enum dc_color_depth color_depth = params->opp_set_disp_pattern_generator_params.color_depth;
2477 struct tg_color *solid_color = params->opp_set_disp_pattern_generator_params.use_solid_color ?
2478 ¶ms->opp_set_disp_pattern_generator_params.solid_color : NULL;
2479 int width = params->opp_set_disp_pattern_generator_params.width;
2480 int height = params->opp_set_disp_pattern_generator_params.height;
2481 int offset = params->opp_set_disp_pattern_generator_params.offset;
2482
2483 if (opp && opp->funcs->opp_set_disp_pattern_generator) {
2484 opp->funcs->opp_set_disp_pattern_generator(opp, test_pattern, color_space,
2485 color_depth, solid_color, width, height, offset);
2486 }
2487 }
2488
hwss_set_abm_pipe(union block_sequence_params * params)2489 void hwss_set_abm_pipe(union block_sequence_params *params)
2490 {
2491 struct dc *dc = params->set_abm_pipe_params.dc;
2492 struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx;
2493
2494 dc->hwss.set_pipe(pipe_ctx);
2495 }
2496
hwss_set_abm_level(union block_sequence_params * params)2497 void hwss_set_abm_level(union block_sequence_params *params)
2498 {
2499 struct abm *abm = params->set_abm_level_params.abm;
2500 unsigned int abm_level = params->set_abm_level_params.abm_level;
2501
2502 if (abm->funcs->set_abm_level)
2503 abm->funcs->set_abm_level(abm, abm_level);
2504 }
2505
hwss_set_abm_immediate_disable(union block_sequence_params * params)2506 void hwss_set_abm_immediate_disable(union block_sequence_params *params)
2507 {
2508 struct dc *dc = params->set_abm_immediate_disable_params.dc;
2509 struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx;
2510
2511 if (dc && dc->hwss.set_abm_immediate_disable)
2512 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2513 }
2514
hwss_mpc_remove_mpcc(union block_sequence_params * params)2515 void hwss_mpc_remove_mpcc(union block_sequence_params *params)
2516 {
2517 struct mpc *mpc = params->mpc_remove_mpcc_params.mpc;
2518 struct mpc_tree *mpc_tree_params = params->mpc_remove_mpcc_params.mpc_tree_params;
2519 struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove;
2520
2521 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
2522 }
2523
hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params * params)2524 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params)
2525 {
2526 struct output_pixel_processor *opp = params->opp_set_mpcc_disconnect_pending_params.opp;
2527 int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst;
2528 bool pending = params->opp_set_mpcc_disconnect_pending_params.pending;
2529
2530 opp->mpcc_disconnect_pending[mpcc_inst] = pending;
2531 }
2532
hwss_dc_set_optimized_required(union block_sequence_params * params)2533 void hwss_dc_set_optimized_required(union block_sequence_params *params)
2534 {
2535 struct dc *dc = params->dc_set_optimized_required_params.dc;
2536 bool optimized_required = params->dc_set_optimized_required_params.optimized_required;
2537
2538 dc->optimized_required = optimized_required;
2539 }
2540
hwss_hubp_disconnect(union block_sequence_params * params)2541 void hwss_hubp_disconnect(union block_sequence_params *params)
2542 {
2543 struct hubp *hubp = params->hubp_disconnect_params.hubp;
2544
2545 if (hubp->funcs->hubp_disconnect)
2546 hubp->funcs->hubp_disconnect(hubp);
2547 }
2548
hwss_hubbub_force_pstate_change_control(union block_sequence_params * params)2549 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params)
2550 {
2551 struct hubbub *hubbub = params->hubbub_force_pstate_change_control_params.hubbub;
2552 bool enable = params->hubbub_force_pstate_change_control_params.enable;
2553 bool wait = params->hubbub_force_pstate_change_control_params.wait;
2554
2555 if (hubbub->funcs->force_pstate_change_control) {
2556 hubbub->funcs->force_pstate_change_control(hubbub, enable, wait);
2557 /* Add delay when enabling pstate change control */
2558 if (enable)
2559 udelay(500);
2560 }
2561 }
2562
hwss_tg_enable_crtc(union block_sequence_params * params)2563 void hwss_tg_enable_crtc(union block_sequence_params *params)
2564 {
2565 struct timing_generator *tg = params->tg_enable_crtc_params.tg;
2566
2567 if (tg->funcs->enable_crtc)
2568 tg->funcs->enable_crtc(tg);
2569 }
2570
hwss_tg_set_gsl(union block_sequence_params * params)2571 void hwss_tg_set_gsl(union block_sequence_params *params)
2572 {
2573 struct timing_generator *tg = params->tg_set_gsl_params.tg;
2574 struct gsl_params *gsl = ¶ms->tg_set_gsl_params.gsl;
2575
2576 if (tg->funcs->set_gsl)
2577 tg->funcs->set_gsl(tg, gsl);
2578 }
2579
hwss_tg_set_gsl_source_select(union block_sequence_params * params)2580 void hwss_tg_set_gsl_source_select(union block_sequence_params *params)
2581 {
2582 struct timing_generator *tg = params->tg_set_gsl_source_select_params.tg;
2583 int group_idx = params->tg_set_gsl_source_select_params.group_idx;
2584 uint32_t gsl_ready_signal = params->tg_set_gsl_source_select_params.gsl_ready_signal;
2585
2586 if (tg->funcs->set_gsl_source_select)
2587 tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal);
2588 }
2589
hwss_hubp_wait_flip_pending(union block_sequence_params * params)2590 void hwss_hubp_wait_flip_pending(union block_sequence_params *params)
2591 {
2592 struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp;
2593 unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us;
2594 unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us;
2595 int j = 0;
2596
2597 for (j = 0; j < timeout_us / polling_interval_us
2598 && hubp->funcs->hubp_is_flip_pending(hubp); j++)
2599 udelay(polling_interval_us);
2600 }
2601
hwss_tg_wait_double_buffer_pending(union block_sequence_params * params)2602 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params)
2603 {
2604 struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg;
2605 unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us;
2606 unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us;
2607 int j = 0;
2608
2609 if (tg->funcs->get_optc_double_buffer_pending) {
2610 for (j = 0; j < timeout_us / polling_interval_us
2611 && tg->funcs->get_optc_double_buffer_pending(tg); j++)
2612 udelay(polling_interval_us);
2613 }
2614 }
2615
hwss_update_force_pstate(union block_sequence_params * params)2616 void hwss_update_force_pstate(union block_sequence_params *params)
2617 {
2618 struct dc *dc = params->update_force_pstate_params.dc;
2619 struct dc_state *context = params->update_force_pstate_params.context;
2620 struct dce_hwseq *hwseq = dc->hwseq;
2621
2622 if (hwseq->funcs.update_force_pstate)
2623 hwseq->funcs.update_force_pstate(dc, context);
2624 }
2625
hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params * params)2626 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params)
2627 {
2628 struct hubbub *hubbub = params->hubbub_apply_dedcn21_147_wa_params.hubbub;
2629
2630 hubbub->funcs->apply_DEDCN21_147_wa(hubbub);
2631 }
2632
hwss_hubbub_allow_self_refresh_control(union block_sequence_params * params)2633 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params)
2634 {
2635 struct hubbub *hubbub = params->hubbub_allow_self_refresh_control_params.hubbub;
2636 bool allow = params->hubbub_allow_self_refresh_control_params.allow;
2637
2638 hubbub->funcs->allow_self_refresh_control(hubbub, allow);
2639
2640 if (!allow && params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied)
2641 *params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true;
2642 }
2643
hwss_tg_get_frame_count(union block_sequence_params * params)2644 void hwss_tg_get_frame_count(union block_sequence_params *params)
2645 {
2646 struct timing_generator *tg = params->tg_get_frame_count_params.tg;
2647 unsigned int *frame_count = params->tg_get_frame_count_params.frame_count;
2648
2649 *frame_count = tg->funcs->get_frame_count(tg);
2650 }
2651
hwss_mpc_set_dwb_mux(union block_sequence_params * params)2652 void hwss_mpc_set_dwb_mux(union block_sequence_params *params)
2653 {
2654 struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc;
2655 int dwb_id = params->mpc_set_dwb_mux_params.dwb_id;
2656 int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id;
2657
2658 if (mpc->funcs->set_dwb_mux)
2659 mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id);
2660 }
2661
hwss_mpc_disable_dwb_mux(union block_sequence_params * params)2662 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params)
2663 {
2664 struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc;
2665 unsigned int dwb_id = params->mpc_disable_dwb_mux_params.dwb_id;
2666
2667 if (mpc->funcs->disable_dwb_mux)
2668 mpc->funcs->disable_dwb_mux(mpc, dwb_id);
2669 }
2670
hwss_mcif_wb_config_buf(union block_sequence_params * params)2671 void hwss_mcif_wb_config_buf(union block_sequence_params *params)
2672 {
2673 struct mcif_wb *mcif_wb = params->mcif_wb_config_buf_params.mcif_wb;
2674 struct mcif_buf_params *mcif_buf_params = params->mcif_wb_config_buf_params.mcif_buf_params;
2675 unsigned int dest_height = params->mcif_wb_config_buf_params.dest_height;
2676
2677 if (mcif_wb->funcs->config_mcif_buf)
2678 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, dest_height);
2679 }
2680
hwss_mcif_wb_config_arb(union block_sequence_params * params)2681 void hwss_mcif_wb_config_arb(union block_sequence_params *params)
2682 {
2683 struct mcif_wb *mcif_wb = params->mcif_wb_config_arb_params.mcif_wb;
2684 struct mcif_arb_params *mcif_arb_params = params->mcif_wb_config_arb_params.mcif_arb_params;
2685
2686 if (mcif_wb->funcs->config_mcif_arb)
2687 mcif_wb->funcs->config_mcif_arb(mcif_wb, mcif_arb_params);
2688 }
2689
hwss_mcif_wb_enable(union block_sequence_params * params)2690 void hwss_mcif_wb_enable(union block_sequence_params *params)
2691 {
2692 struct mcif_wb *mcif_wb = params->mcif_wb_enable_params.mcif_wb;
2693
2694 if (mcif_wb->funcs->enable_mcif)
2695 mcif_wb->funcs->enable_mcif(mcif_wb);
2696 }
2697
hwss_mcif_wb_disable(union block_sequence_params * params)2698 void hwss_mcif_wb_disable(union block_sequence_params *params)
2699 {
2700 struct mcif_wb *mcif_wb = params->mcif_wb_disable_params.mcif_wb;
2701
2702 if (mcif_wb->funcs->disable_mcif)
2703 mcif_wb->funcs->disable_mcif(mcif_wb);
2704 }
2705
hwss_dwbc_enable(union block_sequence_params * params)2706 void hwss_dwbc_enable(union block_sequence_params *params)
2707 {
2708 struct dwbc *dwb = params->dwbc_enable_params.dwb;
2709 struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params;
2710
2711 if (dwb->funcs->enable)
2712 dwb->funcs->enable(dwb, dwb_params);
2713 }
2714
hwss_dwbc_disable(union block_sequence_params * params)2715 void hwss_dwbc_disable(union block_sequence_params *params)
2716 {
2717 struct dwbc *dwb = params->dwbc_disable_params.dwb;
2718
2719 if (dwb->funcs->disable)
2720 dwb->funcs->disable(dwb);
2721 }
2722
hwss_dwbc_update(union block_sequence_params * params)2723 void hwss_dwbc_update(union block_sequence_params *params)
2724 {
2725 struct dwbc *dwb = params->dwbc_update_params.dwb;
2726 struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params;
2727
2728 if (dwb->funcs->update)
2729 dwb->funcs->update(dwb, dwb_params);
2730 }
2731
hwss_hubp_update_mall_sel(union block_sequence_params * params)2732 void hwss_hubp_update_mall_sel(union block_sequence_params *params)
2733 {
2734 struct hubp *hubp = params->hubp_update_mall_sel_params.hubp;
2735 uint32_t mall_sel = params->hubp_update_mall_sel_params.mall_sel;
2736 bool cache_cursor = params->hubp_update_mall_sel_params.cache_cursor;
2737
2738 if (hubp && hubp->funcs->hubp_update_mall_sel)
2739 hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor);
2740 }
2741
hwss_hubp_prepare_subvp_buffering(union block_sequence_params * params)2742 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params)
2743 {
2744 struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp;
2745 bool enable = params->hubp_prepare_subvp_buffering_params.enable;
2746
2747 if (hubp && hubp->funcs->hubp_prepare_subvp_buffering)
2748 hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable);
2749 }
2750
hwss_hubp_set_blank_en(union block_sequence_params * params)2751 void hwss_hubp_set_blank_en(union block_sequence_params *params)
2752 {
2753 struct hubp *hubp = params->hubp_set_blank_en_params.hubp;
2754 bool enable = params->hubp_set_blank_en_params.enable;
2755
2756 if (hubp && hubp->funcs->set_hubp_blank_en)
2757 hubp->funcs->set_hubp_blank_en(hubp, enable);
2758 }
2759
hwss_hubp_disable_control(union block_sequence_params * params)2760 void hwss_hubp_disable_control(union block_sequence_params *params)
2761 {
2762 struct hubp *hubp = params->hubp_disable_control_params.hubp;
2763 bool disable = params->hubp_disable_control_params.disable;
2764
2765 if (hubp && hubp->funcs->hubp_disable_control)
2766 hubp->funcs->hubp_disable_control(hubp, disable);
2767 }
2768
hwss_hubbub_soft_reset(union block_sequence_params * params)2769 void hwss_hubbub_soft_reset(union block_sequence_params *params)
2770 {
2771 struct hubbub *hubbub = params->hubbub_soft_reset_params.hubbub;
2772 bool reset = params->hubbub_soft_reset_params.reset;
2773
2774 if (hubbub)
2775 params->hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset);
2776 }
2777
hwss_hubp_clk_cntl(union block_sequence_params * params)2778 void hwss_hubp_clk_cntl(union block_sequence_params *params)
2779 {
2780 struct hubp *hubp = params->hubp_clk_cntl_params.hubp;
2781 bool enable = params->hubp_clk_cntl_params.enable;
2782
2783 if (hubp && hubp->funcs->hubp_clk_cntl) {
2784 hubp->funcs->hubp_clk_cntl(hubp, enable);
2785 hubp->power_gated = !enable;
2786 }
2787 }
2788
hwss_hubp_init(union block_sequence_params * params)2789 void hwss_hubp_init(union block_sequence_params *params)
2790 {
2791 struct hubp *hubp = params->hubp_init_params.hubp;
2792
2793 if (hubp && hubp->funcs->hubp_init)
2794 hubp->funcs->hubp_init(hubp);
2795 }
2796
hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params * params)2797 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params)
2798 {
2799 struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp;
2800 struct vm_system_aperture_param apt;
2801
2802 apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default;
2803 apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high;
2804 apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low;
2805
2806 if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings)
2807 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
2808 }
2809
hwss_hubp_set_flip_int(union block_sequence_params * params)2810 void hwss_hubp_set_flip_int(union block_sequence_params *params)
2811 {
2812 struct hubp *hubp = params->hubp_set_flip_int_params.hubp;
2813
2814 if (hubp && hubp->funcs->hubp_set_flip_int)
2815 hubp->funcs->hubp_set_flip_int(hubp);
2816 }
2817
hwss_dpp_dppclk_control(union block_sequence_params * params)2818 void hwss_dpp_dppclk_control(union block_sequence_params *params)
2819 {
2820 struct dpp *dpp = params->dpp_dppclk_control_params.dpp;
2821 bool dppclk_div = params->dpp_dppclk_control_params.dppclk_div;
2822 bool enable = params->dpp_dppclk_control_params.enable;
2823
2824 if (dpp && dpp->funcs->dpp_dppclk_control)
2825 dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable);
2826 }
2827
hwss_disable_phantom_crtc(union block_sequence_params * params)2828 void hwss_disable_phantom_crtc(union block_sequence_params *params)
2829 {
2830 struct timing_generator *tg = params->disable_phantom_crtc_params.tg;
2831
2832 if (tg && tg->funcs->disable_phantom_crtc)
2833 tg->funcs->disable_phantom_crtc(tg);
2834 }
2835
hwss_dsc_pg_status(union block_sequence_params * params)2836 void hwss_dsc_pg_status(union block_sequence_params *params)
2837 {
2838 struct dce_hwseq *hws = params->dsc_pg_status_params.hws;
2839 int dsc_inst = params->dsc_pg_status_params.dsc_inst;
2840
2841 if (hws && hws->funcs.dsc_pg_status)
2842 params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst);
2843 }
2844
hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params * params)2845 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params)
2846 {
2847 struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc;
2848
2849 if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated)
2850 return;
2851 if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false)
2852 return;
2853
2854 if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear)
2855 dsc->funcs->dsc_wait_disconnect_pending_clear(dsc);
2856 }
2857
hwss_dsc_disable(union block_sequence_params * params)2858 void hwss_dsc_disable(union block_sequence_params *params)
2859 {
2860 struct display_stream_compressor *dsc = params->dsc_disable_params.dsc;
2861
2862 if (!params->dsc_disable_params.is_ungated)
2863 return;
2864 if (*params->dsc_disable_params.is_ungated == false)
2865 return;
2866
2867 if (dsc && dsc->funcs->dsc_disable)
2868 dsc->funcs->dsc_disable(dsc);
2869 }
2870
hwss_dccg_set_ref_dscclk(union block_sequence_params * params)2871 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params)
2872 {
2873 struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg;
2874 int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst;
2875
2876 if (!params->dccg_set_ref_dscclk_params.is_ungated)
2877 return;
2878 if (*params->dccg_set_ref_dscclk_params.is_ungated == false)
2879 return;
2880
2881 if (dccg && dccg->funcs->set_ref_dscclk)
2882 dccg->funcs->set_ref_dscclk(dccg, dsc_inst);
2883 }
2884
hwss_dpp_pg_control(union block_sequence_params * params)2885 void hwss_dpp_pg_control(union block_sequence_params *params)
2886 {
2887 struct dce_hwseq *hws = params->dpp_pg_control_params.hws;
2888 unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst;
2889 bool power_on = params->dpp_pg_control_params.power_on;
2890
2891 if (hws->funcs.dpp_pg_control)
2892 hws->funcs.dpp_pg_control(hws, dpp_inst, power_on);
2893 }
2894
hwss_hubp_pg_control(union block_sequence_params * params)2895 void hwss_hubp_pg_control(union block_sequence_params *params)
2896 {
2897 struct dce_hwseq *hws = params->hubp_pg_control_params.hws;
2898 unsigned int hubp_inst = params->hubp_pg_control_params.hubp_inst;
2899 bool power_on = params->hubp_pg_control_params.power_on;
2900
2901 if (hws->funcs.hubp_pg_control)
2902 hws->funcs.hubp_pg_control(hws, hubp_inst, power_on);
2903 }
2904
hwss_hubp_reset(union block_sequence_params * params)2905 void hwss_hubp_reset(union block_sequence_params *params)
2906 {
2907 struct hubp *hubp = params->hubp_reset_params.hubp;
2908
2909 if (hubp && hubp->funcs->hubp_reset)
2910 hubp->funcs->hubp_reset(hubp);
2911 }
2912
hwss_dpp_reset(union block_sequence_params * params)2913 void hwss_dpp_reset(union block_sequence_params *params)
2914 {
2915 struct dpp *dpp = params->dpp_reset_params.dpp;
2916
2917 if (dpp && dpp->funcs->dpp_reset)
2918 dpp->funcs->dpp_reset(dpp);
2919 }
2920
hwss_dpp_root_clock_control(union block_sequence_params * params)2921 void hwss_dpp_root_clock_control(union block_sequence_params *params)
2922 {
2923 struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws;
2924 unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst;
2925 bool clock_on = params->dpp_root_clock_control_params.clock_on;
2926
2927 if (hws->funcs.dpp_root_clock_control)
2928 hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on);
2929 }
2930
hwss_dc_ip_request_cntl(union block_sequence_params * params)2931 void hwss_dc_ip_request_cntl(union block_sequence_params *params)
2932 {
2933 struct dc *dc = params->dc_ip_request_cntl_params.dc;
2934 bool enable = params->dc_ip_request_cntl_params.enable;
2935 struct dce_hwseq *hws = dc->hwseq;
2936
2937 if (hws->funcs.dc_ip_request_cntl)
2938 hws->funcs.dc_ip_request_cntl(dc, enable);
2939 }
2940
hwss_dccg_update_dpp_dto(union block_sequence_params * params)2941 void hwss_dccg_update_dpp_dto(union block_sequence_params *params)
2942 {
2943 struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg;
2944 int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst;
2945 int dppclk_khz = params->dccg_update_dpp_dto_params.dppclk_khz;
2946
2947 if (dccg && dccg->funcs->update_dpp_dto)
2948 dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz);
2949 }
2950
hwss_hubp_vtg_sel(union block_sequence_params * params)2951 void hwss_hubp_vtg_sel(union block_sequence_params *params)
2952 {
2953 struct hubp *hubp = params->hubp_vtg_sel_params.hubp;
2954 uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst;
2955
2956 if (hubp && hubp->funcs->hubp_vtg_sel)
2957 hubp->funcs->hubp_vtg_sel(hubp, otg_inst);
2958 }
2959
hwss_hubp_setup2(union block_sequence_params * params)2960 void hwss_hubp_setup2(union block_sequence_params *params)
2961 {
2962 struct hubp *hubp = params->hubp_setup2_params.hubp;
2963 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs;
2964 union dml2_global_sync_programming *global_sync = params->hubp_setup2_params.global_sync;
2965 struct dc_crtc_timing *timing = params->hubp_setup2_params.timing;
2966
2967 if (hubp && hubp->funcs->hubp_setup2)
2968 hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);
2969 }
2970
hwss_hubp_setup(union block_sequence_params * params)2971 void hwss_hubp_setup(union block_sequence_params *params)
2972 {
2973 struct hubp *hubp = params->hubp_setup_params.hubp;
2974 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs;
2975 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs;
2976 struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs;
2977 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params->hubp_setup_params.pipe_dest;
2978
2979 if (hubp && hubp->funcs->hubp_setup)
2980 hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest);
2981 }
2982
hwss_hubp_set_unbounded_requesting(union block_sequence_params * params)2983 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params)
2984 {
2985 struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp;
2986 bool unbounded_req = params->hubp_set_unbounded_requesting_params.unbounded_req;
2987
2988 if (hubp && hubp->funcs->set_unbounded_requesting)
2989 hubp->funcs->set_unbounded_requesting(hubp, unbounded_req);
2990 }
2991
hwss_hubp_setup_interdependent2(union block_sequence_params * params)2992 void hwss_hubp_setup_interdependent2(union block_sequence_params *params)
2993 {
2994 struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp;
2995 struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs;
2996
2997 if (hubp && hubp->funcs->hubp_setup_interdependent2)
2998 hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);
2999 }
3000
hwss_hubp_setup_interdependent(union block_sequence_params * params)3001 void hwss_hubp_setup_interdependent(union block_sequence_params *params)
3002 {
3003 struct hubp *hubp = params->hubp_setup_interdependent_params.hubp;
3004 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs;
3005 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs;
3006
3007 if (hubp && hubp->funcs->hubp_setup_interdependent)
3008 hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs);
3009 }
3010
hwss_dpp_set_cursor_matrix(union block_sequence_params * params)3011 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params)
3012 {
3013 struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp;
3014 enum dc_color_space color_space = params->dpp_set_cursor_matrix_params.color_space;
3015 struct dc_csc_transform *cursor_csc_color_matrix = params->dpp_set_cursor_matrix_params.cursor_csc_color_matrix;
3016
3017 if (dpp && dpp->funcs->set_cursor_matrix)
3018 dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix);
3019 }
3020
hwss_mpc_update_mpcc(union block_sequence_params * params)3021 void hwss_mpc_update_mpcc(union block_sequence_params *params)
3022 {
3023 struct dc *dc = params->mpc_update_mpcc_params.dc;
3024 struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx;
3025 struct dce_hwseq *hws = dc->hwseq;
3026
3027 if (hws->funcs.update_mpcc)
3028 hws->funcs.update_mpcc(dc, pipe_ctx);
3029 }
3030
hwss_mpc_update_blending(union block_sequence_params * params)3031 void hwss_mpc_update_blending(union block_sequence_params *params)
3032 {
3033 struct mpc *mpc = params->mpc_update_blending_params.mpc;
3034 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_update_blending_params.blnd_cfg;
3035 int mpcc_id = params->mpc_update_blending_params.mpcc_id;
3036
3037 if (mpc && mpc->funcs->update_blending)
3038 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
3039 }
3040
hwss_mpc_assert_idle_mpcc(union block_sequence_params * params)3041 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params)
3042 {
3043 struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc;
3044 int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id;
3045
3046 if (mpc && mpc->funcs->wait_for_idle)
3047 mpc->funcs->wait_for_idle(mpc, mpcc_id);
3048 }
3049
hwss_mpc_insert_plane(union block_sequence_params * params)3050 void hwss_mpc_insert_plane(union block_sequence_params *params)
3051 {
3052 struct mpc *mpc = params->mpc_insert_plane_params.mpc;
3053 struct mpc_tree *tree = params->mpc_insert_plane_params.mpc_tree_params;
3054 struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_insert_plane_params.blnd_cfg;
3055 struct mpcc_sm_cfg *sm_cfg = params->mpc_insert_plane_params.sm_cfg;
3056 struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc;
3057 int mpcc_id = params->mpc_insert_plane_params.mpcc_id;
3058 int dpp_id = params->mpc_insert_plane_params.dpp_id;
3059
3060 if (mpc && mpc->funcs->insert_plane)
3061 mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc,
3062 dpp_id, mpcc_id);
3063 }
3064
hwss_dpp_set_scaler(union block_sequence_params * params)3065 void hwss_dpp_set_scaler(union block_sequence_params *params)
3066 {
3067 struct dpp *dpp = params->dpp_set_scaler_params.dpp;
3068 const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data;
3069
3070 if (dpp && dpp->funcs->dpp_set_scaler)
3071 dpp->funcs->dpp_set_scaler(dpp, scl_data);
3072 }
3073
hwss_hubp_mem_program_viewport(union block_sequence_params * params)3074 void hwss_hubp_mem_program_viewport(union block_sequence_params *params)
3075 {
3076 struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp;
3077 const struct rect *viewport = params->hubp_mem_program_viewport_params.viewport;
3078 const struct rect *viewport_c = params->hubp_mem_program_viewport_params.viewport_c;
3079
3080 if (hubp && hubp->funcs->mem_program_viewport)
3081 hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);
3082 }
3083
hwss_abort_cursor_offload_update(union block_sequence_params * params)3084 void hwss_abort_cursor_offload_update(union block_sequence_params *params)
3085 {
3086 struct dc *dc = params->abort_cursor_offload_update_params.dc;
3087 struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;
3088
3089 if (dc && dc->hwss.abort_cursor_offload_update)
3090 dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
3091 }
3092
hwss_set_cursor_attribute(union block_sequence_params * params)3093 void hwss_set_cursor_attribute(union block_sequence_params *params)
3094 {
3095 struct dc *dc = params->set_cursor_attribute_params.dc;
3096 struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx;
3097
3098 if (dc && dc->hwss.set_cursor_attribute)
3099 dc->hwss.set_cursor_attribute(pipe_ctx);
3100 }
3101
hwss_set_cursor_position(union block_sequence_params * params)3102 void hwss_set_cursor_position(union block_sequence_params *params)
3103 {
3104 struct dc *dc = params->set_cursor_position_params.dc;
3105 struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx;
3106
3107 if (dc && dc->hwss.set_cursor_position)
3108 dc->hwss.set_cursor_position(pipe_ctx);
3109 }
3110
hwss_set_cursor_sdr_white_level(union block_sequence_params * params)3111 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params)
3112 {
3113 struct dc *dc = params->set_cursor_sdr_white_level_params.dc;
3114 struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx;
3115
3116 if (dc && dc->hwss.set_cursor_sdr_white_level)
3117 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
3118 }
3119
hwss_program_output_csc(union block_sequence_params * params)3120 void hwss_program_output_csc(union block_sequence_params *params)
3121 {
3122 struct dc *dc = params->program_output_csc_params.dc;
3123 struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx;
3124 enum dc_color_space colorspace = params->program_output_csc_params.colorspace;
3125 uint16_t *matrix = params->program_output_csc_params.matrix;
3126 int opp_id = params->program_output_csc_params.opp_id;
3127
3128 if (dc && dc->hwss.program_output_csc)
3129 dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id);
3130 }
3131
hwss_hubp_set_blank(union block_sequence_params * params)3132 void hwss_hubp_set_blank(union block_sequence_params *params)
3133 {
3134 struct hubp *hubp = params->hubp_set_blank_params.hubp;
3135 bool blank = params->hubp_set_blank_params.blank;
3136
3137 if (hubp && hubp->funcs->set_blank)
3138 hubp->funcs->set_blank(hubp, blank);
3139 }
3140
hwss_phantom_hubp_post_enable(union block_sequence_params * params)3141 void hwss_phantom_hubp_post_enable(union block_sequence_params *params)
3142 {
3143 struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp;
3144
3145 if (hubp && hubp->funcs->phantom_hubp_post_enable)
3146 hubp->funcs->phantom_hubp_post_enable(hubp);
3147 }
3148
hwss_add_dccg_set_dto_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int inst,int num_slices_h)3149 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,
3150 struct dccg *dccg, int inst, int num_slices_h)
3151 {
3152 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3153 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK;
3154 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;
3155 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst;
3156 seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h;
3157 (*seq_state->num_steps)++;
3158 }
3159 }
3160
hwss_add_dsc_calculate_and_set_config(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx,bool enable,int opp_cnt)3161 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,
3162 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt)
3163 {
3164 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3165 seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG;
3166 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;
3167 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable;
3168 seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt;
3169 (*seq_state->num_steps)++;
3170 }
3171 }
3172
hwss_add_mpc_remove_mpcc(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpc_tree * mpc_tree_params,struct mpcc * mpcc_to_remove)3173 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,
3174 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove)
3175 {
3176 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3177 seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC;
3178 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc;
3179 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params;
3180 seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove;
3181 (*seq_state->num_steps)++;
3182 }
3183 }
3184
hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,int mpcc_inst,bool pending)3185 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,
3186 struct output_pixel_processor *opp, int mpcc_inst, bool pending)
3187 {
3188 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3189 seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING;
3190 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp;
3191 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst;
3192 seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending;
3193 (*seq_state->num_steps)++;
3194 }
3195 }
3196
hwss_add_hubp_disconnect(struct block_sequence_state * seq_state,struct hubp * hubp)3197 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,
3198 struct hubp *hubp)
3199 {
3200 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3201 seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT;
3202 seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp;
3203 (*seq_state->num_steps)++;
3204 }
3205 }
3206
hwss_add_dsc_enable_with_opp(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)3207 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,
3208 struct pipe_ctx *pipe_ctx)
3209 {
3210 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3211 seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP;
3212 seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx;
3213 (*seq_state->num_steps)++;
3214 }
3215 }
3216
hwss_add_tg_set_dsc_config(struct block_sequence_state * seq_state,struct timing_generator * tg,struct dsc_optc_config * dsc_optc_cfg,bool enable)3217 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,
3218 struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable)
3219 {
3220 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3221 seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG;
3222 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg;
3223 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg;
3224 seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable;
3225 (*seq_state->num_steps)++;
3226 }
3227 }
3228
hwss_add_dsc_disconnect(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc)3229 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,
3230 struct display_stream_compressor *dsc)
3231 {
3232 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3233 seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT;
3234 seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc;
3235 (*seq_state->num_steps)++;
3236 }
3237 }
3238
hwss_add_dc_set_optimized_required(struct block_sequence_state * seq_state,struct dc * dc,bool optimized_required)3239 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,
3240 struct dc *dc, bool optimized_required)
3241 {
3242 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3243 seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED;
3244 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc;
3245 seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required;
3246 (*seq_state->num_steps)++;
3247 }
3248 }
3249
hwss_add_abm_set_immediate_disable(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3250 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,
3251 struct dc *dc, struct pipe_ctx *pipe_ctx)
3252 {
3253 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3254 seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE;
3255 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc;
3256 seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx;
3257 (*seq_state->num_steps)++;
3258 }
3259 }
3260
hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,enum controller_dp_test_pattern test_pattern,enum controller_dp_color_space color_space,enum dc_color_depth color_depth,struct tg_color solid_color,bool use_solid_color,int width,int height,int offset)3261 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,
3262 struct output_pixel_processor *opp,
3263 enum controller_dp_test_pattern test_pattern,
3264 enum controller_dp_color_space color_space,
3265 enum dc_color_depth color_depth,
3266 struct tg_color solid_color,
3267 bool use_solid_color,
3268 int width,
3269 int height,
3270 int offset)
3271 {
3272 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3273 seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR;
3274 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp;
3275 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern;
3276 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space;
3277 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth;
3278 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color;
3279 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color;
3280 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width;
3281 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height;
3282 seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset;
3283 (*seq_state->num_steps)++;
3284 }
3285 }
3286
3287 /*
3288 * Helper function to add MPC update blending to block sequence
3289 */
hwss_add_mpc_update_blending(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpcc_blnd_cfg blnd_cfg,int mpcc_id)3290 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,
3291 struct mpc *mpc,
3292 struct mpcc_blnd_cfg blnd_cfg,
3293 int mpcc_id)
3294 {
3295 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3296 seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING;
3297 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc;
3298 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg;
3299 seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id;
3300 (*seq_state->num_steps)++;
3301 }
3302 }
3303
3304 /*
3305 * Helper function to add MPC insert plane to block sequence
3306 */
hwss_add_mpc_insert_plane(struct block_sequence_state * seq_state,struct mpc * mpc,struct mpc_tree * mpc_tree_params,struct mpcc_blnd_cfg blnd_cfg,struct mpcc_sm_cfg * sm_cfg,struct mpcc * insert_above_mpcc,int dpp_id,int mpcc_id)3307 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,
3308 struct mpc *mpc,
3309 struct mpc_tree *mpc_tree_params,
3310 struct mpcc_blnd_cfg blnd_cfg,
3311 struct mpcc_sm_cfg *sm_cfg,
3312 struct mpcc *insert_above_mpcc,
3313 int dpp_id,
3314 int mpcc_id)
3315 {
3316 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3317 seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE;
3318 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc;
3319 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params;
3320 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg;
3321 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg;
3322 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc;
3323 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id;
3324 seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id;
3325 (*seq_state->num_steps)++;
3326 }
3327 }
3328
3329 /*
3330 * Helper function to add MPC assert idle MPCC to block sequence
3331 */
hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state * seq_state,struct mpc * mpc,int mpcc_id)3332 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,
3333 struct mpc *mpc,
3334 int mpcc_id)
3335 {
3336 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3337 seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC;
3338 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc;
3339 seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id;
3340 (*seq_state->num_steps)++;
3341 }
3342 }
3343
3344 /*
3345 * Helper function to add HUBP set blank to block sequence
3346 */
hwss_add_hubp_set_blank(struct block_sequence_state * seq_state,struct hubp * hubp,bool blank)3347 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,
3348 struct hubp *hubp,
3349 bool blank)
3350 {
3351 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3352 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK;
3353 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp;
3354 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank;
3355 (*seq_state->num_steps)++;
3356 }
3357 }
3358
hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,bool use_default_params,struct pipe_ctx * pipe_ctx)3359 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,
3360 struct output_pixel_processor *opp,
3361 bool use_default_params,
3362 struct pipe_ctx *pipe_ctx)
3363 {
3364 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3365 seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION;
3366 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp;
3367 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params;
3368 seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx;
3369 (*seq_state->num_steps)++;
3370 }
3371 }
3372
hwss_add_dc_ip_request_cntl(struct block_sequence_state * seq_state,struct dc * dc,bool enable)3373 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
3374 struct dc *dc,
3375 bool enable)
3376 {
3377 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3378 seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL;
3379 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc;
3380 seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable;
3381 (*seq_state->num_steps)++;
3382 }
3383 }
3384
hwss_add_dwbc_update(struct block_sequence_state * seq_state,struct dwbc * dwb,struct dc_dwb_params * dwb_params)3385 void hwss_add_dwbc_update(struct block_sequence_state *seq_state,
3386 struct dwbc *dwb,
3387 struct dc_dwb_params *dwb_params)
3388 {
3389 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3390 seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE;
3391 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb;
3392 seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params;
3393 (*seq_state->num_steps)++;
3394 }
3395 }
3396
hwss_add_mcif_wb_config_buf(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb,struct mcif_buf_params * mcif_buf_params,unsigned int dest_height)3397 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,
3398 struct mcif_wb *mcif_wb,
3399 struct mcif_buf_params *mcif_buf_params,
3400 unsigned int dest_height)
3401 {
3402 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3403 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF;
3404 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb;
3405 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params;
3406 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height;
3407 (*seq_state->num_steps)++;
3408 }
3409 }
3410
hwss_add_mcif_wb_config_arb(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb,struct mcif_arb_params * mcif_arb_params)3411 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,
3412 struct mcif_wb *mcif_wb,
3413 struct mcif_arb_params *mcif_arb_params)
3414 {
3415 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3416 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB;
3417 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb;
3418 seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params;
3419 (*seq_state->num_steps)++;
3420 }
3421 }
3422
hwss_add_mcif_wb_enable(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb)3423 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,
3424 struct mcif_wb *mcif_wb)
3425 {
3426 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3427 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE;
3428 seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb;
3429 (*seq_state->num_steps)++;
3430 }
3431 }
3432
hwss_add_mcif_wb_disable(struct block_sequence_state * seq_state,struct mcif_wb * mcif_wb)3433 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,
3434 struct mcif_wb *mcif_wb)
3435 {
3436 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3437 seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE;
3438 seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb;
3439 (*seq_state->num_steps)++;
3440 }
3441 }
3442
hwss_add_mpc_set_dwb_mux(struct block_sequence_state * seq_state,struct mpc * mpc,int dwb_id,int mpcc_id)3443 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,
3444 struct mpc *mpc,
3445 int dwb_id,
3446 int mpcc_id)
3447 {
3448 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3449 seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX;
3450 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc;
3451 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id;
3452 seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id;
3453 (*seq_state->num_steps)++;
3454 }
3455 }
3456
hwss_add_mpc_disable_dwb_mux(struct block_sequence_state * seq_state,struct mpc * mpc,unsigned int dwb_id)3457 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,
3458 struct mpc *mpc,
3459 unsigned int dwb_id)
3460 {
3461 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3462 seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX;
3463 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc;
3464 seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id;
3465 (*seq_state->num_steps)++;
3466 }
3467 }
3468
hwss_add_dwbc_enable(struct block_sequence_state * seq_state,struct dwbc * dwb,struct dc_dwb_params * dwb_params)3469 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,
3470 struct dwbc *dwb,
3471 struct dc_dwb_params *dwb_params)
3472 {
3473 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3474 seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE;
3475 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb;
3476 seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params;
3477 (*seq_state->num_steps)++;
3478 }
3479 }
3480
hwss_add_dwbc_disable(struct block_sequence_state * seq_state,struct dwbc * dwb)3481 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,
3482 struct dwbc *dwb)
3483 {
3484 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3485 seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE;
3486 seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb;
3487 (*seq_state->num_steps)++;
3488 }
3489 }
3490
hwss_add_tg_set_gsl(struct block_sequence_state * seq_state,struct timing_generator * tg,struct gsl_params gsl)3491 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,
3492 struct timing_generator *tg,
3493 struct gsl_params gsl)
3494 {
3495 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3496 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL;
3497 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg;
3498 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl;
3499 (*seq_state->num_steps)++;
3500 }
3501 }
3502
hwss_add_tg_set_gsl_source_select(struct block_sequence_state * seq_state,struct timing_generator * tg,int group_idx,uint32_t gsl_ready_signal)3503 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,
3504 struct timing_generator *tg,
3505 int group_idx,
3506 uint32_t gsl_ready_signal)
3507 {
3508 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3509 seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT;
3510 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg;
3511 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx;
3512 seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal;
3513 (*seq_state->num_steps)++;
3514 }
3515 }
3516
hwss_add_hubp_update_mall_sel(struct block_sequence_state * seq_state,struct hubp * hubp,uint32_t mall_sel,bool cache_cursor)3517 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,
3518 struct hubp *hubp,
3519 uint32_t mall_sel,
3520 bool cache_cursor)
3521 {
3522 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3523 seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL;
3524 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp;
3525 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel;
3526 seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor;
3527 (*seq_state->num_steps)++;
3528 }
3529 }
3530
hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3531 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,
3532 struct hubp *hubp,
3533 bool enable)
3534 {
3535 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3536 seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING;
3537 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;
3538 seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable;
3539 (*seq_state->num_steps)++;
3540 }
3541 }
3542
hwss_add_hubp_set_blank_en(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3543 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,
3544 struct hubp *hubp,
3545 bool enable)
3546 {
3547 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3548 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN;
3549 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp;
3550 seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable;
3551 (*seq_state->num_steps)++;
3552 }
3553 }
3554
hwss_add_hubp_disable_control(struct block_sequence_state * seq_state,struct hubp * hubp,bool disable)3555 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,
3556 struct hubp *hubp,
3557 bool disable)
3558 {
3559 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3560 seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL;
3561 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp;
3562 seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable;
3563 (*seq_state->num_steps)++;
3564 }
3565 }
3566
hwss_add_hubbub_soft_reset(struct block_sequence_state * seq_state,struct hubbub * hubbub,void (* hubbub_soft_reset)(struct hubbub * hubbub,bool reset),bool reset)3567 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,
3568 struct hubbub *hubbub,
3569 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset),
3570 bool reset)
3571 {
3572 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3573 seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET;
3574 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub;
3575 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset;
3576 seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset;
3577 (*seq_state->num_steps)++;
3578 }
3579 }
3580
hwss_add_hubp_clk_cntl(struct block_sequence_state * seq_state,struct hubp * hubp,bool enable)3581 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,
3582 struct hubp *hubp,
3583 bool enable)
3584 {
3585 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3586 seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL;
3587 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp;
3588 seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable;
3589 (*seq_state->num_steps)++;
3590 }
3591 }
3592
hwss_add_dpp_dppclk_control(struct block_sequence_state * seq_state,struct dpp * dpp,bool dppclk_div,bool enable)3593 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,
3594 struct dpp *dpp,
3595 bool dppclk_div,
3596 bool enable)
3597 {
3598 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3599 seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL;
3600 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp;
3601 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div;
3602 seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable;
3603 (*seq_state->num_steps)++;
3604 }
3605 }
3606
hwss_add_disable_phantom_crtc(struct block_sequence_state * seq_state,struct timing_generator * tg)3607 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,
3608 struct timing_generator *tg)
3609 {
3610 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3611 seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC;
3612 seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg;
3613 (*seq_state->num_steps)++;
3614 }
3615 }
3616
hwss_add_dsc_pg_status(struct block_sequence_state * seq_state,struct dce_hwseq * hws,int dsc_inst,bool is_ungated)3617 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,
3618 struct dce_hwseq *hws,
3619 int dsc_inst,
3620 bool is_ungated)
3621 {
3622 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3623 seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS;
3624 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws;
3625 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst;
3626 seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated;
3627 (*seq_state->num_steps)++;
3628 }
3629 }
3630
hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc,bool * is_ungated)3631 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,
3632 struct display_stream_compressor *dsc,
3633 bool *is_ungated)
3634 {
3635 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3636 seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR;
3637 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc;
3638 seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated;
3639 (*seq_state->num_steps)++;
3640 }
3641 }
3642
hwss_add_dsc_disable(struct block_sequence_state * seq_state,struct display_stream_compressor * dsc,bool * is_ungated)3643 void hwss_add_dsc_disable(struct block_sequence_state *seq_state,
3644 struct display_stream_compressor *dsc,
3645 bool *is_ungated)
3646 {
3647 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3648 seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE;
3649 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc;
3650 seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated;
3651 (*seq_state->num_steps)++;
3652 }
3653 }
3654
hwss_add_dccg_set_ref_dscclk(struct block_sequence_state * seq_state,struct dccg * dccg,int dsc_inst,bool * is_ungated)3655 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,
3656 struct dccg *dccg,
3657 int dsc_inst,
3658 bool *is_ungated)
3659 {
3660 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3661 seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK;
3662 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;
3663 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst;
3664 seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated;
3665 (*seq_state->num_steps)++;
3666 }
3667 }
3668
hwss_add_dpp_root_clock_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int dpp_inst,bool clock_on)3669 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,
3670 struct dce_hwseq *hws,
3671 unsigned int dpp_inst,
3672 bool clock_on)
3673 {
3674 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3675 seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL;
3676 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws;
3677 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst;
3678 seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on;
3679 (*seq_state->num_steps)++;
3680 }
3681 }
3682
hwss_add_dpp_pg_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int dpp_inst,bool power_on)3683 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,
3684 struct dce_hwseq *hws,
3685 unsigned int dpp_inst,
3686 bool power_on)
3687 {
3688 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3689 seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL;
3690 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws;
3691 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst;
3692 seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on;
3693 (*seq_state->num_steps)++;
3694 }
3695 }
3696
hwss_add_hubp_pg_control(struct block_sequence_state * seq_state,struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)3697 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,
3698 struct dce_hwseq *hws,
3699 unsigned int hubp_inst,
3700 bool power_on)
3701 {
3702 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3703 seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL;
3704 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws;
3705 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst;
3706 seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on;
3707 (*seq_state->num_steps)++;
3708 }
3709 }
3710
hwss_add_hubp_init(struct block_sequence_state * seq_state,struct hubp * hubp)3711 void hwss_add_hubp_init(struct block_sequence_state *seq_state,
3712 struct hubp *hubp)
3713 {
3714 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3715 seq_state->steps[*seq_state->num_steps].func = HUBP_INIT;
3716 seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp;
3717 (*seq_state->num_steps)++;
3718 }
3719 }
3720
hwss_add_hubp_reset(struct block_sequence_state * seq_state,struct hubp * hubp)3721 void hwss_add_hubp_reset(struct block_sequence_state *seq_state,
3722 struct hubp *hubp)
3723 {
3724 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3725 seq_state->steps[*seq_state->num_steps].func = HUBP_RESET;
3726 seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp;
3727 (*seq_state->num_steps)++;
3728 }
3729 }
3730
hwss_add_dpp_reset(struct block_sequence_state * seq_state,struct dpp * dpp)3731 void hwss_add_dpp_reset(struct block_sequence_state *seq_state,
3732 struct dpp *dpp)
3733 {
3734 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3735 seq_state->steps[*seq_state->num_steps].func = DPP_RESET;
3736 seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp;
3737 (*seq_state->num_steps)++;
3738 }
3739 }
3740
hwss_add_opp_pipe_clock_control(struct block_sequence_state * seq_state,struct output_pixel_processor * opp,bool enable)3741 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,
3742 struct output_pixel_processor *opp,
3743 bool enable)
3744 {
3745 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3746 seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL;
3747 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp;
3748 seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable;
3749 (*seq_state->num_steps)++;
3750 }
3751 }
3752
hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state * seq_state,struct hubp * hubp,uint64_t sys_default,uint64_t sys_low,uint64_t sys_high)3753 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,
3754 struct hubp *hubp,
3755 uint64_t sys_default,
3756 uint64_t sys_low,
3757 uint64_t sys_high)
3758 {
3759 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3760 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS;
3761 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;
3762 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default;
3763 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low;
3764 seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high;
3765 (*seq_state->num_steps)++;
3766 }
3767 }
3768
hwss_add_hubp_set_flip_int(struct block_sequence_state * seq_state,struct hubp * hubp)3769 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,
3770 struct hubp *hubp)
3771 {
3772 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3773 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT;
3774 seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp;
3775 (*seq_state->num_steps)++;
3776 }
3777 }
3778
hwss_add_dccg_update_dpp_dto(struct block_sequence_state * seq_state,struct dccg * dccg,int dpp_inst,int dppclk_khz)3779 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,
3780 struct dccg *dccg,
3781 int dpp_inst,
3782 int dppclk_khz)
3783 {
3784 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3785 seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO;
3786 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;
3787 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst;
3788 seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz;
3789 (*seq_state->num_steps)++;
3790 }
3791 }
3792
hwss_add_hubp_vtg_sel(struct block_sequence_state * seq_state,struct hubp * hubp,uint32_t otg_inst)3793 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,
3794 struct hubp *hubp,
3795 uint32_t otg_inst)
3796 {
3797 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3798 seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL;
3799 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp;
3800 seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst;
3801 (*seq_state->num_steps)++;
3802 }
3803 }
3804
hwss_add_hubp_setup2(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_dchub_per_pipe_register_set * hubp_regs,union dml2_global_sync_programming * global_sync,struct dc_crtc_timing * timing)3805 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,
3806 struct hubp *hubp,
3807 struct dml2_dchub_per_pipe_register_set *hubp_regs,
3808 union dml2_global_sync_programming *global_sync,
3809 struct dc_crtc_timing *timing)
3810 {
3811 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3812 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2;
3813 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp;
3814 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;
3815 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync;
3816 seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing;
3817 (*seq_state->num_steps)++;
3818 }
3819 }
3820
hwss_add_hubp_setup(struct block_sequence_state * seq_state,struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_regs,struct _vcs_dpi_display_ttu_regs_st * ttu_regs,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)3821 void hwss_add_hubp_setup(struct block_sequence_state *seq_state,
3822 struct hubp *hubp,
3823 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
3824 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
3825 struct _vcs_dpi_display_rq_regs_st *rq_regs,
3826 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
3827 {
3828 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3829 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP;
3830 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp;
3831 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs;
3832 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs;
3833 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs;
3834 seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest;
3835 (*seq_state->num_steps)++;
3836 }
3837 }
3838
hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state * seq_state,struct hubp * hubp,bool unbounded_req)3839 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,
3840 struct hubp *hubp,
3841 bool unbounded_req)
3842 {
3843 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3844 seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING;
3845 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;
3846 seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req;
3847 (*seq_state->num_steps)++;
3848 }
3849 }
3850
hwss_add_hubp_setup_interdependent2(struct block_sequence_state * seq_state,struct hubp * hubp,struct dml2_dchub_per_pipe_register_set * hubp_regs)3851 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,
3852 struct hubp *hubp,
3853 struct dml2_dchub_per_pipe_register_set *hubp_regs)
3854 {
3855 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3856 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2;
3857 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;
3858 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;
3859 (*seq_state->num_steps)++;
3860 }
3861 }
3862
hwss_add_hubp_setup_interdependent(struct block_sequence_state * seq_state,struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_regs,struct _vcs_dpi_display_ttu_regs_st * ttu_regs)3863 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,
3864 struct hubp *hubp,
3865 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
3866 struct _vcs_dpi_display_ttu_regs_st *ttu_regs)
3867 {
3868 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3869 seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT;
3870 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp;
3871 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs;
3872 seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs;
3873 (*seq_state->num_steps)++;
3874 }
3875 }
3876
hwss_add_hubp_program_surface_config(struct block_sequence_state * seq_state,struct hubp * hubp,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,int compat_level)3877 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,
3878 struct hubp *hubp,
3879 enum surface_pixel_format format,
3880 struct dc_tiling_info *tiling_info,
3881 struct plane_size plane_size,
3882 enum dc_rotation_angle rotation,
3883 struct dc_plane_dcc_param *dcc,
3884 bool horizontal_mirror,
3885 int compat_level)
3886 {
3887 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3888 seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG;
3889 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp;
3890 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format;
3891 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info;
3892 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size;
3893 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation;
3894 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc;
3895 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror;
3896 seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level;
3897 (*seq_state->num_steps)++;
3898 }
3899 }
3900
hwss_add_dpp_setup_dpp(struct block_sequence_state * seq_state,struct pipe_ctx * pipe_ctx)3901 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,
3902 struct pipe_ctx *pipe_ctx)
3903 {
3904 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3905 seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP;
3906 seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx;
3907 (*seq_state->num_steps)++;
3908 }
3909 }
3910
hwss_add_dpp_set_cursor_matrix(struct block_sequence_state * seq_state,struct dpp * dpp,enum dc_color_space color_space,struct dc_csc_transform * cursor_csc_color_matrix)3911 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,
3912 struct dpp *dpp,
3913 enum dc_color_space color_space,
3914 struct dc_csc_transform *cursor_csc_color_matrix)
3915 {
3916 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3917 seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX;
3918 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;
3919 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space;
3920 seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix;
3921 (*seq_state->num_steps)++;
3922 }
3923 }
3924
hwss_add_dpp_set_scaler(struct block_sequence_state * seq_state,struct dpp * dpp,const struct scaler_data * scl_data)3925 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,
3926 struct dpp *dpp,
3927 const struct scaler_data *scl_data)
3928 {
3929 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3930 seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER;
3931 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp;
3932 seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data;
3933 (*seq_state->num_steps)++;
3934 }
3935 }
3936
hwss_add_hubp_mem_program_viewport(struct block_sequence_state * seq_state,struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)3937 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,
3938 struct hubp *hubp,
3939 const struct rect *viewport,
3940 const struct rect *viewport_c)
3941 {
3942 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3943 seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT;
3944 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;
3945 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport;
3946 seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c;
3947 (*seq_state->num_steps)++;
3948 }
3949 }
3950
hwss_add_abort_cursor_offload_update(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3951 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
3952 struct dc *dc,
3953 struct pipe_ctx *pipe_ctx)
3954 {
3955 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3956 seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;
3957 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;
3958 seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;
3959 (*seq_state->num_steps)++;
3960 }
3961 }
3962
hwss_add_set_cursor_attribute(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3963 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
3964 struct dc *dc,
3965 struct pipe_ctx *pipe_ctx)
3966 {
3967 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3968 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE;
3969 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc;
3970 seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx;
3971 (*seq_state->num_steps)++;
3972 }
3973 }
3974
hwss_add_set_cursor_position(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3975 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,
3976 struct dc *dc,
3977 struct pipe_ctx *pipe_ctx)
3978 {
3979 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3980 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION;
3981 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc;
3982 seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx;
3983 (*seq_state->num_steps)++;
3984 }
3985 }
3986
hwss_add_set_cursor_sdr_white_level(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx)3987 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,
3988 struct dc *dc,
3989 struct pipe_ctx *pipe_ctx)
3990 {
3991 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
3992 seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;
3993 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc;
3994 seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx;
3995 (*seq_state->num_steps)++;
3996 }
3997 }
3998
hwss_add_program_output_csc(struct block_sequence_state * seq_state,struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)3999 void hwss_add_program_output_csc(struct block_sequence_state *seq_state,
4000 struct dc *dc,
4001 struct pipe_ctx *pipe_ctx,
4002 enum dc_color_space colorspace,
4003 uint16_t *matrix,
4004 int opp_id)
4005 {
4006 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4007 seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC;
4008 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc;
4009 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx;
4010 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace;
4011 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix;
4012 seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id;
4013 (*seq_state->num_steps)++;
4014 }
4015 }
4016
hwss_add_phantom_hubp_post_enable(struct block_sequence_state * seq_state,struct hubp * hubp)4017 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,
4018 struct hubp *hubp)
4019 {
4020 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4021 seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE;
4022 seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;
4023 (*seq_state->num_steps)++;
4024 }
4025 }
4026
hwss_add_update_force_pstate(struct block_sequence_state * seq_state,struct dc * dc,struct dc_state * context)4027 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,
4028 struct dc *dc,
4029 struct dc_state *context)
4030 {
4031 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4032 seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE;
4033 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc;
4034 seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context;
4035 (*seq_state->num_steps)++;
4036 }
4037 }
4038
hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state * seq_state,struct hubbub * hubbub)4039 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,
4040 struct hubbub *hubbub)
4041 {
4042 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4043 seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA;
4044 seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub;
4045 (*seq_state->num_steps)++;
4046 }
4047 }
4048
hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state * seq_state,struct hubbub * hubbub,bool allow,bool * disallow_self_refresh_applied)4049 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,
4050 struct hubbub *hubbub,
4051 bool allow,
4052 bool *disallow_self_refresh_applied)
4053 {
4054 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4055 seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL;
4056 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub;
4057 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow;
4058 seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied;
4059 (*seq_state->num_steps)++;
4060 }
4061 }
4062
hwss_add_tg_get_frame_count(struct block_sequence_state * seq_state,struct timing_generator * tg,unsigned int * frame_count)4063 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,
4064 struct timing_generator *tg,
4065 unsigned int *frame_count)
4066 {
4067 if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
4068 seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT;
4069 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg;
4070 seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count;
4071 (*seq_state->num_steps)++;
4072 }
4073 }
4074