1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STM32 Digital Camera Memory Interface Pixel Processor
4 *
5 * Copyright (C) STMicroelectronics SA 2023
6 * Authors: Hugues Fruchet <hugues.fruchet@foss.st.com>
7 * Alain Volmat <alain.volmat@foss.st.com>
8 * for STMicroelectronics.
9 */
10
11 #include <linux/v4l2-mediabus.h>
12 #include <media/mipi-csi2.h>
13 #include <media/v4l2-event.h>
14 #include <media/v4l2-subdev.h>
15
16 #include "dcmipp-common.h"
17
18 #define DCMIPP_PRCR 0x104
19 #define DCMIPP_PRCR_FORMAT_SHIFT 16
20 #define DCMIPP_PRCR_FORMAT_YUV422 0x1e
21 #define DCMIPP_PRCR_FORMAT_RGB565 0x22
22 #define DCMIPP_PRCR_FORMAT_RGB888 0x24
23 #define DCMIPP_PRCR_FORMAT_RAW8 0x2a
24 #define DCMIPP_PRCR_FORMAT_RAW10 0x2b
25 #define DCMIPP_PRCR_FORMAT_RAW12 0x2c
26 #define DCMIPP_PRCR_FORMAT_RAW14 0x2d
27 #define DCMIPP_PRCR_FORMAT_G8 0x4a
28 #define DCMIPP_PRCR_FORMAT_G10 0x4b
29 #define DCMIPP_PRCR_FORMAT_G12 0x4c
30 #define DCMIPP_PRCR_FORMAT_G14 0x4d
31 #define DCMIPP_PRCR_FORMAT_BYTE_STREAM 0x5a
32 #define DCMIPP_PRCR_ESS BIT(4)
33 #define DCMIPP_PRCR_PCKPOL BIT(5)
34 #define DCMIPP_PRCR_HSPOL BIT(6)
35 #define DCMIPP_PRCR_VSPOL BIT(7)
36 #define DCMIPP_PRCR_ENABLE BIT(14)
37 #define DCMIPP_PRCR_SWAPCYCLES BIT(25)
38
39 #define DCMIPP_PRESCR 0x108
40 #define DCMIPP_PRESUR 0x10c
41
42 #define DCMIPP_CMCR 0x204
43 #define DCMIPP_CMCR_INSEL BIT(0)
44
45 #define DCMIPP_P0FSCR 0x404
46 #define DCMIPP_P0FSCR_DTMODE_MASK GENMASK(17, 16)
47 #define DCMIPP_P0FSCR_DTMODE_SHIFT 16
48 #define DCMIPP_P0FSCR_DTMODE_DTIDA 0x00
49 #define DCMIPP_P0FSCR_DTMODE_ALLDT 0x03
50 #define DCMIPP_P0FSCR_DTIDA_MASK GENMASK(5, 0)
51 #define DCMIPP_P0FSCR_DTIDA_SHIFT 0
52
53 #define IS_SINK(pad) (!(pad))
54 #define IS_SRC(pad) ((pad))
55
56 struct dcmipp_inp_pix_map {
57 unsigned int code_sink;
58 unsigned int code_src;
59 /* Parallel related information */
60 u8 prcr_format;
61 u8 prcr_swapcycles;
62 /* CSI related information */
63 unsigned int dt;
64 };
65
66 #define PIXMAP_SINK_SRC_PRCR_SWAP(sink, src, prcr, swap, data_type) \
67 { \
68 .code_sink = MEDIA_BUS_FMT_##sink, \
69 .code_src = MEDIA_BUS_FMT_##src, \
70 .prcr_format = DCMIPP_PRCR_FORMAT_##prcr, \
71 .prcr_swapcycles = swap, \
72 .dt = data_type, \
73 }
74 static const struct dcmipp_inp_pix_map dcmipp_inp_pix_map_list[] = {
75 /* RGB565 */
76 PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_LE, RGB565_2X8_LE, RGB565, 1, MIPI_CSI2_DT_RGB565),
77 PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_BE, RGB565_2X8_LE, RGB565, 0, MIPI_CSI2_DT_RGB565),
78 PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_1X16, RGB565_1X16, RGB565, 0, MIPI_CSI2_DT_RGB565),
79 /* RGB888 */
80 PIXMAP_SINK_SRC_PRCR_SWAP(RGB888_3X8, RGB888_3X8, RGB888, 0, MIPI_CSI2_DT_RGB888),
81 PIXMAP_SINK_SRC_PRCR_SWAP(RGB888_1X24, RGB888_1X24, RGB888, 0, MIPI_CSI2_DT_RGB888),
82 /* YUV422 */
83 PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, YUYV8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
84 PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_1X16, YUYV8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
85 PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, UYVY8_2X8, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
86 PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, UYVY8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
87 PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_1X16, UYVY8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
88 PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, YUYV8_2X8, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
89 PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_2X8, YVYU8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
90 PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_1X16, YVYU8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
91 PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_2X8, VYUY8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
92 PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_1X16, VYUY8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
93 /* GREY */
94 PIXMAP_SINK_SRC_PRCR_SWAP(Y8_1X8, Y8_1X8, G8, 0, MIPI_CSI2_DT_RAW8),
95 PIXMAP_SINK_SRC_PRCR_SWAP(Y10_1X10, Y10_1X10, G10, 0, MIPI_CSI2_DT_RAW10),
96 PIXMAP_SINK_SRC_PRCR_SWAP(Y12_1X12, Y12_1X12, G12, 0, MIPI_CSI2_DT_RAW12),
97 PIXMAP_SINK_SRC_PRCR_SWAP(Y14_1X14, Y14_1X14, G14, 0, MIPI_CSI2_DT_RAW14),
98 /* Raw Bayer */
99 PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR8_1X8, SBGGR8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
100 PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG8_1X8, SGBRG8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
101 PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG8_1X8, SGRBG8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
102 PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB8_1X8, SRGGB8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
103 PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR10_1X10, SBGGR10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
104 PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG10_1X10, SGBRG10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
105 PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG10_1X10, SGRBG10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
106 PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB10_1X10, SRGGB10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
107 PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR12_1X12, SBGGR12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
108 PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG12_1X12, SGBRG12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
109 PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG12_1X12, SGRBG12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
110 PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB12_1X12, SRGGB12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
111 PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR14_1X14, SBGGR14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
112 PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG14_1X14, SGBRG14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
113 PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG14_1X14, SGRBG14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
114 PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB14_1X14, SRGGB14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
115 /* JPEG */
116 PIXMAP_SINK_SRC_PRCR_SWAP(JPEG_1X8, JPEG_1X8, BYTE_STREAM, 0, 0),
117 };
118
119 /*
120 * Search through the pix_map table, skipping two consecutive entry with the
121 * same code
122 */
dcmipp_inp_pix_map_by_index(unsigned int index,unsigned int pad)123 static inline const struct dcmipp_inp_pix_map *dcmipp_inp_pix_map_by_index
124 (unsigned int index,
125 unsigned int pad)
126 {
127 unsigned int i = 0;
128 u32 prev_code = 0, cur_code;
129
130 while (i < ARRAY_SIZE(dcmipp_inp_pix_map_list)) {
131 if (IS_SRC(pad))
132 cur_code = dcmipp_inp_pix_map_list[i].code_src;
133 else
134 cur_code = dcmipp_inp_pix_map_list[i].code_sink;
135
136 if (cur_code == prev_code) {
137 i++;
138 continue;
139 }
140 prev_code = cur_code;
141
142 if (index == 0)
143 break;
144 i++;
145 index--;
146 }
147
148 if (i >= ARRAY_SIZE(dcmipp_inp_pix_map_list))
149 return NULL;
150
151 return &dcmipp_inp_pix_map_list[i];
152 }
153
dcmipp_inp_pix_map_by_code(u32 code_sink,u32 code_src)154 static inline const struct dcmipp_inp_pix_map *dcmipp_inp_pix_map_by_code
155 (u32 code_sink, u32 code_src)
156 {
157 unsigned int i;
158
159 for (i = 0; i < ARRAY_SIZE(dcmipp_inp_pix_map_list); i++) {
160 if ((dcmipp_inp_pix_map_list[i].code_sink == code_sink &&
161 dcmipp_inp_pix_map_list[i].code_src == code_src) ||
162 (dcmipp_inp_pix_map_list[i].code_sink == code_src &&
163 dcmipp_inp_pix_map_list[i].code_src == code_sink) ||
164 (dcmipp_inp_pix_map_list[i].code_sink == code_sink &&
165 code_src == 0) ||
166 (code_sink == 0 &&
167 dcmipp_inp_pix_map_list[i].code_src == code_src))
168 return &dcmipp_inp_pix_map_list[i];
169 }
170 return NULL;
171 }
172
173 struct dcmipp_inp_device {
174 struct dcmipp_ent_device ved;
175 struct v4l2_subdev sd;
176 struct device *dev;
177 void __iomem *regs;
178 };
179
180 static const struct v4l2_mbus_framefmt fmt_default = {
181 .width = DCMIPP_FMT_WIDTH_DEFAULT,
182 .height = DCMIPP_FMT_HEIGHT_DEFAULT,
183 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
184 .field = V4L2_FIELD_NONE,
185 .colorspace = DCMIPP_COLORSPACE_DEFAULT,
186 .ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,
187 .quantization = DCMIPP_QUANTIZATION_DEFAULT,
188 .xfer_func = DCMIPP_XFER_FUNC_DEFAULT,
189 };
190
dcmipp_inp_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)191 static int dcmipp_inp_init_state(struct v4l2_subdev *sd,
192 struct v4l2_subdev_state *sd_state)
193 {
194 unsigned int i;
195
196 for (i = 0; i < sd->entity.num_pads; i++) {
197 struct v4l2_mbus_framefmt *mf;
198
199 mf = v4l2_subdev_state_get_format(sd_state, i);
200 *mf = fmt_default;
201 }
202
203 return 0;
204 }
205
dcmipp_inp_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)206 static int dcmipp_inp_enum_mbus_code(struct v4l2_subdev *sd,
207 struct v4l2_subdev_state *sd_state,
208 struct v4l2_subdev_mbus_code_enum *code)
209 {
210 const struct dcmipp_inp_pix_map *vpix =
211 dcmipp_inp_pix_map_by_index(code->index, code->pad);
212
213 if (!vpix)
214 return -EINVAL;
215
216 code->code = IS_SRC(code->pad) ? vpix->code_src : vpix->code_sink;
217
218 return 0;
219 }
220
dcmipp_inp_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)221 static int dcmipp_inp_enum_frame_size(struct v4l2_subdev *sd,
222 struct v4l2_subdev_state *sd_state,
223 struct v4l2_subdev_frame_size_enum *fse)
224 {
225 const struct dcmipp_inp_pix_map *vpix;
226
227 if (fse->index)
228 return -EINVAL;
229
230 /* Only accept code in the pix map table */
231 vpix = dcmipp_inp_pix_map_by_code(IS_SINK(fse->pad) ? fse->code : 0,
232 IS_SRC(fse->pad) ? fse->code : 0);
233 if (!vpix)
234 return -EINVAL;
235
236 fse->min_width = DCMIPP_FRAME_MIN_WIDTH;
237 fse->max_width = DCMIPP_FRAME_MAX_WIDTH;
238 fse->min_height = DCMIPP_FRAME_MIN_HEIGHT;
239 fse->max_height = DCMIPP_FRAME_MAX_HEIGHT;
240
241 return 0;
242 }
243
dcmipp_inp_adjust_fmt(struct dcmipp_inp_device * inp,struct v4l2_mbus_framefmt * fmt,__u32 pad)244 static void dcmipp_inp_adjust_fmt(struct dcmipp_inp_device *inp,
245 struct v4l2_mbus_framefmt *fmt, __u32 pad)
246 {
247 const struct dcmipp_inp_pix_map *vpix;
248
249 /* Only accept code in the pix map table */
250 vpix = dcmipp_inp_pix_map_by_code(IS_SINK(pad) ? fmt->code : 0,
251 IS_SRC(pad) ? fmt->code : 0);
252 if (!vpix)
253 fmt->code = fmt_default.code;
254
255 /* Exclude JPEG if BT656 bus is selected */
256 if (vpix && vpix->code_sink == MEDIA_BUS_FMT_JPEG_1X8 &&
257 inp->ved.bus_type == V4L2_MBUS_BT656)
258 fmt->code = fmt_default.code;
259
260 fmt->width = clamp_t(u32, fmt->width, DCMIPP_FRAME_MIN_WIDTH,
261 DCMIPP_FRAME_MAX_WIDTH) & ~1;
262 fmt->height = clamp_t(u32, fmt->height, DCMIPP_FRAME_MIN_HEIGHT,
263 DCMIPP_FRAME_MAX_HEIGHT) & ~1;
264
265 if (fmt->field == V4L2_FIELD_ANY || fmt->field == V4L2_FIELD_ALTERNATE)
266 fmt->field = fmt_default.field;
267
268 dcmipp_colorimetry_clamp(fmt);
269 }
270
dcmipp_inp_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)271 static int dcmipp_inp_set_fmt(struct v4l2_subdev *sd,
272 struct v4l2_subdev_state *sd_state,
273 struct v4l2_subdev_format *fmt)
274 {
275 struct dcmipp_inp_device *inp = v4l2_get_subdevdata(sd);
276 struct v4l2_mbus_framefmt *mf;
277
278 if (v4l2_subdev_is_streaming(sd))
279 return -EBUSY;
280
281 mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
282
283 /* Set the new format */
284 dcmipp_inp_adjust_fmt(inp, &fmt->format, fmt->pad);
285
286 dev_dbg(inp->dev, "%s: format update: old:%dx%d (0x%x, %d, %d, %d, %d) new:%dx%d (0x%x, %d, %d, %d, %d)\n",
287 inp->sd.name,
288 /* old */
289 mf->width, mf->height, mf->code,
290 mf->colorspace, mf->quantization,
291 mf->xfer_func, mf->ycbcr_enc,
292 /* new */
293 fmt->format.width, fmt->format.height, fmt->format.code,
294 fmt->format.colorspace, fmt->format.quantization,
295 fmt->format.xfer_func, fmt->format.ycbcr_enc);
296
297 *mf = fmt->format;
298
299 /* When setting the sink format, report that format on the src pad */
300 if (IS_SINK(fmt->pad)) {
301 mf = v4l2_subdev_state_get_format(sd_state, 1);
302 *mf = fmt->format;
303 dcmipp_inp_adjust_fmt(inp, mf, 1);
304 }
305
306 return 0;
307 }
308
dcmipp_inp_configure_parallel(struct dcmipp_inp_device * inp,struct v4l2_subdev_state * state)309 static int dcmipp_inp_configure_parallel(struct dcmipp_inp_device *inp,
310 struct v4l2_subdev_state *state)
311 {
312 u32 val = 0;
313 const struct dcmipp_inp_pix_map *vpix;
314 struct v4l2_mbus_framefmt *sink_fmt;
315 struct v4l2_mbus_framefmt *src_fmt;
316
317 /* Set vertical synchronization polarity */
318 if (inp->ved.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
319 val |= DCMIPP_PRCR_VSPOL;
320
321 /* Set horizontal synchronization polarity */
322 if (inp->ved.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
323 val |= DCMIPP_PRCR_HSPOL;
324
325 /* Set pixel clock polarity */
326 if (inp->ved.bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
327 val |= DCMIPP_PRCR_PCKPOL;
328
329 /*
330 * BT656 embedded synchronisation bus mode.
331 *
332 * Default SAV/EAV mode is supported here with default codes
333 * SAV=0xff000080 & EAV=0xff00009d.
334 * With DCMIPP this means LSC=SAV=0x80 & LEC=EAV=0x9d.
335 */
336 if (inp->ved.bus_type == V4L2_MBUS_BT656) {
337 val |= DCMIPP_PRCR_ESS;
338
339 /* Unmask all codes */
340 reg_write(inp, DCMIPP_PRESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */
341
342 /* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */
343 reg_write(inp, DCMIPP_PRESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */
344 }
345
346 /* Set format */
347 sink_fmt = v4l2_subdev_state_get_format(state, 0);
348 src_fmt = v4l2_subdev_state_get_format(state, 1);
349
350 vpix = dcmipp_inp_pix_map_by_code(sink_fmt->code, src_fmt->code);
351 if (!vpix) {
352 dev_err(inp->dev, "Invalid sink/src format configuration\n");
353 return -EINVAL;
354 }
355
356 val |= vpix->prcr_format << DCMIPP_PRCR_FORMAT_SHIFT;
357
358 /* swap cycles */
359 if (vpix->prcr_swapcycles)
360 val |= DCMIPP_PRCR_SWAPCYCLES;
361
362 reg_write(inp, DCMIPP_PRCR, val);
363
364 /* Select the DCMIPP parallel interface */
365 reg_write(inp, DCMIPP_CMCR, 0);
366
367 /* Enable parallel interface */
368 reg_set(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
369
370 return 0;
371 }
372
dcmipp_inp_configure_csi(struct dcmipp_inp_device * inp,struct v4l2_subdev_state * state)373 static int dcmipp_inp_configure_csi(struct dcmipp_inp_device *inp,
374 struct v4l2_subdev_state *state)
375 {
376 const struct dcmipp_inp_pix_map *vpix;
377 struct v4l2_mbus_framefmt *sink_fmt;
378 struct v4l2_mbus_framefmt *src_fmt;
379
380 /* Get format information */
381 sink_fmt = v4l2_subdev_state_get_format(state, 0);
382 src_fmt = v4l2_subdev_state_get_format(state, 1);
383
384 vpix = dcmipp_inp_pix_map_by_code(sink_fmt->code, src_fmt->code);
385 if (!vpix) {
386 dev_err(inp->dev, "Invalid sink/src format configuration\n");
387 return -EINVAL;
388 }
389
390 /* Apply configuration on each input pipe */
391 reg_clear(inp, DCMIPP_P0FSCR,
392 DCMIPP_P0FSCR_DTMODE_MASK | DCMIPP_P0FSCR_DTIDA_MASK);
393
394 /* In case of JPEG we don't know the DT so we allow all data */
395 /*
396 * TODO - check instead dt == 0 for the time being to allow other
397 * unknown data-type
398 */
399 if (!vpix->dt)
400 reg_set(inp, DCMIPP_P0FSCR,
401 DCMIPP_P0FSCR_DTMODE_ALLDT << DCMIPP_P0FSCR_DTMODE_SHIFT);
402 else
403 reg_set(inp, DCMIPP_P0FSCR,
404 vpix->dt << DCMIPP_P0FSCR_DTIDA_SHIFT |
405 DCMIPP_P0FSCR_DTMODE_DTIDA);
406
407 /* Select the DCMIPP CSI interface */
408 reg_write(inp, DCMIPP_CMCR, DCMIPP_CMCR_INSEL);
409
410 return 0;
411 }
412
dcmipp_inp_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)413 static int dcmipp_inp_enable_streams(struct v4l2_subdev *sd,
414 struct v4l2_subdev_state *state,
415 u32 pad, u64 streams_mask)
416 {
417 struct dcmipp_inp_device *inp =
418 container_of(sd, struct dcmipp_inp_device, sd);
419 struct v4l2_subdev *s_subdev;
420 struct media_pad *s_pad;
421 int ret = 0;
422
423 /* Get source subdev */
424 s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
425 if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
426 return -EINVAL;
427 s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
428
429 if (inp->ved.bus_type == V4L2_MBUS_PARALLEL ||
430 inp->ved.bus_type == V4L2_MBUS_BT656)
431 ret = dcmipp_inp_configure_parallel(inp, state);
432 else if (inp->ved.bus_type == V4L2_MBUS_CSI2_DPHY)
433 ret = dcmipp_inp_configure_csi(inp, state);
434 if (ret)
435 return ret;
436
437 ret = v4l2_subdev_enable_streams(s_subdev, s_pad->index, BIT_ULL(0));
438 if (ret < 0) {
439 dev_err(inp->dev,
440 "failed to start source subdev streaming (%d)\n", ret);
441 return ret;
442 }
443
444 return 0;
445 }
446
dcmipp_inp_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)447 static int dcmipp_inp_disable_streams(struct v4l2_subdev *sd,
448 struct v4l2_subdev_state *state,
449 u32 pad, u64 streams_mask)
450 {
451 struct dcmipp_inp_device *inp =
452 container_of(sd, struct dcmipp_inp_device, sd);
453 struct v4l2_subdev *s_subdev;
454 struct media_pad *s_pad;
455 int ret;
456
457 /* Get source subdev */
458 s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
459 if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
460 return -EINVAL;
461 s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
462
463 ret = v4l2_subdev_disable_streams(s_subdev, s_pad->index, BIT_ULL(0));
464 if (ret < 0) {
465 dev_err(inp->dev,
466 "failed to stop source subdev streaming (%d)\n", ret);
467 return ret;
468 }
469
470 if (inp->ved.bus_type == V4L2_MBUS_PARALLEL ||
471 inp->ved.bus_type == V4L2_MBUS_BT656) {
472 /* Disable parallel interface */
473 reg_clear(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
474 }
475
476 return 0;
477 }
478
479 static const struct v4l2_subdev_pad_ops dcmipp_inp_pad_ops = {
480 .enum_mbus_code = dcmipp_inp_enum_mbus_code,
481 .enum_frame_size = dcmipp_inp_enum_frame_size,
482 .get_fmt = v4l2_subdev_get_fmt,
483 .set_fmt = dcmipp_inp_set_fmt,
484 .enable_streams = dcmipp_inp_enable_streams,
485 .disable_streams = dcmipp_inp_disable_streams,
486 };
487
488 static const struct v4l2_subdev_video_ops dcmipp_inp_video_ops = {
489 .s_stream = v4l2_subdev_s_stream_helper,
490 };
491
492 static const struct v4l2_subdev_ops dcmipp_inp_ops = {
493 .pad = &dcmipp_inp_pad_ops,
494 .video = &dcmipp_inp_video_ops,
495 };
496
dcmipp_inp_release(struct v4l2_subdev * sd)497 static void dcmipp_inp_release(struct v4l2_subdev *sd)
498 {
499 struct dcmipp_inp_device *inp =
500 container_of(sd, struct dcmipp_inp_device, sd);
501
502 kfree(inp);
503 }
504
505 static const struct v4l2_subdev_internal_ops dcmipp_inp_int_ops = {
506 .init_state = dcmipp_inp_init_state,
507 .release = dcmipp_inp_release,
508 };
509
dcmipp_inp_ent_release(struct dcmipp_ent_device * ved)510 void dcmipp_inp_ent_release(struct dcmipp_ent_device *ved)
511 {
512 struct dcmipp_inp_device *inp =
513 container_of(ved, struct dcmipp_inp_device, ved);
514
515 dcmipp_ent_sd_unregister(ved, &inp->sd);
516 }
517
dcmipp_inp_ent_init(struct device * dev,const char * entity_name,struct v4l2_device * v4l2_dev,void __iomem * regs)518 struct dcmipp_ent_device *dcmipp_inp_ent_init(struct device *dev,
519 const char *entity_name,
520 struct v4l2_device *v4l2_dev,
521 void __iomem *regs)
522 {
523 struct dcmipp_inp_device *inp;
524 const unsigned long pads_flag[] = {
525 MEDIA_PAD_FL_SINK, MEDIA_PAD_FL_SOURCE,
526 };
527 int ret;
528
529 /* Allocate the inp struct */
530 inp = kzalloc_obj(*inp);
531 if (!inp)
532 return ERR_PTR(-ENOMEM);
533
534 inp->regs = regs;
535
536 /* Initialize ved and sd */
537 ret = dcmipp_ent_sd_register(&inp->ved, &inp->sd, v4l2_dev,
538 entity_name, MEDIA_ENT_F_VID_IF_BRIDGE,
539 ARRAY_SIZE(pads_flag), pads_flag,
540 &dcmipp_inp_int_ops, &dcmipp_inp_ops,
541 NULL, NULL);
542 if (ret) {
543 kfree(inp);
544 return ERR_PTR(ret);
545 }
546
547 inp->dev = dev;
548
549 return &inp->ved;
550 }
551