1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2026 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info.h"
9 #include "gen1_2/internal.h"
10 #include "iwl-prph.h"
11
_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans * trans,size_t size,dma_addr_t * phys,int depth)12 static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
13 size_t size,
14 dma_addr_t *phys,
15 int depth)
16 {
17 void *result;
18
19 if (WARN(depth > 2,
20 "failed to allocate DMA memory not crossing 2^32 boundary"))
21 return NULL;
22
23 result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
24
25 if (!result)
26 return NULL;
27
28 if (unlikely(iwl_txq_crosses_4g_boundary(*phys, size))) {
29 void *old = result;
30 dma_addr_t oldphys = *phys;
31
32 result = _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size,
33 phys,
34 depth + 1);
35 dma_free_coherent(trans->dev, size, old, oldphys);
36 }
37
38 return result;
39 }
40
iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans * trans,size_t size,dma_addr_t * phys)41 void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
42 size_t size,
43 dma_addr_t *phys)
44 {
45 return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
46 }
47
iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans * trans,const void * data,u32 len,struct iwl_dram_data * dram)48 int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
49 const void *data, u32 len,
50 struct iwl_dram_data *dram)
51 {
52 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
53 &dram->physical);
54 if (!dram->block)
55 return -ENOMEM;
56
57 dram->size = len;
58 memcpy(dram->block, data, len);
59
60 return 0;
61 }
62
iwl_pcie_ctxt_info_free_paging(struct iwl_trans * trans)63 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
64 {
65 struct iwl_self_init_dram *dram = &trans->init_dram;
66 int i;
67
68 if (!dram->paging) {
69 WARN_ON(dram->paging_cnt);
70 return;
71 }
72
73 /* free paging*/
74 for (i = 0; i < dram->paging_cnt; i++)
75 dma_free_coherent(trans->dev, dram->paging[i].size,
76 dram->paging[i].block,
77 dram->paging[i].physical);
78
79 kfree(dram->paging);
80 dram->paging_cnt = 0;
81 dram->paging = NULL;
82 }
83
iwl_pcie_init_fw_sec(struct iwl_trans * trans,const struct fw_img * fw,struct iwl_context_info_dram_nonfseq * ctxt_dram)84 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
85 const struct fw_img *fw,
86 struct iwl_context_info_dram_nonfseq *ctxt_dram)
87 {
88 struct iwl_self_init_dram *dram = &trans->init_dram;
89 int i, ret, lmac_cnt, umac_cnt, paging_cnt;
90
91 if (WARN(dram->paging,
92 "paging shouldn't already be initialized (%d pages)\n",
93 dram->paging_cnt))
94 iwl_pcie_ctxt_info_free_paging(trans);
95
96 lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
97 /* add 1 due to separator */
98 umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
99 /* add 2 due to separators */
100 paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
101
102 if (WARN_ON(lmac_cnt > ARRAY_SIZE(ctxt_dram->lmac_img) ||
103 umac_cnt > ARRAY_SIZE(ctxt_dram->umac_img) ||
104 paging_cnt > ARRAY_SIZE(ctxt_dram->virtual_img)))
105 return -EINVAL;
106
107 dram->fw = kzalloc_objs(*dram->fw, umac_cnt + lmac_cnt);
108 if (!dram->fw)
109 return -ENOMEM;
110 dram->paging = kzalloc_objs(*dram->paging, paging_cnt);
111 if (!dram->paging)
112 return -ENOMEM;
113
114 /* initialize lmac sections */
115 for (i = 0; i < lmac_cnt; i++) {
116 ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
117 fw->sec[i].len,
118 &dram->fw[dram->fw_cnt]);
119 if (ret)
120 return ret;
121 ctxt_dram->lmac_img[i] =
122 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
123 dram->fw_cnt++;
124 }
125
126 /* initialize umac sections */
127 for (i = 0; i < umac_cnt; i++) {
128 /* access FW with +1 to make up for lmac separator */
129 ret = iwl_pcie_ctxt_info_alloc_dma(trans,
130 fw->sec[dram->fw_cnt + 1].data,
131 fw->sec[dram->fw_cnt + 1].len,
132 &dram->fw[dram->fw_cnt]);
133 if (ret)
134 return ret;
135 ctxt_dram->umac_img[i] =
136 cpu_to_le64(dram->fw[dram->fw_cnt].physical);
137 dram->fw_cnt++;
138 }
139
140 /*
141 * Initialize paging.
142 * Paging memory isn't stored in dram->fw as the umac and lmac - it is
143 * stored separately.
144 * This is since the timing of its release is different -
145 * while fw memory can be released on alive, the paging memory can be
146 * freed only when the device goes down.
147 * Given that, the logic here in accessing the fw image is a bit
148 * different - fw_cnt isn't changing so loop counter is added to it.
149 */
150 for (i = 0; i < paging_cnt; i++) {
151 /* access FW with +2 to make up for lmac & umac separators */
152 int fw_idx = dram->fw_cnt + i + 2;
153
154 ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
155 fw->sec[fw_idx].len,
156 &dram->paging[i]);
157 if (ret)
158 return ret;
159
160 ctxt_dram->virtual_img[i] =
161 cpu_to_le64(dram->paging[i].physical);
162 dram->paging_cnt++;
163 }
164
165 return 0;
166 }
167
iwl_pcie_ctxt_info_init(struct iwl_trans * trans,const struct fw_img * img)168 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
169 const struct fw_img *img)
170 {
171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
172 struct iwl_context_info *ctxt_info;
173 struct iwl_context_info_rbd_cfg *rx_cfg;
174 u32 control_flags = 0, rb_size, cb_size;
175 dma_addr_t phys;
176 int ret;
177
178 ctxt_info = iwl_pcie_ctxt_info_dma_alloc_coherent(trans,
179 sizeof(*ctxt_info),
180 &phys);
181 if (!ctxt_info)
182 return -ENOMEM;
183
184 trans_pcie->ctxt_info_dma_addr = phys;
185
186 ctxt_info->version.version = 0;
187 ctxt_info->version.mac_id =
188 cpu_to_le16((u16)trans->info.hw_rev);
189 /* size is in DWs */
190 ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
191
192 switch (trans->conf.rx_buf_size) {
193 case IWL_AMSDU_2K:
194 rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
195 break;
196 case IWL_AMSDU_4K:
197 rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
198 break;
199 case IWL_AMSDU_8K:
200 rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
201 break;
202 case IWL_AMSDU_12K:
203 rb_size = IWL_CTXT_INFO_RB_SIZE_16K;
204 break;
205 default:
206 WARN_ON(1);
207 rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
208 }
209
210 cb_size = RX_QUEUE_CB_SIZE(iwl_trans_get_num_rbds(trans));
211 if (WARN_ON(cb_size > 12))
212 cb_size = 12;
213
214 control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
215 control_flags |= u32_encode_bits(cb_size, IWL_CTXT_INFO_RB_CB_SIZE);
216 control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
217 ctxt_info->control.control_flags = cpu_to_le32(control_flags);
218
219 /* initialize RX default queue */
220 rx_cfg = &ctxt_info->rbd_cfg;
221 rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
222 rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
223 rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
224
225 /* initialize TX command queue */
226 ctxt_info->hcmd_cfg.cmd_queue_addr =
227 cpu_to_le64(trans_pcie->txqs.txq[trans->conf.cmd_queue]->dma_addr);
228 ctxt_info->hcmd_cfg.cmd_queue_size =
229 TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
230
231 /* allocate ucode sections in dram and set addresses */
232 ret = iwl_pcie_init_fw_sec(trans, img, &ctxt_info->dram);
233 if (ret) {
234 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
235 ctxt_info, trans_pcie->ctxt_info_dma_addr);
236 return ret;
237 }
238
239 trans_pcie->ctxt_info = ctxt_info;
240
241 iwl_enable_fw_load_int_ctx_info(trans, false);
242
243 /* Configure debug, if exists */
244 if (iwl_pcie_dbg_on(trans))
245 iwl_pcie_apply_destination(trans);
246
247 /* kick FW self load */
248 iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
249
250 /* Context info will be released upon alive or failure to get one */
251
252 return 0;
253 }
254
iwl_pcie_ctxt_info_free(struct iwl_trans * trans)255 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
256 {
257 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
258
259 if (!trans_pcie->ctxt_info)
260 return;
261
262 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
263 trans_pcie->ctxt_info,
264 trans_pcie->ctxt_info_dma_addr);
265 trans_pcie->ctxt_info_dma_addr = 0;
266 trans_pcie->ctxt_info = NULL;
267
268 iwl_pcie_ctxt_info_free_fw_img(trans);
269 }
270