1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VMX-preemption timer test 4 * 5 * Copyright (C) 2020, Google, LLC. 6 * 7 * Test to ensure the VM-Enter after migration doesn't 8 * incorrectly restarts the timer with the full timer 9 * value instead of partially decayed timer value 10 * 11 */ 12 #include <fcntl.h> 13 #include <stdio.h> 14 #include <stdlib.h> 15 #include <string.h> 16 #include <sys/ioctl.h> 17 18 #include "test_util.h" 19 20 #include "kvm_util.h" 21 #include "processor.h" 22 #include "vmx.h" 23 24 #define PREEMPTION_TIMER_VALUE 100000000ull 25 #define PREEMPTION_TIMER_VALUE_THRESHOLD1 80000000ull 26 27 u32 vmx_pt_rate; 28 bool l2_save_restore_done; 29 static u64 l2_vmx_pt_start; 30 volatile u64 l2_vmx_pt_finish; 31 32 union vmx_basic basic; 33 union vmx_ctrl_msr ctrl_pin_rev; 34 union vmx_ctrl_msr ctrl_exit_rev; 35 36 void l2_guest_code(void) 37 { 38 u64 vmx_pt_delta; 39 40 vmcall(); 41 l2_vmx_pt_start = (rdtsc() >> vmx_pt_rate) << vmx_pt_rate; 42 43 /* 44 * Wait until the 1st threshold has passed 45 */ 46 do { 47 l2_vmx_pt_finish = rdtsc(); 48 vmx_pt_delta = (l2_vmx_pt_finish - l2_vmx_pt_start) >> 49 vmx_pt_rate; 50 } while (vmx_pt_delta < PREEMPTION_TIMER_VALUE_THRESHOLD1); 51 52 /* 53 * Force L2 through Save and Restore cycle 54 */ 55 GUEST_SYNC(1); 56 57 l2_save_restore_done = 1; 58 59 /* 60 * Now wait for the preemption timer to fire and 61 * exit to L1 62 */ 63 while ((l2_vmx_pt_finish = rdtsc())) 64 ; 65 } 66 67 void l1_guest_code(struct vmx_pages *vmx_pages) 68 { 69 u64 l1_vmx_pt_start; 70 u64 l1_vmx_pt_finish; 71 u64 l1_tsc_deadline, l2_tsc_deadline; 72 73 GUEST_ASSERT(vmx_pages->vmcs_gpa); 74 GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages)); 75 GUEST_ASSERT(load_vmcs(vmx_pages)); 76 GUEST_ASSERT(vmptrstz() == vmx_pages->vmcs_gpa); 77 78 prepare_vmcs(vmx_pages, l2_guest_code); 79 80 /* 81 * Check for Preemption timer support 82 */ 83 basic.val = rdmsr(MSR_IA32_VMX_BASIC); 84 ctrl_pin_rev.val = rdmsr(basic.ctrl ? MSR_IA32_VMX_TRUE_PINBASED_CTLS 85 : MSR_IA32_VMX_PINBASED_CTLS); 86 ctrl_exit_rev.val = rdmsr(basic.ctrl ? MSR_IA32_VMX_TRUE_EXIT_CTLS 87 : MSR_IA32_VMX_EXIT_CTLS); 88 89 if (!(ctrl_pin_rev.clr & PIN_BASED_VMX_PREEMPTION_TIMER) || 90 !(ctrl_exit_rev.clr & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) 91 return; 92 93 GUEST_ASSERT(!vmlaunch()); 94 GUEST_ASSERT(vmreadz(VM_EXIT_REASON) == EXIT_REASON_VMCALL); 95 vmwrite(GUEST_RIP, vmreadz(GUEST_RIP) + vmreadz(VM_EXIT_INSTRUCTION_LEN)); 96 97 /* 98 * Turn on PIN control and resume the guest 99 */ 100 GUEST_ASSERT(!vmwrite(PIN_BASED_VM_EXEC_CONTROL, 101 vmreadz(PIN_BASED_VM_EXEC_CONTROL) | 102 PIN_BASED_VMX_PREEMPTION_TIMER)); 103 104 GUEST_ASSERT(!vmwrite(VMX_PREEMPTION_TIMER_VALUE, 105 PREEMPTION_TIMER_VALUE)); 106 107 vmx_pt_rate = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 108 109 l2_save_restore_done = 0; 110 111 l1_vmx_pt_start = (rdtsc() >> vmx_pt_rate) << vmx_pt_rate; 112 113 GUEST_ASSERT(!vmresume()); 114 115 l1_vmx_pt_finish = rdtsc(); 116 117 /* 118 * Ensure exit from L2 happens after L2 goes through 119 * save and restore 120 */ 121 GUEST_ASSERT(l2_save_restore_done); 122 123 /* 124 * Ensure the exit from L2 is due to preemption timer expiry 125 */ 126 GUEST_ASSERT(vmreadz(VM_EXIT_REASON) == EXIT_REASON_PREEMPTION_TIMER); 127 128 l1_tsc_deadline = l1_vmx_pt_start + 129 (PREEMPTION_TIMER_VALUE << vmx_pt_rate); 130 131 l2_tsc_deadline = l2_vmx_pt_start + 132 (PREEMPTION_TIMER_VALUE << vmx_pt_rate); 133 134 /* 135 * Sync with the host and pass the l1|l2 pt_expiry_finish times and 136 * tsc deadlines so that host can verify they are as expected 137 */ 138 GUEST_SYNC_ARGS(2, l1_vmx_pt_finish, l1_tsc_deadline, 139 l2_vmx_pt_finish, l2_tsc_deadline); 140 } 141 142 void guest_code(struct vmx_pages *vmx_pages) 143 { 144 if (vmx_pages) 145 l1_guest_code(vmx_pages); 146 147 GUEST_DONE(); 148 } 149 150 int main(int argc, char *argv[]) 151 { 152 gva_t vmx_pages_gva = 0; 153 154 struct kvm_regs regs1, regs2; 155 struct kvm_vm *vm; 156 struct kvm_vcpu *vcpu; 157 struct kvm_x86_state *state; 158 struct ucall uc; 159 int stage; 160 161 /* 162 * AMD currently does not implement any VMX features, so for now we 163 * just early out. 164 */ 165 TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX)); 166 167 TEST_REQUIRE(kvm_has_cap(KVM_CAP_NESTED_STATE)); 168 169 /* Create VM */ 170 vm = vm_create_with_one_vcpu(&vcpu, guest_code); 171 172 vcpu_regs_get(vcpu, ®s1); 173 174 vcpu_alloc_vmx(vm, &vmx_pages_gva); 175 vcpu_args_set(vcpu, 1, vmx_pages_gva); 176 177 for (stage = 1;; stage++) { 178 vcpu_run(vcpu); 179 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); 180 181 switch (get_ucall(vcpu, &uc)) { 182 case UCALL_ABORT: 183 REPORT_GUEST_ASSERT(uc); 184 /* NOT REACHED */ 185 case UCALL_SYNC: 186 break; 187 case UCALL_DONE: 188 goto done; 189 default: 190 TEST_FAIL("Unknown ucall %lu", uc.cmd); 191 } 192 193 /* UCALL_SYNC is handled here. */ 194 TEST_ASSERT(!strcmp((const char *)uc.args[0], "hello") && 195 uc.args[1] == stage, "Stage %d: Unexpected register values vmexit, got %lx", 196 stage, (ulong)uc.args[1]); 197 /* 198 * If this stage 2 then we should verify the vmx pt expiry 199 * is as expected. 200 * From L1's perspective verify Preemption timer hasn't 201 * expired too early. 202 * From L2's perspective verify Preemption timer hasn't 203 * expired too late. 204 */ 205 if (stage == 2) { 206 207 pr_info("Stage %d: L1 PT expiry TSC (%lu) , L1 TSC deadline (%lu)\n", 208 stage, uc.args[2], uc.args[3]); 209 210 pr_info("Stage %d: L2 PT expiry TSC (%lu) , L2 TSC deadline (%lu)\n", 211 stage, uc.args[4], uc.args[5]); 212 213 TEST_ASSERT(uc.args[2] >= uc.args[3], 214 "Stage %d: L1 PT expiry TSC (%lu) < L1 TSC deadline (%lu)", 215 stage, uc.args[2], uc.args[3]); 216 217 TEST_ASSERT(uc.args[4] < uc.args[5], 218 "Stage %d: L2 PT expiry TSC (%lu) > L2 TSC deadline (%lu)", 219 stage, uc.args[4], uc.args[5]); 220 } 221 222 state = vcpu_save_state(vcpu); 223 memset(®s1, 0, sizeof(regs1)); 224 vcpu_regs_get(vcpu, ®s1); 225 226 kvm_vm_release(vm); 227 228 /* Restore state in a new VM. */ 229 vcpu = vm_recreate_with_one_vcpu(vm); 230 vcpu_load_state(vcpu, state); 231 kvm_x86_state_cleanup(state); 232 233 memset(®s2, 0, sizeof(regs2)); 234 vcpu_regs_get(vcpu, ®s2); 235 TEST_ASSERT(!memcmp(®s1, ®s2, sizeof(regs2)), 236 "Unexpected register values after vcpu_load_state; rdi: %lx rsi: %lx", 237 (ulong) regs2.rdi, (ulong) regs2.rsi); 238 } 239 240 done: 241 kvm_vm_free(vm); 242 } 243