1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * adv7180.c Analog Devices ADV7180 video decoder driver
4 * Copyright (c) 2009 Intel Corporation
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 */
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/interrupt.h>
13 #include <linux/i2c.h>
14 #include <linux/slab.h>
15 #include <linux/of.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ctrls.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
24
25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
29 #define ADV7180_STD_NTSC_J 0x4
30 #define ADV7180_STD_NTSC_M 0x5
31 #define ADV7180_STD_PAL60 0x6
32 #define ADV7180_STD_NTSC_443 0x7
33 #define ADV7180_STD_PAL_BG 0x8
34 #define ADV7180_STD_PAL_N 0x9
35 #define ADV7180_STD_PAL_M 0xa
36 #define ADV7180_STD_PAL_M_PED 0xb
37 #define ADV7180_STD_PAL_COMB_N 0xc
38 #define ADV7180_STD_PAL_COMB_N_PED 0xd
39 #define ADV7180_STD_PAL_SECAM 0xe
40 #define ADV7180_STD_PAL_SECAM_PED 0xf
41
42 #define ADV7180_REG_INPUT_CONTROL 0x0000
43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
44
45 #define ADV7182_REG_INPUT_VIDSEL 0x0002
46 #define ADV7182_REG_INPUT_RESERVED BIT(2)
47
48 #define ADV7180_REG_OUTPUT_CONTROL 0x0003
49 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
50 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
51
52 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007
53 #define ADV7180_AUTODETECT_DEFAULT 0x7f
54 /* Contrast */
55 #define ADV7180_REG_CON 0x0008 /*Unsigned */
56 #define ADV7180_CON_MIN 0
57 #define ADV7180_CON_DEF 128
58 #define ADV7180_CON_MAX 255
59 /* Brightness*/
60 #define ADV7180_REG_BRI 0x000a /*Signed */
61 #define ADV7180_BRI_MIN -128
62 #define ADV7180_BRI_DEF 0
63 #define ADV7180_BRI_MAX 127
64 /* Hue */
65 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
66 #define ADV7180_HUE_MIN -127
67 #define ADV7180_HUE_DEF 0
68 #define ADV7180_HUE_MAX 128
69
70 #define ADV7180_REG_DEF_VALUE_Y 0x000c
71 #define ADV7180_DEF_VAL_EN 0x1
72 #define ADV7180_DEF_VAL_AUTO_EN 0x2
73 #define ADV7180_REG_CTRL 0x000e
74 #define ADV7180_CTRL_IRQ_SPACE 0x20
75
76 #define ADV7180_REG_PWR_MAN 0x0f
77 #define ADV7180_PWR_MAN_ON 0x04
78 #define ADV7180_PWR_MAN_OFF 0x24
79 #define ADV7180_PWR_MAN_RES 0x80
80
81 #define ADV7180_REG_STATUS1 0x0010
82 #define ADV7180_STATUS1_IN_LOCK 0x01
83 #define ADV7180_STATUS1_AUTOD_MASK 0x70
84 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
85 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
86 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
87 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
88 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
89 #define ADV7180_STATUS1_AUTOD_SECAM 0x50
90 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
91 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
92
93 #define ADV7180_REG_IDENT 0x0011
94 #define ADV7180_ID_7180 0x18
95
96 #define ADV7180_REG_STATUS3 0x0013
97 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014
98 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017
99 #define ADV7180_REG_CTRL_2 0x001d
100 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031
101 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
102 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d
103 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e
104 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f
105 #define ADV7180_REG_LOCK_CNT 0x0051
106 #define ADV7180_REG_CVBS_TRIM 0x0052
107 #define ADV7180_REG_CLAMP_ADJ 0x005a
108 #define ADV7180_REG_RES_CIR 0x005f
109 #define ADV7180_REG_DIFF_MODE 0x0060
110
111 #define ADV7180_REG_ICONF1 0x2040
112 #define ADV7180_ICONF1_ACTIVE_LOW 0x01
113 #define ADV7180_ICONF1_PSYNC_ONLY 0x10
114 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
115 /* Saturation */
116 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
117 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
118 #define ADV7180_SAT_MIN 0
119 #define ADV7180_SAT_DEF 128
120 #define ADV7180_SAT_MAX 255
121
122 #define ADV7180_IRQ1_LOCK 0x01
123 #define ADV7180_IRQ1_UNLOCK 0x02
124 #define ADV7180_REG_ISR1 0x2042
125 #define ADV7180_REG_ICR1 0x2043
126 #define ADV7180_REG_IMR1 0x2044
127 #define ADV7180_REG_IMR2 0x2048
128 #define ADV7180_IRQ3_AD_CHANGE 0x08
129 #define ADV7180_REG_ISR3 0x204A
130 #define ADV7180_REG_ICR3 0x204B
131 #define ADV7180_REG_IMR3 0x204C
132 #define ADV7180_REG_IMR4 0x2050
133
134 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
135 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
136
137 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
138 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
139
140 #define ADV7180_REG_ACE_CTRL1 0x4080
141 #define ADV7180_REG_ACE_CTRL5 0x4084
142 #define ADV7180_REG_FLCONTROL 0x40e0
143 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
144
145 #define ADV7180_REG_RST_CLAMP 0x809c
146 #define ADV7180_REG_AGC_ADJ1 0x80b6
147 #define ADV7180_REG_AGC_ADJ2 0x80c0
148
149 #define ADV7180_CSI_REG_PWRDN 0x00
150 #define ADV7180_CSI_PWRDN 0x80
151
152 #define ADV7180_INPUT_CVBS_AIN1 0x00
153 #define ADV7180_INPUT_CVBS_AIN2 0x01
154 #define ADV7180_INPUT_CVBS_AIN3 0x02
155 #define ADV7180_INPUT_CVBS_AIN4 0x03
156 #define ADV7180_INPUT_CVBS_AIN5 0x04
157 #define ADV7180_INPUT_CVBS_AIN6 0x05
158 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
159 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
160 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
161 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
162 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
163
164 #define ADV7182_INPUT_CVBS_AIN1 0x00
165 #define ADV7182_INPUT_CVBS_AIN2 0x01
166 #define ADV7182_INPUT_CVBS_AIN3 0x02
167 #define ADV7182_INPUT_CVBS_AIN4 0x03
168 #define ADV7182_INPUT_CVBS_AIN5 0x04
169 #define ADV7182_INPUT_CVBS_AIN6 0x05
170 #define ADV7182_INPUT_CVBS_AIN7 0x06
171 #define ADV7182_INPUT_CVBS_AIN8 0x07
172 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
173 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
174 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
175 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
176 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
177 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
178 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
179 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
180 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
181 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
182
183 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
184 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
185
186 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
187
188 /* Initial number of frames to skip to avoid possible garbage */
189 #define ADV7180_NUM_OF_SKIP_FRAMES 2
190
191 struct adv7180_state;
192
193 #define ADV7180_FLAG_RESET_POWERED BIT(0)
194 #define ADV7180_FLAG_V2 BIT(1)
195 #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
196 #define ADV7180_FLAG_I2P BIT(3)
197 #define ADV7180_FLAG_TEST_PATTERN BIT(4)
198
199 struct adv7180_chip_info {
200 unsigned int flags;
201 unsigned int valid_input_mask;
202 int (*set_std)(struct adv7180_state *st, unsigned int std);
203 int (*select_input)(struct adv7180_state *st, unsigned int input);
204 int (*init)(struct adv7180_state *state);
205 };
206
207 struct adv7180_state {
208 struct v4l2_ctrl_handler ctrl_hdl;
209 struct v4l2_subdev sd;
210 struct media_pad pad;
211 struct mutex mutex; /* mutual excl. when accessing chip */
212 int irq;
213 struct gpio_desc *pwdn_gpio;
214 struct gpio_desc *rst_gpio;
215 v4l2_std_id curr_norm;
216 bool streaming;
217 u8 input;
218
219 struct i2c_client *client;
220 unsigned int register_page;
221 struct i2c_client *csi_client;
222 struct i2c_client *vpp_client;
223 const struct adv7180_chip_info *chip_info;
224 enum v4l2_field field;
225 bool force_bt656_4;
226 };
227 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
228 struct adv7180_state, \
229 ctrl_hdl)->sd)
230
adv7180_select_page(struct adv7180_state * state,unsigned int page)231 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
232 {
233 if (state->register_page != page) {
234 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
235 page);
236 state->register_page = page;
237 }
238
239 return 0;
240 }
241
adv7180_write(struct adv7180_state * state,unsigned int reg,unsigned int value)242 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
243 unsigned int value)
244 {
245 lockdep_assert_held(&state->mutex);
246 adv7180_select_page(state, reg >> 8);
247 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
248 }
249
adv7180_read(struct adv7180_state * state,unsigned int reg)250 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
251 {
252 lockdep_assert_held(&state->mutex);
253 adv7180_select_page(state, reg >> 8);
254 return i2c_smbus_read_byte_data(state->client, reg & 0xff);
255 }
256
adv7180_csi_write(struct adv7180_state * state,unsigned int reg,unsigned int value)257 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
258 unsigned int value)
259 {
260 return i2c_smbus_write_byte_data(state->csi_client, reg, value);
261 }
262
adv7180_set_video_standard(struct adv7180_state * state,unsigned int std)263 static int adv7180_set_video_standard(struct adv7180_state *state,
264 unsigned int std)
265 {
266 return state->chip_info->set_std(state, std);
267 }
268
adv7180_vpp_write(struct adv7180_state * state,unsigned int reg,unsigned int value)269 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
270 unsigned int value)
271 {
272 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
273 }
274
adv7180_set_power(struct adv7180_state * state,bool on)275 static int adv7180_set_power(struct adv7180_state *state, bool on)
276 {
277 u8 val;
278 int ret;
279
280 if (on)
281 val = ADV7180_PWR_MAN_ON;
282 else
283 val = ADV7180_PWR_MAN_OFF;
284
285 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
286 if (ret)
287 return ret;
288
289 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
290 if (on) {
291 adv7180_csi_write(state, 0xDE, 0x02);
292 adv7180_csi_write(state, 0xD2, 0xF7);
293 adv7180_csi_write(state, 0xD8, 0x65);
294 adv7180_csi_write(state, 0xE0, 0x09);
295 adv7180_csi_write(state, 0x2C, 0x00);
296 if (state->field == V4L2_FIELD_NONE)
297 adv7180_csi_write(state, 0x1D, 0x80);
298 adv7180_csi_write(state, 0x00, 0x00);
299 } else {
300 adv7180_csi_write(state, 0x00, 0x80);
301 }
302 }
303
304 return 0;
305 }
306
adv7180_std_to_v4l2(u8 status1)307 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
308 {
309 /* in case V4L2_IN_ST_NO_SIGNAL */
310 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
311 return V4L2_STD_UNKNOWN;
312
313 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
314 case ADV7180_STATUS1_AUTOD_NTSM_M_J:
315 return V4L2_STD_NTSC;
316 case ADV7180_STATUS1_AUTOD_NTSC_4_43:
317 return V4L2_STD_NTSC_443;
318 case ADV7180_STATUS1_AUTOD_PAL_M:
319 return V4L2_STD_PAL_M;
320 case ADV7180_STATUS1_AUTOD_PAL_60:
321 return V4L2_STD_PAL_60;
322 case ADV7180_STATUS1_AUTOD_PAL_B_G:
323 return V4L2_STD_PAL;
324 case ADV7180_STATUS1_AUTOD_SECAM:
325 return V4L2_STD_SECAM;
326 case ADV7180_STATUS1_AUTOD_PAL_COMB:
327 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
328 case ADV7180_STATUS1_AUTOD_SECAM_525:
329 return V4L2_STD_SECAM;
330 default:
331 return V4L2_STD_UNKNOWN;
332 }
333 }
334
v4l2_std_to_adv7180(v4l2_std_id std)335 static int v4l2_std_to_adv7180(v4l2_std_id std)
336 {
337 if (std == V4L2_STD_PAL_60)
338 return ADV7180_STD_PAL60;
339 if (std == V4L2_STD_NTSC_443)
340 return ADV7180_STD_NTSC_443;
341 if (std == V4L2_STD_PAL_N)
342 return ADV7180_STD_PAL_N;
343 if (std == V4L2_STD_PAL_M)
344 return ADV7180_STD_PAL_M;
345 if (std == V4L2_STD_PAL_Nc)
346 return ADV7180_STD_PAL_COMB_N;
347
348 if (std & V4L2_STD_PAL)
349 return ADV7180_STD_PAL_BG;
350 if (std & V4L2_STD_NTSC)
351 return ADV7180_STD_NTSC_M;
352 if (std & V4L2_STD_SECAM)
353 return ADV7180_STD_PAL_SECAM;
354
355 return -EINVAL;
356 }
357
adv7180_status_to_v4l2(u8 status1)358 static u32 adv7180_status_to_v4l2(u8 status1)
359 {
360 if (!(status1 & ADV7180_STATUS1_IN_LOCK))
361 return V4L2_IN_ST_NO_SIGNAL;
362
363 return 0;
364 }
365
__adv7180_status(struct adv7180_state * state,u32 * status,v4l2_std_id * std)366 static int __adv7180_status(struct adv7180_state *state, u32 *status,
367 v4l2_std_id *std)
368 {
369 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
370
371 if (status1 < 0)
372 return status1;
373
374 if (status)
375 *status = adv7180_status_to_v4l2(status1);
376 if (std)
377 *std = adv7180_std_to_v4l2(status1);
378
379 return 0;
380 }
381
to_state(struct v4l2_subdev * sd)382 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
383 {
384 return container_of(sd, struct adv7180_state, sd);
385 }
386
adv7180_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)387 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
388 {
389 struct adv7180_state *state = to_state(sd);
390 int ret;
391
392 guard(mutex)(&state->mutex);
393
394 /*
395 * We can't sample the standard if the device is streaming as that would
396 * interfere with the capture session as the VID_SEL reg is touched.
397 */
398 if (state->streaming)
399 return -EBUSY;
400
401 /* Set the standard to autodetect PAL B/G/H/I/D, NTSC J or SECAM */
402 ret = adv7180_set_video_standard(state,
403 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
404 if (ret)
405 return ret;
406
407 /* Allow some time for the autodetection to run. */
408 msleep(100);
409
410 return __adv7180_status(state, NULL, std);
411 }
412
adv7180_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)413 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
414 u32 output, u32 config)
415 {
416 struct adv7180_state *state = to_state(sd);
417 int ret = mutex_lock_interruptible(&state->mutex);
418
419 if (ret)
420 return ret;
421
422 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
423 ret = -EINVAL;
424 goto out;
425 }
426
427 ret = state->chip_info->select_input(state, input);
428
429 if (ret == 0)
430 state->input = input;
431 out:
432 mutex_unlock(&state->mutex);
433 return ret;
434 }
435
adv7180_g_input_status(struct v4l2_subdev * sd,u32 * status)436 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
437 {
438 struct adv7180_state *state = to_state(sd);
439 int ret = mutex_lock_interruptible(&state->mutex);
440 if (ret)
441 return ret;
442
443 ret = __adv7180_status(state, status, NULL);
444 mutex_unlock(&state->mutex);
445 return ret;
446 }
447
adv7180_program_std(struct adv7180_state * state)448 static int adv7180_program_std(struct adv7180_state *state)
449 {
450 int ret;
451
452 ret = v4l2_std_to_adv7180(state->curr_norm);
453 if (ret < 0)
454 return ret;
455
456 ret = adv7180_set_video_standard(state, ret);
457 if (ret < 0)
458 return ret;
459 return 0;
460 }
461
adv7180_s_std(struct v4l2_subdev * sd,v4l2_std_id std)462 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
463 {
464 struct adv7180_state *state = to_state(sd);
465 int ret;
466
467 guard(mutex)(&state->mutex);
468
469 /* Make sure we can support this std */
470 ret = v4l2_std_to_adv7180(std);
471 if (ret < 0)
472 return ret;
473
474 state->curr_norm = std;
475
476 return 0;
477 }
478
adv7180_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)479 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
480 {
481 struct adv7180_state *state = to_state(sd);
482
483 *norm = state->curr_norm;
484
485 return 0;
486 }
487
adv7180_get_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)488 static int adv7180_get_frame_interval(struct v4l2_subdev *sd,
489 struct v4l2_subdev_state *sd_state,
490 struct v4l2_subdev_frame_interval *fi)
491 {
492 struct adv7180_state *state = to_state(sd);
493
494 /*
495 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
496 * subdev active state API.
497 */
498 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
499 return -EINVAL;
500
501 if (state->curr_norm & V4L2_STD_525_60) {
502 fi->interval.numerator = 1001;
503 fi->interval.denominator = 30000;
504 } else {
505 fi->interval.numerator = 1;
506 fi->interval.denominator = 25;
507 }
508
509 /*
510 * If the de-interlacer is active, the chip produces full video frames
511 * at the field rate.
512 */
513 if (state->field == V4L2_FIELD_NONE)
514 fi->interval.denominator *= 2;
515
516 return 0;
517 }
518
adv7180_set_power_pin(struct adv7180_state * state,bool on)519 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
520 {
521 if (!state->pwdn_gpio)
522 return;
523
524 if (on) {
525 gpiod_set_value_cansleep(state->pwdn_gpio, 0);
526 usleep_range(5000, 10000);
527 } else {
528 gpiod_set_value_cansleep(state->pwdn_gpio, 1);
529 }
530 }
531
adv7180_set_reset_pin(struct adv7180_state * state,bool on)532 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
533 {
534 if (!state->rst_gpio)
535 return;
536
537 if (on) {
538 gpiod_set_value_cansleep(state->rst_gpio, 1);
539 } else {
540 gpiod_set_value_cansleep(state->rst_gpio, 0);
541 usleep_range(5000, 10000);
542 }
543 }
544
545 static const char * const test_pattern_menu[] = {
546 "Single color",
547 "Color bars",
548 "Luma ramp",
549 "Boundary box",
550 "Disable",
551 };
552
adv7180_test_pattern(struct adv7180_state * state,int value)553 static int adv7180_test_pattern(struct adv7180_state *state, int value)
554 {
555 unsigned int reg = 0;
556
557 /* Map menu value into register value */
558 if (value < 3)
559 reg = value;
560 if (value == 3)
561 reg = 5;
562
563 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
564
565 if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
566 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
567 reg &= ~ADV7180_DEF_VAL_EN;
568 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
569 return 0;
570 }
571
572 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
573 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
574 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
575
576 return 0;
577 }
578
adv7180_s_ctrl(struct v4l2_ctrl * ctrl)579 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
580 {
581 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
582 struct adv7180_state *state = to_state(sd);
583 int ret = 0;
584 int val;
585
586 lockdep_assert_held(&state->mutex);
587
588 val = ctrl->val;
589 switch (ctrl->id) {
590 case V4L2_CID_BRIGHTNESS:
591 ret = adv7180_write(state, ADV7180_REG_BRI, val);
592 break;
593 case V4L2_CID_HUE:
594 /*Hue is inverted according to HSL chart */
595 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
596 break;
597 case V4L2_CID_CONTRAST:
598 ret = adv7180_write(state, ADV7180_REG_CON, val);
599 break;
600 case V4L2_CID_SATURATION:
601 /*
602 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
603 *Let's not confuse the user, everybody understands saturation
604 */
605 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
606 if (ret < 0)
607 break;
608 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
609 break;
610 case V4L2_CID_ADV_FAST_SWITCH:
611 if (ctrl->val) {
612 /* ADI required write */
613 adv7180_write(state, 0x80d9, 0x44);
614 adv7180_write(state, ADV7180_REG_FLCONTROL,
615 ADV7180_FLCONTROL_FL_ENABLE);
616 } else {
617 /* ADI required write */
618 adv7180_write(state, 0x80d9, 0xc4);
619 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
620 }
621 break;
622 case V4L2_CID_TEST_PATTERN:
623 ret = adv7180_test_pattern(state, val);
624 break;
625 default:
626 ret = -EINVAL;
627 }
628
629 return ret;
630 }
631
632 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
633 .s_ctrl = adv7180_s_ctrl,
634 };
635
636 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
637 .ops = &adv7180_ctrl_ops,
638 .id = V4L2_CID_ADV_FAST_SWITCH,
639 .name = "Fast Switching",
640 .type = V4L2_CTRL_TYPE_BOOLEAN,
641 .min = 0,
642 .max = 1,
643 .step = 1,
644 };
645
adv7180_init_controls(struct adv7180_state * state)646 static int adv7180_init_controls(struct adv7180_state *state)
647 {
648 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
649 state->ctrl_hdl.lock = &state->mutex;
650
651 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
652 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
653 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
654 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
655 V4L2_CID_CONTRAST, ADV7180_CON_MIN,
656 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
657 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
658 V4L2_CID_SATURATION, ADV7180_SAT_MIN,
659 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
660 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
661 V4L2_CID_HUE, ADV7180_HUE_MIN,
662 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
663 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
664
665 if (state->chip_info->flags & ADV7180_FLAG_TEST_PATTERN) {
666 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl,
667 &adv7180_ctrl_ops,
668 V4L2_CID_TEST_PATTERN,
669 ARRAY_SIZE(test_pattern_menu) - 1,
670 0,
671 ARRAY_SIZE(test_pattern_menu) - 1,
672 test_pattern_menu);
673 }
674
675 state->sd.ctrl_handler = &state->ctrl_hdl;
676 if (state->ctrl_hdl.error) {
677 int err = state->ctrl_hdl.error;
678
679 v4l2_ctrl_handler_free(&state->ctrl_hdl);
680 return err;
681 }
682
683 return 0;
684 }
adv7180_exit_controls(struct adv7180_state * state)685 static void adv7180_exit_controls(struct adv7180_state *state)
686 {
687 v4l2_ctrl_handler_free(&state->ctrl_hdl);
688 }
689
adv7180_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)690 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
691 struct v4l2_subdev_state *sd_state,
692 struct v4l2_subdev_mbus_code_enum *code)
693 {
694 if (code->index != 0)
695 return -EINVAL;
696
697 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
698
699 return 0;
700 }
701
adv7180_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)702 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
703 struct v4l2_mbus_framefmt *fmt)
704 {
705 struct adv7180_state *state = to_state(sd);
706
707 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
708 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
709 fmt->width = 720;
710 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
711
712 if (state->field == V4L2_FIELD_ALTERNATE)
713 fmt->height /= 2;
714
715 return 0;
716 }
717
adv7180_set_field_mode(struct adv7180_state * state)718 static int adv7180_set_field_mode(struct adv7180_state *state)
719 {
720 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
721 return 0;
722
723 if (state->field == V4L2_FIELD_NONE) {
724 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
725 adv7180_csi_write(state, 0x01, 0x20);
726 adv7180_csi_write(state, 0x02, 0x28);
727 adv7180_csi_write(state, 0x03, 0x38);
728 adv7180_csi_write(state, 0x04, 0x30);
729 adv7180_csi_write(state, 0x05, 0x30);
730 adv7180_csi_write(state, 0x06, 0x80);
731 adv7180_csi_write(state, 0x07, 0x70);
732 adv7180_csi_write(state, 0x08, 0x50);
733 }
734 adv7180_vpp_write(state, 0xa3, 0x00);
735 adv7180_vpp_write(state, 0x5b, 0x00);
736 adv7180_vpp_write(state, 0x55, 0x80);
737 } else {
738 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
739 adv7180_csi_write(state, 0x01, 0x18);
740 adv7180_csi_write(state, 0x02, 0x18);
741 adv7180_csi_write(state, 0x03, 0x30);
742 adv7180_csi_write(state, 0x04, 0x20);
743 adv7180_csi_write(state, 0x05, 0x28);
744 adv7180_csi_write(state, 0x06, 0x40);
745 adv7180_csi_write(state, 0x07, 0x58);
746 adv7180_csi_write(state, 0x08, 0x30);
747 }
748 adv7180_vpp_write(state, 0xa3, 0x70);
749 adv7180_vpp_write(state, 0x5b, 0x80);
750 adv7180_vpp_write(state, 0x55, 0x00);
751 }
752
753 return 0;
754 }
755
adv7180_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)756 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
757 struct v4l2_subdev_state *sd_state,
758 struct v4l2_subdev_format *format)
759 {
760 struct adv7180_state *state = to_state(sd);
761
762 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
763 format->format = *v4l2_subdev_state_get_format(sd_state, 0);
764 } else {
765 adv7180_mbus_fmt(sd, &format->format);
766 format->format.field = state->field;
767 }
768
769 return 0;
770 }
771
adv7180_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)772 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
773 struct v4l2_subdev_state *sd_state,
774 struct v4l2_subdev_format *format)
775 {
776 struct adv7180_state *state = to_state(sd);
777 struct v4l2_mbus_framefmt *framefmt;
778 int ret;
779
780 switch (format->format.field) {
781 case V4L2_FIELD_NONE:
782 if (state->chip_info->flags & ADV7180_FLAG_I2P)
783 break;
784 fallthrough;
785 default:
786 format->format.field = V4L2_FIELD_ALTERNATE;
787 break;
788 }
789
790 ret = adv7180_mbus_fmt(sd, &format->format);
791
792 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
793 state->field = format->format.field;
794 } else {
795 framefmt = v4l2_subdev_state_get_format(sd_state, 0);
796 *framefmt = format->format;
797 }
798
799 return ret;
800 }
801
adv7180_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)802 static int adv7180_init_state(struct v4l2_subdev *sd,
803 struct v4l2_subdev_state *sd_state)
804 {
805 struct v4l2_subdev_format fmt = {
806 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
807 : V4L2_SUBDEV_FORMAT_ACTIVE,
808 };
809
810 return adv7180_set_pad_format(sd, sd_state, &fmt);
811 }
812
adv7180_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)813 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
814 unsigned int pad,
815 struct v4l2_mbus_config *cfg)
816 {
817 struct adv7180_state *state = to_state(sd);
818
819 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
820 cfg->type = V4L2_MBUS_CSI2_DPHY;
821 cfg->bus.mipi_csi2.num_data_lanes = 1;
822 cfg->bus.mipi_csi2.flags = 0;
823 } else {
824 /*
825 * The ADV7180 sensor supports BT.601/656 output modes.
826 * The BT.656 is default and not yet configurable by s/w.
827 */
828 cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
829 V4L2_MBUS_PCLK_SAMPLE_RISING |
830 V4L2_MBUS_DATA_ACTIVE_HIGH;
831 cfg->type = V4L2_MBUS_BT656;
832 }
833
834 return 0;
835 }
836
adv7180_get_skip_frames(struct v4l2_subdev * sd,u32 * frames)837 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
838 {
839 *frames = ADV7180_NUM_OF_SKIP_FRAMES;
840
841 return 0;
842 }
843
adv7180_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)844 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
845 {
846 *norm = V4L2_STD_ALL;
847 return 0;
848 }
849
init_device(struct adv7180_state * state)850 static int init_device(struct adv7180_state *state)
851 {
852 int ret;
853
854 lockdep_assert_held(&state->mutex);
855
856 ret = adv7180_program_std(state);
857 if (ret)
858 return ret;
859
860 adv7180_set_field_mode(state);
861
862 __v4l2_ctrl_handler_setup(&state->ctrl_hdl);
863
864 return ret;
865 }
866
adv7180_reset_device(struct adv7180_state * state)867 static int adv7180_reset_device(struct adv7180_state *state)
868 {
869 int ret;
870
871 lockdep_assert_held(&state->mutex);
872
873 adv7180_set_power_pin(state, true);
874 adv7180_set_reset_pin(state, false);
875
876 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
877 usleep_range(5000, 10000);
878
879 /*
880 * If the devices decoder is power on after reset, power off so the
881 * device can be configured.
882 */
883 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
884 adv7180_set_power(state, false);
885
886 ret = state->chip_info->init(state);
887 if (ret)
888 return ret;
889
890 ret = init_device(state);
891 if (ret)
892 return ret;
893
894 /* register for interrupts */
895 if (state->irq > 0) {
896 /* config the Interrupt pin to be active low */
897 ret = adv7180_write(state, ADV7180_REG_ICONF1,
898 ADV7180_ICONF1_ACTIVE_LOW |
899 ADV7180_ICONF1_PSYNC_ONLY);
900 if (ret < 0)
901 return ret;
902
903 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
904 if (ret < 0)
905 return ret;
906
907 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
908 if (ret < 0)
909 return ret;
910
911 /* enable AD change interrupts */
912 ret = adv7180_write(state, ADV7180_REG_IMR3,
913 ADV7180_IRQ3_AD_CHANGE);
914 if (ret < 0)
915 return ret;
916
917 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
918 if (ret < 0)
919 return ret;
920 }
921
922 /*
923 * If the devices decoder is power on after reset, restore the power
924 * after configuration. This is to preserve the behavior of the driver,
925 * not doing this result in the first 35+ frames captured being garbage.
926 */
927 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
928 adv7180_set_power(state, true);
929
930 return 0;
931 }
932
adv7180_s_stream(struct v4l2_subdev * sd,int enable)933 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
934 {
935 struct adv7180_state *state = to_state(sd);
936 int ret;
937
938 /* Must wait until querystd released the lock */
939 guard(mutex)(&state->mutex);
940
941 /*
942 * Always power off the decoder even if streaming is to be enabled, the
943 * decoder needs to be off for the device to be configured.
944 */
945 ret = adv7180_set_power(state, false);
946 if (ret)
947 return ret;
948
949 if (enable) {
950 ret = init_device(state);
951 if (ret)
952 return ret;
953
954 ret = adv7180_set_power(state, true);
955 if (ret)
956 return ret;
957 }
958
959 state->streaming = enable;
960
961 return 0;
962 }
963
adv7180_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)964 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
965 struct v4l2_fh *fh,
966 struct v4l2_event_subscription *sub)
967 {
968 switch (sub->type) {
969 case V4L2_EVENT_SOURCE_CHANGE:
970 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
971 case V4L2_EVENT_CTRL:
972 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
973 default:
974 return -EINVAL;
975 }
976 }
977
978 #ifdef CONFIG_VIDEO_ADV_DEBUG
adv7180_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)979 static int adv7180_g_register(struct v4l2_subdev *sd,
980 struct v4l2_dbg_register *reg)
981 {
982 struct adv7180_state *state = to_state(sd);
983 int ret;
984
985 ret = adv7180_read(state, reg->reg);
986 if (ret < 0)
987 return ret;
988
989 reg->val = ret;
990 reg->size = 1;
991
992 return 0;
993 }
994
adv7180_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)995 static int adv7180_s_register(struct v4l2_subdev *sd,
996 const struct v4l2_dbg_register *reg)
997 {
998 struct adv7180_state *state = to_state(sd);
999
1000 return adv7180_write(state, reg->reg, reg->val);
1001 }
1002 #endif
1003
1004 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
1005 .s_std = adv7180_s_std,
1006 .g_std = adv7180_g_std,
1007 .querystd = adv7180_querystd,
1008 .g_input_status = adv7180_g_input_status,
1009 .s_routing = adv7180_s_routing,
1010 .g_tvnorms = adv7180_g_tvnorms,
1011 .s_stream = adv7180_s_stream,
1012 };
1013
1014 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
1015 .subscribe_event = adv7180_subscribe_event,
1016 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1017 #ifdef CONFIG_VIDEO_ADV_DEBUG
1018 .g_register = adv7180_g_register,
1019 .s_register = adv7180_s_register,
1020 #endif
1021 };
1022
1023 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
1024 .enum_mbus_code = adv7180_enum_mbus_code,
1025 .set_fmt = adv7180_set_pad_format,
1026 .get_fmt = adv7180_get_pad_format,
1027 .get_frame_interval = adv7180_get_frame_interval,
1028 .get_mbus_config = adv7180_get_mbus_config,
1029 };
1030
1031 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
1032 .g_skip_frames = adv7180_get_skip_frames,
1033 };
1034
1035 static const struct v4l2_subdev_ops adv7180_ops = {
1036 .core = &adv7180_core_ops,
1037 .video = &adv7180_video_ops,
1038 .pad = &adv7180_pad_ops,
1039 .sensor = &adv7180_sensor_ops,
1040 };
1041
1042 static const struct v4l2_subdev_internal_ops adv7180_internal_ops = {
1043 .init_state = adv7180_init_state,
1044 };
1045
adv7180_irq(int irq,void * devid)1046 static irqreturn_t adv7180_irq(int irq, void *devid)
1047 {
1048 struct adv7180_state *state = devid;
1049 u8 isr3;
1050
1051 mutex_lock(&state->mutex);
1052 isr3 = adv7180_read(state, ADV7180_REG_ISR3);
1053 /* clear */
1054 adv7180_write(state, ADV7180_REG_ICR3, isr3);
1055
1056 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
1057 static const struct v4l2_event src_ch = {
1058 .type = V4L2_EVENT_SOURCE_CHANGE,
1059 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1060 };
1061
1062 v4l2_subdev_notify_event(&state->sd, &src_ch);
1063 }
1064 mutex_unlock(&state->mutex);
1065
1066 return IRQ_HANDLED;
1067 }
1068
adv7180_init(struct adv7180_state * state)1069 static int adv7180_init(struct adv7180_state *state)
1070 {
1071 int ret;
1072
1073 /* ITU-R BT.656-4 compatible */
1074 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1075 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1076 if (ret < 0)
1077 return ret;
1078
1079 /* Manually set V bit end position in NTSC mode */
1080 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
1081 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1082 }
1083
adv7180_set_std(struct adv7180_state * state,unsigned int std)1084 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
1085 {
1086 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
1087 (std << 4) | state->input);
1088 }
1089
adv7180_select_input(struct adv7180_state * state,unsigned int input)1090 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
1091 {
1092 int ret;
1093
1094 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
1095 if (ret < 0)
1096 return ret;
1097
1098 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1099 ret |= input;
1100 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1101 }
1102
adv7182_init(struct adv7180_state * state)1103 static int adv7182_init(struct adv7180_state *state)
1104 {
1105 if (state->csi_client)
1106 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1107 state->csi_client->addr << 1);
1108
1109 if (state->vpp_client)
1110 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1111 state->vpp_client->addr << 1);
1112
1113 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1114 /* ADI recommended writes for improved video quality */
1115 adv7180_write(state, 0x0080, 0x51);
1116 adv7180_write(state, 0x0081, 0x51);
1117 adv7180_write(state, 0x0082, 0x68);
1118 }
1119
1120 /* ADI required writes */
1121 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1122 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1123 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1124 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1125 } else {
1126 if (state->chip_info->flags & ADV7180_FLAG_V2) {
1127 if (state->force_bt656_4) {
1128 /* ITU-R BT.656-4 compatible */
1129 adv7180_write(state,
1130 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1131 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1132 /* Manually set NEWAVMODE */
1133 adv7180_write(state,
1134 ADV7180_REG_VSYNC_FIELD_CTL_1,
1135 ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1136 /* Manually set V bit end position in NTSC mode */
1137 adv7180_write(state,
1138 ADV7180_REG_NTSC_V_BIT_END,
1139 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1140 } else {
1141 adv7180_write(state,
1142 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1143 0x17);
1144 }
1145 } else {
1146 adv7180_write(state,
1147 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1148 0x07);
1149 }
1150 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1151 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1152 }
1153
1154 adv7180_write(state, 0x0013, 0x00);
1155
1156 return 0;
1157 }
1158
adv7182_set_std(struct adv7180_state * state,unsigned int std)1159 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1160 {
1161 /* Failing to set the reserved bit can result in increased video noise */
1162 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1163 (std << 4) | ADV7182_REG_INPUT_RESERVED);
1164 }
1165
1166 enum adv7182_input_type {
1167 ADV7182_INPUT_TYPE_CVBS,
1168 ADV7182_INPUT_TYPE_DIFF_CVBS,
1169 ADV7182_INPUT_TYPE_SVIDEO,
1170 ADV7182_INPUT_TYPE_YPBPR,
1171 };
1172
adv7182_get_input_type(unsigned int input)1173 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1174 {
1175 switch (input) {
1176 case ADV7182_INPUT_CVBS_AIN1:
1177 case ADV7182_INPUT_CVBS_AIN2:
1178 case ADV7182_INPUT_CVBS_AIN3:
1179 case ADV7182_INPUT_CVBS_AIN4:
1180 case ADV7182_INPUT_CVBS_AIN5:
1181 case ADV7182_INPUT_CVBS_AIN6:
1182 case ADV7182_INPUT_CVBS_AIN7:
1183 case ADV7182_INPUT_CVBS_AIN8:
1184 return ADV7182_INPUT_TYPE_CVBS;
1185 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1186 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1187 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1188 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1189 return ADV7182_INPUT_TYPE_SVIDEO;
1190 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1191 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1192 return ADV7182_INPUT_TYPE_YPBPR;
1193 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1194 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1195 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1196 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1197 return ADV7182_INPUT_TYPE_DIFF_CVBS;
1198 default: /* Will never happen */
1199 return 0;
1200 }
1201 }
1202
1203 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1204 static unsigned int adv7182_lbias_settings[][3] = {
1205 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1206 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1207 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1208 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1209 };
1210
1211 static unsigned int adv7280_lbias_settings[][3] = {
1212 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1213 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1214 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1215 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1216 };
1217
adv7182_select_input(struct adv7180_state * state,unsigned int input)1218 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1219 {
1220 enum adv7182_input_type input_type;
1221 unsigned int *lbias;
1222 unsigned int i;
1223 int ret;
1224
1225 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1226 if (ret)
1227 return ret;
1228
1229 /* Reset clamp circuitry - ADI recommended writes */
1230 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1231 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1232
1233 input_type = adv7182_get_input_type(input);
1234
1235 switch (input_type) {
1236 case ADV7182_INPUT_TYPE_CVBS:
1237 case ADV7182_INPUT_TYPE_DIFF_CVBS:
1238 /* ADI recommends to use the SH1 filter */
1239 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1240 break;
1241 default:
1242 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1243 break;
1244 }
1245
1246 if (state->chip_info->flags & ADV7180_FLAG_V2)
1247 lbias = adv7280_lbias_settings[input_type];
1248 else
1249 lbias = adv7182_lbias_settings[input_type];
1250
1251 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1252 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1253
1254 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1255 /* ADI required writes to make differential CVBS work */
1256 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1257 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1258 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1259 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1260 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1261 } else {
1262 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1263 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1264 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1265 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1266 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1267 }
1268
1269 return 0;
1270 }
1271
1272 static const struct adv7180_chip_info adv7180_info = {
1273 .flags = ADV7180_FLAG_RESET_POWERED,
1274 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1275 * all inputs and let the card driver take care of validation
1276 */
1277 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1278 BIT(ADV7180_INPUT_CVBS_AIN2) |
1279 BIT(ADV7180_INPUT_CVBS_AIN3) |
1280 BIT(ADV7180_INPUT_CVBS_AIN4) |
1281 BIT(ADV7180_INPUT_CVBS_AIN5) |
1282 BIT(ADV7180_INPUT_CVBS_AIN6) |
1283 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1284 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1285 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1286 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1287 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1288 .init = adv7180_init,
1289 .set_std = adv7180_set_std,
1290 .select_input = adv7180_select_input,
1291 };
1292
1293 static const struct adv7180_chip_info adv7182_info = {
1294 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1295 BIT(ADV7182_INPUT_CVBS_AIN2) |
1296 BIT(ADV7182_INPUT_CVBS_AIN3) |
1297 BIT(ADV7182_INPUT_CVBS_AIN4) |
1298 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1299 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1300 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1301 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1302 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1303 .init = adv7182_init,
1304 .set_std = adv7182_set_std,
1305 .select_input = adv7182_select_input,
1306 };
1307
1308 static const struct adv7180_chip_info adv7280_info = {
1309 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1310 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1311 BIT(ADV7182_INPUT_CVBS_AIN2) |
1312 BIT(ADV7182_INPUT_CVBS_AIN3) |
1313 BIT(ADV7182_INPUT_CVBS_AIN4) |
1314 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1315 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1316 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1317 .init = adv7182_init,
1318 .set_std = adv7182_set_std,
1319 .select_input = adv7182_select_input,
1320 };
1321
1322 static const struct adv7180_chip_info adv7280_m_info = {
1323 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1324 ADV7180_FLAG_TEST_PATTERN,
1325 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1326 BIT(ADV7182_INPUT_CVBS_AIN2) |
1327 BIT(ADV7182_INPUT_CVBS_AIN3) |
1328 BIT(ADV7182_INPUT_CVBS_AIN4) |
1329 BIT(ADV7182_INPUT_CVBS_AIN5) |
1330 BIT(ADV7182_INPUT_CVBS_AIN6) |
1331 BIT(ADV7182_INPUT_CVBS_AIN7) |
1332 BIT(ADV7182_INPUT_CVBS_AIN8) |
1333 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1334 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1335 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1336 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1337 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1338 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1339 .init = adv7182_init,
1340 .set_std = adv7182_set_std,
1341 .select_input = adv7182_select_input,
1342 };
1343
1344 static const struct adv7180_chip_info adv7281_info = {
1345 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1346 ADV7180_FLAG_TEST_PATTERN,
1347 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1348 BIT(ADV7182_INPUT_CVBS_AIN2) |
1349 BIT(ADV7182_INPUT_CVBS_AIN7) |
1350 BIT(ADV7182_INPUT_CVBS_AIN8) |
1351 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1352 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1353 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1354 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1355 .init = adv7182_init,
1356 .set_std = adv7182_set_std,
1357 .select_input = adv7182_select_input,
1358 };
1359
1360 static const struct adv7180_chip_info adv7281_m_info = {
1361 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1362 ADV7180_FLAG_TEST_PATTERN,
1363 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1364 BIT(ADV7182_INPUT_CVBS_AIN2) |
1365 BIT(ADV7182_INPUT_CVBS_AIN3) |
1366 BIT(ADV7182_INPUT_CVBS_AIN4) |
1367 BIT(ADV7182_INPUT_CVBS_AIN7) |
1368 BIT(ADV7182_INPUT_CVBS_AIN8) |
1369 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1370 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1371 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1372 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1373 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1374 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1375 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1376 .init = adv7182_init,
1377 .set_std = adv7182_set_std,
1378 .select_input = adv7182_select_input,
1379 };
1380
1381 static const struct adv7180_chip_info adv7281_ma_info = {
1382 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 |
1383 ADV7180_FLAG_TEST_PATTERN,
1384 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1385 BIT(ADV7182_INPUT_CVBS_AIN2) |
1386 BIT(ADV7182_INPUT_CVBS_AIN3) |
1387 BIT(ADV7182_INPUT_CVBS_AIN4) |
1388 BIT(ADV7182_INPUT_CVBS_AIN5) |
1389 BIT(ADV7182_INPUT_CVBS_AIN6) |
1390 BIT(ADV7182_INPUT_CVBS_AIN7) |
1391 BIT(ADV7182_INPUT_CVBS_AIN8) |
1392 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1393 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1394 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1395 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1396 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1397 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1398 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1399 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1400 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1401 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1402 .init = adv7182_init,
1403 .set_std = adv7182_set_std,
1404 .select_input = adv7182_select_input,
1405 };
1406
1407 static const struct adv7180_chip_info adv7282_info = {
1408 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P | ADV7180_FLAG_TEST_PATTERN,
1409 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1410 BIT(ADV7182_INPUT_CVBS_AIN2) |
1411 BIT(ADV7182_INPUT_CVBS_AIN7) |
1412 BIT(ADV7182_INPUT_CVBS_AIN8) |
1413 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1414 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1415 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1416 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1417 .init = adv7182_init,
1418 .set_std = adv7182_set_std,
1419 .select_input = adv7182_select_input,
1420 };
1421
1422 static const struct adv7180_chip_info adv7282_m_info = {
1423 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P |
1424 ADV7180_FLAG_TEST_PATTERN,
1425 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1426 BIT(ADV7182_INPUT_CVBS_AIN2) |
1427 BIT(ADV7182_INPUT_CVBS_AIN3) |
1428 BIT(ADV7182_INPUT_CVBS_AIN4) |
1429 BIT(ADV7182_INPUT_CVBS_AIN7) |
1430 BIT(ADV7182_INPUT_CVBS_AIN8) |
1431 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1432 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1433 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1434 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1435 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1436 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1437 .init = adv7182_init,
1438 .set_std = adv7182_set_std,
1439 .select_input = adv7182_select_input,
1440 };
1441
adv7180_probe(struct i2c_client * client)1442 static int adv7180_probe(struct i2c_client *client)
1443 {
1444 struct device_node *np = client->dev.of_node;
1445 struct adv7180_state *state;
1446 struct v4l2_subdev *sd;
1447 int ret;
1448
1449 /* Check if the adapter supports the needed features */
1450 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1451 return -EIO;
1452
1453 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1454 if (state == NULL)
1455 return -ENOMEM;
1456
1457 state->client = client;
1458 state->field = V4L2_FIELD_ALTERNATE;
1459 state->chip_info = i2c_get_match_data(client);
1460
1461 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1462 GPIOD_OUT_HIGH);
1463 if (IS_ERR(state->pwdn_gpio)) {
1464 ret = PTR_ERR(state->pwdn_gpio);
1465 v4l_err(client, "request for power pin failed: %d\n", ret);
1466 return ret;
1467 }
1468
1469 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1470 GPIOD_OUT_HIGH);
1471 if (IS_ERR(state->rst_gpio)) {
1472 ret = PTR_ERR(state->rst_gpio);
1473 v4l_err(client, "request for reset pin failed: %d\n", ret);
1474 return ret;
1475 }
1476
1477 if (of_property_read_bool(np, "adv,force-bt656-4") ||
1478 of_property_read_bool(np, "adi,force-bt656-4"))
1479 state->force_bt656_4 = true;
1480
1481 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1482 state->csi_client =
1483 i2c_new_ancillary_device(client, "csi",
1484 ADV7180_DEFAULT_CSI_I2C_ADDR);
1485 if (IS_ERR(state->csi_client))
1486 return PTR_ERR(state->csi_client);
1487 }
1488
1489 if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1490 state->vpp_client =
1491 i2c_new_ancillary_device(client, "vpp",
1492 ADV7180_DEFAULT_VPP_I2C_ADDR);
1493 if (IS_ERR(state->vpp_client)) {
1494 ret = PTR_ERR(state->vpp_client);
1495 goto err_unregister_csi_client;
1496 }
1497 }
1498
1499 state->irq = client->irq;
1500 mutex_init(&state->mutex);
1501 state->curr_norm = V4L2_STD_NTSC;
1502
1503 state->input = 0;
1504 sd = &state->sd;
1505 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1506 sd->internal_ops = &adv7180_internal_ops;
1507 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1508
1509 ret = adv7180_init_controls(state);
1510 if (ret)
1511 goto err_unregister_vpp_client;
1512
1513 state->pad.flags = MEDIA_PAD_FL_SOURCE;
1514 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1515 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1516 if (ret)
1517 goto err_free_ctrl;
1518
1519 mutex_lock(&state->mutex);
1520 ret = adv7180_reset_device(state);
1521 mutex_unlock(&state->mutex);
1522 if (ret)
1523 goto err_media_entity_cleanup;
1524
1525 if (state->irq > 0) {
1526 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1527 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1528 KBUILD_MODNAME, state);
1529 if (ret)
1530 goto err_media_entity_cleanup;
1531 }
1532
1533 ret = v4l2_async_register_subdev(sd);
1534 if (ret)
1535 goto err_free_irq;
1536
1537 mutex_lock(&state->mutex);
1538 ret = adv7180_read(state, ADV7180_REG_IDENT);
1539 mutex_unlock(&state->mutex);
1540 if (ret < 0)
1541 goto err_v4l2_async_unregister;
1542
1543 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1544 ret, client->addr, client->adapter->name);
1545
1546 return 0;
1547
1548 err_v4l2_async_unregister:
1549 v4l2_async_unregister_subdev(sd);
1550 err_free_irq:
1551 if (state->irq > 0)
1552 free_irq(client->irq, state);
1553 err_media_entity_cleanup:
1554 media_entity_cleanup(&sd->entity);
1555 err_free_ctrl:
1556 adv7180_exit_controls(state);
1557 err_unregister_vpp_client:
1558 i2c_unregister_device(state->vpp_client);
1559 err_unregister_csi_client:
1560 i2c_unregister_device(state->csi_client);
1561 mutex_destroy(&state->mutex);
1562 return ret;
1563 }
1564
adv7180_remove(struct i2c_client * client)1565 static void adv7180_remove(struct i2c_client *client)
1566 {
1567 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1568 struct adv7180_state *state = to_state(sd);
1569
1570 v4l2_async_unregister_subdev(sd);
1571
1572 if (state->irq > 0)
1573 free_irq(client->irq, state);
1574
1575 media_entity_cleanup(&sd->entity);
1576 adv7180_exit_controls(state);
1577
1578 i2c_unregister_device(state->vpp_client);
1579 i2c_unregister_device(state->csi_client);
1580
1581 adv7180_set_reset_pin(state, true);
1582 adv7180_set_power_pin(state, false);
1583
1584 mutex_destroy(&state->mutex);
1585 }
1586
1587 #ifdef CONFIG_PM_SLEEP
adv7180_suspend(struct device * dev)1588 static int adv7180_suspend(struct device *dev)
1589 {
1590 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1591 struct adv7180_state *state = to_state(sd);
1592
1593 guard(mutex)(&state->mutex);
1594
1595 return adv7180_set_power(state, false);
1596 }
1597
adv7180_resume(struct device * dev)1598 static int adv7180_resume(struct device *dev)
1599 {
1600 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1601 struct adv7180_state *state = to_state(sd);
1602 int ret;
1603
1604 guard(mutex)(&state->mutex);
1605
1606 ret = adv7180_reset_device(state);
1607 if (ret < 0)
1608 return ret;
1609
1610 /* If we were streaming when suspending, start decoder. */
1611 if (state->streaming) {
1612 ret = adv7180_set_power(state, true);
1613 if (ret)
1614 return ret;
1615 }
1616
1617 return 0;
1618 }
1619
1620 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1621 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1622
1623 #else
1624 #define ADV7180_PM_OPS NULL
1625 #endif
1626
1627 static const struct i2c_device_id adv7180_id[] = {
1628 { .name = "adv7180", .driver_data = (kernel_ulong_t)&adv7180_info },
1629 { .name = "adv7180cp", .driver_data = (kernel_ulong_t)&adv7180_info },
1630 { .name = "adv7180st", .driver_data = (kernel_ulong_t)&adv7180_info },
1631 { .name = "adv7182", .driver_data = (kernel_ulong_t)&adv7182_info },
1632 { .name = "adv7280", .driver_data = (kernel_ulong_t)&adv7280_info },
1633 { .name = "adv7280-m", .driver_data = (kernel_ulong_t)&adv7280_m_info },
1634 { .name = "adv7281", .driver_data = (kernel_ulong_t)&adv7281_info },
1635 { .name = "adv7281-m", .driver_data = (kernel_ulong_t)&adv7281_m_info },
1636 { .name = "adv7281-ma", .driver_data = (kernel_ulong_t)&adv7281_ma_info },
1637 { .name = "adv7282", .driver_data = (kernel_ulong_t)&adv7282_info },
1638 { .name = "adv7282-m", .driver_data = (kernel_ulong_t)&adv7282_m_info },
1639 { }
1640 };
1641 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1642
1643 static const struct of_device_id adv7180_of_id[] = {
1644 { .compatible = "adi,adv7180", &adv7180_info },
1645 { .compatible = "adi,adv7180cp", &adv7180_info },
1646 { .compatible = "adi,adv7180st", &adv7180_info },
1647 { .compatible = "adi,adv7182", &adv7182_info },
1648 { .compatible = "adi,adv7280", &adv7280_info },
1649 { .compatible = "adi,adv7280-m", &adv7280_m_info },
1650 { .compatible = "adi,adv7281", &adv7281_info },
1651 { .compatible = "adi,adv7281-m", &adv7281_m_info },
1652 { .compatible = "adi,adv7281-ma", &adv7281_ma_info },
1653 { .compatible = "adi,adv7282", &adv7282_info },
1654 { .compatible = "adi,adv7282-m", &adv7282_m_info },
1655 {}
1656 };
1657 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1658
1659 static struct i2c_driver adv7180_driver = {
1660 .driver = {
1661 .name = KBUILD_MODNAME,
1662 .pm = ADV7180_PM_OPS,
1663 .of_match_table = adv7180_of_id,
1664 },
1665 .probe = adv7180_probe,
1666 .remove = adv7180_remove,
1667 .id_table = adv7180_id,
1668 };
1669
1670 module_i2c_driver(adv7180_driver);
1671
1672 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1673 MODULE_AUTHOR("Mocean Laboratories");
1674 MODULE_LICENSE("GPL v2");
1675