1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <dt-bindings/sound/qcom,q6afe.h> 6 #include <linux/slab.h> 7 #include <linux/kernel.h> 8 #include <linux/uaccess.h> 9 #include <linux/wait.h> 10 #include <linux/jiffies.h> 11 #include <linux/sched.h> 12 #include <linux/module.h> 13 #include <linux/kref.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/spinlock.h> 17 #include <linux/delay.h> 18 #include <linux/soc/qcom/apr.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dai.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include "q6dsp-errno.h" 24 #include "q6core.h" 25 #include "q6afe.h" 26 27 /* AFE CMDs */ 28 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 29 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 30 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 31 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 32 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 33 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 34 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 35 #define AFE_MODULE_TDM 0x0001028A 36 37 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 38 #define AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS 0x000102A5 39 #define AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT 0x000102AA 40 41 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 42 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 43 44 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 45 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 46 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 47 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 48 #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 49 #define AFE_PARAM_ID_USB_AUDIO_CONFIG 0x000102A4 50 #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 51 #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 52 #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 53 54 /* I2S config specific */ 55 #define AFE_API_VERSION_I2S_CONFIG 0x1 56 #define AFE_PORT_I2S_SD0 0x1 57 #define AFE_PORT_I2S_SD1 0x2 58 #define AFE_PORT_I2S_SD2 0x3 59 #define AFE_PORT_I2S_SD3 0x4 60 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 61 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 62 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 63 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 64 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 65 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 66 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 67 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 68 #define AFE_PORT_I2S_QUAD01 0x5 69 #define AFE_PORT_I2S_QUAD23 0x6 70 #define AFE_PORT_I2S_6CHS 0x7 71 #define AFE_PORT_I2S_8CHS 0x8 72 #define AFE_PORT_I2S_MONO 0x0 73 #define AFE_PORT_I2S_STEREO 0x1 74 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 75 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 76 #define AFE_LINEAR_PCM_DATA 0x0 77 78 #define AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 0x1 79 80 /* Port IDs */ 81 #define AFE_API_VERSION_HDMI_CONFIG 0x1 82 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 83 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 84 85 /* USB AFE port */ 86 #define AFE_PORT_ID_USB_RX 0x7000 87 88 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 89 /* Clock set API version */ 90 #define AFE_API_VERSION_CLOCK_SET 1 91 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 92 #define AFE_MODULE_CLOCK_SET 0x0001028F 93 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 94 95 /* SLIMbus Rx port on channel 0. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 97 /* SLIMbus Tx port on channel 0. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 99 /* SLIMbus Rx port on channel 1. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 101 /* SLIMbus Tx port on channel 1. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 103 /* SLIMbus Rx port on channel 2. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 105 /* SLIMbus Tx port on channel 2. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 107 /* SLIMbus Rx port on channel 3. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 109 /* SLIMbus Tx port on channel 3. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 111 /* SLIMbus Rx port on channel 4. */ 112 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 113 /* SLIMbus Tx port on channel 4. */ 114 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 115 /* SLIMbus Rx port on channel 5. */ 116 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 117 /* SLIMbus Tx port on channel 5. */ 118 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 119 /* SLIMbus Rx port on channel 6. */ 120 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 121 /* SLIMbus Tx port on channel 6. */ 122 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 123 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 124 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 125 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 126 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 127 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 128 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 129 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 130 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 131 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 132 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 133 #define AFE_PORT_ID_SENARY_MI2S_RX 0x1018 134 #define AFE_PORT_ID_SENARY_MI2S_TX 0x1019 135 #define AFE_PORT_ID_INT0_MI2S_RX 0x102e 136 #define AFE_PORT_ID_INT0_MI2S_TX 0x102f 137 #define AFE_PORT_ID_INT1_MI2S_RX 0x1030 138 #define AFE_PORT_ID_INT1_MI2S_TX 0x1031 139 #define AFE_PORT_ID_INT2_MI2S_RX 0x1032 140 #define AFE_PORT_ID_INT2_MI2S_TX 0x1033 141 #define AFE_PORT_ID_INT3_MI2S_RX 0x1034 142 #define AFE_PORT_ID_INT3_MI2S_TX 0x1035 143 #define AFE_PORT_ID_INT4_MI2S_RX 0x1036 144 #define AFE_PORT_ID_INT4_MI2S_TX 0x1037 145 #define AFE_PORT_ID_INT5_MI2S_RX 0x1038 146 #define AFE_PORT_ID_INT5_MI2S_TX 0x1039 147 #define AFE_PORT_ID_INT6_MI2S_RX 0x103a 148 #define AFE_PORT_ID_INT6_MI2S_TX 0x103b 149 150 /* Start of the range of port IDs for TDM devices. */ 151 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 152 153 /* End of the range of port IDs for TDM devices. */ 154 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 155 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 156 157 /* Size of the range of port IDs for TDM ports. */ 158 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 159 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 160 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 161 162 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 163 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 164 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 165 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 166 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 167 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 168 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 169 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 170 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 171 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 172 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 173 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 174 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 175 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 176 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 177 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 178 179 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 180 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 181 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 182 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 183 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 184 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 185 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 186 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 187 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 188 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 189 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 190 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 191 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 192 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 193 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 194 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 195 196 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 197 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 198 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 199 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 200 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 201 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 202 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 203 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 204 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 205 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 206 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 207 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 208 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 209 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 210 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 211 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 212 213 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 214 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 215 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 216 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 217 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 218 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 219 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 220 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 221 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 222 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 223 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 224 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 225 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 226 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 227 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 228 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 229 230 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 231 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 232 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 233 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 234 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 235 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 236 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 237 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 238 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 239 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 240 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 241 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 242 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 243 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 244 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 245 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 246 247 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 248 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 249 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 250 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 251 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 252 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 253 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 254 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 255 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 256 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 257 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 258 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 259 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 260 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 261 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 262 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 263 264 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 265 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 266 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 267 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 268 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 269 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 270 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 271 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 272 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 273 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 274 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 275 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 276 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 277 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 278 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 279 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 280 281 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 282 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 283 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 284 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 285 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 286 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 287 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 288 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 289 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 290 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 291 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 292 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 293 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 294 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 295 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 296 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 297 298 #define AFE_PORT_ID_QUINARY_TDM_RX \ 299 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 300 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 301 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 302 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 303 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 304 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 305 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 306 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 307 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 308 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 309 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 310 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 311 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 312 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 313 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 314 315 #define AFE_PORT_ID_QUINARY_TDM_TX \ 316 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 317 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 318 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 319 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 320 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 321 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 322 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 323 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 324 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 325 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 326 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 327 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 328 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 329 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 330 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 331 332 /* AFE WSA Codec DMA Rx port 0 */ 333 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 334 /* AFE WSA Codec DMA Tx port 0 */ 335 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 336 /* AFE WSA Codec DMA Rx port 1 */ 337 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 338 /* AFE WSA Codec DMA Tx port 1 */ 339 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 340 /* AFE WSA Codec DMA Tx port 2 */ 341 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 342 /* AFE VA Codec DMA Tx port 0 */ 343 #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 344 /* AFE VA Codec DMA Tx port 1 */ 345 #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 346 /* AFE VA Codec DMA Tx port 2 */ 347 #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 348 /* AFE Rx Codec DMA Rx port 0 */ 349 #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 350 /* AFE Tx Codec DMA Tx port 0 */ 351 #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 352 /* AFE Rx Codec DMA Rx port 1 */ 353 #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 354 /* AFE Tx Codec DMA Tx port 1 */ 355 #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 356 /* AFE Rx Codec DMA Rx port 2 */ 357 #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 358 /* AFE Tx Codec DMA Tx port 2 */ 359 #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 360 /* AFE Rx Codec DMA Rx port 3 */ 361 #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 362 /* AFE Tx Codec DMA Tx port 3 */ 363 #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 364 /* AFE Rx Codec DMA Rx port 4 */ 365 #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 366 /* AFE Tx Codec DMA Tx port 4 */ 367 #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 368 /* AFE Rx Codec DMA Rx port 5 */ 369 #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A 370 /* AFE Tx Codec DMA Tx port 5 */ 371 #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B 372 /* AFE Rx Codec DMA Rx port 6 */ 373 #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C 374 /* AFE Rx Codec DMA Rx port 7 */ 375 #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E 376 377 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 378 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 379 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 380 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 381 #define AFE_API_VERSION_TDM_CONFIG 1 382 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 383 #define AFE_API_VERSION_CODEC_DMA_CONFIG 1 384 385 #define TIMEOUT_MS 3000 386 #define AFE_CMD_RESP_AVAIL 0 387 #define AFE_CMD_RESP_NONE 1 388 #define AFE_CLK_TOKEN 1024 389 390 struct q6afe { 391 struct apr_device *apr; 392 struct device *dev; 393 struct q6core_svc_api_info ainfo; 394 struct mutex lock; 395 struct aprv2_ibasic_rsp_result_t result; 396 wait_queue_head_t wait; 397 struct list_head port_list; 398 spinlock_t port_list_lock; 399 }; 400 401 struct afe_port_cmd_device_start { 402 u16 port_id; 403 u16 reserved; 404 } __packed; 405 406 struct afe_port_cmd_device_stop { 407 u16 port_id; 408 u16 reserved; 409 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 410 } __packed; 411 412 struct afe_port_param_data_v2 { 413 u32 module_id; 414 u32 param_id; 415 u16 param_size; 416 u16 reserved; 417 } __packed; 418 419 struct afe_svc_cmd_set_param { 420 uint32_t payload_size; 421 uint32_t payload_address_lsw; 422 uint32_t payload_address_msw; 423 uint32_t mem_map_handle; 424 } __packed; 425 426 struct afe_port_cmd_set_param_v2 { 427 u16 port_id; 428 u16 payload_size; 429 u32 payload_address_lsw; 430 u32 payload_address_msw; 431 u32 mem_map_handle; 432 } __packed; 433 434 struct afe_param_id_hdmi_multi_chan_audio_cfg { 435 u32 hdmi_cfg_minor_version; 436 u16 datatype; 437 u16 channel_allocation; 438 u32 sample_rate; 439 u16 bit_width; 440 u16 reserved; 441 } __packed; 442 443 struct afe_param_id_slimbus_cfg { 444 u32 sb_cfg_minor_version; 445 /* Minor version used for tracking the version of the SLIMBUS 446 * configuration interface. 447 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 448 */ 449 450 u16 slimbus_dev_id; 451 /* SLIMbus hardware device ID, which is required to handle 452 * multiple SLIMbus hardware blocks. 453 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 454 */ 455 u16 bit_width; 456 /* Bit width of the sample. 457 * Supported values: 16, 24 458 */ 459 u16 data_format; 460 /* Data format supported by the SLIMbus hardware. The default is 461 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 462 * hardware does not perform any format conversions before the data 463 * transfer. 464 */ 465 u16 num_channels; 466 /* Number of channels. 467 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 468 */ 469 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 470 /* Mapping of shared channel IDs (128 to 255) to which the 471 * master port is to be connected. 472 * Shared_channel_mapping[i] represents the shared channel assigned 473 * for audio channel i in multichannel audio data. 474 */ 475 u32 sample_rate; 476 /* Sampling rate of the port. 477 * Supported values: 478 * - #AFE_PORT_SAMPLE_RATE_8K 479 * - #AFE_PORT_SAMPLE_RATE_16K 480 * - #AFE_PORT_SAMPLE_RATE_48K 481 * - #AFE_PORT_SAMPLE_RATE_96K 482 * - #AFE_PORT_SAMPLE_RATE_192K 483 */ 484 } __packed; 485 486 struct afe_clk_cfg { 487 u32 i2s_cfg_minor_version; 488 u32 clk_val1; 489 u32 clk_val2; 490 u16 clk_src; 491 u16 clk_root; 492 u16 clk_set_mode; 493 u16 reserved; 494 } __packed; 495 496 struct afe_digital_clk_cfg { 497 u32 i2s_cfg_minor_version; 498 u32 clk_val; 499 u16 clk_root; 500 u16 reserved; 501 } __packed; 502 503 struct afe_param_id_i2s_cfg { 504 u32 i2s_cfg_minor_version; 505 u16 bit_width; 506 u16 channel_mode; 507 u16 mono_stereo; 508 u16 ws_src; 509 u32 sample_rate; 510 u16 data_format; 511 u16 reserved; 512 } __packed; 513 514 struct afe_param_id_tdm_cfg { 515 u32 tdm_cfg_minor_version; 516 u32 num_channels; 517 u32 sample_rate; 518 u32 bit_width; 519 u16 data_format; 520 u16 sync_mode; 521 u16 sync_src; 522 u16 nslots_per_frame; 523 u16 ctrl_data_out_enable; 524 u16 ctrl_invert_sync_pulse; 525 u16 ctrl_sync_data_delay; 526 u16 slot_width; 527 u32 slot_mask; 528 } __packed; 529 530 struct afe_param_id_cdc_dma_cfg { 531 u32 cdc_dma_cfg_minor_version; 532 u32 sample_rate; 533 u16 bit_width; 534 u16 data_format; 535 u16 num_channels; 536 u16 active_channels_mask; 537 } __packed; 538 539 struct afe_param_id_usb_cfg { 540 /* Minor version used for tracking USB audio device configuration. 541 * Supported values: AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 542 */ 543 u32 cfg_minor_version; 544 /* Sampling rate of the port. 545 * Supported values: 546 * - AFE_PORT_SAMPLE_RATE_8K 547 * - AFE_PORT_SAMPLE_RATE_11025 548 * - AFE_PORT_SAMPLE_RATE_12K 549 * - AFE_PORT_SAMPLE_RATE_16K 550 * - AFE_PORT_SAMPLE_RATE_22050 551 * - AFE_PORT_SAMPLE_RATE_24K 552 * - AFE_PORT_SAMPLE_RATE_32K 553 * - AFE_PORT_SAMPLE_RATE_44P1K 554 * - AFE_PORT_SAMPLE_RATE_48K 555 * - AFE_PORT_SAMPLE_RATE_96K 556 * - AFE_PORT_SAMPLE_RATE_192K 557 */ 558 u32 sample_rate; 559 /* Bit width of the sample. 560 * Supported values: 16, 24 561 */ 562 u16 bit_width; 563 /* Number of channels. 564 * Supported values: 1 and 2 565 */ 566 u16 num_channels; 567 /* Data format supported by the USB. The supported value is 568 * 0 (#AFE_USB_AUDIO_DATA_FORMAT_LINEAR_PCM). 569 */ 570 u16 data_format; 571 /* this field must be 0 */ 572 u16 reserved; 573 /* device token of actual end USB audio device */ 574 u32 dev_token; 575 /* endianness of this interface */ 576 u32 endian; 577 /* service interval */ 578 u32 service_interval; 579 } __packed; 580 581 /** 582 * struct afe_param_id_usb_audio_dev_params 583 * @cfg_minor_version: Minor version used for tracking USB audio device 584 * configuration. 585 * Supported values: 586 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 587 * @dev_token: device token of actual end USB audio device 588 **/ 589 struct afe_param_id_usb_audio_dev_params { 590 u32 cfg_minor_version; 591 u32 dev_token; 592 } __packed; 593 594 /** 595 * struct afe_param_id_usb_audio_dev_lpcm_fmt 596 * @cfg_minor_version: Minor version used for tracking USB audio device 597 * configuration. 598 * Supported values: 599 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 600 * @endian: endianness of this interface 601 **/ 602 struct afe_param_id_usb_audio_dev_lpcm_fmt { 603 u32 cfg_minor_version; 604 u32 endian; 605 } __packed; 606 607 #define AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL 0x000102B7 608 609 /** 610 * struct afe_param_id_usb_audio_svc_interval 611 * @cfg_minor_version: Minor version used for tracking USB audio device 612 * configuration. 613 * Supported values: 614 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 615 * @svc_interval: service interval 616 **/ 617 struct afe_param_id_usb_audio_svc_interval { 618 u32 cfg_minor_version; 619 u32 svc_interval; 620 } __packed; 621 622 union afe_port_config { 623 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 624 struct afe_param_id_slimbus_cfg slim_cfg; 625 struct afe_param_id_i2s_cfg i2s_cfg; 626 struct afe_param_id_tdm_cfg tdm_cfg; 627 struct afe_param_id_cdc_dma_cfg dma_cfg; 628 struct afe_param_id_usb_cfg usb_cfg; 629 } __packed; 630 631 632 struct afe_clk_set { 633 uint32_t clk_set_minor_version; 634 uint32_t clk_id; 635 uint32_t clk_freq_in_hz; 636 uint16_t clk_attri; 637 uint16_t clk_root; 638 uint32_t enable; 639 }; 640 641 struct afe_param_id_slot_mapping_cfg { 642 u32 minor_version; 643 u16 num_channels; 644 u16 bitwidth; 645 u32 data_align_type; 646 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 647 } __packed; 648 649 struct q6afe_port { 650 wait_queue_head_t wait; 651 union afe_port_config port_cfg; 652 struct afe_param_id_slot_mapping_cfg *scfg; 653 struct aprv2_ibasic_rsp_result_t result; 654 int token; 655 int id; 656 int cfg_type; 657 struct q6afe *afe; 658 struct kref refcount; 659 struct list_head node; 660 }; 661 662 struct afe_cmd_remote_lpass_core_hw_vote_request { 663 uint32_t hw_block_id; 664 char client_name[8]; 665 } __packed; 666 667 struct afe_cmd_remote_lpass_core_hw_devote_request { 668 uint32_t hw_block_id; 669 uint32_t client_handle; 670 } __packed; 671 672 673 674 struct afe_port_map { 675 int port_id; 676 int token; 677 int is_rx; 678 int is_dig_pcm; 679 }; 680 681 /* 682 * Mapping between Virtual Port IDs to DSP AFE Port ID 683 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 684 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 685 */ 686 687 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 688 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 689 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 690 SLIMBUS_0_RX, 1, 1}, 691 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 692 SLIMBUS_1_RX, 1, 1}, 693 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 694 SLIMBUS_2_RX, 1, 1}, 695 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 696 SLIMBUS_3_RX, 1, 1}, 697 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 698 SLIMBUS_4_RX, 1, 1}, 699 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 700 SLIMBUS_5_RX, 1, 1}, 701 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 702 SLIMBUS_6_RX, 1, 1}, 703 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 704 SLIMBUS_0_TX, 0, 1}, 705 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 706 SLIMBUS_1_TX, 0, 1}, 707 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 708 SLIMBUS_2_TX, 0, 1}, 709 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 710 SLIMBUS_3_TX, 0, 1}, 711 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 712 SLIMBUS_4_TX, 0, 1}, 713 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 714 SLIMBUS_5_TX, 0, 1}, 715 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 716 SLIMBUS_6_TX, 0, 1}, 717 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 718 PRIMARY_MI2S_RX, 1, 1}, 719 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 720 PRIMARY_MI2S_RX, 0, 1}, 721 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 722 SECONDARY_MI2S_RX, 1, 1}, 723 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 724 SECONDARY_MI2S_TX, 0, 1}, 725 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 726 TERTIARY_MI2S_RX, 1, 1}, 727 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 728 TERTIARY_MI2S_TX, 0, 1}, 729 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 730 QUATERNARY_MI2S_RX, 1, 1}, 731 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 732 QUATERNARY_MI2S_TX, 0, 1}, 733 [QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, 734 QUINARY_MI2S_RX, 1, 1}, 735 [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, 736 QUINARY_MI2S_TX, 0, 1}, 737 [SENARY_MI2S_RX] = { AFE_PORT_ID_SENARY_MI2S_RX, 738 SENARY_MI2S_RX, 1, 1}, 739 [SENARY_MI2S_TX] = { AFE_PORT_ID_SENARY_MI2S_TX, 740 SENARY_MI2S_TX, 0, 1}, 741 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 742 PRIMARY_TDM_RX_0, 1, 1}, 743 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 744 PRIMARY_TDM_TX_0, 0, 1}, 745 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 746 PRIMARY_TDM_RX_1, 1, 1}, 747 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 748 PRIMARY_TDM_TX_1, 0, 1}, 749 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 750 PRIMARY_TDM_RX_2, 1, 1}, 751 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 752 PRIMARY_TDM_TX_2, 0, 1}, 753 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 754 PRIMARY_TDM_RX_3, 1, 1}, 755 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 756 PRIMARY_TDM_TX_3, 0, 1}, 757 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 758 PRIMARY_TDM_RX_4, 1, 1}, 759 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 760 PRIMARY_TDM_TX_4, 0, 1}, 761 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 762 PRIMARY_TDM_RX_5, 1, 1}, 763 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 764 PRIMARY_TDM_TX_5, 0, 1}, 765 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 766 PRIMARY_TDM_RX_6, 1, 1}, 767 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 768 PRIMARY_TDM_TX_6, 0, 1}, 769 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 770 PRIMARY_TDM_RX_7, 1, 1}, 771 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 772 PRIMARY_TDM_TX_7, 0, 1}, 773 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 774 SECONDARY_TDM_RX_0, 1, 1}, 775 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 776 SECONDARY_TDM_TX_0, 0, 1}, 777 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 778 SECONDARY_TDM_RX_1, 1, 1}, 779 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 780 SECONDARY_TDM_TX_1, 0, 1}, 781 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 782 SECONDARY_TDM_RX_2, 1, 1}, 783 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 784 SECONDARY_TDM_TX_2, 0, 1}, 785 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 786 SECONDARY_TDM_RX_3, 1, 1}, 787 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 788 SECONDARY_TDM_TX_3, 0, 1}, 789 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 790 SECONDARY_TDM_RX_4, 1, 1}, 791 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 792 SECONDARY_TDM_TX_4, 0, 1}, 793 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 794 SECONDARY_TDM_RX_5, 1, 1}, 795 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 796 SECONDARY_TDM_TX_5, 0, 1}, 797 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 798 SECONDARY_TDM_RX_6, 1, 1}, 799 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 800 SECONDARY_TDM_TX_6, 0, 1}, 801 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 802 SECONDARY_TDM_RX_7, 1, 1}, 803 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 804 SECONDARY_TDM_TX_7, 0, 1}, 805 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 806 TERTIARY_TDM_RX_0, 1, 1}, 807 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 808 TERTIARY_TDM_TX_0, 0, 1}, 809 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 810 TERTIARY_TDM_RX_1, 1, 1}, 811 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 812 TERTIARY_TDM_TX_1, 0, 1}, 813 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 814 TERTIARY_TDM_RX_2, 1, 1}, 815 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 816 TERTIARY_TDM_TX_2, 0, 1}, 817 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 818 TERTIARY_TDM_RX_3, 1, 1}, 819 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 820 TERTIARY_TDM_TX_3, 0, 1}, 821 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 822 TERTIARY_TDM_RX_4, 1, 1}, 823 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 824 TERTIARY_TDM_TX_4, 0, 1}, 825 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 826 TERTIARY_TDM_RX_5, 1, 1}, 827 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 828 TERTIARY_TDM_TX_5, 0, 1}, 829 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 830 TERTIARY_TDM_RX_6, 1, 1}, 831 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 832 TERTIARY_TDM_TX_6, 0, 1}, 833 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 834 TERTIARY_TDM_RX_7, 1, 1}, 835 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 836 TERTIARY_TDM_TX_7, 0, 1}, 837 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 838 QUATERNARY_TDM_RX_0, 1, 1}, 839 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 840 QUATERNARY_TDM_TX_0, 0, 1}, 841 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 842 QUATERNARY_TDM_RX_1, 1, 1}, 843 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 844 QUATERNARY_TDM_TX_1, 0, 1}, 845 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 846 QUATERNARY_TDM_RX_2, 1, 1}, 847 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 848 QUATERNARY_TDM_TX_2, 0, 1}, 849 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 850 QUATERNARY_TDM_RX_3, 1, 1}, 851 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 852 QUATERNARY_TDM_TX_3, 0, 1}, 853 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 854 QUATERNARY_TDM_RX_4, 1, 1}, 855 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 856 QUATERNARY_TDM_TX_4, 0, 1}, 857 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 858 QUATERNARY_TDM_RX_5, 1, 1}, 859 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 860 QUATERNARY_TDM_TX_5, 0, 1}, 861 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 862 QUATERNARY_TDM_RX_6, 1, 1}, 863 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 864 QUATERNARY_TDM_TX_6, 0, 1}, 865 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 866 QUATERNARY_TDM_RX_7, 1, 1}, 867 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 868 QUATERNARY_TDM_TX_7, 0, 1}, 869 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 870 QUINARY_TDM_RX_0, 1, 1}, 871 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 872 QUINARY_TDM_TX_0, 0, 1}, 873 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 874 QUINARY_TDM_RX_1, 1, 1}, 875 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 876 QUINARY_TDM_TX_1, 0, 1}, 877 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 878 QUINARY_TDM_RX_2, 1, 1}, 879 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 880 QUINARY_TDM_TX_2, 0, 1}, 881 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 882 QUINARY_TDM_RX_3, 1, 1}, 883 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 884 QUINARY_TDM_TX_3, 0, 1}, 885 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 886 QUINARY_TDM_RX_4, 1, 1}, 887 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 888 QUINARY_TDM_TX_4, 0, 1}, 889 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 890 QUINARY_TDM_RX_5, 1, 1}, 891 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 892 QUINARY_TDM_TX_5, 0, 1}, 893 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 894 QUINARY_TDM_RX_6, 1, 1}, 895 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 896 QUINARY_TDM_TX_6, 0, 1}, 897 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 898 QUINARY_TDM_RX_7, 1, 1}, 899 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 900 QUINARY_TDM_TX_7, 0, 1}, 901 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 902 DISPLAY_PORT_RX, 1, 1}, 903 [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, 904 WSA_CODEC_DMA_RX_0, 1, 1}, 905 [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, 906 WSA_CODEC_DMA_TX_0, 0, 1}, 907 [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, 908 WSA_CODEC_DMA_RX_1, 1, 1}, 909 [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, 910 WSA_CODEC_DMA_TX_1, 0, 1}, 911 [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, 912 WSA_CODEC_DMA_TX_2, 0, 1}, 913 [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, 914 VA_CODEC_DMA_TX_0, 0, 1}, 915 [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, 916 VA_CODEC_DMA_TX_1, 0, 1}, 917 [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, 918 VA_CODEC_DMA_TX_2, 0, 1}, 919 [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, 920 RX_CODEC_DMA_RX_0, 1, 1}, 921 [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, 922 TX_CODEC_DMA_TX_0, 0, 1}, 923 [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, 924 RX_CODEC_DMA_RX_1, 1, 1}, 925 [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, 926 TX_CODEC_DMA_TX_1, 0, 1}, 927 [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, 928 RX_CODEC_DMA_RX_2, 1, 1}, 929 [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, 930 TX_CODEC_DMA_TX_2, 0, 1}, 931 [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, 932 RX_CODEC_DMA_RX_3, 1, 1}, 933 [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, 934 TX_CODEC_DMA_TX_3, 0, 1}, 935 [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, 936 RX_CODEC_DMA_RX_4, 1, 1}, 937 [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, 938 TX_CODEC_DMA_TX_4, 0, 1}, 939 [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, 940 RX_CODEC_DMA_RX_5, 1, 1}, 941 [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, 942 TX_CODEC_DMA_TX_5, 0, 1}, 943 [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, 944 RX_CODEC_DMA_RX_6, 1, 1}, 945 [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, 946 RX_CODEC_DMA_RX_7, 1, 1}, 947 [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, 948 [LPI_MI2S_RX_0] = { AFE_PORT_ID_INT0_MI2S_RX, 949 LPI_MI2S_RX_0, 1, 1}, 950 [LPI_MI2S_TX_0] = { AFE_PORT_ID_INT0_MI2S_TX, 951 LPI_MI2S_TX_0, 0, 1}, 952 [LPI_MI2S_RX_1] = { AFE_PORT_ID_INT1_MI2S_RX, 953 LPI_MI2S_RX_1, 1, 1}, 954 [LPI_MI2S_TX_1] = { AFE_PORT_ID_INT1_MI2S_TX, 955 LPI_MI2S_TX_1, 0, 1}, 956 [LPI_MI2S_RX_2] = { AFE_PORT_ID_INT2_MI2S_RX, 957 LPI_MI2S_RX_2, 1, 1}, 958 [LPI_MI2S_TX_2] = { AFE_PORT_ID_INT2_MI2S_TX, 959 LPI_MI2S_TX_2, 0, 1}, 960 [LPI_MI2S_RX_3] = { AFE_PORT_ID_INT3_MI2S_RX, 961 LPI_MI2S_RX_3, 1, 1}, 962 [LPI_MI2S_TX_3] = { AFE_PORT_ID_INT3_MI2S_TX, 963 LPI_MI2S_TX_3, 0, 1}, 964 [LPI_MI2S_RX_4] = { AFE_PORT_ID_INT4_MI2S_RX, 965 LPI_MI2S_RX_4, 1, 1}, 966 [LPI_MI2S_TX_4] = { AFE_PORT_ID_INT4_MI2S_TX, 967 LPI_MI2S_TX_4, 0, 1}, 968 [LPI_MI2S_RX_5] = { AFE_PORT_ID_INT5_MI2S_RX, 969 LPI_MI2S_RX_5, 1, 1}, 970 [LPI_MI2S_TX_5] = { AFE_PORT_ID_INT5_MI2S_TX, 971 LPI_MI2S_TX_5, 0, 1}, 972 [LPI_MI2S_RX_6] = { AFE_PORT_ID_INT6_MI2S_RX, 973 LPI_MI2S_RX_6, 1, 1}, 974 [LPI_MI2S_TX_6] = { AFE_PORT_ID_INT6_MI2S_TX, 975 LPI_MI2S_TX_6, 0, 1}, 976 }; 977 978 static void q6afe_port_free(struct kref *ref) 979 { 980 struct q6afe_port *port; 981 struct q6afe *afe; 982 983 port = container_of(ref, struct q6afe_port, refcount); 984 afe = port->afe; 985 scoped_guard(spinlock_irqsave, &afe->port_list_lock) 986 list_del(&port->node); 987 kfree(port->scfg); 988 kfree(port); 989 } 990 991 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 992 { 993 struct q6afe_port *p; 994 struct q6afe_port *ret = NULL; 995 996 guard(spinlock_irqsave)(&afe->port_list_lock); 997 list_for_each_entry(p, &afe->port_list, node) 998 if (p->token == token) { 999 ret = p; 1000 kref_get(&p->refcount); 1001 break; 1002 } 1003 1004 return ret; 1005 } 1006 1007 static int q6afe_callback(struct apr_device *adev, const struct apr_resp_pkt *data) 1008 { 1009 struct q6afe *afe = dev_get_drvdata(&adev->dev); 1010 const struct aprv2_ibasic_rsp_result_t *res; 1011 const struct apr_hdr *hdr = &data->hdr; 1012 struct q6afe_port *port; 1013 1014 if (!data->payload_size) 1015 return 0; 1016 1017 res = data->payload; 1018 switch (hdr->opcode) { 1019 case APR_BASIC_RSP_RESULT: { 1020 if (res->status) { 1021 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 1022 res->opcode, res->status); 1023 } 1024 switch (res->opcode) { 1025 case AFE_PORT_CMD_SET_PARAM_V2: 1026 case AFE_PORT_CMD_DEVICE_STOP: 1027 case AFE_PORT_CMD_DEVICE_START: 1028 case AFE_SVC_CMD_SET_PARAM: 1029 port = q6afe_find_port(afe, hdr->token); 1030 if (port) { 1031 port->result = *res; 1032 wake_up(&port->wait); 1033 kref_put(&port->refcount, q6afe_port_free); 1034 } else if (hdr->token == AFE_CLK_TOKEN) { 1035 afe->result = *res; 1036 wake_up(&afe->wait); 1037 } 1038 break; 1039 default: 1040 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 1041 break; 1042 } 1043 } 1044 break; 1045 case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: 1046 afe->result.opcode = hdr->opcode; 1047 afe->result.status = res->status; 1048 wake_up(&afe->wait); 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 return 0; 1055 } 1056 1057 /** 1058 * q6afe_get_port_id() - Get port id from a given port index 1059 * 1060 * @index: port index 1061 * 1062 * Return: Will be an negative on error or valid port_id on success 1063 */ 1064 int q6afe_get_port_id(int index) 1065 { 1066 if (index < 0 || index >= AFE_PORT_MAX) 1067 return -EINVAL; 1068 1069 return port_maps[index].port_id; 1070 } 1071 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 1072 1073 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 1074 struct q6afe_port *port, uint32_t rsp_opcode) 1075 { 1076 wait_queue_head_t *wait; 1077 struct aprv2_ibasic_rsp_result_t *result; 1078 int ret; 1079 1080 mutex_lock(&afe->lock); 1081 if (port) { 1082 wait = &port->wait; 1083 result = &port->result; 1084 } else { 1085 result = &afe->result; 1086 wait = &afe->wait; 1087 } 1088 1089 result->opcode = 0; 1090 result->status = 0; 1091 1092 ret = apr_send_pkt(afe->apr, pkt); 1093 if (ret < 0) { 1094 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 1095 ret = -EINVAL; 1096 goto err; 1097 } 1098 1099 ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), 1100 msecs_to_jiffies(TIMEOUT_MS)); 1101 if (!ret) { 1102 ret = -ETIMEDOUT; 1103 } else if (result->status > 0) { 1104 dev_err(afe->dev, "DSP returned error[%x]\n", 1105 result->status); 1106 ret = -EINVAL; 1107 } else { 1108 ret = 0; 1109 } 1110 1111 err: 1112 mutex_unlock(&afe->lock); 1113 1114 return ret; 1115 } 1116 1117 static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, 1118 void *data, int param_id, int module_id, int psize, 1119 int token) 1120 { 1121 struct afe_svc_cmd_set_param *param; 1122 struct afe_port_param_data_v2 *pdata; 1123 struct apr_pkt *pkt; 1124 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1125 void *pl; 1126 1127 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1128 if (!p) 1129 return -ENOMEM; 1130 1131 pkt = p; 1132 param = p + APR_HDR_SIZE; 1133 pdata = p + APR_HDR_SIZE + sizeof(*param); 1134 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1135 memcpy(pl, data, psize); 1136 1137 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1138 APR_HDR_LEN(APR_HDR_SIZE), 1139 APR_PKT_VER); 1140 pkt->hdr.pkt_size = pkt_size; 1141 pkt->hdr.src_port = 0; 1142 pkt->hdr.dest_port = 0; 1143 pkt->hdr.token = token; 1144 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 1145 1146 param->payload_size = sizeof(*pdata) + psize; 1147 param->payload_address_lsw = 0x00; 1148 param->payload_address_msw = 0x00; 1149 param->mem_map_handle = 0x00; 1150 pdata->module_id = module_id; 1151 pdata->param_id = param_id; 1152 pdata->param_size = psize; 1153 1154 ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); 1155 if (ret) 1156 dev_err(afe->dev, "AFE set params failed %d\n", ret); 1157 1158 return ret; 1159 } 1160 1161 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 1162 int param_id, int module_id, int psize) 1163 { 1164 return q6afe_set_param(port->afe, port, data, param_id, module_id, 1165 psize, port->token); 1166 } 1167 1168 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 1169 int param_id, int module_id, int psize) 1170 { 1171 struct afe_port_cmd_set_param_v2 *param; 1172 struct afe_port_param_data_v2 *pdata; 1173 struct q6afe *afe = port->afe; 1174 struct apr_pkt *pkt; 1175 u16 port_id = port->id; 1176 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1177 void *pl; 1178 1179 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1180 if (!p) 1181 return -ENOMEM; 1182 1183 pkt = p; 1184 param = p + APR_HDR_SIZE; 1185 pdata = p + APR_HDR_SIZE + sizeof(*param); 1186 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1187 memcpy(pl, data, psize); 1188 1189 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1190 APR_HDR_LEN(APR_HDR_SIZE), 1191 APR_PKT_VER); 1192 pkt->hdr.pkt_size = pkt_size; 1193 pkt->hdr.src_port = 0; 1194 pkt->hdr.dest_port = 0; 1195 pkt->hdr.token = port->token; 1196 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 1197 1198 param->port_id = port_id; 1199 param->payload_size = sizeof(*pdata) + psize; 1200 param->payload_address_lsw = 0x00; 1201 param->payload_address_msw = 0x00; 1202 param->mem_map_handle = 0x00; 1203 pdata->module_id = module_id; 1204 pdata->param_id = param_id; 1205 pdata->param_size = psize; 1206 1207 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); 1208 if (ret) 1209 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1210 port_id, ret); 1211 1212 return ret; 1213 } 1214 1215 static int q6afe_port_set_lpass_clock(struct q6afe_port *port, 1216 struct afe_clk_cfg *cfg) 1217 { 1218 return q6afe_port_set_param_v2(port, cfg, 1219 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 1220 AFE_MODULE_AUDIO_DEV_INTERFACE, 1221 sizeof(*cfg)); 1222 } 1223 1224 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 1225 struct afe_clk_set *cfg) 1226 { 1227 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 1228 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 1229 } 1230 1231 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 1232 struct afe_digital_clk_cfg *cfg) 1233 { 1234 return q6afe_port_set_param_v2(port, cfg, 1235 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 1236 AFE_MODULE_AUDIO_DEV_INTERFACE, 1237 sizeof(*cfg)); 1238 } 1239 1240 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 1241 int clk_root, unsigned int freq) 1242 { 1243 struct q6afe *afe = dev_get_drvdata(dev->parent); 1244 struct afe_clk_set cset = {0,}; 1245 1246 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1247 cset.clk_id = clk_id; 1248 cset.clk_freq_in_hz = freq; 1249 cset.clk_attri = attri; 1250 cset.clk_root = clk_root; 1251 cset.enable = !!freq; 1252 1253 return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, 1254 AFE_MODULE_CLOCK_SET, sizeof(cset), 1255 AFE_CLK_TOKEN); 1256 } 1257 EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); 1258 1259 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 1260 int clk_src, int clk_root, 1261 unsigned int freq, int dir) 1262 { 1263 struct afe_clk_cfg ccfg = {0,}; 1264 struct afe_clk_set cset = {0,}; 1265 struct afe_digital_clk_cfg dcfg = {0,}; 1266 int ret; 1267 1268 switch (clk_id) { 1269 case LPAIF_DIG_CLK: 1270 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1271 dcfg.clk_val = freq; 1272 dcfg.clk_root = clk_root; 1273 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 1274 break; 1275 case LPAIF_BIT_CLK: 1276 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1277 ccfg.clk_val1 = freq; 1278 ccfg.clk_src = clk_src; 1279 ccfg.clk_root = clk_root; 1280 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 1281 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1282 break; 1283 1284 case LPAIF_OSR_CLK: 1285 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1286 ccfg.clk_val2 = freq; 1287 ccfg.clk_src = clk_src; 1288 ccfg.clk_root = clk_root; 1289 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1290 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1291 break; 1292 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1293 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1294 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1295 case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: 1296 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1297 cset.clk_id = clk_id; 1298 cset.clk_freq_in_hz = freq; 1299 cset.clk_attri = clk_src; 1300 cset.clk_root = clk_root; 1301 cset.enable = !!freq; 1302 ret = q6afe_set_lpass_clock_v2(port, &cset); 1303 break; 1304 default: 1305 ret = -EINVAL; 1306 break; 1307 } 1308 1309 return ret; 1310 } 1311 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1312 1313 /** 1314 * q6afe_port_stop() - Stop a afe port 1315 * 1316 * @port: Instance of port to stop 1317 * 1318 * Return: Will be an negative on packet size on success. 1319 */ 1320 int q6afe_port_stop(struct q6afe_port *port) 1321 { 1322 struct afe_port_cmd_device_stop *stop; 1323 struct q6afe *afe = port->afe; 1324 struct apr_pkt *pkt; 1325 int port_id = port->id; 1326 int ret = 0; 1327 int index, pkt_size; 1328 1329 index = port->token; 1330 if (index < 0 || index >= AFE_PORT_MAX) { 1331 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1332 return -EINVAL; 1333 } 1334 1335 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1336 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1337 if (!p) 1338 return -ENOMEM; 1339 1340 pkt = p; 1341 stop = p + APR_HDR_SIZE; 1342 1343 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1344 APR_HDR_LEN(APR_HDR_SIZE), 1345 APR_PKT_VER); 1346 pkt->hdr.pkt_size = pkt_size; 1347 pkt->hdr.src_port = 0; 1348 pkt->hdr.dest_port = 0; 1349 pkt->hdr.token = index; 1350 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1351 stop->port_id = port_id; 1352 stop->reserved = 0; 1353 1354 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); 1355 if (ret) 1356 dev_err(afe->dev, "AFE close failed %d\n", ret); 1357 1358 return ret; 1359 } 1360 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1361 1362 /** 1363 * q6afe_slim_port_prepare() - Prepare slim afe port. 1364 * 1365 * @port: Instance of afe port 1366 * @cfg: SLIM configuration for the afe port 1367 * 1368 */ 1369 void q6afe_slim_port_prepare(struct q6afe_port *port, 1370 struct q6afe_slim_cfg *cfg) 1371 { 1372 union afe_port_config *pcfg = &port->port_cfg; 1373 1374 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1375 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1376 pcfg->slim_cfg.bit_width = cfg->bit_width; 1377 pcfg->slim_cfg.num_channels = cfg->num_channels; 1378 pcfg->slim_cfg.data_format = cfg->data_format; 1379 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1380 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1381 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1382 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1383 1384 } 1385 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1386 1387 /** 1388 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1389 * 1390 * @port: Instance of afe port 1391 * @cfg: TDM configuration for the afe port 1392 * 1393 */ 1394 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1395 struct q6afe_tdm_cfg *cfg) 1396 { 1397 union afe_port_config *pcfg = &port->port_cfg; 1398 1399 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1400 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1401 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1402 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1403 pcfg->tdm_cfg.data_format = cfg->data_format; 1404 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1405 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1406 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1407 1408 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1409 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1410 port->scfg = kzalloc_obj(*port->scfg); 1411 if (!port->scfg) 1412 return; 1413 1414 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1415 port->scfg->num_channels = cfg->num_channels; 1416 port->scfg->bitwidth = cfg->bit_width; 1417 port->scfg->data_align_type = cfg->data_align_type; 1418 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1419 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1420 } 1421 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1422 1423 /** 1424 * afe_port_send_usb_dev_param() - Send USB dev token 1425 * 1426 * @port: Instance of afe port 1427 * @cardidx: USB SND card index to reference 1428 * @pcmidx: USB SND PCM device index to reference 1429 * 1430 * The USB dev token carries information about which USB SND card instance and 1431 * PCM device to execute the offload on. This information is carried through 1432 * to the stream enable QMI request, which is handled by the offload class 1433 * driver. The information is parsed to determine which USB device to query 1434 * the required resources for. 1435 */ 1436 int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx) 1437 { 1438 struct afe_param_id_usb_audio_dev_params usb_dev; 1439 int ret; 1440 1441 memset(&usb_dev, 0, sizeof(usb_dev)); 1442 1443 usb_dev.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1444 usb_dev.dev_token = (cardidx << 16) | (pcmidx << 8); 1445 ret = q6afe_port_set_param_v2(port, &usb_dev, 1446 AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS, 1447 AFE_MODULE_AUDIO_DEV_INTERFACE, 1448 sizeof(usb_dev)); 1449 if (ret) 1450 dev_err(port->afe->dev, "%s: AFE device param cmd failed %d\n", 1451 __func__, ret); 1452 1453 return ret; 1454 } 1455 EXPORT_SYMBOL_GPL(afe_port_send_usb_dev_param); 1456 1457 static int afe_port_send_usb_params(struct q6afe_port *port, struct q6afe_usb_cfg *cfg) 1458 { 1459 union afe_port_config *pcfg = &port->port_cfg; 1460 struct afe_param_id_usb_audio_dev_lpcm_fmt lpcm_fmt; 1461 struct afe_param_id_usb_audio_svc_interval svc_int; 1462 int ret; 1463 1464 if (!pcfg) { 1465 dev_err(port->afe->dev, "%s: Error, no configuration data\n", __func__); 1466 return -EINVAL; 1467 } 1468 1469 memset(&lpcm_fmt, 0, sizeof(lpcm_fmt)); 1470 memset(&svc_int, 0, sizeof(svc_int)); 1471 1472 lpcm_fmt.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1473 lpcm_fmt.endian = pcfg->usb_cfg.endian; 1474 ret = q6afe_port_set_param_v2(port, &lpcm_fmt, 1475 AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT, 1476 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(lpcm_fmt)); 1477 if (ret) { 1478 dev_err(port->afe->dev, "%s: AFE device param cmd LPCM_FMT failed %d\n", 1479 __func__, ret); 1480 return ret; 1481 } 1482 1483 svc_int.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1484 svc_int.svc_interval = pcfg->usb_cfg.service_interval; 1485 ret = q6afe_port_set_param_v2(port, &svc_int, 1486 AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL, 1487 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(svc_int)); 1488 if (ret) 1489 dev_err(port->afe->dev, "%s: AFE device param cmd svc_interval failed %d\n", 1490 __func__, ret); 1491 1492 return ret; 1493 } 1494 1495 /** 1496 * q6afe_usb_port_prepare() - Prepare usb afe port. 1497 * 1498 * @port: Instance of afe port 1499 * @cfg: USB configuration for the afe port 1500 * 1501 */ 1502 void q6afe_usb_port_prepare(struct q6afe_port *port, 1503 struct q6afe_usb_cfg *cfg) 1504 { 1505 union afe_port_config *pcfg = &port->port_cfg; 1506 1507 pcfg->usb_cfg.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1508 pcfg->usb_cfg.sample_rate = cfg->sample_rate; 1509 pcfg->usb_cfg.num_channels = cfg->num_channels; 1510 pcfg->usb_cfg.bit_width = cfg->bit_width; 1511 1512 afe_port_send_usb_params(port, cfg); 1513 } 1514 EXPORT_SYMBOL_GPL(q6afe_usb_port_prepare); 1515 1516 /** 1517 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1518 * 1519 * @port: Instance of afe port 1520 * @cfg: HDMI configuration for the afe port 1521 * 1522 */ 1523 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1524 struct q6afe_hdmi_cfg *cfg) 1525 { 1526 union afe_port_config *pcfg = &port->port_cfg; 1527 1528 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1529 AFE_API_VERSION_HDMI_CONFIG; 1530 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1531 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1532 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1533 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1534 } 1535 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1536 1537 /** 1538 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1539 * 1540 * @port: Instance of afe port 1541 * @cfg: I2S configuration for the afe port 1542 * Return: Will be an negative on error and zero on success. 1543 */ 1544 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1545 { 1546 union afe_port_config *pcfg = &port->port_cfg; 1547 struct device *dev = port->afe->dev; 1548 int num_sd_lines; 1549 1550 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1551 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1552 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1553 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1554 1555 switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1556 case SND_SOC_DAIFMT_BP_FP: 1557 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1558 break; 1559 case SND_SOC_DAIFMT_BC_FC: 1560 /* CPU is slave */ 1561 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1562 break; 1563 default: 1564 break; 1565 } 1566 1567 num_sd_lines = hweight_long(cfg->sd_line_mask); 1568 1569 switch (num_sd_lines) { 1570 case 0: 1571 dev_err(dev, "no line is assigned\n"); 1572 return -EINVAL; 1573 case 1: 1574 switch (cfg->sd_line_mask) { 1575 case AFE_PORT_I2S_SD0_MASK: 1576 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1577 break; 1578 case AFE_PORT_I2S_SD1_MASK: 1579 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1580 break; 1581 case AFE_PORT_I2S_SD2_MASK: 1582 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1583 break; 1584 case AFE_PORT_I2S_SD3_MASK: 1585 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1586 break; 1587 default: 1588 dev_err(dev, "Invalid SD lines\n"); 1589 return -EINVAL; 1590 } 1591 break; 1592 case 2: 1593 switch (cfg->sd_line_mask) { 1594 case AFE_PORT_I2S_SD0_1_MASK: 1595 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1596 break; 1597 case AFE_PORT_I2S_SD2_3_MASK: 1598 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1599 break; 1600 default: 1601 dev_err(dev, "Invalid SD lines\n"); 1602 return -EINVAL; 1603 } 1604 break; 1605 case 3: 1606 switch (cfg->sd_line_mask) { 1607 case AFE_PORT_I2S_SD0_1_2_MASK: 1608 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1609 break; 1610 default: 1611 dev_err(dev, "Invalid SD lines\n"); 1612 return -EINVAL; 1613 } 1614 break; 1615 case 4: 1616 switch (cfg->sd_line_mask) { 1617 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1618 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1619 1620 break; 1621 default: 1622 dev_err(dev, "Invalid SD lines\n"); 1623 return -EINVAL; 1624 } 1625 break; 1626 default: 1627 dev_err(dev, "Invalid SD lines\n"); 1628 return -EINVAL; 1629 } 1630 1631 switch (cfg->num_channels) { 1632 case 1: 1633 case 2: 1634 switch (pcfg->i2s_cfg.channel_mode) { 1635 case AFE_PORT_I2S_QUAD01: 1636 case AFE_PORT_I2S_6CHS: 1637 case AFE_PORT_I2S_8CHS: 1638 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1639 break; 1640 case AFE_PORT_I2S_QUAD23: 1641 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1642 break; 1643 } 1644 1645 if (cfg->num_channels == 2) 1646 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1647 else 1648 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1649 1650 break; 1651 case 3: 1652 case 4: 1653 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1654 dev_err(dev, "Invalid Channel mode\n"); 1655 return -EINVAL; 1656 } 1657 break; 1658 case 5: 1659 case 6: 1660 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1661 dev_err(dev, "Invalid Channel mode\n"); 1662 return -EINVAL; 1663 } 1664 break; 1665 case 7: 1666 case 8: 1667 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1668 dev_err(dev, "Invalid Channel mode\n"); 1669 return -EINVAL; 1670 } 1671 break; 1672 default: 1673 break; 1674 } 1675 1676 return 0; 1677 } 1678 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1679 1680 /** 1681 * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. 1682 * 1683 * @port: Instance of afe port 1684 * @cfg: DMA configuration for the afe port 1685 * 1686 */ 1687 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 1688 struct q6afe_cdc_dma_cfg *cfg) 1689 { 1690 union afe_port_config *pcfg = &port->port_cfg; 1691 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; 1692 1693 dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; 1694 dma_cfg->sample_rate = cfg->sample_rate; 1695 dma_cfg->bit_width = cfg->bit_width; 1696 dma_cfg->data_format = cfg->data_format; 1697 dma_cfg->num_channels = cfg->num_channels; 1698 if (!cfg->active_channels_mask) 1699 dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; 1700 } 1701 EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); 1702 /** 1703 * q6afe_port_start() - Start a afe port 1704 * 1705 * @port: Instance of port to start 1706 * 1707 * Return: Will be an negative on packet size on success. 1708 */ 1709 int q6afe_port_start(struct q6afe_port *port) 1710 { 1711 struct afe_port_cmd_device_start *start; 1712 struct q6afe *afe = port->afe; 1713 int port_id = port->id; 1714 int ret, param_id = port->cfg_type; 1715 struct apr_pkt *pkt; 1716 int pkt_size; 1717 1718 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1719 AFE_MODULE_AUDIO_DEV_INTERFACE, 1720 sizeof(port->port_cfg)); 1721 if (ret) { 1722 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1723 port_id, ret); 1724 return ret; 1725 } 1726 1727 if (port->scfg) { 1728 ret = q6afe_port_set_param_v2(port, port->scfg, 1729 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1730 AFE_MODULE_TDM, sizeof(*port->scfg)); 1731 if (ret) { 1732 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1733 port_id, ret); 1734 return ret; 1735 } 1736 } 1737 1738 pkt_size = APR_HDR_SIZE + sizeof(*start); 1739 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1740 if (!p) 1741 return -ENOMEM; 1742 1743 pkt = p; 1744 start = p + APR_HDR_SIZE; 1745 1746 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1747 APR_HDR_LEN(APR_HDR_SIZE), 1748 APR_PKT_VER); 1749 pkt->hdr.pkt_size = pkt_size; 1750 pkt->hdr.src_port = 0; 1751 pkt->hdr.dest_port = 0; 1752 pkt->hdr.token = port->token; 1753 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1754 1755 start->port_id = port_id; 1756 1757 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); 1758 if (ret) 1759 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1760 port_id, ret); 1761 1762 return ret; 1763 } 1764 EXPORT_SYMBOL_GPL(q6afe_port_start); 1765 1766 /** 1767 * q6afe_port_get_from_id() - Get port instance from a port id 1768 * 1769 * @dev: Pointer to afe child device. 1770 * @id: port id 1771 * 1772 * Return: Will be an error pointer on error or a valid afe port 1773 * on success. 1774 */ 1775 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1776 { 1777 int port_id; 1778 struct q6afe *afe = dev_get_drvdata(dev->parent); 1779 struct q6afe_port *port; 1780 int cfg_type; 1781 1782 if (id < 0 || id >= AFE_PORT_MAX) { 1783 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1784 return ERR_PTR(-EINVAL); 1785 } 1786 1787 /* if port is multiple times bind/unbind before callback finishes */ 1788 port = q6afe_find_port(afe, id); 1789 if (port) { 1790 dev_err(dev, "AFE Port already open\n"); 1791 return port; 1792 } 1793 1794 port_id = port_maps[id].port_id; 1795 1796 switch (port_id) { 1797 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1798 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1799 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1800 break; 1801 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1802 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1803 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1804 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1805 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1806 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1807 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1808 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1809 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1810 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1811 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1812 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1813 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1814 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1815 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1816 break; 1817 1818 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1819 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1820 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1821 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1822 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1823 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1824 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1825 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1826 case AFE_PORT_ID_QUINARY_MI2S_RX: 1827 case AFE_PORT_ID_QUINARY_MI2S_TX: 1828 case AFE_PORT_ID_SENARY_MI2S_RX: 1829 case AFE_PORT_ID_SENARY_MI2S_TX: 1830 case AFE_PORT_ID_INT0_MI2S_RX: 1831 case AFE_PORT_ID_INT0_MI2S_TX: 1832 case AFE_PORT_ID_INT1_MI2S_RX: 1833 case AFE_PORT_ID_INT1_MI2S_TX: 1834 case AFE_PORT_ID_INT2_MI2S_RX: 1835 case AFE_PORT_ID_INT2_MI2S_TX: 1836 case AFE_PORT_ID_INT3_MI2S_RX: 1837 case AFE_PORT_ID_INT3_MI2S_TX: 1838 case AFE_PORT_ID_INT4_MI2S_RX: 1839 case AFE_PORT_ID_INT4_MI2S_TX: 1840 case AFE_PORT_ID_INT5_MI2S_RX: 1841 case AFE_PORT_ID_INT5_MI2S_TX: 1842 case AFE_PORT_ID_INT6_MI2S_RX: 1843 case AFE_PORT_ID_INT6_MI2S_TX: 1844 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1845 break; 1846 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1847 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1848 break; 1849 case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: 1850 cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; 1851 break; 1852 case AFE_PORT_ID_USB_RX: 1853 cfg_type = AFE_PARAM_ID_USB_AUDIO_CONFIG; 1854 break; 1855 default: 1856 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1857 return ERR_PTR(-EINVAL); 1858 } 1859 1860 port = kzalloc(sizeof(*port), GFP_KERNEL); 1861 if (!port) 1862 return ERR_PTR(-ENOMEM); 1863 1864 init_waitqueue_head(&port->wait); 1865 1866 port->token = id; 1867 port->id = port_id; 1868 port->afe = afe; 1869 port->cfg_type = cfg_type; 1870 kref_init(&port->refcount); 1871 1872 scoped_guard(spinlock_irqsave, &afe->port_list_lock) 1873 list_add_tail(&port->node, &afe->port_list); 1874 1875 return port; 1876 1877 } 1878 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1879 1880 /** 1881 * q6afe_port_put() - Release port reference 1882 * 1883 * @port: Instance of port to put 1884 */ 1885 void q6afe_port_put(struct q6afe_port *port) 1886 { 1887 kref_put(&port->refcount, q6afe_port_free); 1888 } 1889 EXPORT_SYMBOL_GPL(q6afe_port_put); 1890 1891 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1892 uint32_t client_handle) 1893 { 1894 struct q6afe *afe = dev_get_drvdata(dev->parent); 1895 struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; 1896 struct apr_pkt *pkt; 1897 int ret = 0; 1898 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1899 1900 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1901 if (!p) 1902 return -ENOMEM; 1903 1904 pkt = p; 1905 vote_cfg = p + APR_HDR_SIZE; 1906 1907 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1908 APR_HDR_LEN(APR_HDR_SIZE), 1909 APR_PKT_VER); 1910 pkt->hdr.pkt_size = pkt_size; 1911 pkt->hdr.src_port = 0; 1912 pkt->hdr.dest_port = 0; 1913 pkt->hdr.token = hw_block_id; 1914 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; 1915 vote_cfg->hw_block_id = hw_block_id; 1916 vote_cfg->client_handle = client_handle; 1917 1918 ret = apr_send_pkt(afe->apr, pkt); 1919 if (ret < 0) 1920 dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); 1921 1922 return ret; 1923 } 1924 EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); 1925 1926 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1927 const char *client_name, uint32_t *client_handle) 1928 { 1929 struct q6afe *afe = dev_get_drvdata(dev->parent); 1930 struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; 1931 struct apr_pkt *pkt; 1932 int ret = 0; 1933 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1934 1935 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1936 if (!p) 1937 return -ENOMEM; 1938 1939 pkt = p; 1940 vote_cfg = p + APR_HDR_SIZE; 1941 1942 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1943 APR_HDR_LEN(APR_HDR_SIZE), 1944 APR_PKT_VER); 1945 pkt->hdr.pkt_size = pkt_size; 1946 pkt->hdr.src_port = 0; 1947 pkt->hdr.dest_port = 0; 1948 pkt->hdr.token = hw_block_id; 1949 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; 1950 vote_cfg->hw_block_id = hw_block_id; 1951 strscpy(vote_cfg->client_name, client_name, 1952 sizeof(vote_cfg->client_name)); 1953 1954 ret = afe_apr_send_pkt(afe, pkt, NULL, 1955 AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); 1956 if (ret) 1957 dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); 1958 1959 return ret; 1960 } 1961 EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); 1962 1963 static int q6afe_probe(struct apr_device *adev) 1964 { 1965 struct q6afe *afe; 1966 struct device *dev = &adev->dev; 1967 1968 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1969 if (!afe) 1970 return -ENOMEM; 1971 1972 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1973 afe->apr = adev; 1974 mutex_init(&afe->lock); 1975 init_waitqueue_head(&afe->wait); 1976 afe->dev = dev; 1977 INIT_LIST_HEAD(&afe->port_list); 1978 spin_lock_init(&afe->port_list_lock); 1979 1980 dev_set_drvdata(dev, afe); 1981 1982 return devm_of_platform_populate(dev); 1983 } 1984 1985 #ifdef CONFIG_OF 1986 static const struct of_device_id q6afe_device_id[] = { 1987 { .compatible = "qcom,q6afe" }, 1988 {}, 1989 }; 1990 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1991 #endif 1992 1993 static struct apr_driver qcom_q6afe_driver = { 1994 .probe = q6afe_probe, 1995 .callback = q6afe_callback, 1996 .driver = { 1997 .name = "qcom-q6afe", 1998 .of_match_table = of_match_ptr(q6afe_device_id), 1999 2000 }, 2001 }; 2002 2003 module_apr_driver(qcom_q6afe_driver); 2004 MODULE_DESCRIPTION("Q6 Audio Front End"); 2005 MODULE_LICENSE("GPL v2"); 2006