1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dmi.h>
14 #include <linux/eeprom_93cx6.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/math.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm.h>
22 #include <linux/property.h>
23 #include <linux/string.h>
24 #include <linux/types.h>
25
26 #include <linux/serial_8250.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial_reg.h>
29
30 #include <asm/byteorder.h>
31
32 #include "8250.h"
33 #include "8250_pcilib.h"
34
35 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
36 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
37 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
38 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
39 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
40 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
41 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
42
43 #define PCI_DEVICE_ID_ADVANTECH_XR17V352 0x0018
44
45 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
46 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
47 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
48 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
49 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
50 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
51 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
52
53 #define PCI_VENDOR_ID_CONNECT_TECH 0x12c4
54 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340
55 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341
56 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342
57 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350
58 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351
59 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352
60 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353
61 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354
62 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355
63 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360
64 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361
65 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362
66 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370
67 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371
68 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372
69 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373
70 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374
71 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375
72 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376
73 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380
74 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381
75 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382
76 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392
77 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0
78 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1
79 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2
80 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3
81 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602
82 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000
83 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002
84 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004
85 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008
86 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C
87 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010
88 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c
89 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d
90 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110
91
92 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
93 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
94 #define PCI_DEVICE_ID_EXAR_XR17V252 0x0252
95 #define PCI_DEVICE_ID_EXAR_XR17V254 0x0254
96 #define PCI_DEVICE_ID_EXAR_XR17V258 0x0258
97
98 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
99 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
100
101 #define UART_EXAR_INT0 0x80
102 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
103 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
104 #define UART_EXAR_DVID 0x8d /* Device identification */
105
106 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
107 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
108 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
109 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
110 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
111 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
112 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
113
114 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
115 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
116
117 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
118 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
119 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
120 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
121 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
122 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
123 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
124 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
125 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
126 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
127 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
128 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
129
130 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
131
132 #define UART_EXAR_DLD 0x02 /* Divisor Fractional */
133 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
134
135 /* EEPROM registers */
136 #define UART_EXAR_REGB 0x8e
137 #define UART_EXAR_REGB_EECK BIT(4)
138 #define UART_EXAR_REGB_EECS BIT(5)
139 #define UART_EXAR_REGB_EEDI BIT(6)
140 #define UART_EXAR_REGB_EEDO BIT(7)
141
142 #define UART_EXAR_XR17C15X_PORT_OFFSET 0x200
143 #define UART_EXAR_XR17V25X_PORT_OFFSET 0x200
144 #define UART_EXAR_XR17V35X_PORT_OFFSET 0x400
145
146 /*
147 * IOT2040 MPIO wiring semantics:
148 *
149 * MPIO Port Function
150 * ---- ---- --------
151 * 0 2 Mode bit 0
152 * 1 2 Mode bit 1
153 * 2 2 Terminate bus
154 * 3 - <reserved>
155 * 4 3 Mode bit 0
156 * 5 3 Mode bit 1
157 * 6 3 Terminate bus
158 * 7 - <reserved>
159 * 8 2 Enable
160 * 9 3 Enable
161 * 10 - Red LED
162 * 11..15 - <unused>
163 */
164
165 /* IOT2040 MPIOs 0..7 */
166 #define IOT2040_UART_MODE_RS232 0x01
167 #define IOT2040_UART_MODE_RS485 0x02
168 #define IOT2040_UART_MODE_RS422 0x03
169 #define IOT2040_UART_TERMINATE_BUS 0x04
170
171 #define IOT2040_UART1_MASK 0x0f
172 #define IOT2040_UART2_SHIFT 4
173
174 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
175 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
176
177 /* IOT2040 MPIOs 8..15 */
178 #define IOT2040_UARTS_ENABLE 0x03
179 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
180
181 /* CTI EEPROM offsets */
182 #define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words */
183 #define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words */
184 #define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word */
185
186 #define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words */
187 #define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words */
188 #define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word */
189
190 #define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word */
191 #define CTI_EE_OFF_XR17V35X_BRD_FLAGS 0x13 /* 1 word */
192 #define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word */
193
194 #define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0)
195 #define CTI_EE_MASK_OSC_FREQ GENMASK(31, 0)
196
197 #define CTI_FPGA_RS485_IO_REG 0x2008
198 #define CTI_FPGA_CFG_INT_EN_REG 0x48
199 #define CTI_FPGA_CFG_INT_EN_EXT_BIT BIT(15) /* External int enable bit */
200
201 #define CTI_DEFAULT_PCI_OSC_FREQ 29491200
202 #define CTI_DEFAULT_PCIE_OSC_FREQ 125000000
203 #define CTI_DEFAULT_FPGA_OSC_FREQ 33333333
204
205 /*
206 * CTI Serial port line types. These match the values stored in the first
207 * nibble of the CTI EEPROM port_flags word.
208 */
209 enum cti_port_type {
210 CTI_PORT_TYPE_NONE = 0,
211 CTI_PORT_TYPE_RS232, // RS232 ONLY
212 CTI_PORT_TYPE_RS422_485, // RS422/RS485 ONLY
213 CTI_PORT_TYPE_RS232_422_485_HW, // RS232/422/485 HW ONLY Switchable
214 CTI_PORT_TYPE_RS232_422_485_SW, // RS232/422/485 SW ONLY Switchable
215 CTI_PORT_TYPE_RS232_422_485_4B, // RS232/422/485 HW/SW (4bit ex. BCG004)
216 CTI_PORT_TYPE_RS232_422_485_2B, // RS232/422/485 HW/SW (2bit ex. BBG008)
217 CTI_PORT_TYPE_MAX,
218 };
219
220 #define CTI_PORT_TYPE_VALID(_port_type) \
221 (((_port_type) > CTI_PORT_TYPE_NONE) && \
222 ((_port_type) < CTI_PORT_TYPE_MAX))
223
224 #define CTI_PORT_TYPE_RS485(_port_type) \
225 (((_port_type) > CTI_PORT_TYPE_RS232) && \
226 ((_port_type) < CTI_PORT_TYPE_MAX))
227
228 struct exar8250;
229
230 struct exar8250_platform {
231 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
232 struct serial_rs485 *rs485);
233 const struct serial_rs485 *rs485_supported;
234 int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port);
235 void (*unregister_gpio)(struct uart_8250_port *port);
236 };
237
238 /**
239 * struct exar8250_board - board information
240 * @num_ports: number of serial ports
241 * @reg_shift: describes UART register mapping in PCI memory
242 * @setup: quirk run at ->probe() stage for each port
243 * @exit: quirk run at ->remove() stage
244 */
245 struct exar8250_board {
246 unsigned int num_ports;
247 unsigned int reg_shift;
248 int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev,
249 struct uart_8250_port *port, int idx);
250 void (*exit)(struct pci_dev *pcidev);
251 };
252
253 struct exar8250 {
254 unsigned int nr;
255 unsigned int osc_freq;
256 struct exar8250_board *board;
257 struct eeprom_93cx6 eeprom;
258 void __iomem *virt;
259 int line[];
260 };
261
exar_write_reg(struct exar8250 * priv,unsigned int reg,u8 value)262 static inline void exar_write_reg(struct exar8250 *priv,
263 unsigned int reg, u8 value)
264 {
265 writeb(value, priv->virt + reg);
266 }
267
exar_read_reg(struct exar8250 * priv,unsigned int reg)268 static inline u8 exar_read_reg(struct exar8250 *priv, unsigned int reg)
269 {
270 return readb(priv->virt + reg);
271 }
272
exar_eeprom_93cx6_reg_read(struct eeprom_93cx6 * eeprom)273 static void exar_eeprom_93cx6_reg_read(struct eeprom_93cx6 *eeprom)
274 {
275 struct exar8250 *priv = eeprom->data;
276 u8 regb = exar_read_reg(priv, UART_EXAR_REGB);
277
278 /* EECK and EECS always read 0 from REGB so only set EEDO */
279 eeprom->reg_data_out = regb & UART_EXAR_REGB_EEDO;
280 }
281
exar_eeprom_93cx6_reg_write(struct eeprom_93cx6 * eeprom)282 static void exar_eeprom_93cx6_reg_write(struct eeprom_93cx6 *eeprom)
283 {
284 struct exar8250 *priv = eeprom->data;
285 u8 regb = 0;
286
287 if (eeprom->reg_data_in)
288 regb |= UART_EXAR_REGB_EEDI;
289 if (eeprom->reg_data_clock)
290 regb |= UART_EXAR_REGB_EECK;
291 if (eeprom->reg_chip_select)
292 regb |= UART_EXAR_REGB_EECS;
293
294 exar_write_reg(priv, UART_EXAR_REGB, regb);
295 }
296
exar_eeprom_init(struct exar8250 * priv)297 static void exar_eeprom_init(struct exar8250 *priv)
298 {
299 priv->eeprom.data = priv;
300 priv->eeprom.register_read = exar_eeprom_93cx6_reg_read;
301 priv->eeprom.register_write = exar_eeprom_93cx6_reg_write;
302 priv->eeprom.width = PCI_EEPROM_WIDTH_93C46;
303 priv->eeprom.quirks |= PCI_EEPROM_QUIRK_EXTRA_READ_CYCLE;
304 }
305
306 /**
307 * exar_mpio_config_output() - Configure an Exar MPIO as an output
308 * @priv: Device's private structure
309 * @mpio_num: MPIO number/offset to configure
310 *
311 * Configure a single MPIO as an output and disable tristate. It is recommended
312 * to set the level with exar_mpio_set_high()/exar_mpio_set_low() prior to
313 * calling this function to ensure default MPIO pin state.
314 *
315 * Return: 0 on success, negative error code on failure
316 */
exar_mpio_config_output(struct exar8250 * priv,unsigned int mpio_num)317 static int exar_mpio_config_output(struct exar8250 *priv,
318 unsigned int mpio_num)
319 {
320 unsigned int mpio_offset;
321 u8 sel_reg; // MPIO Select register (input/output)
322 u8 tri_reg; // MPIO Tristate register
323 u8 value;
324
325 if (mpio_num < 8) {
326 sel_reg = UART_EXAR_MPIOSEL_7_0;
327 tri_reg = UART_EXAR_MPIO3T_7_0;
328 mpio_offset = mpio_num;
329 } else if (mpio_num >= 8 && mpio_num < 16) {
330 sel_reg = UART_EXAR_MPIOSEL_15_8;
331 tri_reg = UART_EXAR_MPIO3T_15_8;
332 mpio_offset = mpio_num - 8;
333 } else {
334 return -EINVAL;
335 }
336
337 // Disable MPIO pin tri-state
338 value = exar_read_reg(priv, tri_reg);
339 value &= ~BIT(mpio_offset);
340 exar_write_reg(priv, tri_reg, value);
341
342 value = exar_read_reg(priv, sel_reg);
343 value &= ~BIT(mpio_offset);
344 exar_write_reg(priv, sel_reg, value);
345
346 return 0;
347 }
348
349 /**
350 * _exar_mpio_set() - Set an Exar MPIO output high or low
351 * @priv: Device's private structure
352 * @mpio_num: MPIO number/offset to set
353 * @high: Set MPIO high if true, low if false
354 *
355 * Set a single MPIO high or low. exar_mpio_config_output() must also be called
356 * to configure the pin as an output.
357 *
358 * Return: 0 on success, negative error code on failure
359 */
_exar_mpio_set(struct exar8250 * priv,unsigned int mpio_num,bool high)360 static int _exar_mpio_set(struct exar8250 *priv,
361 unsigned int mpio_num, bool high)
362 {
363 unsigned int mpio_offset;
364 u8 lvl_reg;
365 u8 value;
366
367 if (mpio_num < 8) {
368 lvl_reg = UART_EXAR_MPIOLVL_7_0;
369 mpio_offset = mpio_num;
370 } else if (mpio_num >= 8 && mpio_num < 16) {
371 lvl_reg = UART_EXAR_MPIOLVL_15_8;
372 mpio_offset = mpio_num - 8;
373 } else {
374 return -EINVAL;
375 }
376
377 value = exar_read_reg(priv, lvl_reg);
378 if (high)
379 value |= BIT(mpio_offset);
380 else
381 value &= ~BIT(mpio_offset);
382 exar_write_reg(priv, lvl_reg, value);
383
384 return 0;
385 }
386
exar_mpio_set_low(struct exar8250 * priv,unsigned int mpio_num)387 static int exar_mpio_set_low(struct exar8250 *priv, unsigned int mpio_num)
388 {
389 return _exar_mpio_set(priv, mpio_num, false);
390 }
391
exar_mpio_set_high(struct exar8250 * priv,unsigned int mpio_num)392 static int exar_mpio_set_high(struct exar8250 *priv, unsigned int mpio_num)
393 {
394 return _exar_mpio_set(priv, mpio_num, true);
395 }
396
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)397 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
398 struct serial_rs485 *rs485)
399 {
400 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
401 u8 __iomem *p = port->membase;
402 u8 value;
403
404 value = readb(p + UART_EXAR_FCTR);
405 if (is_rs485)
406 value |= UART_FCTR_EXAR_485;
407 else
408 value &= ~UART_FCTR_EXAR_485;
409
410 writeb(value, p + UART_EXAR_FCTR);
411
412 if (is_rs485)
413 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
414
415 return 0;
416 }
417
418 static const struct serial_rs485 generic_rs485_supported = {
419 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
420 };
421
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)422 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
423 {
424 /*
425 * Exar UARTs have a SLEEP register that enables or disables each UART
426 * to enter sleep mode separately. On the XR17V35x the register
427 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
428 * the UART channel may only write to the corresponding bit.
429 */
430 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
431 }
432
433 /*
434 * XR17V35x UARTs have an extra fractional divisor register (DLD)
435 * Calculate divisor with extra 4-bit fractional portion
436 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)437 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
438 unsigned int *frac)
439 {
440 unsigned int quot_16;
441
442 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
443 *frac = quot_16 & 0x0f;
444
445 return quot_16 >> 4;
446 }
447
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)448 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
449 unsigned int quot, unsigned int quot_frac)
450 {
451 serial8250_do_set_divisor(p, baud, quot);
452
453 /* Preserve bits not related to baudrate; DLD[7:4]. */
454 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
455 serial_port_out(p, 0x2, quot_frac);
456 }
457
xr17v35x_startup(struct uart_port * port)458 static int xr17v35x_startup(struct uart_port *port)
459 {
460 /*
461 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
462 * MCR [7:5] and MSR [7:0]
463 */
464 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
465
466 /*
467 * Make sure all interrupts are masked until initialization is
468 * complete and the FIFOs are cleared
469 *
470 * Synchronize UART_IER access against the console.
471 */
472 uart_port_lock_irq(port);
473 serial_port_out(port, UART_IER, 0);
474 uart_port_unlock_irq(port);
475
476 return serial8250_do_startup(port);
477 }
478
exar_shutdown(struct uart_port * port)479 static void exar_shutdown(struct uart_port *port)
480 {
481 bool tx_complete = false;
482 struct uart_8250_port *up = up_to_u8250p(port);
483 struct tty_port *tport = &port->state->port;
484 int i = 0;
485 u16 lsr;
486
487 do {
488 lsr = serial_in(up, UART_LSR);
489 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
490 tx_complete = true;
491 else
492 tx_complete = false;
493 usleep_range(1000, 1100);
494 } while (!kfifo_is_empty(&tport->xmit_fifo) &&
495 !tx_complete && i++ < 1000);
496
497 serial8250_do_shutdown(port);
498 }
499
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)500 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
501 int idx, unsigned int offset,
502 struct uart_8250_port *port)
503 {
504 const struct exar8250_board *board = priv->board;
505 unsigned char status;
506 int err;
507
508 err = serial8250_pci_setup_port(pcidev, port, 0, offset, board->reg_shift);
509 if (err)
510 return err;
511
512 /*
513 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
514 * with when DLAB is set which will cause the device to incorrectly match
515 * and assign port type to PORT_16650. The EFR for this UART is found
516 * at offset 0x09. Instead check the Deice ID (DVID) register
517 * for a 2, 4 or 8 port UART.
518 */
519 status = readb(port->port.membase + UART_EXAR_DVID);
520 if (status == 0x82 || status == 0x84 || status == 0x88) {
521 port->port.type = PORT_XR17V35X;
522
523 port->port.get_divisor = xr17v35x_get_divisor;
524 port->port.set_divisor = xr17v35x_set_divisor;
525
526 port->port.startup = xr17v35x_startup;
527 } else {
528 port->port.type = PORT_XR17D15X;
529 }
530
531 port->port.pm = exar_pm;
532 port->port.shutdown = exar_shutdown;
533
534 return 0;
535 }
536
537 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)538 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
539 struct uart_8250_port *port, int idx)
540 {
541 unsigned int offset = idx * 0x200;
542 unsigned int baud = 1843200;
543 u8 __iomem *p;
544 int err;
545
546 port->port.uartclk = baud * 16;
547
548 err = default_setup(priv, pcidev, idx, offset, port);
549 if (err)
550 return err;
551
552 p = port->port.membase;
553
554 writeb(0x00, p + UART_EXAR_8XMODE);
555 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
556 writeb(32, p + UART_EXAR_TXTRG);
557 writeb(32, p + UART_EXAR_RXTRG);
558
559 /* Skip the initial (per device) setup */
560 if (idx)
561 return 0;
562
563 /*
564 * Setup Multipurpose Input/Output pins.
565 */
566 switch (pcidev->device) {
567 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
568 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
569 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
570 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
571 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
572 break;
573 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
574 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
575 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
576 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
577 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
578 break;
579 default:
580 break;
581 }
582 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
583 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
584 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
585
586 return 0;
587 }
588
589 /**
590 * cti_tristate_disable() - Disable RS485 transciever tristate
591 * @priv: Device's private structure
592 * @port_num: Port number to set tristate off
593 *
594 * Most RS485 capable cards have a power on tristate jumper/switch that ensures
595 * the RS422/RS485 transceiver does not drive a multi-drop RS485 bus when it is
596 * not the master. When this jumper is installed the user must set the RS485
597 * mode to Full or Half duplex to disable tristate prior to using the port.
598 *
599 * Some Exar UARTs have an auto-tristate feature while others require setting
600 * an MPIO to disable the tristate.
601 *
602 * Return: 0 on success, negative error code on failure
603 */
cti_tristate_disable(struct exar8250 * priv,unsigned int port_num)604 static int cti_tristate_disable(struct exar8250 *priv, unsigned int port_num)
605 {
606 int ret;
607
608 ret = exar_mpio_set_high(priv, port_num);
609 if (ret)
610 return ret;
611
612 return exar_mpio_config_output(priv, port_num);
613 }
614
615 /**
616 * cti_plx_int_enable() - Enable UART interrupts to PLX bridge
617 * @priv: Device's private structure
618 *
619 * Some older CTI cards require MPIO_0 to be set low to enable the
620 * interrupts from the UART to the PLX PCI->PCIe bridge.
621 *
622 * Return: 0 on success, negative error code on failure
623 */
cti_plx_int_enable(struct exar8250 * priv)624 static int cti_plx_int_enable(struct exar8250 *priv)
625 {
626 int ret;
627
628 ret = exar_mpio_set_low(priv, 0);
629 if (ret)
630 return ret;
631
632 return exar_mpio_config_output(priv, 0);
633 }
634
635 /**
636 * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM
637 * @priv: Device's private structure
638 * @eeprom_offset: Offset where the oscillator frequency is stored
639 *
640 * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequency
641 * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe clock.
642 *
643 * Return: frequency on success, negative error code on failure
644 */
cti_read_osc_freq(struct exar8250 * priv,u8 eeprom_offset)645 static int cti_read_osc_freq(struct exar8250 *priv, u8 eeprom_offset)
646 {
647 __le16 ee_words[2];
648 u32 osc_freq;
649
650 eeprom_93cx6_multiread(&priv->eeprom, eeprom_offset, ee_words, ARRAY_SIZE(ee_words));
651
652 osc_freq = le16_to_cpu(ee_words[0]) | (le16_to_cpu(ee_words[1]) << 16);
653 if (osc_freq == CTI_EE_MASK_OSC_FREQ)
654 return -EIO;
655
656 return osc_freq;
657 }
658
659 /**
660 * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v25x
661 * @priv: Device's private structure
662 * @pcidev: Pointer to the PCI device for this port
663 * @port_num: Port to get type of
664 *
665 * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs.
666 *
667 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
668 */
cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)669 static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 *priv,
670 struct pci_dev *pcidev,
671 unsigned int port_num)
672 {
673 switch (pcidev->subsystem_device) {
674 // RS232 only cards
675 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232:
676 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232:
677 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232:
678 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232:
679 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS:
680 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232:
681 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS:
682 return CTI_PORT_TYPE_RS232;
683 // 1x RS232, 1x RS422/RS485
684 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1:
685 return (port_num == 0) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
686 // 2x RS232, 2x RS422/RS485
687 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2:
688 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
689 // 4x RS232, 4x RS422/RS485
690 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4:
691 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
692 return (port_num < 4) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
693 // RS232/RS422/RS485 HW (jumper) selectable
694 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2:
695 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4:
696 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8:
697 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO:
698 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A:
699 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B:
700 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
701 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
702 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
703 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
704 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
705 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
706 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
707 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
708 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
709 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
710 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
711 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
712 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
713 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
714 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
715 return CTI_PORT_TYPE_RS232_422_485_HW;
716 // RS422/RS485 HW (jumper) selectable
717 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485:
718 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485:
719 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485:
720 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
721 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
722 return CTI_PORT_TYPE_RS422_485;
723 // 6x RS232, 2x RS422/RS485
724 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
725 return (port_num < 6) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
726 // 2x RS232, 6x RS422/RS485
727 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
728 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
729 default:
730 dev_err(&pcidev->dev, "unknown/unsupported device\n");
731 return CTI_PORT_TYPE_NONE;
732 }
733 }
734
735 /**
736 * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card
737 * @priv: Device's private structure
738 * @pcidev: Pointer to the PCI device for this port
739 * @port_num: Port to get type of
740 *
741 * FPGA based cards port types are based on PCI IDs.
742 *
743 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
744 */
cti_get_port_type_fpga(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)745 static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv,
746 struct pci_dev *pcidev,
747 unsigned int port_num)
748 {
749 switch (pcidev->device) {
750 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
751 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
752 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
753 return CTI_PORT_TYPE_RS232_422_485_HW;
754 default:
755 dev_err(&pcidev->dev, "unknown/unsupported device\n");
756 return CTI_PORT_TYPE_NONE;
757 }
758 }
759
760 /**
761 * cti_get_port_type_xr17v35x() - Read port type from the EEPROM
762 * @priv: Device's private structure
763 * @pcidev: Pointer to the PCI device for this port
764 * @port_num: port offset
765 *
766 * CTI XR17V35X based cards have the port types stored in the EEPROM.
767 * This function reads the port type for a single port.
768 *
769 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
770 */
cti_get_port_type_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)771 static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv,
772 struct pci_dev *pcidev,
773 unsigned int port_num)
774 {
775 enum cti_port_type port_type;
776 u16 port_flags;
777 u8 offset;
778
779 offset = CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num;
780 eeprom_93cx6_read(&priv->eeprom, offset, &port_flags);
781
782 port_type = FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags);
783 if (CTI_PORT_TYPE_VALID(port_type))
784 return port_type;
785
786 /*
787 * If the port type is missing the card assume it is a
788 * RS232/RS422/RS485 card to be safe.
789 *
790 * There is one known board (BEG013) that only has 3 of 4 port types
791 * written to the EEPROM so this acts as a work around.
792 */
793 dev_warn(&pcidev->dev, "failed to get port %d type from EEPROM\n", port_num);
794
795 return CTI_PORT_TYPE_RS232_422_485_HW;
796 }
797
cti_rs485_config_mpio_tristate(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)798 static int cti_rs485_config_mpio_tristate(struct uart_port *port,
799 struct ktermios *termios,
800 struct serial_rs485 *rs485)
801 {
802 struct exar8250 *priv = (struct exar8250 *)port->private_data;
803 int ret;
804
805 ret = generic_rs485_config(port, termios, rs485);
806 if (ret)
807 return ret;
808
809 // Disable power-on RS485 tri-state via MPIO
810 return cti_tristate_disable(priv, port->port_id);
811 }
812
cti_board_init_osc_freq(struct exar8250 * priv,struct pci_dev * pcidev,u8 eeprom_offset)813 static void cti_board_init_osc_freq(struct exar8250 *priv, struct pci_dev *pcidev, u8 eeprom_offset)
814 {
815 int osc_freq;
816
817 osc_freq = cti_read_osc_freq(priv, eeprom_offset);
818 if (osc_freq <= 0) {
819 dev_warn(&pcidev->dev, "failed to read OSC freq from EEPROM, using default\n");
820 osc_freq = CTI_DEFAULT_PCI_OSC_FREQ;
821 }
822
823 priv->osc_freq = osc_freq;
824 }
825
cti_port_setup_common(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)826 static int cti_port_setup_common(struct exar8250 *priv,
827 struct pci_dev *pcidev,
828 int idx, unsigned int offset,
829 struct uart_8250_port *port)
830 {
831 int ret;
832
833 port->port.port_id = idx;
834 port->port.uartclk = priv->osc_freq;
835
836 ret = serial8250_pci_setup_port(pcidev, port, 0, offset, 0);
837 if (ret)
838 return ret;
839
840 port->port.private_data = (void *)priv;
841 port->port.pm = exar_pm;
842 port->port.shutdown = exar_shutdown;
843
844 return 0;
845 }
846
cti_board_init_fpga(struct exar8250 * priv,struct pci_dev * pcidev)847 static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
848 {
849 int ret;
850 u16 cfg_val;
851
852 // FPGA OSC is fixed to the 33MHz PCI clock
853 priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
854
855 // Enable external interrupts in special cfg space register
856 ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
857 if (ret)
858 return pcibios_err_to_errno(ret);
859
860 cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
861 ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
862 if (ret)
863 return pcibios_err_to_errno(ret);
864
865 // RS485 gate needs to be enabled; otherwise RTS/CTS will not work
866 exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
867
868 return 0;
869 }
870
cti_port_setup_fpga(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)871 static int cti_port_setup_fpga(struct exar8250 *priv,
872 struct pci_dev *pcidev,
873 struct uart_8250_port *port,
874 int idx)
875 {
876 enum cti_port_type port_type;
877 unsigned int offset;
878 int ret;
879
880 if (idx == 0) {
881 ret = cti_board_init_fpga(priv, pcidev);
882 if (ret)
883 return ret;
884 }
885
886 port_type = cti_get_port_type_fpga(priv, pcidev, idx);
887
888 // FPGA shares port offsets with XR17C15X
889 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
890 port->port.type = PORT_XR17D15X;
891
892 port->port.get_divisor = xr17v35x_get_divisor;
893 port->port.set_divisor = xr17v35x_set_divisor;
894 port->port.startup = xr17v35x_startup;
895
896 if (CTI_PORT_TYPE_RS485(port_type)) {
897 port->port.rs485_config = generic_rs485_config;
898 port->port.rs485_supported = generic_rs485_supported;
899 }
900
901 return cti_port_setup_common(priv, pcidev, idx, offset, port);
902 }
903
cti_board_init_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev)904 static void cti_board_init_xr17v35x(struct exar8250 *priv, struct pci_dev *pcidev)
905 {
906 // XR17V35X uses the PCIe clock rather than an oscillator
907 priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
908 }
909
cti_port_setup_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)910 static int cti_port_setup_xr17v35x(struct exar8250 *priv,
911 struct pci_dev *pcidev,
912 struct uart_8250_port *port,
913 int idx)
914 {
915 enum cti_port_type port_type;
916 unsigned int offset;
917 int ret;
918
919 if (idx == 0)
920 cti_board_init_xr17v35x(priv, pcidev);
921
922 port_type = cti_get_port_type_xr17v35x(priv, pcidev, idx);
923
924 offset = idx * UART_EXAR_XR17V35X_PORT_OFFSET;
925 port->port.type = PORT_XR17V35X;
926
927 port->port.get_divisor = xr17v35x_get_divisor;
928 port->port.set_divisor = xr17v35x_set_divisor;
929 port->port.startup = xr17v35x_startup;
930
931 switch (port_type) {
932 case CTI_PORT_TYPE_RS422_485:
933 case CTI_PORT_TYPE_RS232_422_485_HW:
934 port->port.rs485_config = cti_rs485_config_mpio_tristate;
935 port->port.rs485_supported = generic_rs485_supported;
936 break;
937 case CTI_PORT_TYPE_RS232_422_485_SW:
938 case CTI_PORT_TYPE_RS232_422_485_4B:
939 case CTI_PORT_TYPE_RS232_422_485_2B:
940 port->port.rs485_config = generic_rs485_config;
941 port->port.rs485_supported = generic_rs485_supported;
942 break;
943 default:
944 break;
945 }
946
947 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
948 if (ret)
949 return ret;
950
951 exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00);
952 exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
953 exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 128);
954 exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 128);
955
956 return 0;
957 }
958
cti_board_init_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev)959 static void cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
960 {
961 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
962
963 /* enable interrupts on cards that need the "PLX fix" */
964 switch (pcidev->subsystem_device) {
965 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
966 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
967 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
968 cti_plx_int_enable(priv);
969 break;
970 default:
971 break;
972 }
973 }
974
cti_port_setup_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)975 static int cti_port_setup_xr17v25x(struct exar8250 *priv,
976 struct pci_dev *pcidev,
977 struct uart_8250_port *port,
978 int idx)
979 {
980 enum cti_port_type port_type;
981 unsigned int offset;
982 int ret;
983
984 if (idx == 0)
985 cti_board_init_xr17v25x(priv, pcidev);
986
987 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
988
989 offset = idx * UART_EXAR_XR17V25X_PORT_OFFSET;
990 port->port.type = PORT_XR17D15X;
991
992 // XR17V25X supports fractional baudrates
993 port->port.get_divisor = xr17v35x_get_divisor;
994 port->port.set_divisor = xr17v35x_set_divisor;
995 port->port.startup = xr17v35x_startup;
996
997 if (CTI_PORT_TYPE_RS485(port_type)) {
998 switch (pcidev->subsystem_device) {
999 // These cards support power on 485 tri-state via MPIO
1000 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
1001 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1002 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1003 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1004 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1005 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1006 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1007 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1008 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1009 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1010 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1011 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1012 break;
1013 // Otherwise auto or no power on 485 tri-state support
1014 default:
1015 port->port.rs485_config = generic_rs485_config;
1016 break;
1017 }
1018
1019 port->port.rs485_supported = generic_rs485_supported;
1020 }
1021
1022 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
1023 if (ret)
1024 return ret;
1025
1026 exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00);
1027 exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
1028 exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 32);
1029 exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 32);
1030
1031 return 0;
1032 }
1033
cti_board_init_xr17c15x(struct exar8250 * priv,struct pci_dev * pcidev)1034 static void cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1035 {
1036 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1037
1038 /* enable interrupts on cards that need the "PLX fix" */
1039 switch (pcidev->subsystem_device) {
1040 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1041 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1042 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1043 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1044 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1045 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1046 cti_plx_int_enable(priv);
1047 break;
1048 default:
1049 break;
1050 }
1051 }
1052
cti_port_setup_xr17c15x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1053 static int cti_port_setup_xr17c15x(struct exar8250 *priv,
1054 struct pci_dev *pcidev,
1055 struct uart_8250_port *port,
1056 int idx)
1057 {
1058 enum cti_port_type port_type;
1059 unsigned int offset;
1060
1061 if (idx == 0)
1062 cti_board_init_xr17c15x(priv, pcidev);
1063
1064 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
1065
1066 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
1067 port->port.type = PORT_XR17D15X;
1068
1069 if (CTI_PORT_TYPE_RS485(port_type)) {
1070 switch (pcidev->subsystem_device) {
1071 // These cards support power on 485 tri-state via MPIO
1072 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
1073 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1074 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1075 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1076 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1077 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1078 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1079 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1080 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1081 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1082 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1083 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1084 break;
1085 // Otherwise auto or no power on 485 tri-state support
1086 default:
1087 port->port.rs485_config = generic_rs485_config;
1088 break;
1089 }
1090
1091 port->port.rs485_supported = generic_rs485_supported;
1092 }
1093
1094 return cti_port_setup_common(priv, pcidev, idx, offset, port);
1095 }
1096
1097 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1098 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1099 struct uart_8250_port *port, int idx)
1100 {
1101 unsigned int offset = idx * 0x200;
1102 unsigned int baud = 921600;
1103
1104 port->port.uartclk = baud * 16;
1105 return default_setup(priv, pcidev, idx, offset, port);
1106 }
1107
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)1108 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
1109 {
1110 /*
1111 * The Commtech adapters required the MPIOs to be driven low. The Exar
1112 * devices will export them as GPIOs, so we pre-configure them safely
1113 * as inputs.
1114 */
1115 u8 dir = 0x00;
1116
1117 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
1118 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
1119 // Configure GPIO as inputs for Commtech adapters
1120 dir = 0xff;
1121 } else {
1122 // Configure GPIO as outputs for SeaLevel adapters
1123 dir = 0x00;
1124 }
1125
1126 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1127 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1128 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1129 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1130 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
1131 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1132 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
1133 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
1134 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
1135 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
1136 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
1137 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
1138 }
1139
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)1140 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
1141 const struct software_node *node)
1142 {
1143 struct platform_device *pdev;
1144
1145 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
1146 if (!pdev)
1147 return NULL;
1148
1149 pdev->dev.parent = &pcidev->dev;
1150 device_set_node(&pdev->dev, dev_fwnode(&pcidev->dev));
1151
1152 if (device_add_software_node(&pdev->dev, node) < 0 ||
1153 platform_device_add(pdev) < 0) {
1154 platform_device_put(pdev);
1155 return NULL;
1156 }
1157
1158 return pdev;
1159 }
1160
__xr17v35x_unregister_gpio(struct platform_device * pdev)1161 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
1162 {
1163 device_remove_software_node(&pdev->dev);
1164 platform_device_unregister(pdev);
1165 }
1166
1167 static const struct property_entry exar_gpio_properties[] = {
1168 PROPERTY_ENTRY_U32("exar,first-pin", 0),
1169 PROPERTY_ENTRY_U32("ngpios", 16),
1170 { }
1171 };
1172
1173 static const struct software_node exar_gpio_node = {
1174 .properties = exar_gpio_properties,
1175 };
1176
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)1177 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
1178 {
1179 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1180 port->port.private_data =
1181 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
1182
1183 return 0;
1184 }
1185
xr17v35x_unregister_gpio(struct uart_8250_port * port)1186 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
1187 {
1188 if (!port->port.private_data)
1189 return;
1190
1191 __xr17v35x_unregister_gpio(port->port.private_data);
1192 port->port.private_data = NULL;
1193 }
1194
sealevel_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1195 static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios,
1196 struct serial_rs485 *rs485)
1197 {
1198 u8 __iomem *p = port->membase;
1199 u8 old_lcr;
1200 u8 efr;
1201 u8 dld;
1202 int ret;
1203
1204 ret = generic_rs485_config(port, termios, rs485);
1205 if (ret)
1206 return ret;
1207
1208 if (!(rs485->flags & SER_RS485_ENABLED))
1209 return 0;
1210
1211 old_lcr = readb(p + UART_LCR);
1212
1213 /* Set EFR[4]=1 to enable enhanced feature registers */
1214 efr = readb(p + UART_XR_EFR);
1215 efr |= UART_EFR_ECB;
1216 writeb(efr, p + UART_XR_EFR);
1217
1218 /* Set MCR to use DTR as Auto-RS485 Enable signal */
1219 writeb(UART_MCR_OUT1, p + UART_MCR);
1220
1221 /* Set LCR[7]=1 to enable access to DLD register */
1222 writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
1223
1224 /* Set DLD[7]=1 for inverted RS485 Enable logic */
1225 dld = readb(p + UART_EXAR_DLD);
1226 dld |= UART_EXAR_DLD_485_POLARITY;
1227 writeb(dld, p + UART_EXAR_DLD);
1228
1229 writeb(old_lcr, p + UART_LCR);
1230
1231 return 0;
1232 }
1233
1234 static const struct exar8250_platform exar8250_default_platform = {
1235 .register_gpio = xr17v35x_register_gpio,
1236 .unregister_gpio = xr17v35x_unregister_gpio,
1237 .rs485_config = generic_rs485_config,
1238 .rs485_supported = &generic_rs485_supported,
1239 };
1240
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1241 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
1242 struct serial_rs485 *rs485)
1243 {
1244 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
1245 u8 __iomem *p = port->membase;
1246 u8 mask = IOT2040_UART1_MASK;
1247 u8 mode, value;
1248
1249 if (is_rs485) {
1250 if (rs485->flags & SER_RS485_RX_DURING_TX)
1251 mode = IOT2040_UART_MODE_RS422;
1252 else
1253 mode = IOT2040_UART_MODE_RS485;
1254
1255 if (rs485->flags & SER_RS485_TERMINATE_BUS)
1256 mode |= IOT2040_UART_TERMINATE_BUS;
1257 } else {
1258 mode = IOT2040_UART_MODE_RS232;
1259 }
1260
1261 if (port->line == 3) {
1262 mask <<= IOT2040_UART2_SHIFT;
1263 mode <<= IOT2040_UART2_SHIFT;
1264 }
1265
1266 value = readb(p + UART_EXAR_MPIOLVL_7_0);
1267 value &= ~mask;
1268 value |= mode;
1269 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
1270
1271 return generic_rs485_config(port, termios, rs485);
1272 }
1273
1274 static const struct serial_rs485 iot2040_rs485_supported = {
1275 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
1276 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
1277 };
1278
1279 static const struct property_entry iot2040_gpio_properties[] = {
1280 PROPERTY_ENTRY_U32("exar,first-pin", 10),
1281 PROPERTY_ENTRY_U32("ngpios", 1),
1282 { }
1283 };
1284
1285 static const struct software_node iot2040_gpio_node = {
1286 .properties = iot2040_gpio_properties,
1287 };
1288
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)1289 static int iot2040_register_gpio(struct pci_dev *pcidev,
1290 struct uart_8250_port *port)
1291 {
1292 u8 __iomem *p = port->port.membase;
1293
1294 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
1295 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
1296 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
1297 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
1298
1299 port->port.private_data =
1300 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
1301
1302 return 0;
1303 }
1304
1305 static const struct exar8250_platform iot2040_platform = {
1306 .rs485_config = iot2040_rs485_config,
1307 .rs485_supported = &iot2040_rs485_supported,
1308 .register_gpio = iot2040_register_gpio,
1309 .unregister_gpio = xr17v35x_unregister_gpio,
1310 };
1311
1312 /*
1313 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
1314 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
1315 * board name after the device was found.
1316 */
1317 static const struct dmi_system_id exar_platforms[] = {
1318 {
1319 .matches = {
1320 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1321 },
1322 .driver_data = (void *)&iot2040_platform,
1323 },
1324 {}
1325 };
1326
exar_get_platform(void)1327 static const struct exar8250_platform *exar_get_platform(void)
1328 {
1329 const struct dmi_system_id *dmi_match;
1330
1331 dmi_match = dmi_first_match(exar_platforms);
1332 if (dmi_match)
1333 return dmi_match->driver_data;
1334
1335 return &exar8250_default_platform;
1336 }
1337
1338 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1339 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1340 struct uart_8250_port *port, int idx)
1341 {
1342 const struct exar8250_platform *platform = exar_get_platform();
1343 unsigned int offset = idx * 0x400;
1344 unsigned int baud = 7812500;
1345 u8 __iomem *p;
1346 int ret;
1347
1348 port->port.uartclk = baud * 16;
1349 port->port.rs485_config = platform->rs485_config;
1350 port->port.rs485_supported = *(platform->rs485_supported);
1351
1352 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL)
1353 port->port.rs485_config = sealevel_rs485_config;
1354
1355 /*
1356 * Setup the UART clock for the devices on expansion slot to
1357 * half the clock speed of the main chip (which is 125MHz)
1358 */
1359 if (idx >= 8)
1360 port->port.uartclk /= 2;
1361
1362 ret = default_setup(priv, pcidev, idx, offset, port);
1363 if (ret)
1364 return ret;
1365
1366 p = port->port.membase;
1367
1368 writeb(0x00, p + UART_EXAR_8XMODE);
1369 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1370 writeb(128, p + UART_EXAR_TXTRG);
1371 writeb(128, p + UART_EXAR_RXTRG);
1372
1373 if (idx == 0) {
1374 /* Setup Multipurpose Input/Output pins. */
1375 setup_gpio(pcidev, p);
1376
1377 ret = platform->register_gpio(pcidev, port);
1378 }
1379
1380 return ret;
1381 }
1382
pci_xr17v35x_exit(struct pci_dev * pcidev)1383 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
1384 {
1385 const struct exar8250_platform *platform = exar_get_platform();
1386 struct exar8250 *priv = pci_get_drvdata(pcidev);
1387 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
1388
1389 platform->unregister_gpio(port);
1390 }
1391
exar_misc_clear(struct exar8250 * priv)1392 static inline void exar_misc_clear(struct exar8250 *priv)
1393 {
1394 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
1395 readb(priv->virt + UART_EXAR_INT0);
1396
1397 /* Clear INT0 for Expansion Interface slave ports, too */
1398 if (priv->board->num_ports > 8)
1399 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
1400 }
1401
1402 /*
1403 * These Exar UARTs have an extra interrupt indicator that could fire for a
1404 * few interrupts that are not presented/cleared through IIR. One of which is
1405 * a wakeup interrupt when coming out of sleep. These interrupts are only
1406 * cleared by reading global INT0 or INT1 registers as interrupts are
1407 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
1408 * channel's address space, but for the sake of bus efficiency we register a
1409 * dedicated handler at the PCI device level to handle them.
1410 */
exar_misc_handler(int irq,void * data)1411 static irqreturn_t exar_misc_handler(int irq, void *data)
1412 {
1413 exar_misc_clear(data);
1414
1415 return IRQ_HANDLED;
1416 }
1417
exar_get_nr_ports(struct exar8250_board * board,struct pci_dev * pcidev)1418 static unsigned int exar_get_nr_ports(struct exar8250_board *board, struct pci_dev *pcidev)
1419 {
1420 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
1421 return BIT(((pcidev->device & 0x38) >> 3) - 1);
1422
1423 // Check if board struct overrides number of ports
1424 if (board->num_ports > 0)
1425 return board->num_ports;
1426
1427 // Exar encodes # ports in last nibble of PCI Device ID ex. 0358
1428 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1429 return pcidev->device & 0x0f;
1430
1431 // Handle CTI FPGA cards
1432 if (pcidev->vendor == PCI_VENDOR_ID_CONNECT_TECH) {
1433 switch (pcidev->device) {
1434 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
1435 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
1436 return 12;
1437 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
1438 return 16;
1439 default:
1440 return 0;
1441 }
1442 }
1443
1444 return 0;
1445 }
1446
1447 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)1448 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
1449 {
1450 unsigned int nr_ports, i, bar = 0, maxnr;
1451 struct exar8250_board *board;
1452 struct uart_8250_port uart;
1453 struct exar8250 *priv;
1454 int rc;
1455
1456 board = (struct exar8250_board *)ent->driver_data;
1457 if (!board)
1458 return -EINVAL;
1459
1460 rc = pcim_enable_device(pcidev);
1461 if (rc)
1462 return rc;
1463
1464 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
1465
1466 nr_ports = exar_get_nr_ports(board, pcidev);
1467 if (nr_ports == 0)
1468 return dev_err_probe(&pcidev->dev, -ENODEV, "failed to get number of ports\n");
1469
1470 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
1471 if (!priv)
1472 return -ENOMEM;
1473
1474 priv->board = board;
1475 priv->virt = pcim_iomap(pcidev, bar, 0);
1476 if (!priv->virt)
1477 return -ENOMEM;
1478
1479 pci_set_master(pcidev);
1480
1481 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
1482 if (rc < 0)
1483 return rc;
1484
1485 memset(&uart, 0, sizeof(uart));
1486 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
1487 uart.port.irq = pci_irq_vector(pcidev, 0);
1488 uart.port.dev = &pcidev->dev;
1489
1490 /* Clear interrupts */
1491 exar_misc_clear(priv);
1492
1493 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
1494 IRQF_SHARED, "exar_uart", priv);
1495 if (rc)
1496 return rc;
1497
1498 exar_eeprom_init(priv);
1499
1500 for (i = 0; i < nr_ports && i < maxnr; i++) {
1501 rc = board->setup(priv, pcidev, &uart, i);
1502 if (rc) {
1503 dev_err_probe(&pcidev->dev, rc, "Failed to setup port %u\n", i);
1504 break;
1505 }
1506
1507 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
1508 uart.port.iobase, uart.port.irq, uart.port.iotype);
1509
1510 priv->line[i] = serial8250_register_8250_port(&uart);
1511 if (priv->line[i] < 0) {
1512 dev_err_probe(&pcidev->dev, priv->line[i],
1513 "Couldn't register serial port %lx, type %d, irq %d\n",
1514 uart.port.iobase, uart.port.iotype, uart.port.irq);
1515 break;
1516 }
1517 }
1518 priv->nr = i;
1519 pci_set_drvdata(pcidev, priv);
1520 return 0;
1521 }
1522
exar_pci_remove(struct pci_dev * pcidev)1523 static void exar_pci_remove(struct pci_dev *pcidev)
1524 {
1525 struct exar8250 *priv = pci_get_drvdata(pcidev);
1526 unsigned int i;
1527
1528 for (i = 0; i < priv->nr; i++)
1529 serial8250_unregister_port(priv->line[i]);
1530
1531 /* Ensure that every init quirk is properly torn down */
1532 if (priv->board->exit)
1533 priv->board->exit(pcidev);
1534 }
1535
exar_suspend(struct device * dev)1536 static int exar_suspend(struct device *dev)
1537 {
1538 struct exar8250 *priv = dev_get_drvdata(dev);
1539 unsigned int i;
1540
1541 for (i = 0; i < priv->nr; i++)
1542 if (priv->line[i] >= 0)
1543 serial8250_suspend_port(priv->line[i]);
1544
1545 return 0;
1546 }
1547
exar_resume(struct device * dev)1548 static int exar_resume(struct device *dev)
1549 {
1550 struct exar8250 *priv = dev_get_drvdata(dev);
1551 unsigned int i;
1552
1553 exar_misc_clear(priv);
1554
1555 for (i = 0; i < priv->nr; i++)
1556 if (priv->line[i] >= 0)
1557 serial8250_resume_port(priv->line[i]);
1558
1559 return 0;
1560 }
1561
1562 static DEFINE_SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
1563
1564 static const struct exar8250_board pbn_fastcom335_2 = {
1565 .num_ports = 2,
1566 .setup = pci_fastcom335_setup,
1567 };
1568
1569 static const struct exar8250_board pbn_fastcom335_4 = {
1570 .num_ports = 4,
1571 .setup = pci_fastcom335_setup,
1572 };
1573
1574 static const struct exar8250_board pbn_fastcom335_8 = {
1575 .num_ports = 8,
1576 .setup = pci_fastcom335_setup,
1577 };
1578
1579 static const struct exar8250_board pbn_cti_xr17c15x = {
1580 .setup = cti_port_setup_xr17c15x,
1581 };
1582
1583 static const struct exar8250_board pbn_cti_xr17v25x = {
1584 .setup = cti_port_setup_xr17v25x,
1585 };
1586
1587 static const struct exar8250_board pbn_cti_xr17v35x = {
1588 .setup = cti_port_setup_xr17v35x,
1589 };
1590
1591 static const struct exar8250_board pbn_cti_fpga = {
1592 .setup = cti_port_setup_fpga,
1593 };
1594
1595 static const struct exar8250_board pbn_exar_ibm_saturn = {
1596 .num_ports = 1,
1597 .setup = pci_xr17c154_setup,
1598 };
1599
1600 static const struct exar8250_board pbn_exar_XR17C15x = {
1601 .setup = pci_xr17c154_setup,
1602 };
1603
1604 static const struct exar8250_board pbn_exar_XR17V35x = {
1605 .setup = pci_xr17v35x_setup,
1606 .exit = pci_xr17v35x_exit,
1607 };
1608
1609 static const struct exar8250_board pbn_fastcom35x_2 = {
1610 .num_ports = 2,
1611 .setup = pci_xr17v35x_setup,
1612 .exit = pci_xr17v35x_exit,
1613 };
1614
1615 static const struct exar8250_board pbn_fastcom35x_4 = {
1616 .num_ports = 4,
1617 .setup = pci_xr17v35x_setup,
1618 .exit = pci_xr17v35x_exit,
1619 };
1620
1621 static const struct exar8250_board pbn_fastcom35x_8 = {
1622 .num_ports = 8,
1623 .setup = pci_xr17v35x_setup,
1624 .exit = pci_xr17v35x_exit,
1625 };
1626
1627 static const struct exar8250_board pbn_adv_XR17V352 = {
1628 .num_ports = 2,
1629 .setup = pci_xr17v35x_setup,
1630 .exit = pci_xr17v35x_exit,
1631 };
1632
1633 static const struct exar8250_board pbn_exar_XR17V4358 = {
1634 .num_ports = 12,
1635 .setup = pci_xr17v35x_setup,
1636 .exit = pci_xr17v35x_exit,
1637 };
1638
1639 static const struct exar8250_board pbn_exar_XR17V8358 = {
1640 .num_ports = 16,
1641 .setup = pci_xr17v35x_setup,
1642 .exit = pci_xr17v35x_exit,
1643 };
1644
1645 #define CTI_EXAR_DEVICE(devid, bd) { \
1646 PCI_DEVICE_SUB( \
1647 PCI_VENDOR_ID_EXAR, \
1648 PCI_DEVICE_ID_EXAR_##devid, \
1649 PCI_SUBVENDOR_ID_CONNECT_TECH, \
1650 PCI_ANY_ID), 0, 0, \
1651 (kernel_ulong_t)&bd \
1652 }
1653
1654 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
1655
1656 #define IBM_DEVICE(devid, sdevid, bd) { \
1657 PCI_DEVICE_SUB( \
1658 PCI_VENDOR_ID_EXAR, \
1659 PCI_DEVICE_ID_EXAR_##devid, \
1660 PCI_SUBVENDOR_ID_IBM, \
1661 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
1662 (kernel_ulong_t)&bd \
1663 }
1664
1665 #define USR_DEVICE(devid, sdevid, bd) { \
1666 PCI_DEVICE_SUB( \
1667 PCI_VENDOR_ID_USR, \
1668 PCI_DEVICE_ID_EXAR_##devid, \
1669 PCI_VENDOR_ID_EXAR, \
1670 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
1671 (kernel_ulong_t)&bd \
1672 }
1673
1674 static const struct pci_device_id exar_pci_tbl[] = {
1675 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
1676 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
1677 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
1678 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
1679 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
1680 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
1681 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
1682
1683 /* Connect Tech cards with Exar vendor/device PCI IDs */
1684 CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x),
1685 CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x),
1686 CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x),
1687
1688 CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x),
1689 CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x),
1690 CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x),
1691
1692 CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x),
1693 CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x),
1694 CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x),
1695
1696 /* Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA based) */
1697 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG00X, pbn_cti_fpga),
1698 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG01X, pbn_cti_fpga),
1699 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_16, pbn_cti_fpga),
1700
1701 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
1702
1703 /* USRobotics USR298x-OEM PCI Modems */
1704 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
1705 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
1706
1707 /* ADVANTECH devices */
1708 EXAR_DEVICE(ADVANTECH, XR17V352, pbn_adv_XR17V352),
1709
1710 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
1711 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
1712 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
1713 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
1714
1715 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
1716 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
1717 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
1718 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
1719 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
1720 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
1721 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
1722 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
1723 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
1724
1725 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
1726 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
1727 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
1728 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
1729 { 0, }
1730 };
1731 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
1732
1733 static struct pci_driver exar_pci_driver = {
1734 .name = "exar_serial",
1735 .probe = exar_pci_probe,
1736 .remove = exar_pci_remove,
1737 .driver = {
1738 .pm = pm_sleep_ptr(&exar_pci_pm),
1739 },
1740 .id_table = exar_pci_tbl,
1741 };
1742 module_pci_driver(exar_pci_driver);
1743
1744 MODULE_IMPORT_NS("SERIAL_8250_PCI");
1745 MODULE_LICENSE("GPL");
1746 MODULE_DESCRIPTION("Exar Serial Driver");
1747 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
1748