1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/dmi.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/math.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/property.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_reg.h>
28
29 #include <asm/byteorder.h>
30
31 #include "8250.h"
32 #include "8250_pcilib.h"
33
34 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
35 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
36 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
37 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
38 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
39 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
40 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
41
42 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
43 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
44 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
45 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
46 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
47 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
48 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
49
50 #define PCI_VENDOR_ID_CONNECT_TECH 0x12c4
51 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340
52 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341
53 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342
54 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350
55 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351
56 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352
57 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353
58 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354
59 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355
60 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360
61 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361
62 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362
63 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370
64 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371
65 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372
66 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373
67 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374
68 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375
69 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376
70 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380
71 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381
72 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382
73 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392
74 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0
75 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1
76 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2
77 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3
78 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602
79 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000
80 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002
81 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004
82 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008
83 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C
84 #define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010
85 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c
86 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d
87 #define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110
88
89 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
90 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
91 #define PCI_DEVICE_ID_EXAR_XR17V252 0x0252
92 #define PCI_DEVICE_ID_EXAR_XR17V254 0x0254
93 #define PCI_DEVICE_ID_EXAR_XR17V258 0x0258
94
95 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
96 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
97
98 #define UART_EXAR_INT0 0x80
99 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
100 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
101 #define UART_EXAR_DVID 0x8d /* Device identification */
102
103 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
104 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
105 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
106 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
107 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
108 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
109 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
110
111 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
112 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
113
114 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
115 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
116 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
117 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
118 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
119 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
120 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
121 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
122 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
123 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
124 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
125 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
126
127 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
128
129 #define UART_EXAR_DLD 0x02 /* Divisor Fractional */
130 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
131
132 /* EEPROM registers */
133 #define UART_EXAR_REGB 0x8e
134 #define UART_EXAR_REGB_EECK BIT(4)
135 #define UART_EXAR_REGB_EECS BIT(5)
136 #define UART_EXAR_REGB_EEDI BIT(6)
137 #define UART_EXAR_REGB_EEDO BIT(7)
138 #define UART_EXAR_REGB_EE_ADDR_SIZE 6
139 #define UART_EXAR_REGB_EE_DATA_SIZE 16
140
141 #define UART_EXAR_XR17C15X_PORT_OFFSET 0x200
142 #define UART_EXAR_XR17V25X_PORT_OFFSET 0x200
143 #define UART_EXAR_XR17V35X_PORT_OFFSET 0x400
144
145 /*
146 * IOT2040 MPIO wiring semantics:
147 *
148 * MPIO Port Function
149 * ---- ---- --------
150 * 0 2 Mode bit 0
151 * 1 2 Mode bit 1
152 * 2 2 Terminate bus
153 * 3 - <reserved>
154 * 4 3 Mode bit 0
155 * 5 3 Mode bit 1
156 * 6 3 Terminate bus
157 * 7 - <reserved>
158 * 8 2 Enable
159 * 9 3 Enable
160 * 10 - Red LED
161 * 11..15 - <unused>
162 */
163
164 /* IOT2040 MPIOs 0..7 */
165 #define IOT2040_UART_MODE_RS232 0x01
166 #define IOT2040_UART_MODE_RS485 0x02
167 #define IOT2040_UART_MODE_RS422 0x03
168 #define IOT2040_UART_TERMINATE_BUS 0x04
169
170 #define IOT2040_UART1_MASK 0x0f
171 #define IOT2040_UART2_SHIFT 4
172
173 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
174 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
175
176 /* IOT2040 MPIOs 8..15 */
177 #define IOT2040_UARTS_ENABLE 0x03
178 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
179
180 /* CTI EEPROM offsets */
181 #define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words */
182 #define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words */
183 #define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words */
184 #define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words */
185 #define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word */
186 #define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word */
187 #define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word */
188 #define CTI_EE_OFF_XR17V35X_BRD_FLAGS 0x13 /* 1 word */
189 #define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word */
190
191 #define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0)
192 #define CTI_EE_MASK_OSC_FREQ_LOWER GENMASK(15, 0)
193 #define CTI_EE_MASK_OSC_FREQ_UPPER GENMASK(31, 16)
194
195 #define CTI_FPGA_RS485_IO_REG 0x2008
196 #define CTI_FPGA_CFG_INT_EN_REG 0x48
197 #define CTI_FPGA_CFG_INT_EN_EXT_BIT BIT(15) /* External int enable bit */
198
199 #define CTI_DEFAULT_PCI_OSC_FREQ 29491200
200 #define CTI_DEFAULT_PCIE_OSC_FREQ 125000000
201 #define CTI_DEFAULT_FPGA_OSC_FREQ 33333333
202
203 /*
204 * CTI Serial port line types. These match the values stored in the first
205 * nibble of the CTI EEPROM port_flags word.
206 */
207 enum cti_port_type {
208 CTI_PORT_TYPE_NONE = 0,
209 CTI_PORT_TYPE_RS232, // RS232 ONLY
210 CTI_PORT_TYPE_RS422_485, // RS422/RS485 ONLY
211 CTI_PORT_TYPE_RS232_422_485_HW, // RS232/422/485 HW ONLY Switchable
212 CTI_PORT_TYPE_RS232_422_485_SW, // RS232/422/485 SW ONLY Switchable
213 CTI_PORT_TYPE_RS232_422_485_4B, // RS232/422/485 HW/SW (4bit ex. BCG004)
214 CTI_PORT_TYPE_RS232_422_485_2B, // RS232/422/485 HW/SW (2bit ex. BBG008)
215 CTI_PORT_TYPE_MAX,
216 };
217
218 #define CTI_PORT_TYPE_VALID(_port_type) \
219 (((_port_type) > CTI_PORT_TYPE_NONE) && \
220 ((_port_type) < CTI_PORT_TYPE_MAX))
221
222 #define CTI_PORT_TYPE_RS485(_port_type) \
223 (((_port_type) > CTI_PORT_TYPE_RS232) && \
224 ((_port_type) < CTI_PORT_TYPE_MAX))
225
226 struct exar8250;
227
228 struct exar8250_platform {
229 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
230 struct serial_rs485 *rs485);
231 const struct serial_rs485 *rs485_supported;
232 int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port);
233 void (*unregister_gpio)(struct uart_8250_port *port);
234 };
235
236 /**
237 * struct exar8250_board - board information
238 * @num_ports: number of serial ports
239 * @reg_shift: describes UART register mapping in PCI memory
240 * @setup: quirk run at ->probe() stage for each port
241 * @exit: quirk run at ->remove() stage
242 */
243 struct exar8250_board {
244 unsigned int num_ports;
245 unsigned int reg_shift;
246 int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev,
247 struct uart_8250_port *port, int idx);
248 void (*exit)(struct pci_dev *pcidev);
249 };
250
251 struct exar8250 {
252 unsigned int nr;
253 unsigned int osc_freq;
254 struct exar8250_board *board;
255 void __iomem *virt;
256 int line[];
257 };
258
exar_write_reg(struct exar8250 * priv,unsigned int reg,u8 value)259 static inline void exar_write_reg(struct exar8250 *priv,
260 unsigned int reg, u8 value)
261 {
262 writeb(value, priv->virt + reg);
263 }
264
exar_read_reg(struct exar8250 * priv,unsigned int reg)265 static inline u8 exar_read_reg(struct exar8250 *priv, unsigned int reg)
266 {
267 return readb(priv->virt + reg);
268 }
269
exar_ee_select(struct exar8250 * priv)270 static inline void exar_ee_select(struct exar8250 *priv)
271 {
272 // Set chip select pin high to enable EEPROM reads/writes
273 exar_write_reg(priv, UART_EXAR_REGB, UART_EXAR_REGB_EECS);
274 // Min ~500ns delay needed between CS assert and EEPROM access
275 udelay(1);
276 }
277
exar_ee_deselect(struct exar8250 * priv)278 static inline void exar_ee_deselect(struct exar8250 *priv)
279 {
280 exar_write_reg(priv, UART_EXAR_REGB, 0x00);
281 }
282
exar_ee_write_bit(struct exar8250 * priv,u8 bit)283 static inline void exar_ee_write_bit(struct exar8250 *priv, u8 bit)
284 {
285 u8 value = UART_EXAR_REGB_EECS;
286
287 if (bit)
288 value |= UART_EXAR_REGB_EEDI;
289
290 // Clock out the bit on the EEPROM interface
291 exar_write_reg(priv, UART_EXAR_REGB, value);
292 // 2us delay = ~500khz clock speed
293 udelay(2);
294
295 value |= UART_EXAR_REGB_EECK;
296
297 exar_write_reg(priv, UART_EXAR_REGB, value);
298 udelay(2);
299 }
300
exar_ee_read_bit(struct exar8250 * priv)301 static inline u8 exar_ee_read_bit(struct exar8250 *priv)
302 {
303 u8 regb;
304 u8 value = UART_EXAR_REGB_EECS;
305
306 // Clock in the bit on the EEPROM interface
307 exar_write_reg(priv, UART_EXAR_REGB, value);
308 // 2us delay = ~500khz clock speed
309 udelay(2);
310
311 value |= UART_EXAR_REGB_EECK;
312
313 exar_write_reg(priv, UART_EXAR_REGB, value);
314 udelay(2);
315
316 regb = exar_read_reg(priv, UART_EXAR_REGB);
317
318 return (regb & UART_EXAR_REGB_EEDO ? 1 : 0);
319 }
320
321 /**
322 * exar_ee_read() - Read a word from the EEPROM
323 * @priv: Device's private structure
324 * @ee_addr: Offset of EEPROM to read word from
325 *
326 * Read a single 16bit word from an Exar UART's EEPROM.
327 * The type of the EEPROM is AT93C46D.
328 *
329 * Return: EEPROM word
330 */
exar_ee_read(struct exar8250 * priv,u8 ee_addr)331 static u16 exar_ee_read(struct exar8250 *priv, u8 ee_addr)
332 {
333 int i;
334 u16 data = 0;
335
336 exar_ee_select(priv);
337
338 // Send read command (opcode 110)
339 exar_ee_write_bit(priv, 1);
340 exar_ee_write_bit(priv, 1);
341 exar_ee_write_bit(priv, 0);
342
343 // Send address to read from
344 for (i = UART_EXAR_REGB_EE_ADDR_SIZE - 1; i >= 0; i--)
345 exar_ee_write_bit(priv, ee_addr & BIT(i));
346
347 // Read data 1 bit at a time starting with a dummy bit
348 for (i = UART_EXAR_REGB_EE_DATA_SIZE; i >= 0; i--) {
349 if (exar_ee_read_bit(priv))
350 data |= BIT(i);
351 }
352
353 exar_ee_deselect(priv);
354
355 return data;
356 }
357
358 /**
359 * exar_mpio_config_output() - Configure an Exar MPIO as an output
360 * @priv: Device's private structure
361 * @mpio_num: MPIO number/offset to configure
362 *
363 * Configure a single MPIO as an output and disable tristate. It is reccomended
364 * to set the level with exar_mpio_set_high()/exar_mpio_set_low() prior to
365 * calling this function to ensure default MPIO pin state.
366 *
367 * Return: 0 on success, negative error code on failure
368 */
exar_mpio_config_output(struct exar8250 * priv,unsigned int mpio_num)369 static int exar_mpio_config_output(struct exar8250 *priv,
370 unsigned int mpio_num)
371 {
372 unsigned int mpio_offset;
373 u8 sel_reg; // MPIO Select register (input/output)
374 u8 tri_reg; // MPIO Tristate register
375 u8 value;
376
377 if (mpio_num < 8) {
378 sel_reg = UART_EXAR_MPIOSEL_7_0;
379 tri_reg = UART_EXAR_MPIO3T_7_0;
380 mpio_offset = mpio_num;
381 } else if (mpio_num >= 8 && mpio_num < 16) {
382 sel_reg = UART_EXAR_MPIOSEL_15_8;
383 tri_reg = UART_EXAR_MPIO3T_15_8;
384 mpio_offset = mpio_num - 8;
385 } else {
386 return -EINVAL;
387 }
388
389 // Disable MPIO pin tri-state
390 value = exar_read_reg(priv, tri_reg);
391 value &= ~BIT(mpio_offset);
392 exar_write_reg(priv, tri_reg, value);
393
394 value = exar_read_reg(priv, sel_reg);
395 value &= ~BIT(mpio_offset);
396 exar_write_reg(priv, sel_reg, value);
397
398 return 0;
399 }
400
401 /**
402 * _exar_mpio_set() - Set an Exar MPIO output high or low
403 * @priv: Device's private structure
404 * @mpio_num: MPIO number/offset to set
405 * @high: Set MPIO high if true, low if false
406 *
407 * Set a single MPIO high or low. exar_mpio_config_output() must also be called
408 * to configure the pin as an output.
409 *
410 * Return: 0 on success, negative error code on failure
411 */
_exar_mpio_set(struct exar8250 * priv,unsigned int mpio_num,bool high)412 static int _exar_mpio_set(struct exar8250 *priv,
413 unsigned int mpio_num, bool high)
414 {
415 unsigned int mpio_offset;
416 u8 lvl_reg;
417 u8 value;
418
419 if (mpio_num < 8) {
420 lvl_reg = UART_EXAR_MPIOLVL_7_0;
421 mpio_offset = mpio_num;
422 } else if (mpio_num >= 8 && mpio_num < 16) {
423 lvl_reg = UART_EXAR_MPIOLVL_15_8;
424 mpio_offset = mpio_num - 8;
425 } else {
426 return -EINVAL;
427 }
428
429 value = exar_read_reg(priv, lvl_reg);
430 if (high)
431 value |= BIT(mpio_offset);
432 else
433 value &= ~BIT(mpio_offset);
434 exar_write_reg(priv, lvl_reg, value);
435
436 return 0;
437 }
438
exar_mpio_set_low(struct exar8250 * priv,unsigned int mpio_num)439 static int exar_mpio_set_low(struct exar8250 *priv, unsigned int mpio_num)
440 {
441 return _exar_mpio_set(priv, mpio_num, false);
442 }
443
exar_mpio_set_high(struct exar8250 * priv,unsigned int mpio_num)444 static int exar_mpio_set_high(struct exar8250 *priv, unsigned int mpio_num)
445 {
446 return _exar_mpio_set(priv, mpio_num, true);
447 }
448
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)449 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
450 struct serial_rs485 *rs485)
451 {
452 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
453 u8 __iomem *p = port->membase;
454 u8 value;
455
456 value = readb(p + UART_EXAR_FCTR);
457 if (is_rs485)
458 value |= UART_FCTR_EXAR_485;
459 else
460 value &= ~UART_FCTR_EXAR_485;
461
462 writeb(value, p + UART_EXAR_FCTR);
463
464 if (is_rs485)
465 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
466
467 return 0;
468 }
469
470 static const struct serial_rs485 generic_rs485_supported = {
471 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
472 };
473
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)474 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
475 {
476 /*
477 * Exar UARTs have a SLEEP register that enables or disables each UART
478 * to enter sleep mode separately. On the XR17V35x the register
479 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
480 * the UART channel may only write to the corresponding bit.
481 */
482 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
483 }
484
485 /*
486 * XR17V35x UARTs have an extra fractional divisor register (DLD)
487 * Calculate divisor with extra 4-bit fractional portion
488 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)489 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
490 unsigned int *frac)
491 {
492 unsigned int quot_16;
493
494 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
495 *frac = quot_16 & 0x0f;
496
497 return quot_16 >> 4;
498 }
499
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)500 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
501 unsigned int quot, unsigned int quot_frac)
502 {
503 serial8250_do_set_divisor(p, baud, quot);
504
505 /* Preserve bits not related to baudrate; DLD[7:4]. */
506 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
507 serial_port_out(p, 0x2, quot_frac);
508 }
509
xr17v35x_startup(struct uart_port * port)510 static int xr17v35x_startup(struct uart_port *port)
511 {
512 /*
513 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
514 * MCR [7:5] and MSR [7:0]
515 */
516 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
517
518 /*
519 * Make sure all interrups are masked until initialization is
520 * complete and the FIFOs are cleared
521 *
522 * Synchronize UART_IER access against the console.
523 */
524 uart_port_lock_irq(port);
525 serial_port_out(port, UART_IER, 0);
526 uart_port_unlock_irq(port);
527
528 return serial8250_do_startup(port);
529 }
530
exar_shutdown(struct uart_port * port)531 static void exar_shutdown(struct uart_port *port)
532 {
533 bool tx_complete = false;
534 struct uart_8250_port *up = up_to_u8250p(port);
535 struct tty_port *tport = &port->state->port;
536 int i = 0;
537 u16 lsr;
538
539 do {
540 lsr = serial_in(up, UART_LSR);
541 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
542 tx_complete = true;
543 else
544 tx_complete = false;
545 usleep_range(1000, 1100);
546 } while (!kfifo_is_empty(&tport->xmit_fifo) &&
547 !tx_complete && i++ < 1000);
548
549 serial8250_do_shutdown(port);
550 }
551
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)552 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
553 int idx, unsigned int offset,
554 struct uart_8250_port *port)
555 {
556 const struct exar8250_board *board = priv->board;
557 unsigned char status;
558 int err;
559
560 err = serial8250_pci_setup_port(pcidev, port, 0, offset, board->reg_shift);
561 if (err)
562 return err;
563
564 /*
565 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
566 * with when DLAB is set which will cause the device to incorrectly match
567 * and assign port type to PORT_16650. The EFR for this UART is found
568 * at offset 0x09. Instead check the Deice ID (DVID) register
569 * for a 2, 4 or 8 port UART.
570 */
571 status = readb(port->port.membase + UART_EXAR_DVID);
572 if (status == 0x82 || status == 0x84 || status == 0x88) {
573 port->port.type = PORT_XR17V35X;
574
575 port->port.get_divisor = xr17v35x_get_divisor;
576 port->port.set_divisor = xr17v35x_set_divisor;
577
578 port->port.startup = xr17v35x_startup;
579 } else {
580 port->port.type = PORT_XR17D15X;
581 }
582
583 port->port.pm = exar_pm;
584 port->port.shutdown = exar_shutdown;
585
586 return 0;
587 }
588
589 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)590 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
591 struct uart_8250_port *port, int idx)
592 {
593 unsigned int offset = idx * 0x200;
594 unsigned int baud = 1843200;
595 u8 __iomem *p;
596 int err;
597
598 port->port.uartclk = baud * 16;
599
600 err = default_setup(priv, pcidev, idx, offset, port);
601 if (err)
602 return err;
603
604 p = port->port.membase;
605
606 writeb(0x00, p + UART_EXAR_8XMODE);
607 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
608 writeb(32, p + UART_EXAR_TXTRG);
609 writeb(32, p + UART_EXAR_RXTRG);
610
611 /* Skip the initial (per device) setup */
612 if (idx)
613 return 0;
614
615 /*
616 * Setup Multipurpose Input/Output pins.
617 */
618 switch (pcidev->device) {
619 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
620 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
621 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
622 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
623 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
624 break;
625 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
626 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
627 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
628 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
629 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
630 break;
631 default:
632 break;
633 }
634 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
635 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
636 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
637
638 return 0;
639 }
640
641 /**
642 * cti_tristate_disable() - Disable RS485 transciever tristate
643 * @priv: Device's private structure
644 * @port_num: Port number to set tristate off
645 *
646 * Most RS485 capable cards have a power on tristate jumper/switch that ensures
647 * the RS422/RS485 transceiver does not drive a multi-drop RS485 bus when it is
648 * not the master. When this jumper is installed the user must set the RS485
649 * mode to Full or Half duplex to disable tristate prior to using the port.
650 *
651 * Some Exar UARTs have an auto-tristate feature while others require setting
652 * an MPIO to disable the tristate.
653 *
654 * Return: 0 on success, negative error code on failure
655 */
cti_tristate_disable(struct exar8250 * priv,unsigned int port_num)656 static int cti_tristate_disable(struct exar8250 *priv, unsigned int port_num)
657 {
658 int ret;
659
660 ret = exar_mpio_set_high(priv, port_num);
661 if (ret)
662 return ret;
663
664 return exar_mpio_config_output(priv, port_num);
665 }
666
667 /**
668 * cti_plx_int_enable() - Enable UART interrupts to PLX bridge
669 * @priv: Device's private structure
670 *
671 * Some older CTI cards require MPIO_0 to be set low to enable the
672 * interrupts from the UART to the PLX PCI->PCIe bridge.
673 *
674 * Return: 0 on success, negative error code on failure
675 */
cti_plx_int_enable(struct exar8250 * priv)676 static int cti_plx_int_enable(struct exar8250 *priv)
677 {
678 int ret;
679
680 ret = exar_mpio_set_low(priv, 0);
681 if (ret)
682 return ret;
683
684 return exar_mpio_config_output(priv, 0);
685 }
686
687 /**
688 * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM
689 * @priv: Device's private structure
690 * @eeprom_offset: Offset where the oscillator frequency is stored
691 *
692 * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequency
693 * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe clock.
694 *
695 * Return: frequency on success, negative error code on failure
696 */
cti_read_osc_freq(struct exar8250 * priv,u8 eeprom_offset)697 static int cti_read_osc_freq(struct exar8250 *priv, u8 eeprom_offset)
698 {
699 u16 lower_word;
700 u16 upper_word;
701
702 lower_word = exar_ee_read(priv, eeprom_offset);
703 // Check if EEPROM word was blank
704 if (lower_word == 0xFFFF)
705 return -EIO;
706
707 upper_word = exar_ee_read(priv, (eeprom_offset + 1));
708 if (upper_word == 0xFFFF)
709 return -EIO;
710
711 return FIELD_PREP(CTI_EE_MASK_OSC_FREQ_LOWER, lower_word) |
712 FIELD_PREP(CTI_EE_MASK_OSC_FREQ_UPPER, upper_word);
713 }
714
715 /**
716 * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v25x
717 * @priv: Device's private structure
718 * @pcidev: Pointer to the PCI device for this port
719 * @port_num: Port to get type of
720 *
721 * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs.
722 *
723 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
724 */
cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)725 static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8250 *priv,
726 struct pci_dev *pcidev,
727 unsigned int port_num)
728 {
729 switch (pcidev->subsystem_device) {
730 // RS232 only cards
731 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232:
732 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232:
733 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232:
734 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232:
735 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS:
736 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232:
737 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS:
738 return CTI_PORT_TYPE_RS232;
739 // 1x RS232, 1x RS422/RS485
740 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1:
741 return (port_num == 0) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
742 // 2x RS232, 2x RS422/RS485
743 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2:
744 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
745 // 4x RS232, 4x RS422/RS485
746 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4:
747 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
748 return (port_num < 4) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
749 // RS232/RS422/RS485 HW (jumper) selectable
750 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2:
751 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4:
752 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8:
753 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO:
754 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A:
755 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B:
756 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
757 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
758 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
759 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
760 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
761 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
762 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
763 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
764 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
765 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
766 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
767 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
768 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
769 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
770 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
771 return CTI_PORT_TYPE_RS232_422_485_HW;
772 // RS422/RS485 HW (jumper) selectable
773 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485:
774 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485:
775 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485:
776 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
777 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
778 return CTI_PORT_TYPE_RS422_485;
779 // 6x RS232, 2x RS422/RS485
780 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
781 return (port_num < 6) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
782 // 2x RS232, 6x RS422/RS485
783 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
784 return (port_num < 2) ? CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485;
785 default:
786 dev_err(&pcidev->dev, "unknown/unsupported device\n");
787 return CTI_PORT_TYPE_NONE;
788 }
789 }
790
791 /**
792 * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card
793 * @priv: Device's private structure
794 * @pcidev: Pointer to the PCI device for this port
795 * @port_num: Port to get type of
796 *
797 * FPGA based cards port types are based on PCI IDs.
798 *
799 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
800 */
cti_get_port_type_fpga(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)801 static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv,
802 struct pci_dev *pcidev,
803 unsigned int port_num)
804 {
805 switch (pcidev->device) {
806 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
807 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
808 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
809 return CTI_PORT_TYPE_RS232_422_485_HW;
810 default:
811 dev_err(&pcidev->dev, "unknown/unsupported device\n");
812 return CTI_PORT_TYPE_NONE;
813 }
814 }
815
816 /**
817 * cti_get_port_type_xr17v35x() - Read port type from the EEPROM
818 * @priv: Device's private structure
819 * @pcidev: Pointer to the PCI device for this port
820 * @port_num: port offset
821 *
822 * CTI XR17V35X based cards have the port types stored in the EEPROM.
823 * This function reads the port type for a single port.
824 *
825 * Return: port type on success, CTI_PORT_TYPE_NONE on failure
826 */
cti_get_port_type_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev,unsigned int port_num)827 static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv,
828 struct pci_dev *pcidev,
829 unsigned int port_num)
830 {
831 enum cti_port_type port_type;
832 u16 port_flags;
833 u8 offset;
834
835 offset = CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num;
836 port_flags = exar_ee_read(priv, offset);
837
838 port_type = FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags);
839 if (CTI_PORT_TYPE_VALID(port_type))
840 return port_type;
841
842 /*
843 * If the port type is missing the card assume it is a
844 * RS232/RS422/RS485 card to be safe.
845 *
846 * There is one known board (BEG013) that only has 3 of 4 port types
847 * written to the EEPROM so this acts as a work around.
848 */
849 dev_warn(&pcidev->dev, "failed to get port %d type from EEPROM\n", port_num);
850
851 return CTI_PORT_TYPE_RS232_422_485_HW;
852 }
853
cti_rs485_config_mpio_tristate(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)854 static int cti_rs485_config_mpio_tristate(struct uart_port *port,
855 struct ktermios *termios,
856 struct serial_rs485 *rs485)
857 {
858 struct exar8250 *priv = (struct exar8250 *)port->private_data;
859 int ret;
860
861 ret = generic_rs485_config(port, termios, rs485);
862 if (ret)
863 return ret;
864
865 // Disable power-on RS485 tri-state via MPIO
866 return cti_tristate_disable(priv, port->port_id);
867 }
868
cti_board_init_osc_freq(struct exar8250 * priv,struct pci_dev * pcidev,u8 eeprom_offset)869 static void cti_board_init_osc_freq(struct exar8250 *priv, struct pci_dev *pcidev, u8 eeprom_offset)
870 {
871 int osc_freq;
872
873 osc_freq = cti_read_osc_freq(priv, eeprom_offset);
874 if (osc_freq <= 0) {
875 dev_warn(&pcidev->dev, "failed to read OSC freq from EEPROM, using default\n");
876 osc_freq = CTI_DEFAULT_PCI_OSC_FREQ;
877 }
878
879 priv->osc_freq = osc_freq;
880 }
881
cti_port_setup_common(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)882 static int cti_port_setup_common(struct exar8250 *priv,
883 struct pci_dev *pcidev,
884 int idx, unsigned int offset,
885 struct uart_8250_port *port)
886 {
887 int ret;
888
889 port->port.port_id = idx;
890 port->port.uartclk = priv->osc_freq;
891
892 ret = serial8250_pci_setup_port(pcidev, port, 0, offset, 0);
893 if (ret)
894 return ret;
895
896 port->port.private_data = (void *)priv;
897 port->port.pm = exar_pm;
898 port->port.shutdown = exar_shutdown;
899
900 return 0;
901 }
902
cti_board_init_fpga(struct exar8250 * priv,struct pci_dev * pcidev)903 static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
904 {
905 int ret;
906 u16 cfg_val;
907
908 // FPGA OSC is fixed to the 33MHz PCI clock
909 priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
910
911 // Enable external interrupts in special cfg space register
912 ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
913 if (ret)
914 return pcibios_err_to_errno(ret);
915
916 cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
917 ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
918 if (ret)
919 return pcibios_err_to_errno(ret);
920
921 // RS485 gate needs to be enabled; otherwise RTS/CTS will not work
922 exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
923
924 return 0;
925 }
926
cti_port_setup_fpga(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)927 static int cti_port_setup_fpga(struct exar8250 *priv,
928 struct pci_dev *pcidev,
929 struct uart_8250_port *port,
930 int idx)
931 {
932 enum cti_port_type port_type;
933 unsigned int offset;
934 int ret;
935
936 if (idx == 0) {
937 ret = cti_board_init_fpga(priv, pcidev);
938 if (ret)
939 return ret;
940 }
941
942 port_type = cti_get_port_type_fpga(priv, pcidev, idx);
943
944 // FPGA shares port offsets with XR17C15X
945 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
946 port->port.type = PORT_XR17D15X;
947
948 port->port.get_divisor = xr17v35x_get_divisor;
949 port->port.set_divisor = xr17v35x_set_divisor;
950 port->port.startup = xr17v35x_startup;
951
952 if (CTI_PORT_TYPE_RS485(port_type)) {
953 port->port.rs485_config = generic_rs485_config;
954 port->port.rs485_supported = generic_rs485_supported;
955 }
956
957 return cti_port_setup_common(priv, pcidev, idx, offset, port);
958 }
959
cti_board_init_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev)960 static void cti_board_init_xr17v35x(struct exar8250 *priv, struct pci_dev *pcidev)
961 {
962 // XR17V35X uses the PCIe clock rather than an oscillator
963 priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
964 }
965
cti_port_setup_xr17v35x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)966 static int cti_port_setup_xr17v35x(struct exar8250 *priv,
967 struct pci_dev *pcidev,
968 struct uart_8250_port *port,
969 int idx)
970 {
971 enum cti_port_type port_type;
972 unsigned int offset;
973 int ret;
974
975 if (idx == 0)
976 cti_board_init_xr17v35x(priv, pcidev);
977
978 port_type = cti_get_port_type_xr17v35x(priv, pcidev, idx);
979
980 offset = idx * UART_EXAR_XR17V35X_PORT_OFFSET;
981 port->port.type = PORT_XR17V35X;
982
983 port->port.get_divisor = xr17v35x_get_divisor;
984 port->port.set_divisor = xr17v35x_set_divisor;
985 port->port.startup = xr17v35x_startup;
986
987 switch (port_type) {
988 case CTI_PORT_TYPE_RS422_485:
989 case CTI_PORT_TYPE_RS232_422_485_HW:
990 port->port.rs485_config = cti_rs485_config_mpio_tristate;
991 port->port.rs485_supported = generic_rs485_supported;
992 break;
993 case CTI_PORT_TYPE_RS232_422_485_SW:
994 case CTI_PORT_TYPE_RS232_422_485_4B:
995 case CTI_PORT_TYPE_RS232_422_485_2B:
996 port->port.rs485_config = generic_rs485_config;
997 port->port.rs485_supported = generic_rs485_supported;
998 break;
999 default:
1000 break;
1001 }
1002
1003 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
1004 if (ret)
1005 return ret;
1006
1007 exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00);
1008 exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
1009 exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 128);
1010 exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 128);
1011
1012 return 0;
1013 }
1014
cti_board_init_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev)1015 static void cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
1016 {
1017 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
1018
1019 /* enable interrupts on cards that need the "PLX fix" */
1020 switch (pcidev->subsystem_device) {
1021 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
1022 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
1023 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
1024 cti_plx_int_enable(priv);
1025 break;
1026 default:
1027 break;
1028 }
1029 }
1030
cti_port_setup_xr17v25x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1031 static int cti_port_setup_xr17v25x(struct exar8250 *priv,
1032 struct pci_dev *pcidev,
1033 struct uart_8250_port *port,
1034 int idx)
1035 {
1036 enum cti_port_type port_type;
1037 unsigned int offset;
1038 int ret;
1039
1040 if (idx == 0)
1041 cti_board_init_xr17v25x(priv, pcidev);
1042
1043 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
1044
1045 offset = idx * UART_EXAR_XR17V25X_PORT_OFFSET;
1046 port->port.type = PORT_XR17D15X;
1047
1048 // XR17V25X supports fractional baudrates
1049 port->port.get_divisor = xr17v35x_get_divisor;
1050 port->port.set_divisor = xr17v35x_set_divisor;
1051 port->port.startup = xr17v35x_startup;
1052
1053 if (CTI_PORT_TYPE_RS485(port_type)) {
1054 switch (pcidev->subsystem_device) {
1055 // These cards support power on 485 tri-state via MPIO
1056 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
1057 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1058 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1059 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1060 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1061 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1062 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1063 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1064 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1065 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1066 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1067 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1068 break;
1069 // Otherwise auto or no power on 485 tri-state support
1070 default:
1071 port->port.rs485_config = generic_rs485_config;
1072 break;
1073 }
1074
1075 port->port.rs485_supported = generic_rs485_supported;
1076 }
1077
1078 ret = cti_port_setup_common(priv, pcidev, idx, offset, port);
1079 if (ret)
1080 return ret;
1081
1082 exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00);
1083 exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD);
1084 exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 32);
1085 exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 32);
1086
1087 return 0;
1088 }
1089
cti_board_init_xr17c15x(struct exar8250 * priv,struct pci_dev * pcidev)1090 static void cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1091 {
1092 cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1093
1094 /* enable interrupts on cards that need the "PLX fix" */
1095 switch (pcidev->subsystem_device) {
1096 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1097 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1098 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1099 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1100 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1101 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1102 cti_plx_int_enable(priv);
1103 break;
1104 default:
1105 break;
1106 }
1107 }
1108
cti_port_setup_xr17c15x(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1109 static int cti_port_setup_xr17c15x(struct exar8250 *priv,
1110 struct pci_dev *pcidev,
1111 struct uart_8250_port *port,
1112 int idx)
1113 {
1114 enum cti_port_type port_type;
1115 unsigned int offset;
1116
1117 if (idx == 0)
1118 cti_board_init_xr17c15x(priv, pcidev);
1119
1120 port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
1121
1122 offset = idx * UART_EXAR_XR17C15X_PORT_OFFSET;
1123 port->port.type = PORT_XR17D15X;
1124
1125 if (CTI_PORT_TYPE_RS485(port_type)) {
1126 switch (pcidev->subsystem_device) {
1127 // These cards support power on 485 tri-state via MPIO
1128 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP:
1129 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485:
1130 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP:
1131 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP:
1132 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP:
1133 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT:
1134 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT:
1135 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO:
1136 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO:
1137 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP:
1138 case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485:
1139 port->port.rs485_config = cti_rs485_config_mpio_tristate;
1140 break;
1141 // Otherwise auto or no power on 485 tri-state support
1142 default:
1143 port->port.rs485_config = generic_rs485_config;
1144 break;
1145 }
1146
1147 port->port.rs485_supported = generic_rs485_supported;
1148 }
1149
1150 return cti_port_setup_common(priv, pcidev, idx, offset, port);
1151 }
1152
1153 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1154 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1155 struct uart_8250_port *port, int idx)
1156 {
1157 unsigned int offset = idx * 0x200;
1158 unsigned int baud = 921600;
1159
1160 port->port.uartclk = baud * 16;
1161 return default_setup(priv, pcidev, idx, offset, port);
1162 }
1163
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)1164 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
1165 {
1166 /*
1167 * The Commtech adapters required the MPIOs to be driven low. The Exar
1168 * devices will export them as GPIOs, so we pre-configure them safely
1169 * as inputs.
1170 */
1171 u8 dir = 0x00;
1172
1173 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
1174 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
1175 // Configure GPIO as inputs for Commtech adapters
1176 dir = 0xff;
1177 } else {
1178 // Configure GPIO as outputs for SeaLevel adapters
1179 dir = 0x00;
1180 }
1181
1182 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1183 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1184 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1185 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1186 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
1187 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1188 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
1189 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
1190 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
1191 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
1192 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
1193 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
1194 }
1195
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)1196 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
1197 const struct software_node *node)
1198 {
1199 struct platform_device *pdev;
1200
1201 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
1202 if (!pdev)
1203 return NULL;
1204
1205 pdev->dev.parent = &pcidev->dev;
1206 device_set_node(&pdev->dev, dev_fwnode(&pcidev->dev));
1207
1208 if (device_add_software_node(&pdev->dev, node) < 0 ||
1209 platform_device_add(pdev) < 0) {
1210 platform_device_put(pdev);
1211 return NULL;
1212 }
1213
1214 return pdev;
1215 }
1216
__xr17v35x_unregister_gpio(struct platform_device * pdev)1217 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
1218 {
1219 device_remove_software_node(&pdev->dev);
1220 platform_device_unregister(pdev);
1221 }
1222
1223 static const struct property_entry exar_gpio_properties[] = {
1224 PROPERTY_ENTRY_U32("exar,first-pin", 0),
1225 PROPERTY_ENTRY_U32("ngpios", 16),
1226 { }
1227 };
1228
1229 static const struct software_node exar_gpio_node = {
1230 .properties = exar_gpio_properties,
1231 };
1232
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)1233 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
1234 {
1235 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1236 port->port.private_data =
1237 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
1238
1239 return 0;
1240 }
1241
xr17v35x_unregister_gpio(struct uart_8250_port * port)1242 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
1243 {
1244 if (!port->port.private_data)
1245 return;
1246
1247 __xr17v35x_unregister_gpio(port->port.private_data);
1248 port->port.private_data = NULL;
1249 }
1250
sealevel_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1251 static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios,
1252 struct serial_rs485 *rs485)
1253 {
1254 u8 __iomem *p = port->membase;
1255 u8 old_lcr;
1256 u8 efr;
1257 u8 dld;
1258 int ret;
1259
1260 ret = generic_rs485_config(port, termios, rs485);
1261 if (ret)
1262 return ret;
1263
1264 if (!(rs485->flags & SER_RS485_ENABLED))
1265 return 0;
1266
1267 old_lcr = readb(p + UART_LCR);
1268
1269 /* Set EFR[4]=1 to enable enhanced feature registers */
1270 efr = readb(p + UART_XR_EFR);
1271 efr |= UART_EFR_ECB;
1272 writeb(efr, p + UART_XR_EFR);
1273
1274 /* Set MCR to use DTR as Auto-RS485 Enable signal */
1275 writeb(UART_MCR_OUT1, p + UART_MCR);
1276
1277 /* Set LCR[7]=1 to enable access to DLD register */
1278 writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR);
1279
1280 /* Set DLD[7]=1 for inverted RS485 Enable logic */
1281 dld = readb(p + UART_EXAR_DLD);
1282 dld |= UART_EXAR_DLD_485_POLARITY;
1283 writeb(dld, p + UART_EXAR_DLD);
1284
1285 writeb(old_lcr, p + UART_LCR);
1286
1287 return 0;
1288 }
1289
1290 static const struct exar8250_platform exar8250_default_platform = {
1291 .register_gpio = xr17v35x_register_gpio,
1292 .unregister_gpio = xr17v35x_unregister_gpio,
1293 .rs485_config = generic_rs485_config,
1294 .rs485_supported = &generic_rs485_supported,
1295 };
1296
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1297 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
1298 struct serial_rs485 *rs485)
1299 {
1300 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
1301 u8 __iomem *p = port->membase;
1302 u8 mask = IOT2040_UART1_MASK;
1303 u8 mode, value;
1304
1305 if (is_rs485) {
1306 if (rs485->flags & SER_RS485_RX_DURING_TX)
1307 mode = IOT2040_UART_MODE_RS422;
1308 else
1309 mode = IOT2040_UART_MODE_RS485;
1310
1311 if (rs485->flags & SER_RS485_TERMINATE_BUS)
1312 mode |= IOT2040_UART_TERMINATE_BUS;
1313 } else {
1314 mode = IOT2040_UART_MODE_RS232;
1315 }
1316
1317 if (port->line == 3) {
1318 mask <<= IOT2040_UART2_SHIFT;
1319 mode <<= IOT2040_UART2_SHIFT;
1320 }
1321
1322 value = readb(p + UART_EXAR_MPIOLVL_7_0);
1323 value &= ~mask;
1324 value |= mode;
1325 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
1326
1327 return generic_rs485_config(port, termios, rs485);
1328 }
1329
1330 static const struct serial_rs485 iot2040_rs485_supported = {
1331 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
1332 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
1333 };
1334
1335 static const struct property_entry iot2040_gpio_properties[] = {
1336 PROPERTY_ENTRY_U32("exar,first-pin", 10),
1337 PROPERTY_ENTRY_U32("ngpios", 1),
1338 { }
1339 };
1340
1341 static const struct software_node iot2040_gpio_node = {
1342 .properties = iot2040_gpio_properties,
1343 };
1344
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)1345 static int iot2040_register_gpio(struct pci_dev *pcidev,
1346 struct uart_8250_port *port)
1347 {
1348 u8 __iomem *p = port->port.membase;
1349
1350 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
1351 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
1352 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
1353 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
1354
1355 port->port.private_data =
1356 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
1357
1358 return 0;
1359 }
1360
1361 static const struct exar8250_platform iot2040_platform = {
1362 .rs485_config = iot2040_rs485_config,
1363 .rs485_supported = &iot2040_rs485_supported,
1364 .register_gpio = iot2040_register_gpio,
1365 .unregister_gpio = xr17v35x_unregister_gpio,
1366 };
1367
1368 /*
1369 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
1370 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
1371 * board name after the device was found.
1372 */
1373 static const struct dmi_system_id exar_platforms[] = {
1374 {
1375 .matches = {
1376 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
1377 },
1378 .driver_data = (void *)&iot2040_platform,
1379 },
1380 {}
1381 };
1382
exar_get_platform(void)1383 static const struct exar8250_platform *exar_get_platform(void)
1384 {
1385 const struct dmi_system_id *dmi_match;
1386
1387 dmi_match = dmi_first_match(exar_platforms);
1388 if (dmi_match)
1389 return dmi_match->driver_data;
1390
1391 return &exar8250_default_platform;
1392 }
1393
1394 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)1395 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
1396 struct uart_8250_port *port, int idx)
1397 {
1398 const struct exar8250_platform *platform = exar_get_platform();
1399 unsigned int offset = idx * 0x400;
1400 unsigned int baud = 7812500;
1401 u8 __iomem *p;
1402 int ret;
1403
1404 port->port.uartclk = baud * 16;
1405 port->port.rs485_config = platform->rs485_config;
1406 port->port.rs485_supported = *(platform->rs485_supported);
1407
1408 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL)
1409 port->port.rs485_config = sealevel_rs485_config;
1410
1411 /*
1412 * Setup the UART clock for the devices on expansion slot to
1413 * half the clock speed of the main chip (which is 125MHz)
1414 */
1415 if (idx >= 8)
1416 port->port.uartclk /= 2;
1417
1418 ret = default_setup(priv, pcidev, idx, offset, port);
1419 if (ret)
1420 return ret;
1421
1422 p = port->port.membase;
1423
1424 writeb(0x00, p + UART_EXAR_8XMODE);
1425 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1426 writeb(128, p + UART_EXAR_TXTRG);
1427 writeb(128, p + UART_EXAR_RXTRG);
1428
1429 if (idx == 0) {
1430 /* Setup Multipurpose Input/Output pins. */
1431 setup_gpio(pcidev, p);
1432
1433 ret = platform->register_gpio(pcidev, port);
1434 }
1435
1436 return ret;
1437 }
1438
pci_xr17v35x_exit(struct pci_dev * pcidev)1439 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
1440 {
1441 const struct exar8250_platform *platform = exar_get_platform();
1442 struct exar8250 *priv = pci_get_drvdata(pcidev);
1443 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
1444
1445 platform->unregister_gpio(port);
1446 }
1447
exar_misc_clear(struct exar8250 * priv)1448 static inline void exar_misc_clear(struct exar8250 *priv)
1449 {
1450 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
1451 readb(priv->virt + UART_EXAR_INT0);
1452
1453 /* Clear INT0 for Expansion Interface slave ports, too */
1454 if (priv->board->num_ports > 8)
1455 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
1456 }
1457
1458 /*
1459 * These Exar UARTs have an extra interrupt indicator that could fire for a
1460 * few interrupts that are not presented/cleared through IIR. One of which is
1461 * a wakeup interrupt when coming out of sleep. These interrupts are only
1462 * cleared by reading global INT0 or INT1 registers as interrupts are
1463 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
1464 * channel's address space, but for the sake of bus efficiency we register a
1465 * dedicated handler at the PCI device level to handle them.
1466 */
exar_misc_handler(int irq,void * data)1467 static irqreturn_t exar_misc_handler(int irq, void *data)
1468 {
1469 exar_misc_clear(data);
1470
1471 return IRQ_HANDLED;
1472 }
1473
exar_get_nr_ports(struct exar8250_board * board,struct pci_dev * pcidev)1474 static unsigned int exar_get_nr_ports(struct exar8250_board *board, struct pci_dev *pcidev)
1475 {
1476 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
1477 return BIT(((pcidev->device & 0x38) >> 3) - 1);
1478
1479 // Check if board struct overrides number of ports
1480 if (board->num_ports > 0)
1481 return board->num_ports;
1482
1483 // Exar encodes # ports in last nibble of PCI Device ID ex. 0358
1484 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
1485 return pcidev->device & 0x0f;
1486
1487 // Handle CTI FPGA cards
1488 if (pcidev->vendor == PCI_VENDOR_ID_CONNECT_TECH) {
1489 switch (pcidev->device) {
1490 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X:
1491 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X:
1492 return 12;
1493 case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16:
1494 return 16;
1495 default:
1496 return 0;
1497 }
1498 }
1499
1500 return 0;
1501 }
1502
1503 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)1504 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
1505 {
1506 unsigned int nr_ports, i, bar = 0, maxnr;
1507 struct exar8250_board *board;
1508 struct uart_8250_port uart;
1509 struct exar8250 *priv;
1510 int rc;
1511
1512 board = (struct exar8250_board *)ent->driver_data;
1513 if (!board)
1514 return -EINVAL;
1515
1516 rc = pcim_enable_device(pcidev);
1517 if (rc)
1518 return rc;
1519
1520 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
1521
1522 nr_ports = exar_get_nr_ports(board, pcidev);
1523 if (nr_ports == 0)
1524 return dev_err_probe(&pcidev->dev, -ENODEV, "failed to get number of ports\n");
1525
1526 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
1527 if (!priv)
1528 return -ENOMEM;
1529
1530 priv->board = board;
1531 priv->virt = pcim_iomap(pcidev, bar, 0);
1532 if (!priv->virt)
1533 return -ENOMEM;
1534
1535 pci_set_master(pcidev);
1536
1537 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
1538 if (rc < 0)
1539 return rc;
1540
1541 memset(&uart, 0, sizeof(uart));
1542 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
1543 uart.port.irq = pci_irq_vector(pcidev, 0);
1544 uart.port.dev = &pcidev->dev;
1545
1546 /* Clear interrupts */
1547 exar_misc_clear(priv);
1548
1549 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
1550 IRQF_SHARED, "exar_uart", priv);
1551 if (rc)
1552 return rc;
1553
1554 for (i = 0; i < nr_ports && i < maxnr; i++) {
1555 rc = board->setup(priv, pcidev, &uart, i);
1556 if (rc) {
1557 dev_err_probe(&pcidev->dev, rc, "Failed to setup port %u\n", i);
1558 break;
1559 }
1560
1561 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
1562 uart.port.iobase, uart.port.irq, uart.port.iotype);
1563
1564 priv->line[i] = serial8250_register_8250_port(&uart);
1565 if (priv->line[i] < 0) {
1566 dev_err_probe(&pcidev->dev, priv->line[i],
1567 "Couldn't register serial port %lx, type %d, irq %d\n",
1568 uart.port.iobase, uart.port.iotype, uart.port.irq);
1569 break;
1570 }
1571 }
1572 priv->nr = i;
1573 pci_set_drvdata(pcidev, priv);
1574 return 0;
1575 }
1576
exar_pci_remove(struct pci_dev * pcidev)1577 static void exar_pci_remove(struct pci_dev *pcidev)
1578 {
1579 struct exar8250 *priv = pci_get_drvdata(pcidev);
1580 unsigned int i;
1581
1582 for (i = 0; i < priv->nr; i++)
1583 serial8250_unregister_port(priv->line[i]);
1584
1585 /* Ensure that every init quirk is properly torn down */
1586 if (priv->board->exit)
1587 priv->board->exit(pcidev);
1588 }
1589
exar_suspend(struct device * dev)1590 static int exar_suspend(struct device *dev)
1591 {
1592 struct exar8250 *priv = dev_get_drvdata(dev);
1593 unsigned int i;
1594
1595 for (i = 0; i < priv->nr; i++)
1596 if (priv->line[i] >= 0)
1597 serial8250_suspend_port(priv->line[i]);
1598
1599 return 0;
1600 }
1601
exar_resume(struct device * dev)1602 static int exar_resume(struct device *dev)
1603 {
1604 struct exar8250 *priv = dev_get_drvdata(dev);
1605 unsigned int i;
1606
1607 exar_misc_clear(priv);
1608
1609 for (i = 0; i < priv->nr; i++)
1610 if (priv->line[i] >= 0)
1611 serial8250_resume_port(priv->line[i]);
1612
1613 return 0;
1614 }
1615
1616 static DEFINE_SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
1617
1618 static const struct exar8250_board pbn_fastcom335_2 = {
1619 .num_ports = 2,
1620 .setup = pci_fastcom335_setup,
1621 };
1622
1623 static const struct exar8250_board pbn_fastcom335_4 = {
1624 .num_ports = 4,
1625 .setup = pci_fastcom335_setup,
1626 };
1627
1628 static const struct exar8250_board pbn_fastcom335_8 = {
1629 .num_ports = 8,
1630 .setup = pci_fastcom335_setup,
1631 };
1632
1633 static const struct exar8250_board pbn_cti_xr17c15x = {
1634 .setup = cti_port_setup_xr17c15x,
1635 };
1636
1637 static const struct exar8250_board pbn_cti_xr17v25x = {
1638 .setup = cti_port_setup_xr17v25x,
1639 };
1640
1641 static const struct exar8250_board pbn_cti_xr17v35x = {
1642 .setup = cti_port_setup_xr17v35x,
1643 };
1644
1645 static const struct exar8250_board pbn_cti_fpga = {
1646 .setup = cti_port_setup_fpga,
1647 };
1648
1649 static const struct exar8250_board pbn_exar_ibm_saturn = {
1650 .num_ports = 1,
1651 .setup = pci_xr17c154_setup,
1652 };
1653
1654 static const struct exar8250_board pbn_exar_XR17C15x = {
1655 .setup = pci_xr17c154_setup,
1656 };
1657
1658 static const struct exar8250_board pbn_exar_XR17V35x = {
1659 .setup = pci_xr17v35x_setup,
1660 .exit = pci_xr17v35x_exit,
1661 };
1662
1663 static const struct exar8250_board pbn_fastcom35x_2 = {
1664 .num_ports = 2,
1665 .setup = pci_xr17v35x_setup,
1666 .exit = pci_xr17v35x_exit,
1667 };
1668
1669 static const struct exar8250_board pbn_fastcom35x_4 = {
1670 .num_ports = 4,
1671 .setup = pci_xr17v35x_setup,
1672 .exit = pci_xr17v35x_exit,
1673 };
1674
1675 static const struct exar8250_board pbn_fastcom35x_8 = {
1676 .num_ports = 8,
1677 .setup = pci_xr17v35x_setup,
1678 .exit = pci_xr17v35x_exit,
1679 };
1680
1681 static const struct exar8250_board pbn_exar_XR17V4358 = {
1682 .num_ports = 12,
1683 .setup = pci_xr17v35x_setup,
1684 .exit = pci_xr17v35x_exit,
1685 };
1686
1687 static const struct exar8250_board pbn_exar_XR17V8358 = {
1688 .num_ports = 16,
1689 .setup = pci_xr17v35x_setup,
1690 .exit = pci_xr17v35x_exit,
1691 };
1692
1693 #define CTI_EXAR_DEVICE(devid, bd) { \
1694 PCI_DEVICE_SUB( \
1695 PCI_VENDOR_ID_EXAR, \
1696 PCI_DEVICE_ID_EXAR_##devid, \
1697 PCI_SUBVENDOR_ID_CONNECT_TECH, \
1698 PCI_ANY_ID), 0, 0, \
1699 (kernel_ulong_t)&bd \
1700 }
1701
1702 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
1703
1704 #define IBM_DEVICE(devid, sdevid, bd) { \
1705 PCI_DEVICE_SUB( \
1706 PCI_VENDOR_ID_EXAR, \
1707 PCI_DEVICE_ID_EXAR_##devid, \
1708 PCI_SUBVENDOR_ID_IBM, \
1709 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
1710 (kernel_ulong_t)&bd \
1711 }
1712
1713 #define USR_DEVICE(devid, sdevid, bd) { \
1714 PCI_DEVICE_SUB( \
1715 PCI_VENDOR_ID_USR, \
1716 PCI_DEVICE_ID_EXAR_##devid, \
1717 PCI_VENDOR_ID_EXAR, \
1718 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
1719 (kernel_ulong_t)&bd \
1720 }
1721
1722 static const struct pci_device_id exar_pci_tbl[] = {
1723 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
1724 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
1725 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
1726 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
1727 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
1728 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
1729 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
1730
1731 /* Connect Tech cards with Exar vendor/device PCI IDs */
1732 CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x),
1733 CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x),
1734 CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x),
1735
1736 CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x),
1737 CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x),
1738 CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x),
1739
1740 CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x),
1741 CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x),
1742 CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x),
1743
1744 /* Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA based) */
1745 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG00X, pbn_cti_fpga),
1746 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_12_XIG01X, pbn_cti_fpga),
1747 EXAR_DEVICE(CONNECT_TECH, PCI_XR79X_16, pbn_cti_fpga),
1748
1749 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
1750
1751 /* USRobotics USR298x-OEM PCI Modems */
1752 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
1753 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
1754
1755 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
1756 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
1757 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
1758 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
1759
1760 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
1761 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
1762 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
1763 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
1764 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
1765 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
1766 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
1767 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
1768 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
1769
1770 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
1771 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
1772 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
1773 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
1774 { 0, }
1775 };
1776 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
1777
1778 static struct pci_driver exar_pci_driver = {
1779 .name = "exar_serial",
1780 .probe = exar_pci_probe,
1781 .remove = exar_pci_remove,
1782 .driver = {
1783 .pm = pm_sleep_ptr(&exar_pci_pm),
1784 },
1785 .id_table = exar_pci_tbl,
1786 };
1787 module_pci_driver(exar_pci_driver);
1788
1789 MODULE_IMPORT_NS(SERIAL_8250_PCI);
1790 MODULE_LICENSE("GPL");
1791 MODULE_DESCRIPTION("Exar Serial Driver");
1792 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
1793