1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. 3 4 #define CREATE_TRACE_POINTS 5 #include <trace/events/qcom_geni_spi.h> 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/dma/qcom-gpi-dma.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/log2.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_opp.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/property.h> 19 #include <linux/soc/qcom/geni-se.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spinlock.h> 22 23 /* SPI SE specific registers and respective register fields */ 24 #define SE_SPI_CPHA 0x224 25 #define CPHA BIT(0) 26 27 #define SE_SPI_LOOPBACK 0x22c 28 #define LOOPBACK_ENABLE 0x1 29 #define NORMAL_MODE 0x0 30 #define LOOPBACK_MSK GENMASK(1, 0) 31 32 #define SE_SPI_CPOL 0x230 33 #define CPOL BIT(2) 34 35 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c 36 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0) 37 38 #define SE_SPI_DEMUX_SEL 0x250 39 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) 40 41 #define SE_SPI_TRANS_CFG 0x25c 42 #define CS_TOGGLE BIT(1) 43 44 #define SE_SPI_WORD_LEN 0x268 45 #define WORD_LEN_MSK GENMASK(9, 0) 46 #define MIN_WORD_LEN 4 47 48 #define SE_SPI_TX_TRANS_LEN 0x26c 49 #define SE_SPI_RX_TRANS_LEN 0x270 50 #define TRANS_LEN_MSK GENMASK(23, 0) 51 52 #define SE_SPI_PRE_POST_CMD_DLY 0x274 53 54 #define SE_SPI_DELAY_COUNTERS 0x278 55 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0) 56 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) 57 #define SPI_CS_CLK_DELAY_SHFT 10 58 59 #define SE_SPI_SLAVE_EN (0x2BC) 60 #define SPI_SLAVE_EN BIT(0) 61 62 /* M_CMD OP codes for SPI */ 63 #define SPI_TX_ONLY 1 64 #define SPI_RX_ONLY 2 65 #define SPI_TX_RX 7 66 #define SPI_CS_ASSERT 8 67 #define SPI_CS_DEASSERT 9 68 #define SPI_SCK_ONLY 10 69 /* M_CMD params for SPI */ 70 #define SPI_PRE_CMD_DELAY BIT(0) 71 #define TIMESTAMP_BEFORE BIT(1) 72 #define FRAGMENTATION BIT(2) 73 #define TIMESTAMP_AFTER BIT(3) 74 #define POST_CMD_DELAY BIT(4) 75 76 #define GSI_LOOPBACK_EN BIT(0) 77 #define GSI_CS_TOGGLE BIT(3) 78 #define GSI_CPHA BIT(4) 79 #define GSI_CPOL BIT(5) 80 81 struct spi_geni_master { 82 struct geni_se se; 83 struct device *dev; 84 u32 tx_fifo_depth; 85 u32 fifo_width_bits; 86 u32 tx_wm; 87 u32 last_mode; 88 u8 last_cs; 89 unsigned long cur_speed_hz; 90 unsigned long cur_sclk_hz; 91 unsigned int cur_bits_per_word; 92 unsigned int tx_rem_bytes; 93 unsigned int rx_rem_bytes; 94 const struct spi_transfer *cur_xfer; 95 struct completion cs_done; 96 struct completion cancel_done; 97 struct completion abort_done; 98 struct completion tx_reset_done; 99 struct completion rx_reset_done; 100 unsigned int oversampling; 101 spinlock_t lock; 102 int irq; 103 bool cs_flag; 104 bool abort_failed; 105 struct dma_chan *tx; 106 struct dma_chan *rx; 107 int cur_xfer_mode; 108 }; 109 110 static void spi_slv_setup(struct spi_geni_master *mas) 111 { 112 struct geni_se *se = &mas->se; 113 114 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); 115 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); 116 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); 117 dev_dbg(mas->dev, "spi slave setup done\n"); 118 } 119 120 static int get_spi_clk_cfg(unsigned int speed_hz, 121 struct spi_geni_master *mas, 122 unsigned int *clk_idx, 123 unsigned int *clk_div) 124 { 125 unsigned long sclk_freq; 126 unsigned int actual_hz; 127 int ret; 128 129 ret = geni_se_clk_freq_match(&mas->se, 130 speed_hz * mas->oversampling, 131 clk_idx, &sclk_freq, false); 132 if (ret) { 133 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", 134 ret, speed_hz); 135 return ret; 136 } 137 138 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); 139 actual_hz = sclk_freq / (mas->oversampling * *clk_div); 140 141 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, 142 actual_hz, sclk_freq, *clk_idx, *clk_div); 143 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); 144 if (ret) 145 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); 146 else 147 mas->cur_sclk_hz = sclk_freq; 148 149 return ret; 150 } 151 152 static void handle_se_timeout(struct spi_controller *spi) 153 { 154 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 155 unsigned long time_left; 156 struct geni_se *se = &mas->se; 157 const struct spi_transfer *xfer; 158 159 spin_lock_irq(&mas->lock); 160 if (mas->cur_xfer_mode == GENI_SE_FIFO) 161 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 162 163 xfer = mas->cur_xfer; 164 mas->cur_xfer = NULL; 165 166 /* The controller doesn't support the Cancel commnand in target mode */ 167 if (!spi->target) { 168 reinit_completion(&mas->cancel_done); 169 geni_se_cancel_m_cmd(se); 170 171 spin_unlock_irq(&mas->lock); 172 173 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 174 if (time_left) 175 goto reset_if_dma; 176 177 spin_lock_irq(&mas->lock); 178 } 179 180 reinit_completion(&mas->abort_done); 181 geni_se_abort_m_cmd(se); 182 spin_unlock_irq(&mas->lock); 183 184 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); 185 if (!time_left) { 186 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); 187 188 /* 189 * No need for a lock since SPI core has a lock and we never 190 * access this from an interrupt. 191 */ 192 mas->abort_failed = true; 193 } 194 195 reset_if_dma: 196 if (mas->cur_xfer_mode == GENI_SE_DMA) { 197 if (xfer) { 198 if (xfer->tx_buf) { 199 spin_lock_irq(&mas->lock); 200 reinit_completion(&mas->tx_reset_done); 201 writel(1, se->base + SE_DMA_TX_FSM_RST); 202 spin_unlock_irq(&mas->lock); 203 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 204 if (!time_left) 205 dev_err(mas->dev, "DMA TX RESET failed\n"); 206 } 207 if (xfer->rx_buf) { 208 spin_lock_irq(&mas->lock); 209 reinit_completion(&mas->rx_reset_done); 210 writel(1, se->base + SE_DMA_RX_FSM_RST); 211 spin_unlock_irq(&mas->lock); 212 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 213 if (!time_left) 214 dev_err(mas->dev, "DMA RX RESET failed\n"); 215 } 216 } else { 217 /* 218 * This can happen if a timeout happened and we had to wait 219 * for lock in this function because isr was holding the lock 220 * and handling transfer completion at that time. 221 */ 222 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 223 } 224 } 225 } 226 227 static void handle_gpi_timeout(struct spi_controller *spi) 228 { 229 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 230 231 dmaengine_terminate_sync(mas->tx); 232 dmaengine_terminate_sync(mas->rx); 233 } 234 235 static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg) 236 { 237 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 238 239 switch (mas->cur_xfer_mode) { 240 case GENI_SE_FIFO: 241 case GENI_SE_DMA: 242 handle_se_timeout(spi); 243 break; 244 case GENI_GPI_DMA: 245 handle_gpi_timeout(spi); 246 break; 247 default: 248 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); 249 } 250 } 251 252 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas) 253 { 254 struct geni_se *se = &mas->se; 255 u32 m_irq, m_irq_en; 256 257 if (!mas->abort_failed) 258 return false; 259 260 /* 261 * The only known case where a transfer times out and then a cancel 262 * times out then an abort times out is if something is blocking our 263 * interrupt handler from running. Avoid starting any new transfers 264 * until that sorts itself out. 265 */ 266 spin_lock_irq(&mas->lock); 267 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 268 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); 269 spin_unlock_irq(&mas->lock); 270 271 if (m_irq & m_irq_en) { 272 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", 273 m_irq & m_irq_en); 274 return true; 275 } 276 277 /* 278 * If we're here the problem resolved itself so no need to check more 279 * on future transfers. 280 */ 281 mas->abort_failed = false; 282 283 return false; 284 } 285 286 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode, 287 unsigned int bits_per_word) 288 { 289 unsigned int pack_words; 290 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; 291 struct geni_se *se = &mas->se; 292 u32 word_len; 293 294 /* 295 * If bits_per_word isn't a byte aligned value, set the packing to be 296 * 1 SPI word per FIFO word. 297 */ 298 if (!(mas->fifo_width_bits % bits_per_word)) 299 pack_words = mas->fifo_width_bits / bits_per_word; 300 else 301 pack_words = 1; 302 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, 303 true, true); 304 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; 305 writel(word_len, se->base + SE_SPI_WORD_LEN); 306 } 307 308 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas, 309 unsigned long clk_hz) 310 { 311 u32 clk_sel, m_clk_cfg, idx, div; 312 struct geni_se *se = &mas->se; 313 int ret; 314 315 if (clk_hz == mas->cur_speed_hz) 316 return 0; 317 318 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div); 319 if (ret) { 320 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); 321 return ret; 322 } 323 324 /* 325 * SPI core clock gets configured with the requested frequency 326 * or the frequency closer to the requested frequency. 327 * For that reason requested frequency is stored in the 328 * cur_speed_hz and referred in the consecutive transfer instead 329 * of calling clk_get_rate() API. 330 */ 331 mas->cur_speed_hz = clk_hz; 332 333 clk_sel = idx & CLK_SEL_MSK; 334 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN; 335 writel(clk_sel, se->base + SE_GENI_CLK_SEL); 336 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); 337 338 trace_geni_spi_clk_cfg(mas->dev, clk_hz, mas->cur_sclk_hz, idx, div, 339 mas->cur_bits_per_word); 340 341 /* Set BW quota for CPU as driver supports FIFO mode only. */ 342 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); 343 ret = geni_icc_set_bw(se); 344 if (ret) 345 return ret; 346 347 return 0; 348 } 349 350 static int setup_fifo_params(struct spi_device *spi_slv, 351 struct spi_controller *spi) 352 { 353 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 354 struct geni_se *se = &mas->se; 355 u8 chipselect = spi_get_chipselect(spi_slv, 0); 356 bool cs_changed = (mas->last_cs != chipselect); 357 u32 mode_changed = mas->last_mode ^ spi_slv->mode; 358 359 mas->last_cs = chipselect; 360 mas->last_mode = spi_slv->mode; 361 362 if (mode_changed & SPI_LSB_FIRST) 363 mas->cur_bits_per_word = 0; /* force next setup_se_xfer to call spi_setup_word_len */ 364 if (mode_changed & SPI_LOOP) 365 writel((spi_slv->mode & SPI_LOOP) ? LOOPBACK_ENABLE : 0, se->base + SE_SPI_LOOPBACK); 366 if (cs_changed) 367 writel(chipselect, se->base + SE_SPI_DEMUX_SEL); 368 if (mode_changed & SPI_CPHA) 369 writel((spi_slv->mode & SPI_CPHA) ? CPHA : 0, se->base + SE_SPI_CPHA); 370 if (mode_changed & SPI_CPOL) 371 writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL); 372 if ((mode_changed & SPI_CS_HIGH) || (cs_changed && (spi_slv->mode & SPI_CS_HIGH))) 373 writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV); 374 375 trace_geni_spi_setup_params(mas->dev, chipselect, spi_slv->mode, 376 mode_changed, cs_changed); 377 378 return 0; 379 } 380 381 static void 382 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result) 383 { 384 struct spi_controller *spi = cb; 385 386 spi->cur_msg->status = -EIO; 387 if (result->result != DMA_TRANS_NOERROR) { 388 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); 389 spi_finalize_current_transfer(spi); 390 return; 391 } 392 393 if (!result->residue) { 394 spi->cur_msg->status = 0; 395 dev_dbg(&spi->dev, "DMA txn completed\n"); 396 } else { 397 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); 398 } 399 400 spi_finalize_current_transfer(spi); 401 } 402 403 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas, 404 struct spi_device *spi_slv, struct spi_controller *spi) 405 { 406 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 407 struct dma_slave_config config = {}; 408 struct gpi_spi_config peripheral = {}; 409 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 410 int ret; 411 412 config.peripheral_config = &peripheral; 413 config.peripheral_size = sizeof(peripheral); 414 peripheral.set_config = true; 415 416 if (xfer->bits_per_word != mas->cur_bits_per_word || 417 xfer->speed_hz != mas->cur_speed_hz) { 418 mas->cur_bits_per_word = xfer->bits_per_word; 419 mas->cur_speed_hz = xfer->speed_hz; 420 } 421 422 if (xfer->tx_buf && xfer->rx_buf) { 423 peripheral.cmd = SPI_DUPLEX; 424 } else if (xfer->tx_buf) { 425 peripheral.cmd = SPI_TX; 426 peripheral.rx_len = 0; 427 } else if (xfer->rx_buf) { 428 peripheral.cmd = SPI_RX; 429 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { 430 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); 431 } else { 432 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; 433 434 peripheral.rx_len = (xfer->len / bytes_per_word); 435 } 436 } 437 438 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); 439 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); 440 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); 441 peripheral.cs = spi_get_chipselect(spi_slv, 0); 442 peripheral.pack_en = true; 443 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; 444 445 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, 446 &peripheral.clk_src, &peripheral.clk_div); 447 if (ret) { 448 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); 449 return ret; 450 } 451 452 /* 453 * Set fragmentation to keep CS asserted after this transfer when: 454 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers 455 * - last transfer with cs_change=1: keep CS asserted after the message 456 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to 457 * keep CS asserted across header, wait-state and data phases) 458 */ 459 peripheral.fragmentation = list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? 460 xfer->cs_change : !xfer->cs_change; 461 462 if (peripheral.cmd & SPI_RX) { 463 dmaengine_slave_config(mas->rx, &config); 464 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, 465 DMA_DEV_TO_MEM, flags); 466 if (!rx_desc) { 467 dev_err(mas->dev, "Err setting up rx desc\n"); 468 return -EIO; 469 } 470 } 471 472 /* 473 * Prepare the TX always, even for RX or tx_buf being null, we would 474 * need TX to be prepared per GSI spec 475 */ 476 dmaengine_slave_config(mas->tx, &config); 477 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, 478 DMA_MEM_TO_DEV, flags); 479 if (!tx_desc) { 480 dev_err(mas->dev, "Err setting up tx desc\n"); 481 return -EIO; 482 } 483 484 tx_desc->callback_result = spi_gsi_callback_result; 485 tx_desc->callback_param = spi; 486 487 if (peripheral.cmd & SPI_RX) 488 dmaengine_submit(rx_desc); 489 dmaengine_submit(tx_desc); 490 491 if (peripheral.cmd & SPI_RX) 492 dma_async_issue_pending(mas->rx); 493 494 dma_async_issue_pending(mas->tx); 495 return 1; 496 } 497 498 static u32 get_xfer_len_in_words(struct spi_transfer *xfer, 499 struct spi_geni_master *mas) 500 { 501 u32 len; 502 503 if (!(xfer->bits_per_word % MIN_WORD_LEN)) 504 len = xfer->len * BITS_PER_BYTE / xfer->bits_per_word; 505 else 506 len = xfer->len / (xfer->bits_per_word / BITS_PER_BYTE + 1); 507 len &= TRANS_LEN_MSK; 508 509 return len; 510 } 511 512 static bool geni_can_dma(struct spi_controller *ctlr, 513 struct spi_device *slv, struct spi_transfer *xfer) 514 { 515 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller); 516 u32 len, fifo_size; 517 518 if (mas->cur_xfer_mode == GENI_GPI_DMA) 519 return true; 520 521 /* Set SE DMA mode for SPI target. */ 522 if (ctlr->target) 523 return true; 524 525 len = get_xfer_len_in_words(xfer, mas); 526 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / xfer->bits_per_word; 527 528 if (len > fifo_size) 529 return true; 530 else 531 return false; 532 } 533 534 static int spi_geni_prepare_message(struct spi_controller *spi, 535 struct spi_message *spi_msg) 536 { 537 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 538 int ret; 539 540 switch (mas->cur_xfer_mode) { 541 case GENI_SE_FIFO: 542 case GENI_SE_DMA: 543 if (spi_geni_is_abort_still_pending(mas)) 544 return -EBUSY; 545 ret = setup_fifo_params(spi_msg->spi, spi); 546 if (ret) 547 dev_err(mas->dev, "Couldn't select mode %d\n", ret); 548 return ret; 549 550 case GENI_GPI_DMA: 551 /* nothing to do for GPI DMA */ 552 return 0; 553 } 554 555 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); 556 return -EINVAL; 557 } 558 559 static void spi_geni_release_dma_chan(void *data) 560 { 561 struct spi_geni_master *mas = data; 562 563 if (mas->rx) { 564 dma_release_channel(mas->rx); 565 mas->rx = NULL; 566 } 567 568 if (mas->tx) { 569 dma_release_channel(mas->tx); 570 mas->tx = NULL; 571 } 572 } 573 574 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas) 575 { 576 int ret; 577 578 mas->tx = dma_request_chan(mas->dev, "tx"); 579 if (IS_ERR(mas->tx)) { 580 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), 581 "Failed to get tx DMA ch\n"); 582 goto err_tx; 583 } 584 585 mas->rx = dma_request_chan(mas->dev, "rx"); 586 if (IS_ERR(mas->rx)) { 587 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), 588 "Failed to get rx DMA ch\n"); 589 goto err_rx; 590 } 591 592 ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas); 593 if (ret) { 594 dev_err(mas->dev, "Unable to add action.\n"); 595 return ret; 596 } 597 598 return 0; 599 600 err_rx: 601 mas->rx = NULL; 602 dma_release_channel(mas->tx); 603 err_tx: 604 mas->tx = NULL; 605 return ret; 606 } 607 608 static int spi_geni_init(struct spi_geni_master *mas) 609 { 610 struct spi_controller *spi = dev_get_drvdata(mas->dev); 611 struct geni_se *se = &mas->se; 612 unsigned int proto, major, minor, ver; 613 u32 spi_tx_cfg, fifo_disable; 614 int ret = -ENXIO; 615 616 pm_runtime_get_sync(mas->dev); 617 618 proto = geni_se_read_proto(se); 619 620 if (spi->target) { 621 if (proto != GENI_SE_SPI_SLAVE) { 622 dev_err(mas->dev, "Invalid proto %d\n", proto); 623 goto out_pm; 624 } 625 spi_slv_setup(mas); 626 } else if (proto == GENI_SE_INVALID_PROTO) { 627 ret = geni_load_se_firmware(se, GENI_SE_SPI); 628 if (ret) { 629 dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret); 630 goto out_pm; 631 } 632 } else if (proto != GENI_SE_SPI) { 633 dev_err(mas->dev, "Invalid proto %d\n", proto); 634 goto out_pm; 635 } 636 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); 637 638 /* Width of Tx and Rx FIFO is same */ 639 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); 640 641 /* 642 * Hardware programming guide suggests to configure 643 * RX FIFO RFR level to fifo_depth-2. 644 */ 645 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); 646 /* Transmit an entire FIFO worth of data per IRQ */ 647 mas->tx_wm = 1; 648 ver = geni_se_get_qup_hw_version(se); 649 major = GENI_SE_VERSION_MAJOR(ver); 650 minor = GENI_SE_VERSION_MINOR(ver); 651 652 if (major == 1 && minor == 0) 653 mas->oversampling = 2; 654 else 655 mas->oversampling = 1; 656 657 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; 658 switch (fifo_disable) { 659 case 1: 660 ret = spi_geni_grab_gpi_chan(mas); 661 if (!ret) { /* success case */ 662 mas->cur_xfer_mode = GENI_GPI_DMA; 663 geni_se_select_mode(se, GENI_GPI_DMA); 664 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); 665 break; 666 } else if (ret == -EPROBE_DEFER) { 667 goto out_pm; 668 } 669 /* 670 * in case of failure to get gpi dma channel, we can still do the 671 * FIFO mode, so fallthrough 672 */ 673 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); 674 fallthrough; 675 676 case 0: 677 mas->cur_xfer_mode = GENI_SE_FIFO; 678 geni_se_select_mode(se, GENI_SE_FIFO); 679 /* setup_fifo_params assumes that these registers start with a zero value */ 680 writel(0, se->base + SE_SPI_LOOPBACK); 681 writel(0, se->base + SE_SPI_DEMUX_SEL); 682 writel(0, se->base + SE_SPI_CPHA); 683 writel(0, se->base + SE_SPI_CPOL); 684 writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV); 685 ret = 0; 686 break; 687 } 688 689 /* We never control CS manually */ 690 if (!spi->target) { 691 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); 692 spi_tx_cfg &= ~CS_TOGGLE; 693 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); 694 } 695 696 out_pm: 697 pm_runtime_put(mas->dev); 698 return ret; 699 } 700 701 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas) 702 { 703 /* 704 * Calculate how many bytes we'll put in each FIFO word. If the 705 * transfer words don't pack cleanly into a FIFO word we'll just put 706 * one transfer word in each FIFO word. If they do pack we'll pack 'em. 707 */ 708 if (mas->fifo_width_bits % mas->cur_bits_per_word) 709 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, 710 BITS_PER_BYTE)); 711 712 return mas->fifo_width_bits / BITS_PER_BYTE; 713 } 714 715 static bool geni_spi_handle_tx(struct spi_geni_master *mas) 716 { 717 struct geni_se *se = &mas->se; 718 unsigned int max_bytes; 719 const u8 *tx_buf; 720 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 721 unsigned int i = 0; 722 723 /* Stop the watermark IRQ if nothing to send */ 724 if (!mas->cur_xfer) { 725 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 726 return false; 727 } 728 729 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; 730 if (mas->tx_rem_bytes < max_bytes) 731 max_bytes = mas->tx_rem_bytes; 732 733 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; 734 while (i < max_bytes) { 735 unsigned int j; 736 unsigned int bytes_to_write; 737 u32 fifo_word = 0; 738 u8 *fifo_byte = (u8 *)&fifo_word; 739 740 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); 741 for (j = 0; j < bytes_to_write; j++) 742 fifo_byte[j] = tx_buf[i++]; 743 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); 744 } 745 mas->tx_rem_bytes -= max_bytes; 746 if (!mas->tx_rem_bytes) { 747 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 748 return false; 749 } 750 return true; 751 } 752 753 static void geni_spi_handle_rx(struct spi_geni_master *mas) 754 { 755 struct geni_se *se = &mas->se; 756 u32 rx_fifo_status; 757 unsigned int rx_bytes; 758 unsigned int rx_last_byte_valid; 759 u8 *rx_buf; 760 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas); 761 unsigned int i = 0; 762 763 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); 764 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word; 765 if (rx_fifo_status & RX_LAST) { 766 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK; 767 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT; 768 if (rx_last_byte_valid && rx_last_byte_valid < 4) 769 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; 770 } 771 772 /* Clear out the FIFO and bail if nowhere to put it */ 773 if (!mas->cur_xfer) { 774 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++) 775 readl(se->base + SE_GENI_RX_FIFOn); 776 return; 777 } 778 779 if (mas->rx_rem_bytes < rx_bytes) 780 rx_bytes = mas->rx_rem_bytes; 781 782 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; 783 while (i < rx_bytes) { 784 u32 fifo_word = 0; 785 u8 *fifo_byte = (u8 *)&fifo_word; 786 unsigned int bytes_to_read; 787 unsigned int j; 788 789 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); 790 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); 791 for (j = 0; j < bytes_to_read; j++) 792 rx_buf[i++] = fifo_byte[j]; 793 } 794 mas->rx_rem_bytes -= rx_bytes; 795 } 796 797 static int setup_se_xfer(struct spi_transfer *xfer, 798 struct spi_geni_master *mas, 799 u16 mode, struct spi_controller *spi) 800 { 801 u32 m_cmd = 0; 802 u32 m_params = 0; 803 u32 len; 804 struct geni_se *se = &mas->se; 805 int ret; 806 807 /* 808 * Ensure that our interrupt handler isn't still running from some 809 * prior command before we start messing with the hardware behind 810 * its back. We don't need to _keep_ the lock here since we're only 811 * worried about racing with out interrupt handler. The SPI core 812 * already handles making sure that we're not trying to do two 813 * transfers at once or setting a chip select and doing a transfer 814 * concurrently. 815 * 816 * NOTE: we actually _can't_ hold the lock here because possibly we 817 * might call clk_set_rate() which needs to be able to sleep. 818 */ 819 spin_lock_irq(&mas->lock); 820 spin_unlock_irq(&mas->lock); 821 822 if (xfer->bits_per_word != mas->cur_bits_per_word) { 823 spi_setup_word_len(mas, mode, xfer->bits_per_word); 824 mas->cur_bits_per_word = xfer->bits_per_word; 825 } 826 827 /* Speed and bits per word can be overridden per transfer */ 828 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 829 if (ret) 830 return ret; 831 832 mas->tx_rem_bytes = 0; 833 mas->rx_rem_bytes = 0; 834 835 len = get_xfer_len_in_words(xfer, mas); 836 837 mas->cur_xfer = xfer; 838 if (xfer->tx_buf) { 839 m_cmd |= SPI_TX_ONLY; 840 mas->tx_rem_bytes = xfer->len; 841 writel(len, se->base + SE_SPI_TX_TRANS_LEN); 842 } 843 844 if (xfer->rx_buf) { 845 m_cmd |= SPI_RX_ONLY; 846 writel(len, se->base + SE_SPI_RX_TRANS_LEN); 847 mas->rx_rem_bytes = xfer->len; 848 } 849 850 /* 851 * Select DMA mode if sgt are present; and with only 1 entry 852 * This is not a serious limitation because the xfer buffers are 853 * expected to fit into in 1 entry almost always, and if any 854 * doesn't for any reason we fall back to FIFO mode anyway 855 */ 856 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents) 857 mas->cur_xfer_mode = GENI_SE_FIFO; 858 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) { 859 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n", 860 xfer->tx_sg.nents, xfer->rx_sg.nents); 861 mas->cur_xfer_mode = GENI_SE_FIFO; 862 } else 863 mas->cur_xfer_mode = GENI_SE_DMA; 864 geni_se_select_mode(se, mas->cur_xfer_mode); 865 866 /* 867 * Set FRAGMENTATION to keep CS asserted after this transfer when: 868 * - non-last transfer with cs_change=0: keep CS asserted between chained transfers 869 * - last transfer with cs_change=1: keep CS asserted after the message 870 * (e.g. TPM TIS SPI uses cs_change=1 on single-transfer messages to 871 * keep CS asserted across header, wait-state and data phases) 872 */ 873 if (list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers) ? 874 xfer->cs_change : !xfer->cs_change) 875 m_params = FRAGMENTATION; 876 877 /* 878 * Lock around right before we start the transfer since our 879 * interrupt could come in at any time now. 880 */ 881 spin_lock_irq(&mas->lock); 882 geni_se_setup_m_cmd(se, m_cmd, m_params); 883 884 trace_geni_spi_transfer(mas->dev, len, m_cmd); 885 886 if (mas->cur_xfer_mode == GENI_SE_DMA) { 887 if (m_cmd & SPI_RX_ONLY) 888 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), 889 sg_dma_len(xfer->rx_sg.sgl)); 890 if (m_cmd & SPI_TX_ONLY) 891 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl), 892 sg_dma_len(xfer->tx_sg.sgl)); 893 } else if (m_cmd & SPI_TX_ONLY) { 894 if (geni_spi_handle_tx(mas)) 895 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 896 } 897 898 spin_unlock_irq(&mas->lock); 899 return ret; 900 } 901 902 static int spi_geni_transfer_one(struct spi_controller *spi, 903 struct spi_device *slv, 904 struct spi_transfer *xfer) 905 { 906 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 907 int ret; 908 909 if (spi_geni_is_abort_still_pending(mas)) 910 return -EBUSY; 911 912 /* Terminate and return success for 0 byte length transfer */ 913 if (!xfer->len) 914 return 0; 915 916 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 917 ret = setup_se_xfer(xfer, mas, slv->mode, spi); 918 /* SPI framework expects +ve ret code to wait for transfer complete */ 919 if (!ret) 920 ret = 1; 921 return ret; 922 } 923 return setup_gsi_xfer(xfer, mas, slv, spi); 924 } 925 926 static irqreturn_t geni_spi_isr(int irq, void *data) 927 { 928 struct spi_controller *spi = data; 929 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 930 struct geni_se *se = &mas->se; 931 u32 m_irq, dma_tx_status, dma_rx_status; 932 933 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); 934 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 935 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 936 937 if (!m_irq && !dma_tx_status && !dma_rx_status) 938 return IRQ_NONE; 939 940 trace_geni_spi_irq(mas->dev, m_irq, dma_tx_status, dma_rx_status); 941 942 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | 943 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN | 944 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN)) 945 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); 946 947 spin_lock(&mas->lock); 948 949 if (mas->cur_xfer_mode == GENI_SE_FIFO) { 950 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 951 geni_spi_handle_rx(mas); 952 953 if (m_irq & M_TX_FIFO_WATERMARK_EN) 954 geni_spi_handle_tx(mas); 955 956 if (m_irq & M_CMD_DONE_EN) { 957 if (mas->cur_xfer) { 958 spi_finalize_current_transfer(spi); 959 mas->cur_xfer = NULL; 960 /* 961 * If this happens, then a CMD_DONE came before all the 962 * Tx buffer bytes were sent out. This is unusual, log 963 * this condition and disable the WM interrupt to 964 * prevent the system from stalling due an interrupt 965 * storm. 966 * 967 * If this happens when all Rx bytes haven't been 968 * received, log the condition. The only known time 969 * this can happen is if bits_per_word != 8 and some 970 * registers that expect xfer lengths in num spi_words 971 * weren't written correctly. 972 */ 973 if (mas->tx_rem_bytes) { 974 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 975 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 976 mas->tx_rem_bytes, mas->cur_bits_per_word); 977 } 978 if (mas->rx_rem_bytes) 979 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 980 mas->rx_rem_bytes, mas->cur_bits_per_word); 981 } else { 982 complete(&mas->cs_done); 983 } 984 } 985 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 986 const struct spi_transfer *xfer = mas->cur_xfer; 987 988 if (dma_tx_status) 989 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 990 if (dma_rx_status) 991 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 992 if (dma_tx_status & TX_DMA_DONE) 993 mas->tx_rem_bytes = 0; 994 if (dma_rx_status & RX_DMA_DONE) 995 mas->rx_rem_bytes = 0; 996 if (dma_tx_status & TX_RESET_DONE) 997 complete(&mas->tx_reset_done); 998 if (dma_rx_status & RX_RESET_DONE) 999 complete(&mas->rx_reset_done); 1000 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 1001 spi_finalize_current_transfer(spi); 1002 mas->cur_xfer = NULL; 1003 } 1004 } 1005 1006 if (m_irq & M_CMD_CANCEL_EN) 1007 complete(&mas->cancel_done); 1008 if (m_irq & M_CMD_ABORT_EN) 1009 complete(&mas->abort_done); 1010 1011 /* 1012 * It's safe or a good idea to Ack all of our interrupts at the end 1013 * of the function. Specifically: 1014 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and 1015 * clearing Acks. Clearing at the end relies on nobody else having 1016 * started a new transfer yet or else we could be clearing _their_ 1017 * done bit, but everyone grabs the spinlock before starting a new 1018 * transfer. 1019 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear 1020 * to be "latched level" interrupts so it's important to clear them 1021 * _after_ you've handled the condition and always safe to do so 1022 * since they'll re-assert if they're still happening. 1023 */ 1024 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); 1025 1026 spin_unlock(&mas->lock); 1027 1028 return IRQ_HANDLED; 1029 } 1030 1031 static int spi_geni_target_abort(struct spi_controller *spi) 1032 { 1033 if (!spi->cur_msg) 1034 return 0; 1035 1036 handle_se_timeout(spi); 1037 spi_finalize_current_transfer(spi); 1038 1039 return 0; 1040 } 1041 1042 static int spi_geni_probe(struct platform_device *pdev) 1043 { 1044 int ret, irq; 1045 struct spi_controller *spi; 1046 struct spi_geni_master *mas; 1047 void __iomem *base; 1048 struct clk *clk; 1049 struct device *dev = &pdev->dev; 1050 1051 irq = platform_get_irq(pdev, 0); 1052 if (irq < 0) 1053 return irq; 1054 1055 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1056 if (ret) 1057 return dev_err_probe(dev, ret, "could not set DMA mask\n"); 1058 1059 base = devm_platform_ioremap_resource(pdev, 0); 1060 if (IS_ERR(base)) 1061 return PTR_ERR(base); 1062 1063 clk = devm_clk_get(dev, "se"); 1064 if (IS_ERR(clk)) 1065 return PTR_ERR(clk); 1066 1067 if (device_property_read_bool(dev, "spi-slave")) 1068 spi = devm_spi_alloc_target(dev, sizeof(*mas)); 1069 else 1070 spi = devm_spi_alloc_host(dev, sizeof(*mas)); 1071 1072 if (!spi) 1073 return -ENOMEM; 1074 1075 platform_set_drvdata(pdev, spi); 1076 mas = spi_controller_get_devdata(spi); 1077 mas->irq = irq; 1078 mas->dev = dev; 1079 mas->se.dev = dev; 1080 mas->se.wrapper = dev_get_drvdata(dev->parent); 1081 mas->se.base = base; 1082 mas->se.clk = clk; 1083 1084 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); 1085 if (ret) 1086 return ret; 1087 /* OPP table is optional */ 1088 ret = devm_pm_opp_of_add_table(&pdev->dev); 1089 if (ret && ret != -ENODEV) { 1090 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1091 return ret; 1092 } 1093 1094 spi->bus_num = -1; 1095 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; 1096 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1097 spi->num_chipselect = 4; 1098 spi->max_speed_hz = 50000000; 1099 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */ 1100 spi->prepare_message = spi_geni_prepare_message; 1101 spi->transfer_one = spi_geni_transfer_one; 1102 spi->can_dma = geni_can_dma; 1103 spi->dma_map_dev = dev->parent; 1104 spi->auto_runtime_pm = true; 1105 spi->handle_err = spi_geni_handle_err; 1106 spi->use_gpio_descriptors = true; 1107 1108 init_completion(&mas->cs_done); 1109 init_completion(&mas->cancel_done); 1110 init_completion(&mas->abort_done); 1111 init_completion(&mas->tx_reset_done); 1112 init_completion(&mas->rx_reset_done); 1113 spin_lock_init(&mas->lock); 1114 1115 if (spi->target) 1116 spi->target_abort = spi_geni_target_abort; 1117 1118 ret = geni_icc_get(&mas->se, NULL); 1119 if (ret) 1120 return ret; 1121 1122 pm_runtime_use_autosuspend(&pdev->dev); 1123 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); 1124 ret = devm_pm_runtime_enable(dev); 1125 if (ret) 1126 return ret; 1127 1128 /* Set the bus quota to a reasonable value for register access */ 1129 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); 1130 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 1131 1132 ret = geni_icc_set_bw(&mas->se); 1133 if (ret) 1134 return ret; 1135 1136 ret = spi_geni_init(mas); 1137 if (ret) 1138 return ret; 1139 1140 /* 1141 * TX is required per GSI spec, see setup_gsi_xfer(). 1142 */ 1143 if (mas->cur_xfer_mode == GENI_GPI_DMA) 1144 spi->flags = SPI_CONTROLLER_MUST_TX; 1145 1146 ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi); 1147 if (ret) 1148 return ret; 1149 1150 return devm_spi_register_controller(dev, spi); 1151 } 1152 1153 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) 1154 { 1155 struct spi_controller *spi = dev_get_drvdata(dev); 1156 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 1157 int ret; 1158 1159 /* Drop the performance state vote */ 1160 dev_pm_opp_set_rate(dev, 0); 1161 1162 ret = geni_se_resources_off(&mas->se); 1163 if (ret) 1164 return ret; 1165 1166 return geni_icc_disable(&mas->se); 1167 } 1168 1169 static int __maybe_unused spi_geni_runtime_resume(struct device *dev) 1170 { 1171 struct spi_controller *spi = dev_get_drvdata(dev); 1172 struct spi_geni_master *mas = spi_controller_get_devdata(spi); 1173 int ret; 1174 1175 ret = geni_icc_enable(&mas->se); 1176 if (ret) 1177 return ret; 1178 1179 ret = geni_se_resources_on(&mas->se); 1180 if (ret) 1181 return ret; 1182 1183 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); 1184 } 1185 1186 static int __maybe_unused spi_geni_suspend(struct device *dev) 1187 { 1188 struct spi_controller *spi = dev_get_drvdata(dev); 1189 int ret; 1190 1191 ret = spi_controller_suspend(spi); 1192 if (ret) 1193 return ret; 1194 1195 ret = pm_runtime_force_suspend(dev); 1196 if (ret) 1197 spi_controller_resume(spi); 1198 1199 return ret; 1200 } 1201 1202 static int __maybe_unused spi_geni_resume(struct device *dev) 1203 { 1204 struct spi_controller *spi = dev_get_drvdata(dev); 1205 int ret; 1206 1207 ret = pm_runtime_force_resume(dev); 1208 if (ret) 1209 return ret; 1210 1211 ret = spi_controller_resume(spi); 1212 if (ret) 1213 pm_runtime_force_suspend(dev); 1214 1215 return ret; 1216 } 1217 1218 static const struct dev_pm_ops spi_geni_pm_ops = { 1219 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, 1220 spi_geni_runtime_resume, NULL) 1221 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) 1222 }; 1223 1224 static const struct of_device_id spi_geni_dt_match[] = { 1225 { .compatible = "qcom,geni-spi" }, 1226 {} 1227 }; 1228 MODULE_DEVICE_TABLE(of, spi_geni_dt_match); 1229 1230 static struct platform_driver spi_geni_driver = { 1231 .probe = spi_geni_probe, 1232 .driver = { 1233 .name = "geni_spi", 1234 .pm = &spi_geni_pm_ops, 1235 .of_match_table = spi_geni_dt_match, 1236 }, 1237 }; 1238 module_platform_driver(spi_geni_driver); 1239 1240 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores"); 1241 MODULE_LICENSE("GPL v2"); 1242