1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip 4 * 5 * Copyright (C) 2021 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/cleanup.h> 11 #include <linux/i2c.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/module.h> 15 #include <linux/spi/spi.h> 16 #include <sound/core.h> 17 #include <linux/mutex.h> 18 #include <linux/iopoll.h> 19 20 #include "cs8409.h" 21 #include "../side-codecs/hda_component.h" 22 23 /****************************************************************************** 24 * CS8409 Specific Functions 25 ******************************************************************************/ 26 27 static int cs8409_parse_auto_config(struct hda_codec *codec) 28 { 29 struct cs8409_spec *spec = codec->spec; 30 int err; 31 int i; 32 33 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); 34 if (err < 0) 35 return err; 36 37 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); 38 if (err < 0) 39 return err; 40 41 /* keep the ADCs powered up when it's dynamically switchable */ 42 if (spec->gen.dyn_adc_switch) { 43 unsigned int done = 0; 44 45 for (i = 0; i < spec->gen.input_mux.num_items; i++) { 46 int idx = spec->gen.dyn_adc_idx[i]; 47 48 if (done & (1 << idx)) 49 continue; 50 snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]); 51 done |= 1 << idx; 52 } 53 } 54 55 return 0; 56 } 57 58 static void cs8409_disable_i2c_clock_worker(struct work_struct *work); 59 60 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec) 61 { 62 struct cs8409_spec *spec; 63 64 spec = kzalloc_obj(*spec); 65 if (!spec) 66 return NULL; 67 codec->spec = spec; 68 spec->codec = codec; 69 codec->power_save_node = 1; 70 mutex_init(&spec->i2c_mux); 71 INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker); 72 snd_hda_gen_spec_init(&spec->gen); 73 74 return spec; 75 } 76 77 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx) 78 { 79 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); 80 return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0); 81 } 82 83 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx, 84 unsigned int coef) 85 { 86 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); 87 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef); 88 } 89 90 /* 91 * cs8409_enable_i2c_clock - Disable I2C clocks 92 * @codec: the codec instance 93 * Disable I2C clocks. 94 * This must be called when the i2c mutex is unlocked. 95 */ 96 static void cs8409_disable_i2c_clock(struct hda_codec *codec) 97 { 98 struct cs8409_spec *spec = codec->spec; 99 100 guard(mutex)(&spec->i2c_mux); 101 if (spec->i2c_clck_enabled) { 102 cs8409_vendor_coef_set(spec->codec, 0x0, 103 cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7); 104 spec->i2c_clck_enabled = 0; 105 } 106 } 107 108 /* 109 * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use 110 */ 111 static void cs8409_disable_i2c_clock_worker(struct work_struct *work) 112 { 113 struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work); 114 115 cs8409_disable_i2c_clock(spec->codec); 116 } 117 118 /* 119 * cs8409_enable_i2c_clock - Enable I2C clocks 120 * @codec: the codec instance 121 * Enable I2C clocks. 122 * This must be called when the i2c mutex is locked. 123 */ 124 static void cs8409_enable_i2c_clock(struct hda_codec *codec) 125 { 126 struct cs8409_spec *spec = codec->spec; 127 128 /* Cancel the disable timer, but do not wait for any running disable functions to finish. 129 * If the disable timer runs out before cancel, the delayed work thread will be blocked, 130 * waiting for the mutex to become unlocked. This mutex will be locked for the duration of 131 * any i2c transaction, so the disable function will run to completion immediately 132 * afterwards in the scenario. The next enable call will re-enable the clock, regardless. 133 */ 134 cancel_delayed_work(&spec->i2c_clk_work); 135 136 if (!spec->i2c_clck_enabled) { 137 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8); 138 spec->i2c_clck_enabled = 1; 139 } 140 queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25)); 141 } 142 143 /** 144 * cs8409_i2c_wait_complete - Wait for I2C transaction 145 * @codec: the codec instance 146 * 147 * Wait for I2C transaction to complete. 148 * Return -ETIMEDOUT if transaction wait times out. 149 */ 150 static int cs8409_i2c_wait_complete(struct hda_codec *codec) 151 { 152 unsigned int retval; 153 154 return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18, 155 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS); 156 } 157 158 /** 159 * cs8409_set_i2c_dev_addr - Set i2c address for transaction 160 * @codec: the codec instance 161 * @addr: I2C Address 162 */ 163 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr) 164 { 165 struct cs8409_spec *spec = codec->spec; 166 167 if (spec->dev_addr != addr) { 168 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr); 169 spec->dev_addr = addr; 170 } 171 } 172 173 /** 174 * cs8409_i2c_set_page - CS8409 I2C set page register. 175 * @scodec: the codec instance 176 * @i2c_reg: Page register 177 * 178 * Returns negative on error. 179 */ 180 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg) 181 { 182 struct hda_codec *codec = scodec->codec; 183 184 if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) { 185 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8); 186 if (cs8409_i2c_wait_complete(codec) < 0) 187 return -EIO; 188 scodec->last_page = i2c_reg >> 8; 189 } 190 191 return 0; 192 } 193 194 /** 195 * cs8409_i2c_read - CS8409 I2C Read. 196 * @scodec: the codec instance 197 * @addr: Register to read 198 * 199 * Returns negative on error, otherwise returns read value in bits 0-7. 200 */ 201 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr) 202 { 203 struct hda_codec *codec = scodec->codec; 204 struct cs8409_spec *spec = codec->spec; 205 unsigned int i2c_reg_data; 206 unsigned int read_data; 207 208 if (scodec->suspended) 209 return -EPERM; 210 211 guard(mutex)(&spec->i2c_mux); 212 cs8409_enable_i2c_clock(codec); 213 cs8409_set_i2c_dev_addr(codec, scodec->addr); 214 215 if (cs8409_i2c_set_page(scodec, addr)) 216 goto error; 217 218 i2c_reg_data = (addr << 8) & 0x0ffff; 219 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); 220 if (cs8409_i2c_wait_complete(codec) < 0) 221 goto error; 222 223 /* Register in bits 15-8 and the data in 7-0 */ 224 read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD); 225 226 return read_data & 0x0ff; 227 228 error: 229 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); 230 return -EIO; 231 } 232 233 /** 234 * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence. 235 * @scodec: the codec instance 236 * @seq: Register Sequence to read 237 * @count: Number of registeres to read 238 * 239 * Returns negative on error, values are read into value element of cs8409_i2c_param sequence. 240 */ 241 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count) 242 { 243 struct hda_codec *codec = scodec->codec; 244 struct cs8409_spec *spec = codec->spec; 245 unsigned int i2c_reg_data; 246 int i; 247 248 if (scodec->suspended) 249 return -EPERM; 250 251 guard(mutex)(&spec->i2c_mux); 252 cs8409_set_i2c_dev_addr(codec, scodec->addr); 253 254 for (i = 0; i < count; i++) { 255 cs8409_enable_i2c_clock(codec); 256 if (cs8409_i2c_set_page(scodec, seq[i].addr)) 257 goto error; 258 259 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff; 260 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); 261 262 if (cs8409_i2c_wait_complete(codec) < 0) 263 goto error; 264 265 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff; 266 } 267 268 return 0; 269 270 error: 271 codec_err(codec, "I2C Bulk Read Failed 0x%02x\n", scodec->addr); 272 return -EIO; 273 } 274 275 /** 276 * cs8409_i2c_write - CS8409 I2C Write. 277 * @scodec: the codec instance 278 * @addr: Register to write to 279 * @value: Data to write 280 * 281 * Returns negative on error, otherwise returns 0. 282 */ 283 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value) 284 { 285 struct hda_codec *codec = scodec->codec; 286 struct cs8409_spec *spec = codec->spec; 287 unsigned int i2c_reg_data; 288 289 if (scodec->suspended) 290 return -EPERM; 291 292 guard(mutex)(&spec->i2c_mux); 293 294 cs8409_enable_i2c_clock(codec); 295 cs8409_set_i2c_dev_addr(codec, scodec->addr); 296 297 if (cs8409_i2c_set_page(scodec, addr)) 298 goto error; 299 300 i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff); 301 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); 302 303 if (cs8409_i2c_wait_complete(codec) < 0) 304 goto error; 305 306 return 0; 307 308 error: 309 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); 310 return -EIO; 311 } 312 313 /** 314 * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence. 315 * @scodec: the codec instance 316 * @seq: Register Sequence to write 317 * @count: Number of registeres to write 318 * 319 * Returns negative on error. 320 */ 321 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq, 322 int count) 323 { 324 struct hda_codec *codec = scodec->codec; 325 struct cs8409_spec *spec = codec->spec; 326 unsigned int i2c_reg_data; 327 int i; 328 329 if (scodec->suspended) 330 return -EPERM; 331 332 guard(mutex)(&spec->i2c_mux); 333 cs8409_set_i2c_dev_addr(codec, scodec->addr); 334 335 for (i = 0; i < count; i++) { 336 cs8409_enable_i2c_clock(codec); 337 if (cs8409_i2c_set_page(scodec, seq[i].addr)) 338 goto error; 339 340 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff); 341 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); 342 343 if (cs8409_i2c_wait_complete(codec) < 0) 344 goto error; 345 /* Certain use cases may require a delay 346 * after a write operation before proceeding. 347 */ 348 if (seq[i].delay) 349 fsleep(seq[i].delay); 350 } 351 352 return 0; 353 354 error: 355 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr); 356 return -EIO; 357 } 358 359 static int cs8409_init(struct hda_codec *codec) 360 { 361 int ret = snd_hda_gen_init(codec); 362 363 if (!ret) 364 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT); 365 366 return ret; 367 } 368 369 static int cs8409_build_controls(struct hda_codec *codec) 370 { 371 int err; 372 373 err = snd_hda_gen_build_controls(codec); 374 if (err < 0) 375 return err; 376 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD); 377 378 return 0; 379 } 380 381 /* Enable/Disable Unsolicited Response */ 382 static void cs8409_enable_ur(struct hda_codec *codec, int flag) 383 { 384 struct cs8409_spec *spec = codec->spec; 385 unsigned int ur_gpios = 0; 386 int i; 387 388 for (i = 0; i < spec->num_scodecs; i++) 389 ur_gpios |= spec->scodecs[i]->irq_mask; 390 391 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 392 flag ? ur_gpios : 0); 393 394 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE, 395 flag ? AC_UNSOL_ENABLED : 0); 396 } 397 398 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid) 399 { 400 int caps; 401 402 /* CS8409 is simple HDA bridge and intended to be used with a remote 403 * companion codec. Most of input/output PIN(s) have only basic 404 * capabilities. Receive and Transmit NID(s) have only OUTC and INC 405 * capabilities and no presence detect capable (PDC) and call to 406 * snd_hda_gen_build_controls() will mark them as non detectable 407 * phantom jacks. However, a companion codec may be 408 * connected to these pins which supports jack detect 409 * capabilities. We have to override pin capabilities, 410 * otherwise they will not be created as input devices. 411 */ 412 caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP); 413 if (caps >= 0) 414 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP, 415 (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT))); 416 417 snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP)); 418 } 419 420 static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol, 421 struct snd_ctl_elem_value *ucontrol) 422 { 423 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 424 struct cs8409_spec *spec = codec->spec; 425 426 ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio); 427 return 0; 428 } 429 430 static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol, 431 struct snd_ctl_elem_value *ucontrol) 432 { 433 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 434 struct cs8409_spec *spec = codec->spec; 435 unsigned int gpio_data; 436 437 gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) | 438 (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0); 439 if (gpio_data == spec->gpio_data) 440 return 0; 441 spec->gpio_data = gpio_data; 442 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 443 return 1; 444 } 445 446 static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = { 447 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 448 .info = snd_ctl_boolean_mono_info, 449 .get = cs8409_spk_sw_gpio_get, 450 .put = cs8409_spk_sw_gpio_put, 451 }; 452 453 /****************************************************************************** 454 * CS42L42 Specific Functions 455 ******************************************************************************/ 456 457 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo) 458 { 459 unsigned int ofs = get_amp_offset(kctrl); 460 u8 chs = get_amp_channels(kctrl); 461 462 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 463 uinfo->value.integer.step = 1; 464 uinfo->count = chs == 3 ? 2 : 1; 465 466 switch (ofs) { 467 case CS42L42_VOL_DAC: 468 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN; 469 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX; 470 break; 471 case CS42L42_VOL_ADC: 472 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN; 473 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX; 474 break; 475 default: 476 break; 477 } 478 479 return 0; 480 } 481 482 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) 483 { 484 struct hda_codec *codec = snd_kcontrol_chip(kctrl); 485 struct cs8409_spec *spec = codec->spec; 486 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; 487 int chs = get_amp_channels(kctrl); 488 unsigned int ofs = get_amp_offset(kctrl); 489 long *valp = uctrl->value.integer.value; 490 491 switch (ofs) { 492 case CS42L42_VOL_DAC: 493 if (chs & BIT(0)) 494 *valp++ = cs42l42->vol[ofs]; 495 if (chs & BIT(1)) 496 *valp = cs42l42->vol[ofs+1]; 497 break; 498 case CS42L42_VOL_ADC: 499 if (chs & BIT(0)) 500 *valp = cs42l42->vol[ofs]; 501 break; 502 default: 503 break; 504 } 505 506 return 0; 507 } 508 509 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type, 510 unsigned int chs, bool mute) 511 { 512 if (mute) { 513 if (vol_type == CS42L42_VOL_DAC) { 514 if (chs & BIT(0)) 515 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f); 516 if (chs & BIT(1)) 517 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f); 518 } else if (vol_type == CS42L42_VOL_ADC) { 519 if (chs & BIT(0)) 520 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f); 521 } 522 } else { 523 if (vol_type == CS42L42_VOL_DAC) { 524 if (chs & BIT(0)) 525 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 526 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET]) 527 & CS42L42_MIXER_CH_VOL_MASK); 528 if (chs & BIT(1)) 529 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 530 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET]) 531 & CS42L42_MIXER_CH_VOL_MASK); 532 } else if (vol_type == CS42L42_VOL_ADC) { 533 if (chs & BIT(0)) 534 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 535 cs42l42->vol[CS42L42_ADC_VOL_OFFSET] 536 & CS42L42_REG_AMIC_VOL_MASK); 537 } 538 } 539 } 540 541 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) 542 { 543 struct hda_codec *codec = snd_kcontrol_chip(kctrl); 544 struct cs8409_spec *spec = codec->spec; 545 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; 546 int chs = get_amp_channels(kctrl); 547 unsigned int ofs = get_amp_offset(kctrl); 548 long *valp = uctrl->value.integer.value; 549 550 switch (ofs) { 551 case CS42L42_VOL_DAC: 552 if (chs & BIT(0)) 553 cs42l42->vol[ofs] = *valp; 554 if (chs & BIT(1)) { 555 valp++; 556 cs42l42->vol[ofs + 1] = *valp; 557 } 558 if (spec->playback_started) 559 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false); 560 break; 561 case CS42L42_VOL_ADC: 562 if (chs & BIT(0)) 563 cs42l42->vol[ofs] = *valp; 564 if (spec->capture_started) 565 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false); 566 break; 567 default: 568 break; 569 } 570 571 return 0; 572 } 573 574 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo, 575 struct hda_codec *codec, 576 struct snd_pcm_substream *substream, 577 int action) 578 { 579 struct cs8409_spec *spec = codec->spec; 580 struct sub_codec *cs42l42; 581 int i; 582 bool mute; 583 584 switch (action) { 585 case HDA_GEN_PCM_ACT_PREPARE: 586 mute = false; 587 spec->playback_started = 1; 588 break; 589 case HDA_GEN_PCM_ACT_CLEANUP: 590 mute = true; 591 spec->playback_started = 0; 592 break; 593 default: 594 return; 595 } 596 597 for (i = 0; i < spec->num_scodecs; i++) { 598 cs42l42 = spec->scodecs[i]; 599 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute); 600 } 601 } 602 603 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo, 604 struct hda_codec *codec, 605 struct snd_pcm_substream *substream, 606 int action) 607 { 608 struct cs8409_spec *spec = codec->spec; 609 struct sub_codec *cs42l42; 610 int i; 611 bool mute; 612 613 switch (action) { 614 case HDA_GEN_PCM_ACT_PREPARE: 615 mute = false; 616 spec->capture_started = 1; 617 break; 618 case HDA_GEN_PCM_ACT_CLEANUP: 619 mute = true; 620 spec->capture_started = 0; 621 break; 622 default: 623 return; 624 } 625 626 for (i = 0; i < spec->num_scodecs; i++) { 627 cs42l42 = spec->scodecs[i]; 628 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute); 629 } 630 } 631 632 /* Configure CS42L42 slave codec for jack autodetect */ 633 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42) 634 { 635 cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz); 636 /* Clear WAKE# */ 637 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1); 638 /* Wait ~2.5ms */ 639 usleep_range(2500, 3000); 640 /* Set mode WAKE# output follows the combination logic directly */ 641 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0); 642 /* Clear interrupts status */ 643 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 644 /* Enable interrupt */ 645 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); 646 } 647 648 /* Enable and run CS42L42 slave codec jack auto detect */ 649 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42) 650 { 651 /* Clear interrupts */ 652 cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); 653 cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1); 654 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF); 655 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 656 657 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87); 658 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86); 659 cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07); 660 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD); 661 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); 662 /* Wait ~20ms*/ 663 usleep_range(20000, 25000); 664 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77); 665 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0); 666 } 667 668 static int cs42l42_manual_hs_det(struct sub_codec *cs42l42) 669 { 670 unsigned int hs_det_status; 671 unsigned int hs_det_comp1; 672 unsigned int hs_det_comp2; 673 unsigned int hs_det_sw; 674 unsigned int hs_type; 675 676 /* Set hs detect to manual, active mode */ 677 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 678 (1 << CS42L42_HSDET_CTRL_SHIFT) | 679 (0 << CS42L42_HSDET_SET_SHIFT) | 680 (0 << CS42L42_HSBIAS_REF_SHIFT) | 681 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 682 683 /* Configure HS DET comparator reference levels. */ 684 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 685 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 686 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 687 688 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 689 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 690 691 msleep(100); 692 693 hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 694 695 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 696 CS42L42_HSDET_COMP1_OUT_SHIFT; 697 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 698 CS42L42_HSDET_COMP2_OUT_SHIFT; 699 700 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 701 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 702 703 msleep(100); 704 705 hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 706 707 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 708 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 709 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 710 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 711 712 /* Use Comparator 1 with 1.25V Threshold. */ 713 switch (hs_det_comp1) { 714 case CS42L42_HSDET_COMP_TYPE1: 715 hs_type = CS42L42_PLUG_CTIA; 716 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 717 break; 718 case CS42L42_HSDET_COMP_TYPE2: 719 hs_type = CS42L42_PLUG_OMTP; 720 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 721 break; 722 default: 723 /* Fallback to Comparator 2 with 1.75V Threshold. */ 724 switch (hs_det_comp2) { 725 case CS42L42_HSDET_COMP_TYPE1: 726 hs_type = CS42L42_PLUG_CTIA; 727 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 728 break; 729 case CS42L42_HSDET_COMP_TYPE2: 730 hs_type = CS42L42_PLUG_OMTP; 731 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 732 break; 733 case CS42L42_HSDET_COMP_TYPE3: 734 hs_type = CS42L42_PLUG_HEADPHONE; 735 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 736 break; 737 default: 738 hs_type = CS42L42_PLUG_INVALID; 739 hs_det_sw = CS42L42_HSDET_SW_TYPE4; 740 break; 741 } 742 } 743 744 /* Set Switches */ 745 cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw); 746 747 /* Set HSDET mode to Manual—Disabled */ 748 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 749 (0 << CS42L42_HSDET_CTRL_SHIFT) | 750 (0 << CS42L42_HSDET_SET_SHIFT) | 751 (0 << CS42L42_HSBIAS_REF_SHIFT) | 752 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 753 754 /* Configure HS DET comparator reference levels. */ 755 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 756 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 757 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 758 759 return hs_type; 760 } 761 762 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status) 763 { 764 int status_changed = 0; 765 766 /* TIP_SENSE INSERT/REMOVE */ 767 switch (reg_ts_status) { 768 case CS42L42_TS_PLUG: 769 if (cs42l42->no_type_dect) { 770 status_changed = 1; 771 cs42l42->hp_jack_in = 1; 772 cs42l42->mic_jack_in = 0; 773 } else { 774 cs42l42_run_jack_detect(cs42l42); 775 } 776 break; 777 778 case CS42L42_TS_UNPLUG: 779 status_changed = 1; 780 cs42l42->hp_jack_in = 0; 781 cs42l42->mic_jack_in = 0; 782 break; 783 default: 784 /* jack in transition */ 785 break; 786 } 787 788 codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status); 789 790 return status_changed; 791 } 792 793 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42) 794 { 795 int current_plug_status; 796 int status_changed = 0; 797 int reg_cdc_status; 798 int reg_hs_status; 799 int reg_ts_status; 800 int type; 801 802 /* Read jack detect status registers */ 803 reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); 804 reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 805 reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 806 807 /* If status values are < 0, read error has occurred. */ 808 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0) 809 return -EIO; 810 811 current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) 812 >> CS42L42_TS_PLUG_SHIFT; 813 814 /* HSDET_AUTO_DONE */ 815 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) { 816 817 /* Disable HSDET_AUTO_DONE */ 818 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF); 819 820 type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT; 821 822 /* Configure the HSDET mode. */ 823 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); 824 825 if (cs42l42->no_type_dect) { 826 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); 827 } else { 828 if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) { 829 codec_dbg(cs42l42->codec, 830 "Auto detect value not valid (%d), running manual det\n", 831 type); 832 type = cs42l42_manual_hs_det(cs42l42); 833 } 834 835 switch (type) { 836 case CS42L42_PLUG_CTIA: 837 case CS42L42_PLUG_OMTP: 838 status_changed = 1; 839 cs42l42->hp_jack_in = 1; 840 cs42l42->mic_jack_in = 1; 841 break; 842 case CS42L42_PLUG_HEADPHONE: 843 status_changed = 1; 844 cs42l42->hp_jack_in = 1; 845 cs42l42->mic_jack_in = 0; 846 break; 847 default: 848 status_changed = 1; 849 cs42l42->hp_jack_in = 0; 850 cs42l42->mic_jack_in = 0; 851 break; 852 } 853 codec_dbg(cs42l42->codec, "Detection done (%d)\n", type); 854 } 855 856 /* Enable the HPOUT ground clamp and configure the HP pull-down */ 857 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02); 858 /* Re-Enable Tip Sense Interrupt */ 859 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); 860 } else { 861 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); 862 } 863 864 return status_changed; 865 } 866 867 static void cs42l42_resume(struct sub_codec *cs42l42) 868 { 869 struct hda_codec *codec = cs42l42->codec; 870 struct cs8409_spec *spec = codec->spec; 871 struct cs8409_i2c_param irq_regs[] = { 872 { CS42L42_CODEC_STATUS, 0x00 }, 873 { CS42L42_DET_INT_STATUS1, 0x00 }, 874 { CS42L42_DET_INT_STATUS2, 0x00 }, 875 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 876 }; 877 unsigned int fsv; 878 879 /* Bring CS42L42 out of Reset */ 880 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); 881 spec->gpio_data |= cs42l42->reset_gpio; 882 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 883 usleep_range(10000, 15000); 884 885 cs42l42->suspended = 0; 886 887 /* Initialize CS42L42 companion codec */ 888 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num); 889 890 /* Clear interrupts, by reading interrupt status registers */ 891 cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs)); 892 893 fsv = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL); 894 if (cs42l42->full_scale_vol) { 895 // Set the full scale volume bit 896 fsv |= CS42L42_FULL_SCALE_VOL_MASK; 897 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv); 898 } 899 // Unmute analog channels A and B 900 fsv = (fsv & ~CS42L42_ANA_MUTE_AB); 901 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv); 902 903 /* we have to explicitly allow unsol event handling even during the 904 * resume phase so that the jack event is processed properly 905 */ 906 snd_hda_codec_allow_unsol_events(cs42l42->codec); 907 908 cs42l42_enable_jack_detect(cs42l42); 909 } 910 911 static void cs42l42_suspend(struct sub_codec *cs42l42) 912 { 913 struct hda_codec *codec = cs42l42->codec; 914 struct cs8409_spec *spec = codec->spec; 915 int reg_cdc_status = 0; 916 const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = { 917 { CS42L42_DAC_CTL2, 0x02 }, 918 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 919 { CS42L42_MIXER_CHA_VOL, 0x3F }, 920 { CS42L42_MIXER_ADC_VOL, 0x3F }, 921 { CS42L42_MIXER_CHB_VOL, 0x3F }, 922 { CS42L42_HP_CTL, 0x0D }, 923 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 924 { CS42L42_ASP_CLK_CFG, 0x00 }, 925 { CS42L42_PWR_CTL1, 0xFE }, 926 { CS42L42_PWR_CTL2, 0x8C }, 927 { CS42L42_PWR_CTL1, 0xFF }, 928 }; 929 930 cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq)); 931 932 if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status, 933 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US, 934 true, cs42l42, CS42L42_CODEC_STATUS) < 0) 935 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n"); 936 937 /* Power down CS42L42 ASP/EQ/MIX/HP */ 938 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C); 939 cs42l42->suspended = 1; 940 cs42l42->last_page = 0; 941 cs42l42->hp_jack_in = 0; 942 cs42l42->mic_jack_in = 0; 943 944 /* Put CS42L42 into Reset */ 945 spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); 946 spec->gpio_data &= ~cs42l42->reset_gpio; 947 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 948 } 949 950 static void cs8409_remove(struct hda_codec *codec) 951 { 952 struct cs8409_spec *spec = codec->spec; 953 954 /* Cancel i2c clock disable timer, and disable clock if left enabled */ 955 cancel_delayed_work_sync(&spec->i2c_clk_work); 956 cs8409_disable_i2c_clock(codec); 957 958 snd_hda_gen_remove(codec); 959 } 960 961 /****************************************************************************** 962 * BULLSEYE / WARLOCK / CYBORG Specific Functions 963 * CS8409/CS42L42 964 ******************************************************************************/ 965 966 /* 967 * In the case of CS8409 we do not have unsolicited events from NID's 0x24 968 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will 969 * generate interrupt via gpio 4 to notify jack events. We have to overwrite 970 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers 971 * and then notify status via generic snd_hda_jack_unsol_event() call. 972 */ 973 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res) 974 { 975 struct cs8409_spec *spec = codec->spec; 976 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 977 struct hda_jack_tbl *jk; 978 979 /* jack_unsol_event() will be called every time gpio line changing state. 980 * In this case gpio4 line goes up as a result of reading interrupt status 981 * registers in previous cs8409_jack_unsol_event() call. 982 * We don't need to handle this event, ignoring... 983 */ 984 if (res & cs42l42->irq_mask) 985 return; 986 987 if (cs42l42_jack_unsol_event(cs42l42)) { 988 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID, 989 cs42l42->hp_jack_in ? 0 : PIN_OUT); 990 /* Report jack*/ 991 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0); 992 if (jk) 993 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 994 AC_UNSOL_RES_TAG); 995 /* Report jack*/ 996 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0); 997 if (jk) 998 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 999 AC_UNSOL_RES_TAG); 1000 } 1001 } 1002 1003 static void cs8409_unsol_event(struct hda_codec *codec, unsigned int res) 1004 { 1005 struct cs8409_spec *spec = codec->spec; 1006 1007 if (spec->unsol_event) 1008 spec->unsol_event(codec, res); 1009 else 1010 cs8409_cs42l42_jack_unsol_event(codec, res); 1011 } 1012 1013 /* Manage PDREF, when transition to D3hot */ 1014 static int cs8409_cs42l42_suspend(struct hda_codec *codec) 1015 { 1016 struct cs8409_spec *spec = codec->spec; 1017 int i; 1018 1019 spec->init_done = 0; 1020 1021 cs8409_enable_ur(codec, 0); 1022 1023 for (i = 0; i < spec->num_scodecs; i++) 1024 cs42l42_suspend(spec->scodecs[i]); 1025 1026 /* Cancel i2c clock disable timer, and disable clock if left enabled */ 1027 cancel_delayed_work_sync(&spec->i2c_clk_work); 1028 cs8409_disable_i2c_clock(codec); 1029 1030 snd_hda_shutup_pins(codec); 1031 1032 return 0; 1033 } 1034 1035 /* Vendor specific HW configuration 1036 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... 1037 */ 1038 static void cs8409_cs42l42_hw_init(struct hda_codec *codec) 1039 { 1040 const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg; 1041 const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn; 1042 struct cs8409_spec *spec = codec->spec; 1043 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 1044 1045 if (spec->gpio_mask) 1046 snd_hda_codec_set_gpio(codec, spec->gpio_mask, spec->gpio_dir, 1047 spec->gpio_data, 0); 1048 1049 for (; seq->nid; seq++) 1050 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); 1051 1052 if (codec->fixup_id == CS8409_BULLSEYE) { 1053 for (; seq_bullseye->nid; seq_bullseye++) 1054 cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff); 1055 } 1056 1057 switch (codec->fixup_id) { 1058 case CS8409_CYBORG: 1059 case CS8409_WARLOCK_MLK_DUAL_MIC: 1060 /* DMIC1_MO=00b, DMIC1/2_SR=1 */ 1061 cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003); 1062 break; 1063 case CS8409_ODIN: 1064 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */ 1065 cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00); 1066 break; 1067 default: 1068 break; 1069 } 1070 1071 cs42l42_resume(cs42l42); 1072 1073 /* Enable Unsolicited Response */ 1074 cs8409_enable_ur(codec, 1); 1075 } 1076 1077 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 1078 unsigned int *res) 1079 { 1080 struct hda_codec *codec = container_of(dev, struct hda_codec, core); 1081 struct cs8409_spec *spec = codec->spec; 1082 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 1083 1084 unsigned int nid = ((cmd >> 20) & 0x07f); 1085 unsigned int verb = ((cmd >> 8) & 0x0fff); 1086 1087 /* CS8409 pins have no AC_PINSENSE_PRESENCE 1088 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34 1089 * and return correct pin sense values for read_pin_sense() call from 1090 * hda_jack based on CS42L42 jack detect status. 1091 */ 1092 switch (nid) { 1093 case CS8409_CS42L42_HP_PIN_NID: 1094 if (verb == AC_VERB_GET_PIN_SENSE) { 1095 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; 1096 return 0; 1097 } 1098 break; 1099 case CS8409_CS42L42_AMIC_PIN_NID: 1100 if (verb == AC_VERB_GET_PIN_SENSE) { 1101 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; 1102 return 0; 1103 } 1104 break; 1105 default: 1106 break; 1107 } 1108 1109 return spec->exec_verb(dev, cmd, flags, res); 1110 } 1111 1112 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) 1113 { 1114 struct cs8409_spec *spec = codec->spec; 1115 1116 switch (action) { 1117 case HDA_FIXUP_ACT_PRE_PROBE: 1118 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs); 1119 /* verb exec op override */ 1120 spec->exec_verb = codec->core.exec_verb; 1121 codec->core.exec_verb = cs8409_cs42l42_exec_verb; 1122 1123 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec; 1124 spec->num_scodecs = 1; 1125 spec->scodecs[CS8409_CODEC0]->codec = codec; 1126 1127 spec->gen.suppress_auto_mute = 1; 1128 spec->gen.no_primary_hp = 1; 1129 spec->gen.suppress_vmaster = 1; 1130 1131 spec->speaker_pdn_gpio = 0; 1132 1133 /* GPIO 5 out, 3,4 in */ 1134 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio; 1135 spec->gpio_data = 0; 1136 spec->gpio_mask = 0x03f; 1137 1138 /* Basic initial sequence for specific hw configuration */ 1139 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs); 1140 1141 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID); 1142 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID); 1143 1144 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020; 1145 1146 switch (codec->fixup_id) { 1147 case CS8409_CYBORG: 1148 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1149 CS42L42_FULL_SCALE_VOL_MINUS6DB; 1150 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; 1151 break; 1152 case CS8409_ODIN: 1153 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; 1154 spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; 1155 break; 1156 case CS8409_WARLOCK_MLK: 1157 case CS8409_WARLOCK_MLK_DUAL_MIC: 1158 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; 1159 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; 1160 break; 1161 default: 1162 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1163 CS42L42_FULL_SCALE_VOL_MINUS6DB; 1164 spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; 1165 break; 1166 } 1167 1168 if (spec->speaker_pdn_gpio > 0) { 1169 spec->gpio_dir |= spec->speaker_pdn_gpio; 1170 spec->gpio_data |= spec->speaker_pdn_gpio; 1171 } 1172 1173 break; 1174 case HDA_FIXUP_ACT_PROBE: 1175 /* Fix Sample Rate to 48kHz */ 1176 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; 1177 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; 1178 /* add hooks */ 1179 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; 1180 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; 1181 if (codec->fixup_id != CS8409_ODIN) 1182 /* Set initial DMIC volume to -26 dB */ 1183 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID, 1184 HDA_INPUT, 0, 0xff, 0x19); 1185 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", 1186 &cs42l42_dac_volume_mixer); 1187 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", 1188 &cs42l42_adc_volume_mixer); 1189 if (spec->speaker_pdn_gpio > 0) 1190 snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch", 1191 &cs8409_spk_sw_ctrl); 1192 /* Disable Unsolicited Response during boot */ 1193 cs8409_enable_ur(codec, 0); 1194 snd_hda_codec_set_name(codec, "CS8409/CS42L42"); 1195 break; 1196 case HDA_FIXUP_ACT_INIT: 1197 cs8409_cs42l42_hw_init(codec); 1198 spec->init_done = 1; 1199 if (spec->init_done && spec->build_ctrl_done 1200 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) 1201 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); 1202 break; 1203 case HDA_FIXUP_ACT_BUILD: 1204 spec->build_ctrl_done = 1; 1205 /* Run jack auto detect first time on boot 1206 * after controls have been added, to check if jack has 1207 * been already plugged in. 1208 * Run immediately after init. 1209 */ 1210 if (spec->init_done && spec->build_ctrl_done 1211 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) 1212 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); 1213 break; 1214 default: 1215 break; 1216 } 1217 } 1218 1219 static int cs8409_comp_bind(struct device *dev) 1220 { 1221 struct hda_codec *codec = dev_to_hda_codec(dev); 1222 struct cs8409_spec *spec = codec->spec; 1223 1224 return hda_component_manager_bind(codec, &spec->comps); 1225 } 1226 1227 static void cs8409_comp_unbind(struct device *dev) 1228 { 1229 struct hda_codec *codec = dev_to_hda_codec(dev); 1230 struct cs8409_spec *spec = codec->spec; 1231 1232 hda_component_manager_unbind(codec, &spec->comps); 1233 } 1234 1235 static const struct component_master_ops cs8409_comp_master_ops = { 1236 .bind = cs8409_comp_bind, 1237 .unbind = cs8409_comp_unbind, 1238 }; 1239 1240 static void cs8409_comp_playback_hook(struct hda_pcm_stream *hinfo, struct hda_codec *codec, 1241 struct snd_pcm_substream *sub, int action) 1242 { 1243 struct cs8409_spec *spec = codec->spec; 1244 1245 hda_component_manager_playback_hook(&spec->comps, action); 1246 } 1247 1248 static void cs8409_cdb35l56_four_hw_init(struct hda_codec *codec) 1249 { 1250 const struct cs8409_cir_param *seq = cs8409_cdb35l56_four_hw_cfg; 1251 1252 for (; seq->nid; seq++) 1253 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); 1254 } 1255 1256 static int cs8409_spk_sw_get(struct snd_kcontrol *kcontrol, 1257 struct snd_ctl_elem_value *ucontrol) 1258 { 1259 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 1260 struct cs8409_spec *spec = codec->spec; 1261 1262 ucontrol->value.integer.value[0] = !spec->speaker_muted; 1263 1264 return 0; 1265 } 1266 1267 static int cs8409_spk_sw_put(struct snd_kcontrol *kcontrol, 1268 struct snd_ctl_elem_value *ucontrol) 1269 { 1270 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 1271 struct cs8409_spec *spec = codec->spec; 1272 bool muted = !ucontrol->value.integer.value[0]; 1273 1274 if (muted == spec->speaker_muted) 1275 return 0; 1276 1277 spec->speaker_muted = muted; 1278 1279 return 1; 1280 } 1281 1282 static const struct snd_kcontrol_new cs8409_spk_sw_component_ctrl = { 1283 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1284 .info = snd_ctl_boolean_mono_info, 1285 .get = cs8409_spk_sw_get, 1286 .put = cs8409_spk_sw_put, 1287 }; 1288 1289 void cs8409_cdb35l56_four_autodet_fixup(struct hda_codec *codec, 1290 const struct hda_fixup *fix, 1291 int action) 1292 { 1293 struct device *dev = hda_codec_dev(codec); 1294 struct cs8409_spec *spec = codec->spec; 1295 struct acpi_device *adev; 1296 const char *bus = NULL; 1297 static const struct { 1298 const char *hid; 1299 const char *name; 1300 } acpi_ids[] = {{ "CSC3554", "cs35l54-hda" }, 1301 { "CSC3556", "cs35l56-hda" }, 1302 { "CSC3557", "cs35l57-hda" }}; 1303 char *match; 1304 int i, count = 0, count_devindex = 0; 1305 int ret; 1306 1307 switch (action) { 1308 case HDA_FIXUP_ACT_PRE_PROBE: { 1309 for (i = 0; i < ARRAY_SIZE(acpi_ids); ++i) { 1310 adev = acpi_dev_get_first_match_dev(acpi_ids[i].hid, NULL, -1); 1311 if (adev) 1312 break; 1313 } 1314 if (!adev) { 1315 dev_err(dev, "Failed to find ACPI entry for a Cirrus Amp\n"); 1316 return; 1317 } 1318 1319 count = i2c_acpi_client_count(adev); 1320 if (count > 0) { 1321 bus = "i2c"; 1322 } else { 1323 count = acpi_spi_count_resources(adev); 1324 if (count > 0) 1325 bus = "spi"; 1326 } 1327 1328 struct fwnode_handle *fwnode __free(fwnode_handle) = 1329 fwnode_handle_get(acpi_fwnode_handle(adev)); 1330 acpi_dev_put(adev); 1331 1332 if (!bus) { 1333 dev_err(dev, "Did not find any buses for %s\n", acpi_ids[i].hid); 1334 return; 1335 } 1336 1337 if (!fwnode) { 1338 dev_err(dev, "Could not get fwnode for %s\n", acpi_ids[i].hid); 1339 return; 1340 } 1341 1342 /* 1343 * When available the cirrus,dev-index property is an accurate 1344 * count of the amps in a system and is used in preference to 1345 * the count of bus devices that can contain additional address 1346 * alias entries. 1347 */ 1348 count_devindex = fwnode_property_count_u32(fwnode, "cirrus,dev-index"); 1349 if (count_devindex > 0) 1350 count = count_devindex; 1351 1352 match = devm_kasprintf(dev, GFP_KERNEL, "-%%s:00-%s.%%d", acpi_ids[i].name); 1353 if (!match) 1354 return; 1355 dev_info(dev, "Found %d %s on %s (%s)\n", count, acpi_ids[i].hid, bus, match); 1356 1357 ret = hda_component_manager_init(codec, &spec->comps, count, bus, 1358 acpi_ids[i].hid, match, 1359 &cs8409_comp_master_ops); 1360 if (ret) 1361 return; 1362 1363 spec->gen.pcm_playback_hook = cs8409_comp_playback_hook; 1364 1365 snd_hda_add_verbs(codec, cs8409_cdb35l56_four_init_verbs); 1366 snd_hda_sequence_write(codec, cs8409_cdb35l56_four_init_verbs); 1367 break; 1368 } 1369 case HDA_FIXUP_ACT_PROBE: 1370 spec->speaker_muted = 0; /* speakers begin enabled */ 1371 snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch", 1372 &cs8409_spk_sw_component_ctrl); 1373 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; 1374 snd_hda_codec_set_name(codec, "CS8409/CS35L56"); 1375 break; 1376 case HDA_FIXUP_ACT_INIT: 1377 cs8409_cdb35l56_four_hw_init(codec); 1378 break; 1379 case HDA_FIXUP_ACT_FREE: 1380 hda_component_manager_free(&spec->comps, &cs8409_comp_master_ops); 1381 break; 1382 } 1383 } 1384 1385 /****************************************************************************** 1386 * Dolphin Specific Functions 1387 * CS8409/ 2 X CS42L42 1388 ******************************************************************************/ 1389 1390 /* 1391 * In the case of CS8409 we do not have unsolicited events when 1392 * hs mic and hp are connected. Companion codec CS42L42 will 1393 * generate interrupt via irq_mask to notify jack events. We have to overwrite 1394 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers 1395 * and then notify status via generic snd_hda_jack_unsol_event() call. 1396 */ 1397 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res) 1398 { 1399 struct cs8409_spec *spec = codec->spec; 1400 struct sub_codec *cs42l42; 1401 struct hda_jack_tbl *jk; 1402 1403 cs42l42 = spec->scodecs[CS8409_CODEC0]; 1404 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && 1405 cs42l42_jack_unsol_event(cs42l42)) { 1406 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0); 1407 if (jk) 1408 snd_hda_jack_unsol_event(codec, 1409 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 1410 AC_UNSOL_RES_TAG); 1411 1412 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0); 1413 if (jk) 1414 snd_hda_jack_unsol_event(codec, 1415 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 1416 AC_UNSOL_RES_TAG); 1417 } 1418 1419 cs42l42 = spec->scodecs[CS8409_CODEC1]; 1420 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && 1421 cs42l42_jack_unsol_event(cs42l42)) { 1422 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0); 1423 if (jk) 1424 snd_hda_jack_unsol_event(codec, 1425 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 1426 AC_UNSOL_RES_TAG); 1427 } 1428 } 1429 1430 /* Vendor specific HW configuration 1431 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... 1432 */ 1433 static void dolphin_hw_init(struct hda_codec *codec) 1434 { 1435 const struct cs8409_cir_param *seq = dolphin_hw_cfg; 1436 struct cs8409_spec *spec = codec->spec; 1437 struct sub_codec *cs42l42; 1438 int i; 1439 1440 if (spec->gpio_mask) 1441 snd_hda_codec_set_gpio(codec, spec->gpio_mask, spec->gpio_dir, 1442 spec->gpio_data, 0); 1443 1444 for (; seq->nid; seq++) 1445 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); 1446 1447 for (i = 0; i < spec->num_scodecs; i++) { 1448 cs42l42 = spec->scodecs[i]; 1449 cs42l42_resume(cs42l42); 1450 } 1451 1452 /* Enable Unsolicited Response */ 1453 cs8409_enable_ur(codec, 1); 1454 } 1455 1456 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 1457 unsigned int *res) 1458 { 1459 struct hda_codec *codec = container_of(dev, struct hda_codec, core); 1460 struct cs8409_spec *spec = codec->spec; 1461 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 1462 1463 unsigned int nid = ((cmd >> 20) & 0x07f); 1464 unsigned int verb = ((cmd >> 8) & 0x0fff); 1465 1466 /* CS8409 pins have no AC_PINSENSE_PRESENCE 1467 * capabilities. We have to intercept calls for CS42L42 pins 1468 * and return correct pin sense values for read_pin_sense() call from 1469 * hda_jack based on CS42L42 jack detect status. 1470 */ 1471 switch (nid) { 1472 case DOLPHIN_HP_PIN_NID: 1473 case DOLPHIN_LO_PIN_NID: 1474 if (nid == DOLPHIN_LO_PIN_NID) 1475 cs42l42 = spec->scodecs[CS8409_CODEC1]; 1476 if (verb == AC_VERB_GET_PIN_SENSE) { 1477 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; 1478 return 0; 1479 } 1480 break; 1481 case DOLPHIN_AMIC_PIN_NID: 1482 if (verb == AC_VERB_GET_PIN_SENSE) { 1483 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; 1484 return 0; 1485 } 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 return spec->exec_verb(dev, cmd, flags, res); 1492 } 1493 1494 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) 1495 { 1496 struct cs8409_spec *spec = codec->spec; 1497 struct snd_kcontrol_new *kctrl; 1498 int i; 1499 1500 switch (action) { 1501 case HDA_FIXUP_ACT_PRE_PROBE: 1502 snd_hda_add_verbs(codec, dolphin_init_verbs); 1503 /* verb exec op override */ 1504 spec->exec_verb = codec->core.exec_verb; 1505 codec->core.exec_verb = dolphin_exec_verb; 1506 1507 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0; 1508 spec->scodecs[CS8409_CODEC0]->codec = codec; 1509 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1; 1510 spec->scodecs[CS8409_CODEC1]->codec = codec; 1511 spec->num_scodecs = 2; 1512 spec->gen.suppress_vmaster = 1; 1513 1514 spec->unsol_event = dolphin_jack_unsol_event; 1515 1516 /* GPIO 1,5 out, 0,4 in */ 1517 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio | 1518 spec->scodecs[CS8409_CODEC1]->reset_gpio; 1519 spec->gpio_data = 0; 1520 spec->gpio_mask = 0x03f; 1521 1522 /* Basic initial sequence for specific hw configuration */ 1523 snd_hda_sequence_write(codec, dolphin_init_verbs); 1524 1525 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true, 1526 SND_JACK_HEADPHONE, NULL); 1527 1528 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true, 1529 SND_JACK_MICROPHONE, NULL); 1530 1531 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID); 1532 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID); 1533 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID); 1534 1535 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; 1536 spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; 1537 1538 break; 1539 case HDA_FIXUP_ACT_PROBE: 1540 /* Fix Sample Rate to 48kHz */ 1541 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; 1542 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; 1543 /* add hooks */ 1544 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; 1545 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; 1546 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", 1547 &cs42l42_dac_volume_mixer); 1548 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer); 1549 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume", 1550 &cs42l42_dac_volume_mixer); 1551 /* Update Line Out kcontrol template */ 1552 if (kctrl) 1553 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1, 1554 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE; 1555 cs8409_enable_ur(codec, 0); 1556 snd_hda_codec_set_name(codec, "CS8409/CS42L42"); 1557 break; 1558 case HDA_FIXUP_ACT_INIT: 1559 dolphin_hw_init(codec); 1560 spec->init_done = 1; 1561 if (spec->init_done && spec->build_ctrl_done) { 1562 for (i = 0; i < spec->num_scodecs; i++) { 1563 if (!spec->scodecs[i]->hp_jack_in) 1564 cs42l42_run_jack_detect(spec->scodecs[i]); 1565 } 1566 } 1567 break; 1568 case HDA_FIXUP_ACT_BUILD: 1569 spec->build_ctrl_done = 1; 1570 /* Run jack auto detect first time on boot 1571 * after controls have been added, to check if jack has 1572 * been already plugged in. 1573 * Run immediately after init. 1574 */ 1575 if (spec->init_done && spec->build_ctrl_done) { 1576 for (i = 0; i < spec->num_scodecs; i++) { 1577 if (!spec->scodecs[i]->hp_jack_in) 1578 cs42l42_run_jack_detect(spec->scodecs[i]); 1579 } 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 } 1586 1587 static int cs8409_probe(struct hda_codec *codec, const struct hda_device_id *id) 1588 { 1589 int err; 1590 1591 if (!cs8409_alloc_spec(codec)) 1592 return -ENOMEM; 1593 1594 snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups); 1595 1596 codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id, 1597 codec->bus->pci->subsystem_vendor, 1598 codec->bus->pci->subsystem_device); 1599 1600 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 1601 1602 err = cs8409_parse_auto_config(codec); 1603 if (err < 0) { 1604 cs8409_remove(codec); 1605 return err; 1606 } 1607 1608 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 1609 return 0; 1610 } 1611 1612 static const struct hda_codec_ops cs8409_codec_ops = { 1613 .probe = cs8409_probe, 1614 .remove = cs8409_remove, 1615 .build_controls = cs8409_build_controls, 1616 .build_pcms = snd_hda_gen_build_pcms, 1617 .init = cs8409_init, 1618 .unsol_event = cs8409_unsol_event, 1619 .suspend = cs8409_cs42l42_suspend, 1620 .stream_pm = snd_hda_gen_stream_pm, 1621 }; 1622 1623 static const struct hda_device_id snd_hda_id_cs8409[] = { 1624 HDA_CODEC_ID(0x10138409, "CS8409"), 1625 {} /* terminator */ 1626 }; 1627 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409); 1628 1629 static struct hda_codec_driver cs8409_driver = { 1630 .id = snd_hda_id_cs8409, 1631 .ops = &cs8409_codec_ops, 1632 }; 1633 module_hda_codec_driver(cs8409_driver); 1634 1635 MODULE_LICENSE("GPL"); 1636 MODULE_DESCRIPTION("Cirrus Logic HDA bridge"); 1637 MODULE_IMPORT_NS("SND_HDA_SCODEC_COMPONENT"); 1638