1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Components shared between ASoC and HDA CS35L56 drivers
4 //
5 // Copyright (C) 2023 Cirrus Logic, Inc. and
6 // Cirrus Logic International Semiconductor Ltd.
7
8 #include <linux/array_size.h>
9 #include <linux/firmware/cirrus/wmfw.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/spi/spi.h>
14 #include <linux/types.h>
15 #include <sound/cs-amp-lib.h>
16
17 #include "cs35l56.h"
18
19 static const struct reg_sequence cs35l56_patch[] = {
20 /*
21 * Firmware can change these to non-defaults to satisfy SDCA.
22 * Ensure that they are at known defaults.
23 */
24 { CS35L56_ASP1_ENABLES1, 0x00000000 },
25 { CS35L56_ASP1_CONTROL1, 0x00000028 },
26 { CS35L56_ASP1_CONTROL2, 0x18180200 },
27 { CS35L56_ASP1_CONTROL3, 0x00000002 },
28 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
29 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
30 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
31 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
32 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
33 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
34 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
35 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
36 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
37 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
38 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
39 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
40 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
41 };
42
43 static const struct reg_sequence cs35l56_patch_fw[] = {
44 /* These are not reset by a soft-reset, so patch to defaults. */
45 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
46 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
47 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
48 };
49
50 static const struct reg_sequence cs35l63_patch_fw[] = {
51 /* These are not reset by a soft-reset, so patch to defaults. */
52 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 },
53 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 },
54 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 },
55 };
56
cs35l56_set_patch(struct cs35l56_base * cs35l56_base)57 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
58 {
59 int ret;
60
61 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch,
62 ARRAY_SIZE(cs35l56_patch));
63 if (ret)
64 return ret;
65
66
67 switch (cs35l56_base->type) {
68 case 0x54:
69 case 0x56:
70 case 0x57:
71 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw,
72 ARRAY_SIZE(cs35l56_patch_fw));
73 break;
74 case 0x63:
75 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw,
76 ARRAY_SIZE(cs35l63_patch_fw));
77 break;
78 default:
79 break;
80 }
81
82 return ret;
83 }
84 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED");
85
86 static const struct reg_default cs35l56_reg_defaults[] = {
87 /* no defaults for OTP_MEM - first read populates cache */
88
89 { CS35L56_ASP1_ENABLES1, 0x00000000 },
90 { CS35L56_ASP1_CONTROL1, 0x00000028 },
91 { CS35L56_ASP1_CONTROL2, 0x18180200 },
92 { CS35L56_ASP1_CONTROL3, 0x00000002 },
93 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
94 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
95 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
96 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
97 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
98 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
99 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
100 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
101 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
102 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
103 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
104 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
105 { CS35L56_IRQ1_MASK_1, 0x83ffffff },
106 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
107 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
108 { CS35L56_IRQ1_MASK_8, 0xfc000fff },
109 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff },
110 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
111 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 },
112 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 },
113 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 },
114 };
115
116 static const struct reg_default cs35l63_reg_defaults[] = {
117 /* no defaults for OTP_MEM - first read populates cache */
118
119 { CS35L56_ASP1_ENABLES1, 0x00000000 },
120 { CS35L56_ASP1_CONTROL1, 0x00000028 },
121 { CS35L56_ASP1_CONTROL2, 0x18180200 },
122 { CS35L56_ASP1_CONTROL3, 0x00000002 },
123 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },
124 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },
125 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },
126 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },
127 { CS35L56_ASP1TX1_INPUT, 0x00000000 },
128 { CS35L56_ASP1TX2_INPUT, 0x00000000 },
129 { CS35L56_ASP1TX3_INPUT, 0x00000000 },
130 { CS35L56_ASP1TX4_INPUT, 0x00000000 },
131 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },
132 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },
133 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },
134 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 },
135 { CS35L56_IRQ1_MASK_1, 0x8003ffff },
136 { CS35L56_IRQ1_MASK_2, 0xffff7fff },
137 { CS35L56_IRQ1_MASK_4, 0xe0ffffff },
138 { CS35L56_IRQ1_MASK_8, 0x8c000fff },
139 { CS35L56_IRQ1_MASK_18, 0x0760f000 },
140 { CS35L56_IRQ1_MASK_20, 0x15c00000 },
141 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 },
142 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 },
143 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 },
144 };
145
cs35l56_is_dsp_memory(unsigned int reg)146 static bool cs35l56_is_dsp_memory(unsigned int reg)
147 {
148 switch (reg) {
149 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
150 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095:
151 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191:
152 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
153 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070:
154 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141:
155 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
156 return true;
157 default:
158 return false;
159 }
160 }
161
cs35l56_readable_reg(struct device * dev,unsigned int reg)162 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg)
163 {
164 switch (reg) {
165 case CS35L56_DEVID:
166 case CS35L56_REVID:
167 case CS35L56_RELID:
168 case CS35L56_OTPID:
169 case CS35L56_SFT_RESET:
170 case CS35L56_GLOBAL_ENABLES:
171 case CS35L56_BLOCK_ENABLES:
172 case CS35L56_BLOCK_ENABLES2:
173 case CS35L56_REFCLK_INPUT:
174 case CS35L56_GLOBAL_SAMPLE_RATE:
175 case CS35L56_OTP_MEM_53:
176 case CS35L56_OTP_MEM_54:
177 case CS35L56_OTP_MEM_55:
178 case CS35L56_ASP1_ENABLES1:
179 case CS35L56_ASP1_CONTROL1:
180 case CS35L56_ASP1_CONTROL2:
181 case CS35L56_ASP1_CONTROL3:
182 case CS35L56_ASP1_FRAME_CONTROL1:
183 case CS35L56_ASP1_FRAME_CONTROL5:
184 case CS35L56_ASP1_DATA_CONTROL1:
185 case CS35L56_ASP1_DATA_CONTROL5:
186 case CS35L56_DACPCM1_INPUT:
187 case CS35L56_DACPCM2_INPUT:
188 case CS35L56_ASP1TX1_INPUT:
189 case CS35L56_ASP1TX2_INPUT:
190 case CS35L56_ASP1TX3_INPUT:
191 case CS35L56_ASP1TX4_INPUT:
192 case CS35L56_DSP1RX1_INPUT:
193 case CS35L56_DSP1RX2_INPUT:
194 case CS35L56_SWIRE_DP3_CH1_INPUT:
195 case CS35L56_SWIRE_DP3_CH2_INPUT:
196 case CS35L56_SWIRE_DP3_CH3_INPUT:
197 case CS35L56_SWIRE_DP3_CH4_INPUT:
198 case CS35L56_IRQ1_CFG:
199 case CS35L56_IRQ1_STATUS:
200 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
201 case CS35L56_IRQ1_EINT_18:
202 case CS35L56_IRQ1_EINT_20:
203 case CS35L56_IRQ1_MASK_1:
204 case CS35L56_IRQ1_MASK_2:
205 case CS35L56_IRQ1_MASK_4:
206 case CS35L56_IRQ1_MASK_8:
207 case CS35L56_IRQ1_MASK_18:
208 case CS35L56_IRQ1_MASK_20:
209 case CS35L56_DSP_VIRTUAL1_MBOX_1:
210 case CS35L56_DSP_VIRTUAL1_MBOX_2:
211 case CS35L56_DSP_VIRTUAL1_MBOX_3:
212 case CS35L56_DSP_VIRTUAL1_MBOX_4:
213 case CS35L56_DSP_VIRTUAL1_MBOX_5:
214 case CS35L56_DSP_VIRTUAL1_MBOX_6:
215 case CS35L56_DSP_VIRTUAL1_MBOX_7:
216 case CS35L56_DSP_VIRTUAL1_MBOX_8:
217 case CS35L56_DIE_STS1:
218 case CS35L56_DIE_STS2:
219 case CS35L56_DSP_RESTRICT_STS1:
220 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
221 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
222 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
223 case CS35L56_DSP1_SCRATCH1:
224 case CS35L56_DSP1_SCRATCH2:
225 case CS35L56_DSP1_SCRATCH3:
226 case CS35L56_DSP1_SCRATCH4:
227 return true;
228 default:
229 return cs35l56_is_dsp_memory(reg);
230 }
231 }
232
cs35l56_precious_reg(struct device * dev,unsigned int reg)233 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
234 {
235 switch (reg) {
236 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143:
237 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604:
238 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114:
239 return true;
240 default:
241 return false;
242 }
243 }
244
cs35l56_common_volatile_reg(unsigned int reg)245 static bool cs35l56_common_volatile_reg(unsigned int reg)
246 {
247 switch (reg) {
248 case CS35L56_DEVID:
249 case CS35L56_REVID:
250 case CS35L56_RELID:
251 case CS35L56_OTPID:
252 case CS35L56_SFT_RESET:
253 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */
254 case CS35L56_BLOCK_ENABLES: /* owned by firmware */
255 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */
256 case CS35L56_REFCLK_INPUT: /* owned by firmware */
257 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */
258 case CS35L56_DACPCM1_INPUT: /* owned by firmware */
259 case CS35L56_DACPCM2_INPUT: /* owned by firmware */
260 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */
261 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */
262 case CS35L56_IRQ1_STATUS:
263 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8:
264 case CS35L56_IRQ1_EINT_18:
265 case CS35L56_IRQ1_EINT_20:
266 case CS35L56_DSP_VIRTUAL1_MBOX_1:
267 case CS35L56_DSP_VIRTUAL1_MBOX_2:
268 case CS35L56_DSP_VIRTUAL1_MBOX_3:
269 case CS35L56_DSP_VIRTUAL1_MBOX_4:
270 case CS35L56_DSP_VIRTUAL1_MBOX_5:
271 case CS35L56_DSP_VIRTUAL1_MBOX_6:
272 case CS35L56_DSP_VIRTUAL1_MBOX_7:
273 case CS35L56_DSP_VIRTUAL1_MBOX_8:
274 case CS35L56_DSP_RESTRICT_STS1:
275 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END:
276 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0:
277 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1:
278 case CS35L56_DSP1_SCRATCH1:
279 case CS35L56_DSP1_SCRATCH2:
280 case CS35L56_DSP1_SCRATCH3:
281 case CS35L56_DSP1_SCRATCH4:
282 return true;
283 default:
284 return cs35l56_is_dsp_memory(reg);
285 }
286 }
287
cs35l56_volatile_reg(struct device * dev,unsigned int reg)288 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
289 {
290 switch (reg) {
291 case CS35L56_MAIN_RENDER_USER_MUTE:
292 case CS35L56_MAIN_RENDER_USER_VOLUME:
293 case CS35L56_MAIN_POSTURE_NUMBER:
294 return false;
295 default:
296 return cs35l56_common_volatile_reg(reg);
297 }
298 }
299
cs35l63_volatile_reg(struct device * dev,unsigned int reg)300 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg)
301 {
302 switch (reg) {
303 case CS35L63_MAIN_RENDER_USER_MUTE:
304 case CS35L63_MAIN_RENDER_USER_VOLUME:
305 case CS35L63_MAIN_POSTURE_NUMBER:
306 return false;
307 default:
308 return cs35l56_common_volatile_reg(reg);
309 }
310 }
311
cs35l56_mbox_send(struct cs35l56_base * cs35l56_base,unsigned int command)312 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)
313 {
314 unsigned int val;
315 int ret;
316
317 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command);
318 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1,
319 val, (val == 0),
320 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US);
321 if (ret) {
322 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret);
323 return ret;
324 }
325
326 return 0;
327 }
328 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED");
329
cs35l56_firmware_shutdown(struct cs35l56_base * cs35l56_base)330 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)
331 {
332 int ret;
333 unsigned int val;
334
335 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);
336 if (ret)
337 return ret;
338
339 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
340 cs35l56_base->fw_reg->pm_cur_stat,
341 val, (val == CS35L56_HALO_STATE_SHUTDOWN),
342 CS35L56_HALO_STATE_POLL_US,
343 CS35L56_HALO_STATE_TIMEOUT_US);
344 if (ret < 0)
345 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n",
346 val, ret);
347 return ret;
348 }
349 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED");
350
cs35l56_wait_for_firmware_boot(struct cs35l56_base * cs35l56_base)351 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)
352 {
353 unsigned int val = 0;
354 int read_ret, poll_ret;
355
356 /*
357 * The regmap must remain in cache-only until the chip has
358 * booted, so use a bypassed read of the status register.
359 */
360 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret,
361 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE),
362 CS35L56_HALO_STATE_POLL_US,
363 CS35L56_HALO_STATE_TIMEOUT_US,
364 false,
365 cs35l56_base->regmap,
366 cs35l56_base->fw_reg->halo_state,
367 &val);
368
369 if (poll_ret) {
370 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",
371 read_ret, val);
372 return -EIO;
373 }
374
375 return 0;
376 }
377 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED");
378
cs35l56_wait_control_port_ready(void)379 void cs35l56_wait_control_port_ready(void)
380 {
381 /* Wait for control port to be ready (datasheet tIRS). */
382 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US);
383 }
384 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED");
385
cs35l56_wait_min_reset_pulse(void)386 void cs35l56_wait_min_reset_pulse(void)
387 {
388 /* Satisfy minimum reset pulse width spec */
389 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US);
390 }
391 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED");
392
393 static const struct {
394 u32 addr;
395 u32 value;
396 } cs35l56_spi_system_reset_stages[] = {
397 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET },
398 /* The next write is necessary to delimit the soft reset */
399 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING },
400 };
401
cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base * cs35l56_base,struct spi_device * spi)402 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base,
403 struct spi_device *spi)
404 {
405 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf;
406 struct spi_transfer t = {
407 .tx_buf = buf,
408 .len = sizeof(*buf),
409 };
410 struct spi_message m;
411 int i, ret;
412
413 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) {
414 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr);
415 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value);
416 spi_message_init_with_transfers(&m, &t, 1);
417 ret = spi_sync_locked(spi, &m);
418 if (ret)
419 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret);
420
421 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US,
422 2 * CS35L56_SPI_RESET_TO_PORT_READY_US);
423 }
424 }
425
cs35l56_spi_system_reset(struct cs35l56_base * cs35l56_base)426 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base)
427 {
428 struct spi_device *spi = to_spi_device(cs35l56_base->dev);
429 unsigned int val;
430 int read_ret, ret;
431
432 /*
433 * There must not be any other SPI bus activity while the amp is
434 * soft-resetting.
435 */
436 ret = spi_bus_lock(spi->controller);
437 if (ret) {
438 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret);
439 return;
440 }
441
442 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi);
443 spi_bus_unlock(spi->controller);
444
445 /*
446 * Check firmware boot by testing for a response in MBOX_2.
447 * HALO_STATE cannot be trusted yet because the reset sequence
448 * can leave it with stale state. But MBOX is reset.
449 * The regmap must remain in cache-only until the chip has
450 * booted, so use a bypassed read.
451 */
452 ret = read_poll_timeout(regmap_read_bypassed, read_ret,
453 (val > 0) && (val < 0xffffffff),
454 CS35L56_HALO_STATE_POLL_US,
455 CS35L56_HALO_STATE_TIMEOUT_US,
456 false,
457 cs35l56_base->regmap,
458 CS35L56_DSP_VIRTUAL1_MBOX_2,
459 &val);
460 if (ret) {
461 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n",
462 read_ret, val);
463 }
464 }
465
466 static const struct reg_sequence cs35l56_system_reset_seq[] = {
467 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0),
468 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
469 };
470
471 static const struct reg_sequence cs35l63_system_reset_seq[] = {
472 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0),
473 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
474 };
475
cs35l56_system_reset(struct cs35l56_base * cs35l56_base,bool is_soundwire)476 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
477 {
478 /*
479 * Must enter cache-only first so there can't be any more register
480 * accesses other than the controlled system reset sequence below.
481 */
482 regcache_cache_only(cs35l56_base->regmap, true);
483
484 if (cs35l56_is_spi(cs35l56_base)) {
485 cs35l56_spi_system_reset(cs35l56_base);
486 return;
487 }
488
489 switch (cs35l56_base->type) {
490 case 0x54:
491 case 0x56:
492 case 0x57:
493 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
494 cs35l56_system_reset_seq,
495 ARRAY_SIZE(cs35l56_system_reset_seq));
496 break;
497 case 0x63:
498 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
499 cs35l63_system_reset_seq,
500 ARRAY_SIZE(cs35l63_system_reset_seq));
501 break;
502 default:
503 break;
504 }
505
506 /* On SoundWire the registers won't be accessible until it re-enumerates. */
507 if (is_soundwire)
508 return;
509
510 cs35l56_wait_control_port_ready();
511
512 /* Leave in cache-only. This will be revoked when the chip has rebooted. */
513 }
514 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED");
515
cs35l56_irq_request(struct cs35l56_base * cs35l56_base,int irq)516 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq)
517 {
518 int ret;
519
520 if (irq < 1)
521 return 0;
522
523 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq,
524 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
525 "cs35l56", cs35l56_base);
526 if (!ret)
527 cs35l56_base->irq = irq;
528 else
529 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret);
530
531 return ret;
532 }
533 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED");
534
cs35l56_irq(int irq,void * data)535 irqreturn_t cs35l56_irq(int irq, void *data)
536 {
537 struct cs35l56_base *cs35l56_base = data;
538 unsigned int status1 = 0, status8 = 0, status20 = 0;
539 unsigned int mask1, mask8, mask20;
540 unsigned int val;
541 int rv;
542
543 irqreturn_t ret = IRQ_NONE;
544
545 if (!cs35l56_base->init_done)
546 return IRQ_NONE;
547
548 mutex_lock(&cs35l56_base->irq_lock);
549
550 rv = pm_runtime_resume_and_get(cs35l56_base->dev);
551 if (rv < 0) {
552 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv);
553 goto err_unlock;
554 }
555
556 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
557 if ((val & CS35L56_IRQ1_STS_MASK) == 0) {
558 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n");
559 goto err;
560 }
561
562 /* Ack interrupts */
563 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1);
564 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1);
565 status1 &= ~mask1;
566 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1);
567
568 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8);
569 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8);
570 status8 &= ~mask8;
571 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8);
572
573 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20);
574 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20);
575 status20 &= ~mask20;
576 /* We don't want EINT20 but they default to unmasked: force mask */
577 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
578
579 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8);
580
581 /* Check to see if unmasked bits are active */
582 if (!status1 && !status8 && !status20)
583 goto err;
584
585 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK)
586 dev_crit(cs35l56_base->dev, "Amp short error\n");
587
588 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK)
589 dev_crit(cs35l56_base->dev, "Overtemp error\n");
590
591 ret = IRQ_HANDLED;
592
593 err:
594 pm_runtime_put(cs35l56_base->dev);
595 err_unlock:
596 mutex_unlock(&cs35l56_base->irq_lock);
597
598 return ret;
599 }
600 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED");
601
cs35l56_is_fw_reload_needed(struct cs35l56_base * cs35l56_base)602 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base)
603 {
604 unsigned int val;
605 int ret;
606
607 /*
608 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so
609 * can't be used here to test for memory retention.
610 * Assume that tuning must be re-loaded.
611 */
612 if (cs35l56_base->secured)
613 return true;
614
615 ret = pm_runtime_resume_and_get(cs35l56_base->dev);
616 if (ret) {
617 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret);
618 return ret;
619 }
620
621 ret = regmap_read(cs35l56_base->regmap,
622 cs35l56_base->fw_reg->prot_sts,
623 &val);
624 if (ret)
625 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret);
626 else
627 ret = !!(val & CS35L56_FIRMWARE_MISSING);
628
629 pm_runtime_put_autosuspend(cs35l56_base->dev);
630
631 return ret;
632 }
633 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED");
634
635 static const struct reg_sequence cs35l56_hibernate_seq[] = {
636 /* This must be the last register access */
637 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE),
638 };
639
cs35l56_issue_wake_event(struct cs35l56_base * cs35l56_base)640 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base)
641 {
642 unsigned int val;
643
644 /*
645 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two
646 * transactions to meet the minimum required time from the rising edge
647 * to the last falling edge of wake.
648 *
649 * It uses bypassed read because we must wake the chip before
650 * disabling regmap cache-only.
651 */
652 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
653
654 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US);
655
656 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val);
657
658 cs35l56_wait_control_port_ready();
659 }
660
cs35l56_runtime_suspend_common(struct cs35l56_base * cs35l56_base)661 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base)
662 {
663 unsigned int val;
664 int ret;
665
666 if (!cs35l56_base->init_done)
667 return 0;
668
669 /* Firmware must have entered a power-save state */
670 ret = regmap_read_poll_timeout(cs35l56_base->regmap,
671 cs35l56_base->fw_reg->transducer_actual_ps,
672 val, (val >= CS35L56_PS3),
673 CS35L56_PS3_POLL_US,
674 CS35L56_PS3_TIMEOUT_US);
675 if (ret)
676 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret);
677
678 /* Clear BOOT_DONE so it can be used to detect a reboot */
679 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK);
680
681 if (!cs35l56_base->can_hibernate) {
682 regcache_cache_only(cs35l56_base->regmap, true);
683 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate");
684
685 return 0;
686 }
687
688 /*
689 * Must enter cache-only first so there can't be any more register
690 * accesses other than the controlled hibernate sequence below.
691 */
692 regcache_cache_only(cs35l56_base->regmap, true);
693
694 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
695 cs35l56_hibernate_seq,
696 ARRAY_SIZE(cs35l56_hibernate_seq));
697
698 dev_dbg(cs35l56_base->dev, "Suspended: hibernate");
699
700 return 0;
701 }
702 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED");
703
cs35l56_runtime_resume_common(struct cs35l56_base * cs35l56_base,bool is_soundwire)704 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire)
705 {
706 unsigned int val;
707 int ret;
708
709 if (!cs35l56_base->init_done)
710 return 0;
711
712 if (!cs35l56_base->can_hibernate)
713 goto out_sync;
714
715 /* Must be done before releasing cache-only */
716 if (!is_soundwire)
717 cs35l56_issue_wake_event(cs35l56_base);
718
719 out_sync:
720 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
721 if (ret) {
722 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret);
723 goto err;
724 }
725
726 regcache_cache_only(cs35l56_base->regmap, false);
727
728 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE);
729 if (ret)
730 goto err;
731
732 /* BOOT_DONE will be 1 if the amp reset */
733 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val);
734 if (val & CS35L56_OTP_BOOT_DONE_MASK) {
735 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n");
736 regcache_mark_dirty(cs35l56_base->regmap);
737 }
738
739 regcache_sync(cs35l56_base->regmap);
740
741 dev_dbg(cs35l56_base->dev, "Resumed");
742
743 return 0;
744
745 err:
746 regcache_cache_only(cs35l56_base->regmap, true);
747
748 regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
749 cs35l56_hibernate_seq,
750 ARRAY_SIZE(cs35l56_hibernate_seq));
751
752 return ret;
753 }
754 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED");
755
756 static const struct cs_dsp_region cs35l56_dsp1_regions[] = {
757 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 },
758 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 },
759 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 },
760 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 },
761 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 },
762 };
763
cs35l56_init_cs_dsp(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)764 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
765 {
766 cs_dsp->num = 1;
767 cs_dsp->type = WMFW_HALO;
768 cs_dsp->rev = 0;
769 cs_dsp->dev = cs35l56_base->dev;
770 cs_dsp->regmap = cs35l56_base->regmap;
771 cs_dsp->base = CS35L56_DSP1_CORE_BASE;
772 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID;
773 cs_dsp->mem = cs35l56_dsp1_regions;
774 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions);
775 cs_dsp->no_core_startstop = true;
776 }
777 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED");
778
779 struct cs35l56_pte {
780 u8 x;
781 u8 wafer_id;
782 u8 pte[2];
783 u8 lot[3];
784 u8 y;
785 u8 unused[3];
786 u8 dvs;
787 } __packed;
788 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0);
789
cs35l56_read_silicon_uid(struct cs35l56_base * cs35l56_base,u64 * uid)790 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid)
791 {
792 struct cs35l56_pte pte;
793 u64 unique_id;
794 int ret;
795
796 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte));
797 if (ret) {
798 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret);
799 return ret;
800 }
801
802 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16);
803 unique_id <<= 32;
804 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) |
805 ((u32)pte.dvs << 24);
806
807 *uid = unique_id;
808
809 return 0;
810 }
811
cs35l63_read_silicon_uid(struct cs35l56_base * cs35l56_base,u64 * uid)812 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid)
813 {
814 u32 tmp[2];
815 int ret;
816
817 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp));
818 if (ret) {
819 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret);
820 return ret;
821 }
822
823 *uid = tmp[1];
824 *uid <<= 32;
825 *uid |= tmp[0];
826
827 return 0;
828 }
829
830 /* Firmware calibration controls */
831 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = {
832 .alg_id = 0x9f210,
833 .mem_region = WMFW_ADSP2_YM,
834 .ambient = "CAL_AMBIENT",
835 .calr = "CAL_R",
836 .status = "CAL_STATUS",
837 .checksum = "CAL_CHECKSUM",
838 };
839 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED");
840
841 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = {
842 .alg_id = 0xbf210,
843 .mem_region = WMFW_ADSP2_YM,
844 .ambient = "CAL_AMBIENT",
845 .calr = "CAL_R",
846 .status = "CAL_STATUS",
847 .checksum = "CAL_CHECKSUM",
848 };
849
cs35l56_get_calibration(struct cs35l56_base * cs35l56_base)850 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base)
851 {
852 u64 silicon_uid = 0;
853 int ret;
854
855 /* Driver can't apply calibration to a secured part, so skip */
856 if (cs35l56_base->secured)
857 return 0;
858
859 switch (cs35l56_base->type) {
860 case 0x54:
861 case 0x56:
862 case 0x57:
863 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid);
864 break;
865 case 0x63:
866 ret = cs35l63_read_silicon_uid(cs35l56_base, &silicon_uid);
867 break;
868 default:
869 ret = -ENODEV;
870 break;
871 }
872
873 if (ret < 0)
874 return ret;
875
876 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", silicon_uid);
877
878 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid,
879 cs35l56_base->cal_index,
880 &cs35l56_base->cal_data);
881
882 /* Only return an error status if probe should be aborted */
883 if ((ret == -ENOENT) || (ret == -EOVERFLOW))
884 return 0;
885
886 if (ret < 0)
887 return ret;
888
889 cs35l56_base->cal_data_valid = true;
890
891 return 0;
892 }
893 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED");
894
cs35l56_read_prot_status(struct cs35l56_base * cs35l56_base,bool * fw_missing,unsigned int * fw_version)895 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base,
896 bool *fw_missing, unsigned int *fw_version)
897 {
898 unsigned int prot_status;
899 int ret;
900
901 ret = regmap_read(cs35l56_base->regmap,
902 cs35l56_base->fw_reg->prot_sts, &prot_status);
903 if (ret) {
904 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret);
905 return ret;
906 }
907
908 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING);
909
910 ret = regmap_read(cs35l56_base->regmap,
911 cs35l56_base->fw_reg->fw_ver, fw_version);
912 if (ret) {
913 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret);
914 return ret;
915 }
916
917 return 0;
918 }
919 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED");
920
cs35l56_log_tuning(struct cs35l56_base * cs35l56_base,struct cs_dsp * cs_dsp)921 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp)
922 {
923 __be32 pid, sid, tid;
924 unsigned int alg_id;
925 int ret;
926
927 switch (cs35l56_base->type) {
928 case 0x54:
929 case 0x56:
930 case 0x57:
931 alg_id = 0x9f212;
932 break;
933 default:
934 alg_id = 0xbf212;
935 break;
936 }
937
938 scoped_guard(mutex, &cs_dsp->pwr_lock) {
939 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID",
940 WMFW_ADSP2_XM, alg_id),
941 0, &pid, sizeof(pid));
942 if (!ret)
943 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID",
944 WMFW_ADSP2_XM, alg_id),
945 0, &sid, sizeof(sid));
946 if (!ret)
947 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID",
948 WMFW_ADSP2_XM, alg_id),
949 0, &tid, sizeof(tid));
950 }
951
952 if (ret)
953 dev_warn(cs35l56_base->dev, "Can't read tuning IDs");
954 else
955 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n",
956 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid));
957 }
958 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED");
959
cs35l56_hw_init(struct cs35l56_base * cs35l56_base)960 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
961 {
962 int ret;
963 unsigned int devid, revid, otpid, secured, fw_ver;
964 bool fw_missing;
965
966 /*
967 * When the system is not using a reset_gpio ensure the device is
968 * awake, otherwise the device has just been released from reset and
969 * the driver must wait for the control port to become usable.
970 */
971 if (!cs35l56_base->reset_gpio)
972 cs35l56_issue_wake_event(cs35l56_base);
973 else
974 cs35l56_wait_control_port_ready();
975
976 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);
977 if (ret < 0) {
978 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
979 return ret;
980 }
981 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK);
982
983 ret = cs35l56_wait_for_firmware_boot(cs35l56_base);
984 if (ret)
985 return ret;
986
987 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid);
988 if (ret < 0) {
989 dev_err(cs35l56_base->dev, "Get Device ID failed\n");
990 return ret;
991 }
992 devid &= CS35L56_DEVID_MASK;
993
994 switch (devid) {
995 case 0x35A54:
996 case 0x35A56:
997 case 0x35A57:
998 cs35l56_base->calibration_controls = &cs35l56_calibration_controls;
999 break;
1000 case 0x35A630:
1001 cs35l56_base->calibration_controls = &cs35l63_calibration_controls;
1002 devid = devid >> 4;
1003 break;
1004 default:
1005 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid);
1006 return -ENODEV;
1007 }
1008
1009 cs35l56_base->type = devid & 0xFF;
1010
1011 /* Silicon is now identified and booted so exit cache-only */
1012 regcache_cache_only(cs35l56_base->regmap, false);
1013
1014 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured);
1015 if (ret) {
1016 dev_err(cs35l56_base->dev, "Get Secure status failed\n");
1017 return ret;
1018 }
1019
1020 /* When any bus is restricted treat the device as secured */
1021 if (secured & CS35L56_RESTRICTED_MASK)
1022 cs35l56_base->secured = true;
1023
1024 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid);
1025 if (ret < 0) {
1026 dev_err(cs35l56_base->dev, "Get OTP ID failed\n");
1027 return ret;
1028 }
1029
1030 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver);
1031 if (ret)
1032 return ret;
1033
1034 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n",
1035 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid,
1036 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing);
1037
1038 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */
1039 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff);
1040 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1,
1041 CS35L56_AMP_SHORT_ERR_EINT1_MASK,
1042 0);
1043 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8,
1044 CS35L56_TEMP_ERR_EINT1_MASK,
1045 0);
1046
1047 return 0;
1048 }
1049 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED");
1050
cs35l56_get_speaker_id(struct cs35l56_base * cs35l56_base)1051 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base)
1052 {
1053 struct gpio_descs *descs;
1054 u32 speaker_id;
1055 int i, ret;
1056
1057 /* Attempt to read the speaker type from a device property first */
1058 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id);
1059 if (!ret) {
1060 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
1061 return speaker_id;
1062 }
1063
1064 /* Read the speaker type qualifier from the motherboard GPIOs */
1065 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN);
1066 if (!descs) {
1067 return -ENOENT;
1068 } else if (IS_ERR(descs)) {
1069 ret = PTR_ERR(descs);
1070 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n");
1071 }
1072
1073 speaker_id = 0;
1074 for (i = 0; i < descs->ndescs; i++) {
1075 ret = gpiod_get_value_cansleep(descs->desc[i]);
1076 if (ret < 0) {
1077 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i);
1078 goto err;
1079 }
1080
1081 speaker_id |= (ret << i);
1082 }
1083
1084 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id);
1085 ret = speaker_id;
1086 err:
1087 gpiod_put_array(descs);
1088
1089 return ret;
1090 }
1091 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED");
1092
1093 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = {
1094 [0x0C] = 128000,
1095 [0x0F] = 256000,
1096 [0x11] = 384000,
1097 [0x12] = 512000,
1098 [0x15] = 768000,
1099 [0x17] = 1024000,
1100 [0x1A] = 1500000,
1101 [0x1B] = 1536000,
1102 [0x1C] = 2000000,
1103 [0x1D] = 2048000,
1104 [0x1E] = 2400000,
1105 [0x20] = 3000000,
1106 [0x21] = 3072000,
1107 [0x23] = 4000000,
1108 [0x24] = 4096000,
1109 [0x25] = 4800000,
1110 [0x27] = 6000000,
1111 [0x28] = 6144000,
1112 [0x29] = 6250000,
1113 [0x2A] = 6400000,
1114 [0x2E] = 8000000,
1115 [0x2F] = 8192000,
1116 [0x30] = 9600000,
1117 [0x32] = 12000000,
1118 [0x33] = 12288000,
1119 [0x37] = 13500000,
1120 [0x38] = 19200000,
1121 [0x39] = 22579200,
1122 [0x3B] = 24576000,
1123 };
1124
cs35l56_get_bclk_freq_id(unsigned int freq)1125 int cs35l56_get_bclk_freq_id(unsigned int freq)
1126 {
1127 int i;
1128
1129 if (freq == 0)
1130 return -EINVAL;
1131
1132 /* The BCLK frequency must be a valid PLL REFCLK */
1133 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) {
1134 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq)
1135 return i;
1136 }
1137
1138 return -EINVAL;
1139 }
1140 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED");
1141
1142 static const char * const cs35l56_supplies[/* auto-sized */] = {
1143 "VDD_P",
1144 "VDD_IO",
1145 "VDD_A",
1146 };
1147
cs35l56_fill_supply_names(struct regulator_bulk_data * data)1148 void cs35l56_fill_supply_names(struct regulator_bulk_data *data)
1149 {
1150 int i;
1151
1152 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES);
1153 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++)
1154 data[i].supply = cs35l56_supplies[i];
1155 }
1156 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED");
1157
1158 const char * const cs35l56_tx_input_texts[] = {
1159 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH",
1160 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4",
1161 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON",
1162 "INTERPOLATOR", "SDW1RX1", "SDW1RX2",
1163 };
1164 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED");
1165
1166 const unsigned int cs35l56_tx_input_values[] = {
1167 CS35L56_INPUT_SRC_NONE,
1168 CS35L56_INPUT_SRC_ASP1RX1,
1169 CS35L56_INPUT_SRC_ASP1RX2,
1170 CS35L56_INPUT_SRC_VMON,
1171 CS35L56_INPUT_SRC_IMON,
1172 CS35L56_INPUT_SRC_ERR_VOL,
1173 CS35L56_INPUT_SRC_CLASSH,
1174 CS35L56_INPUT_SRC_VDDBMON,
1175 CS35L56_INPUT_SRC_VBSTMON,
1176 CS35L56_INPUT_SRC_DSP1TX1,
1177 CS35L56_INPUT_SRC_DSP1TX2,
1178 CS35L56_INPUT_SRC_DSP1TX3,
1179 CS35L56_INPUT_SRC_DSP1TX4,
1180 CS35L56_INPUT_SRC_DSP1TX5,
1181 CS35L56_INPUT_SRC_DSP1TX6,
1182 CS35L56_INPUT_SRC_DSP1TX7,
1183 CS35L56_INPUT_SRC_DSP1TX8,
1184 CS35L56_INPUT_SRC_TEMPMON,
1185 CS35L56_INPUT_SRC_INTERPOLATOR,
1186 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1,
1187 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2,
1188 };
1189 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED");
1190
1191 const struct regmap_config cs35l56_regmap_i2c = {
1192 .reg_bits = 32,
1193 .val_bits = 32,
1194 .reg_stride = 4,
1195 .reg_format_endian = REGMAP_ENDIAN_BIG,
1196 .val_format_endian = REGMAP_ENDIAN_BIG,
1197 .max_register = CS35L56_DSP1_PMEM_5114,
1198 .reg_defaults = cs35l56_reg_defaults,
1199 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1200 .volatile_reg = cs35l56_volatile_reg,
1201 .readable_reg = cs35l56_readable_reg,
1202 .precious_reg = cs35l56_precious_reg,
1203 .cache_type = REGCACHE_MAPLE,
1204 };
1205 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED");
1206
1207 const struct regmap_config cs35l56_regmap_spi = {
1208 .reg_bits = 32,
1209 .val_bits = 32,
1210 .pad_bits = 16,
1211 .reg_stride = 4,
1212 .reg_format_endian = REGMAP_ENDIAN_BIG,
1213 .val_format_endian = REGMAP_ENDIAN_BIG,
1214 .max_register = CS35L56_DSP1_PMEM_5114,
1215 .reg_defaults = cs35l56_reg_defaults,
1216 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1217 .volatile_reg = cs35l56_volatile_reg,
1218 .readable_reg = cs35l56_readable_reg,
1219 .precious_reg = cs35l56_precious_reg,
1220 .cache_type = REGCACHE_MAPLE,
1221 };
1222 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED");
1223
1224 const struct regmap_config cs35l56_regmap_sdw = {
1225 .reg_bits = 32,
1226 .val_bits = 32,
1227 .reg_stride = 4,
1228 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1229 .val_format_endian = REGMAP_ENDIAN_BIG,
1230 .max_register = CS35L56_DSP1_PMEM_5114,
1231 .reg_defaults = cs35l56_reg_defaults,
1232 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults),
1233 .volatile_reg = cs35l56_volatile_reg,
1234 .readable_reg = cs35l56_readable_reg,
1235 .precious_reg = cs35l56_precious_reg,
1236 .cache_type = REGCACHE_MAPLE,
1237 };
1238 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED");
1239
1240 const struct regmap_config cs35l63_regmap_i2c = {
1241 .reg_bits = 32,
1242 .val_bits = 32,
1243 .reg_stride = 4,
1244 .reg_base = 0x8000,
1245 .reg_format_endian = REGMAP_ENDIAN_BIG,
1246 .val_format_endian = REGMAP_ENDIAN_BIG,
1247 .max_register = CS35L56_DSP1_PMEM_5114,
1248 .reg_defaults = cs35l63_reg_defaults,
1249 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults),
1250 .volatile_reg = cs35l63_volatile_reg,
1251 .readable_reg = cs35l56_readable_reg,
1252 .precious_reg = cs35l56_precious_reg,
1253 .cache_type = REGCACHE_MAPLE,
1254 };
1255 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED");
1256
1257 const struct regmap_config cs35l63_regmap_sdw = {
1258 .reg_bits = 32,
1259 .val_bits = 32,
1260 .reg_stride = 4,
1261 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
1262 .val_format_endian = REGMAP_ENDIAN_BIG,
1263 .max_register = CS35L56_DSP1_PMEM_5114,
1264 .reg_defaults = cs35l63_reg_defaults,
1265 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults),
1266 .volatile_reg = cs35l63_volatile_reg,
1267 .readable_reg = cs35l56_readable_reg,
1268 .precious_reg = cs35l56_precious_reg,
1269 .cache_type = REGCACHE_MAPLE,
1270 };
1271 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED");
1272
1273 const struct cs35l56_fw_reg cs35l56_fw_reg = {
1274 .fw_ver = CS35L56_DSP1_FW_VER,
1275 .halo_state = CS35L56_DSP1_HALO_STATE,
1276 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE,
1277 .prot_sts = CS35L56_PROTECTION_STATUS,
1278 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS,
1279 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE,
1280 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME,
1281 .posture_number = CS35L56_MAIN_POSTURE_NUMBER,
1282 };
1283 EXPORT_SYMBOL_NS_GPL(cs35l56_fw_reg, "SND_SOC_CS35L56_SHARED");
1284
1285 const struct cs35l56_fw_reg cs35l63_fw_reg = {
1286 .fw_ver = CS35L63_DSP1_FW_VER,
1287 .halo_state = CS35L63_DSP1_HALO_STATE,
1288 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE,
1289 .prot_sts = CS35L63_PROTECTION_STATUS,
1290 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS,
1291 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE,
1292 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME,
1293 .posture_number = CS35L63_MAIN_POSTURE_NUMBER,
1294 };
1295 EXPORT_SYMBOL_NS_GPL(cs35l63_fw_reg, "SND_SOC_CS35L56_SHARED");
1296
1297 MODULE_DESCRIPTION("ASoC CS35L56 Shared");
1298 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1299 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>");
1300 MODULE_LICENSE("GPL");
1301 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB");
1302 MODULE_IMPORT_NS("FW_CS_DSP");
1303