1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_asp_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 }; 47 48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base) 49 { 50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch, 51 ARRAY_SIZE(cs35l56_asp_patch)); 52 } 53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED"); 54 55 static const struct reg_sequence cs35l56_patch[] = { 56 /* 57 * Firmware can change these to non-defaults to satisfy SDCA. 58 * Ensure that they are at known defaults. 59 */ 60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 65 }; 66 67 static const struct reg_sequence cs35l56_patch_fw[] = { 68 /* These are not reset by a soft-reset, so patch to defaults. */ 69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 72 }; 73 74 static const struct reg_sequence cs35l63_patch_fw[] = { 75 /* These are not reset by a soft-reset, so patch to defaults. */ 76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 79 }; 80 81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 82 { 83 int ret; 84 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 86 ARRAY_SIZE(cs35l56_patch)); 87 if (ret) 88 return ret; 89 90 91 switch (cs35l56_base->type) { 92 case 0x54: 93 case 0x56: 94 case 0x57: 95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 96 ARRAY_SIZE(cs35l56_patch_fw)); 97 break; 98 case 0x63: 99 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 100 ARRAY_SIZE(cs35l63_patch_fw)); 101 break; 102 default: 103 break; 104 } 105 106 return ret; 107 } 108 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 109 110 static const struct reg_default cs35l56_reg_defaults[] = { 111 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 112 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 113 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 114 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 115 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 116 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 117 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 118 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 119 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 120 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 121 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 122 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 123 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 124 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 125 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 126 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 127 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 128 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 129 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 130 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 131 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 132 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 133 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 134 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 135 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 136 }; 137 138 static const struct reg_default cs35l63_reg_defaults[] = { 139 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 140 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 141 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 142 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 143 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 144 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 145 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 146 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 147 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 148 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 149 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 150 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 151 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 152 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 153 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 154 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 155 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 156 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 157 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 158 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 159 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 160 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 161 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 162 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 163 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 164 }; 165 166 static bool cs35l56_is_dsp_memory(unsigned int reg) 167 { 168 switch (reg) { 169 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 170 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 171 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 172 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 173 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 174 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 175 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 176 return true; 177 default: 178 return false; 179 } 180 } 181 182 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 183 { 184 switch (reg) { 185 case CS35L56_DEVID: 186 case CS35L56_REVID: 187 case CS35L56_RELID: 188 case CS35L56_OTPID: 189 case CS35L56_SFT_RESET: 190 case CS35L56_GLOBAL_ENABLES: 191 case CS35L56_BLOCK_ENABLES: 192 case CS35L56_BLOCK_ENABLES2: 193 case CS35L56_REFCLK_INPUT: 194 case CS35L56_GLOBAL_SAMPLE_RATE: 195 case CS35L56_OTP_MEM_53: 196 case CS35L56_OTP_MEM_54: 197 case CS35L56_OTP_MEM_55: 198 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 199 case CS35L56_UPDATE_REGS: 200 case CS35L56_ASP1_ENABLES1: 201 case CS35L56_ASP1_CONTROL1: 202 case CS35L56_ASP1_CONTROL2: 203 case CS35L56_ASP1_CONTROL3: 204 case CS35L56_ASP1_FRAME_CONTROL1: 205 case CS35L56_ASP1_FRAME_CONTROL5: 206 case CS35L56_ASP1_DATA_CONTROL1: 207 case CS35L56_ASP1_DATA_CONTROL5: 208 case CS35L56_DACPCM1_INPUT: 209 case CS35L56_DACPCM2_INPUT: 210 case CS35L56_ASP1TX1_INPUT: 211 case CS35L56_ASP1TX2_INPUT: 212 case CS35L56_ASP1TX3_INPUT: 213 case CS35L56_ASP1TX4_INPUT: 214 case CS35L56_DSP1RX1_INPUT: 215 case CS35L56_DSP1RX2_INPUT: 216 case CS35L56_SWIRE_DP3_CH1_INPUT: 217 case CS35L56_SWIRE_DP3_CH2_INPUT: 218 case CS35L56_SWIRE_DP3_CH3_INPUT: 219 case CS35L56_SWIRE_DP3_CH4_INPUT: 220 case CS35L56_IRQ1_CFG: 221 case CS35L56_IRQ1_STATUS: 222 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 223 case CS35L56_IRQ1_EINT_18: 224 case CS35L56_IRQ1_EINT_20: 225 case CS35L56_IRQ1_MASK_1: 226 case CS35L56_IRQ1_MASK_2: 227 case CS35L56_IRQ1_MASK_4: 228 case CS35L56_IRQ1_MASK_8: 229 case CS35L56_IRQ1_MASK_18: 230 case CS35L56_IRQ1_MASK_20: 231 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 232 case CS35L56_MIXER_NGATE_CH1_CFG: 233 case CS35L56_MIXER_NGATE_CH2_CFG: 234 case CS35L56_DSP_VIRTUAL1_MBOX_1: 235 case CS35L56_DSP_VIRTUAL1_MBOX_2: 236 case CS35L56_DSP_VIRTUAL1_MBOX_3: 237 case CS35L56_DSP_VIRTUAL1_MBOX_4: 238 case CS35L56_DSP_VIRTUAL1_MBOX_5: 239 case CS35L56_DSP_VIRTUAL1_MBOX_6: 240 case CS35L56_DSP_VIRTUAL1_MBOX_7: 241 case CS35L56_DSP_VIRTUAL1_MBOX_8: 242 case CS35L56_DIE_STS1: 243 case CS35L56_DIE_STS2: 244 case CS35L56_DSP_RESTRICT_STS1: 245 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 246 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 247 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 248 case CS35L56_DSP1_SCRATCH1: 249 case CS35L56_DSP1_SCRATCH2: 250 case CS35L56_DSP1_SCRATCH3: 251 case CS35L56_DSP1_SCRATCH4: 252 return true; 253 default: 254 return cs35l56_is_dsp_memory(reg); 255 } 256 } 257 258 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 259 { 260 switch (reg) { 261 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 262 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 263 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 264 return true; 265 default: 266 return false; 267 } 268 } 269 270 static bool cs35l56_common_volatile_reg(unsigned int reg) 271 { 272 switch (reg) { 273 case CS35L56_DEVID: 274 case CS35L56_REVID: 275 case CS35L56_RELID: 276 case CS35L56_OTPID: 277 case CS35L56_SFT_RESET: 278 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 279 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 280 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 281 case CS35L56_OTP_MEM_53: 282 case CS35L56_OTP_MEM_54: 283 case CS35L56_OTP_MEM_55: 284 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 285 case CS35L56_UPDATE_REGS: 286 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 287 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 288 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 289 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 290 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 291 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 292 case CS35L56_IRQ1_STATUS: 293 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 294 case CS35L56_IRQ1_EINT_18: 295 case CS35L56_IRQ1_EINT_20: 296 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 297 case CS35L56_MIXER_NGATE_CH1_CFG: 298 case CS35L56_MIXER_NGATE_CH2_CFG: 299 case CS35L56_DSP_VIRTUAL1_MBOX_1: 300 case CS35L56_DSP_VIRTUAL1_MBOX_2: 301 case CS35L56_DSP_VIRTUAL1_MBOX_3: 302 case CS35L56_DSP_VIRTUAL1_MBOX_4: 303 case CS35L56_DSP_VIRTUAL1_MBOX_5: 304 case CS35L56_DSP_VIRTUAL1_MBOX_6: 305 case CS35L56_DSP_VIRTUAL1_MBOX_7: 306 case CS35L56_DSP_VIRTUAL1_MBOX_8: 307 case CS35L56_DSP_RESTRICT_STS1: 308 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 309 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 311 case CS35L56_DSP1_SCRATCH1: 312 case CS35L56_DSP1_SCRATCH2: 313 case CS35L56_DSP1_SCRATCH3: 314 case CS35L56_DSP1_SCRATCH4: 315 return true; 316 default: 317 return cs35l56_is_dsp_memory(reg); 318 } 319 } 320 321 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 322 { 323 switch (reg) { 324 case CS35L56_MAIN_RENDER_USER_MUTE: 325 case CS35L56_MAIN_RENDER_USER_VOLUME: 326 case CS35L56_MAIN_POSTURE_NUMBER: 327 return false; 328 default: 329 return cs35l56_common_volatile_reg(reg); 330 } 331 } 332 333 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 334 { 335 switch (reg) { 336 case CS35L63_MAIN_RENDER_USER_MUTE: 337 case CS35L63_MAIN_RENDER_USER_VOLUME: 338 case CS35L63_MAIN_POSTURE_NUMBER: 339 return false; 340 default: 341 return cs35l56_common_volatile_reg(reg); 342 } 343 } 344 345 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 346 .fw_ver = CS35L56_DSP1_FW_VER, 347 .halo_state = CS35L56_DSP1_HALO_STATE, 348 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 349 .prot_sts = CS35L56_PROTECTION_STATUS, 350 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 351 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 352 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 353 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 354 }; 355 356 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 357 .fw_ver = CS35L56_DSP1_FW_VER, 358 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 359 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 360 .prot_sts = CS35L56_PROTECTION_STATUS, 361 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 362 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 363 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 364 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 365 }; 366 367 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 368 .fw_ver = CS35L63_DSP1_FW_VER, 369 .halo_state = CS35L63_DSP1_HALO_STATE, 370 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 371 .prot_sts = CS35L63_PROTECTION_STATUS, 372 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 373 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 374 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 375 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 376 }; 377 378 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 379 { 380 switch (cs35l56_base->type) { 381 default: 382 switch (cs35l56_base->rev) { 383 case 0xb0: 384 cs35l56_base->fw_reg = &cs35l56_fw_reg; 385 break; 386 default: 387 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 388 break; 389 } 390 break; 391 case 0x63: 392 cs35l56_base->fw_reg = &cs35l63_fw_reg; 393 break; 394 } 395 } 396 397 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 398 { 399 unsigned int val; 400 int ret; 401 402 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 403 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 404 val, (val == 0), 405 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 406 if (ret) { 407 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 408 return ret; 409 } 410 411 return 0; 412 } 413 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 414 415 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 416 { 417 int ret; 418 unsigned int val; 419 420 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 421 if (ret) 422 return ret; 423 424 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 425 cs35l56_base->fw_reg->pm_cur_stat, 426 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 427 CS35L56_HALO_STATE_POLL_US, 428 CS35L56_HALO_STATE_TIMEOUT_US); 429 if (ret < 0) 430 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 431 val, ret); 432 return ret; 433 } 434 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 435 436 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 437 { 438 unsigned int val = 0; 439 int read_ret, poll_ret; 440 441 /* 442 * The regmap must remain in cache-only until the chip has 443 * booted, so use a bypassed read of the status register. 444 */ 445 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 446 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 447 CS35L56_HALO_STATE_POLL_US, 448 CS35L56_HALO_STATE_TIMEOUT_US, 449 false, 450 cs35l56_base->regmap, 451 cs35l56_base->fw_reg->halo_state, 452 &val); 453 454 if (poll_ret) { 455 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 456 read_ret, val); 457 return -EIO; 458 } 459 460 return 0; 461 } 462 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 463 464 void cs35l56_wait_control_port_ready(void) 465 { 466 /* Wait for control port to be ready (datasheet tIRS). */ 467 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 468 } 469 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 470 471 void cs35l56_wait_min_reset_pulse(void) 472 { 473 /* Satisfy minimum reset pulse width spec */ 474 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 475 } 476 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 477 478 static const struct { 479 u32 addr; 480 u32 value; 481 } cs35l56_spi_system_reset_stages[] = { 482 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 483 /* The next write is necessary to delimit the soft reset */ 484 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 485 }; 486 487 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 488 struct spi_device *spi) 489 { 490 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 491 struct spi_transfer t = { 492 .tx_buf = buf, 493 .len = sizeof(*buf), 494 }; 495 struct spi_message m; 496 int i, ret; 497 498 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 499 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 500 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 501 spi_message_init_with_transfers(&m, &t, 1); 502 ret = spi_sync_locked(spi, &m); 503 if (ret) 504 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 505 506 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 507 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 508 } 509 } 510 511 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 512 { 513 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 514 unsigned int val; 515 int read_ret, ret; 516 517 /* 518 * There must not be any other SPI bus activity while the amp is 519 * soft-resetting. 520 */ 521 ret = spi_bus_lock(spi->controller); 522 if (ret) { 523 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 524 return; 525 } 526 527 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 528 spi_bus_unlock(spi->controller); 529 530 /* 531 * Check firmware boot by testing for a response in MBOX_2. 532 * HALO_STATE cannot be trusted yet because the reset sequence 533 * can leave it with stale state. But MBOX is reset. 534 * The regmap must remain in cache-only until the chip has 535 * booted, so use a bypassed read. 536 */ 537 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 538 (val > 0) && (val < 0xffffffff), 539 CS35L56_HALO_STATE_POLL_US, 540 CS35L56_HALO_STATE_TIMEOUT_US, 541 false, 542 cs35l56_base->regmap, 543 CS35L56_DSP_VIRTUAL1_MBOX_2, 544 &val); 545 if (ret) { 546 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 547 read_ret, val); 548 } 549 } 550 551 static const struct reg_sequence cs35l56_system_reset_seq[] = { 552 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 553 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 554 }; 555 556 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 557 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 558 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 559 }; 560 561 static const struct reg_sequence cs35l63_system_reset_seq[] = { 562 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 563 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 564 }; 565 566 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 567 { 568 /* 569 * Must enter cache-only first so there can't be any more register 570 * accesses other than the controlled system reset sequence below. 571 */ 572 regcache_cache_only(cs35l56_base->regmap, true); 573 574 if (cs35l56_is_spi(cs35l56_base)) { 575 cs35l56_spi_system_reset(cs35l56_base); 576 return; 577 } 578 579 switch (cs35l56_base->type) { 580 case 0x54: 581 case 0x56: 582 case 0x57: 583 switch (cs35l56_base->rev) { 584 case 0xb0: 585 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 586 cs35l56_system_reset_seq, 587 ARRAY_SIZE(cs35l56_system_reset_seq)); 588 break; 589 default: 590 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 591 cs35l56_b2_system_reset_seq, 592 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 593 break; 594 } 595 break; 596 case 0x63: 597 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 598 cs35l63_system_reset_seq, 599 ARRAY_SIZE(cs35l63_system_reset_seq)); 600 break; 601 default: 602 break; 603 } 604 605 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 606 if (is_soundwire) 607 return; 608 609 cs35l56_wait_control_port_ready(); 610 611 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 612 } 613 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 614 615 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 616 { 617 int ret; 618 619 if (irq < 1) 620 return 0; 621 622 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 623 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 624 "cs35l56", cs35l56_base); 625 if (!ret) 626 cs35l56_base->irq = irq; 627 else 628 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 629 630 return ret; 631 } 632 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 633 634 irqreturn_t cs35l56_irq(int irq, void *data) 635 { 636 struct cs35l56_base *cs35l56_base = data; 637 unsigned int status1 = 0, status8 = 0, status20 = 0; 638 unsigned int mask1, mask8, mask20; 639 unsigned int val; 640 int rv; 641 642 irqreturn_t ret = IRQ_NONE; 643 644 if (!cs35l56_base->init_done) 645 return IRQ_NONE; 646 647 mutex_lock(&cs35l56_base->irq_lock); 648 649 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 650 if (rv < 0) { 651 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 652 goto err_unlock; 653 } 654 655 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 656 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 657 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 658 goto err; 659 } 660 661 /* Ack interrupts */ 662 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 663 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 664 status1 &= ~mask1; 665 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 666 667 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 668 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 669 status8 &= ~mask8; 670 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 671 672 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 673 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 674 status20 &= ~mask20; 675 /* We don't want EINT20 but they default to unmasked: force mask */ 676 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 677 678 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 679 680 /* Check to see if unmasked bits are active */ 681 if (!status1 && !status8 && !status20) 682 goto err; 683 684 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 685 dev_crit(cs35l56_base->dev, "Amp short error\n"); 686 687 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 688 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 689 690 ret = IRQ_HANDLED; 691 692 err: 693 pm_runtime_put(cs35l56_base->dev); 694 err_unlock: 695 mutex_unlock(&cs35l56_base->irq_lock); 696 697 return ret; 698 } 699 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 700 701 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 702 { 703 unsigned int val; 704 int ret; 705 706 /* 707 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 708 * can't be used here to test for memory retention. 709 * Assume that tuning must be re-loaded. 710 */ 711 if (cs35l56_base->secured) 712 return true; 713 714 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 715 if (ret) { 716 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 717 return ret; 718 } 719 720 ret = regmap_read(cs35l56_base->regmap, 721 cs35l56_base->fw_reg->prot_sts, 722 &val); 723 if (ret) 724 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 725 else 726 ret = !!(val & CS35L56_FIRMWARE_MISSING); 727 728 pm_runtime_put_autosuspend(cs35l56_base->dev); 729 730 return ret; 731 } 732 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 733 734 static const struct reg_sequence cs35l56_hibernate_seq[] = { 735 /* This must be the last register access */ 736 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 737 }; 738 739 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 740 { 741 unsigned int val; 742 743 /* 744 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 745 * transactions to meet the minimum required time from the rising edge 746 * to the last falling edge of wake. 747 * 748 * It uses bypassed read because we must wake the chip before 749 * disabling regmap cache-only. 750 */ 751 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 752 753 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 754 755 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 756 757 cs35l56_wait_control_port_ready(); 758 } 759 760 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 761 { 762 unsigned int val; 763 int ret; 764 765 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 766 cs35l56_base->fw_reg->transducer_actual_ps, 767 val, (val >= CS35L56_PS3), 768 CS35L56_PS3_POLL_US, 769 CS35L56_PS3_TIMEOUT_US); 770 if (ret) 771 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 772 773 return ret; 774 } 775 776 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 777 { 778 if (!cs35l56_base->init_done) 779 return 0; 780 781 /* Firmware must have entered a power-save state */ 782 cs35l56_wait_for_ps3(cs35l56_base); 783 784 /* Clear BOOT_DONE so it can be used to detect a reboot */ 785 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 786 787 if (!cs35l56_base->can_hibernate) { 788 regcache_cache_only(cs35l56_base->regmap, true); 789 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 790 791 return 0; 792 } 793 794 /* 795 * Must enter cache-only first so there can't be any more register 796 * accesses other than the controlled hibernate sequence below. 797 */ 798 regcache_cache_only(cs35l56_base->regmap, true); 799 800 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 801 cs35l56_hibernate_seq, 802 ARRAY_SIZE(cs35l56_hibernate_seq)); 803 804 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 805 806 return 0; 807 } 808 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 809 810 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 811 { 812 unsigned int val; 813 int ret; 814 815 if (!cs35l56_base->init_done) 816 return 0; 817 818 if (!cs35l56_base->can_hibernate) 819 goto out_sync; 820 821 /* Must be done before releasing cache-only */ 822 if (!is_soundwire) 823 cs35l56_issue_wake_event(cs35l56_base); 824 825 out_sync: 826 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 827 if (ret) { 828 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 829 goto err; 830 } 831 832 regcache_cache_only(cs35l56_base->regmap, false); 833 834 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 835 if (ret) 836 goto err; 837 838 /* BOOT_DONE will be 1 if the amp reset */ 839 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 840 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 841 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 842 regcache_mark_dirty(cs35l56_base->regmap); 843 } 844 845 regcache_sync(cs35l56_base->regmap); 846 847 dev_dbg(cs35l56_base->dev, "Resumed"); 848 849 return 0; 850 851 err: 852 regcache_cache_only(cs35l56_base->regmap, true); 853 854 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 855 cs35l56_hibernate_seq, 856 ARRAY_SIZE(cs35l56_hibernate_seq)); 857 858 return ret; 859 } 860 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 861 862 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 863 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 864 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 865 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 866 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 867 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 868 }; 869 870 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 871 { 872 cs_dsp->num = 1; 873 cs_dsp->type = WMFW_HALO; 874 cs_dsp->rev = 0; 875 cs_dsp->dev = cs35l56_base->dev; 876 cs_dsp->regmap = cs35l56_base->regmap; 877 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 878 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 879 cs_dsp->mem = cs35l56_dsp1_regions; 880 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 881 cs_dsp->no_core_startstop = true; 882 883 cs35l56_base->dsp = cs_dsp; 884 } 885 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 886 887 struct cs35l56_pte { 888 u8 x; 889 u8 wafer_id; 890 u8 pte[2]; 891 u8 lot[3]; 892 u8 y; 893 u8 unused[3]; 894 u8 dvs; 895 } __packed; 896 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 897 898 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 899 { 900 struct cs35l56_pte pte; 901 u64 unique_id; 902 int ret; 903 904 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 905 if (ret) { 906 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 907 return ret; 908 } 909 910 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 911 unique_id <<= 32; 912 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 913 ((u32)pte.dvs << 24); 914 915 cs35l56_base->silicon_uid = unique_id; 916 917 return 0; 918 } 919 920 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 921 { 922 u32 tmp[2]; 923 u64 unique_id; 924 int ret; 925 926 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 927 if (ret) { 928 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 929 return ret; 930 } 931 932 unique_id = tmp[1]; 933 unique_id <<= 32; 934 unique_id |= tmp[0]; 935 936 cs35l56_base->silicon_uid = unique_id; 937 938 return 0; 939 } 940 941 /* Firmware calibration controls */ 942 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 943 .alg_id = 0x9f210, 944 .mem_region = WMFW_ADSP2_YM, 945 .ambient = "CAL_AMBIENT", 946 .calr = "CAL_R", 947 .status = "CAL_STATUS", 948 .checksum = "CAL_CHECKSUM", 949 }; 950 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 951 952 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 953 .alg_id = 0xbf210, 954 .mem_region = WMFW_ADSP2_YM, 955 .ambient = "CAL_AMBIENT", 956 .calr = "CAL_R", 957 .status = "CAL_STATUS", 958 .checksum = "CAL_CHECKSUM", 959 }; 960 961 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 962 { 963 int ret; 964 965 /* Driver can't apply calibration to a secured part, so skip */ 966 if (cs35l56_base->secured) 967 return 0; 968 969 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 970 cs35l56_base->silicon_uid, 971 cs35l56_base->cal_index, 972 &cs35l56_base->cal_data); 973 974 /* Only return an error status if probe should be aborted */ 975 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 976 return 0; 977 978 if (ret < 0) 979 return ret; 980 981 cs35l56_base->cal_data_valid = true; 982 983 return 0; 984 } 985 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 986 987 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 988 const struct cirrus_amp_cal_data *data) 989 { 990 991 /* Ignore if it is empty */ 992 if (!data->calTime[0] && !data->calTime[1]) 993 return -ENODATA; 994 995 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 996 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 997 return -EINVAL; 998 } 999 1000 cs35l56_base->cal_data = *data; 1001 cs35l56_base->cal_data_valid = true; 1002 1003 return 0; 1004 } 1005 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 1006 1007 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 1008 { 1009 const struct cirrus_amp_cal_controls *calibration_controls = 1010 cs35l56_base->calibration_controls; 1011 struct cs_dsp *dsp = cs35l56_base->dsp; 1012 struct cirrus_amp_cal_data cal_data; 1013 struct cs_dsp_coeff_ctl *ctl; 1014 bool ngate_ch1_was_enabled = false; 1015 bool ngate_ch2_was_enabled = false; 1016 int cali_norm_en_alg_id, cali_norm_en_mem; 1017 int ret; 1018 __be32 val; 1019 1020 if (cs35l56_base->silicon_uid == 0) { 1021 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1022 return -ENXIO; 1023 } 1024 1025 switch (cs35l56_base->type) { 1026 case 0x54: 1027 case 0x56: 1028 case 0x57: 1029 if (cs35l56_base->rev < 0xb2) { 1030 cali_norm_en_alg_id = 0x9f22f; 1031 cali_norm_en_mem = WMFW_ADSP2_YM; 1032 } else { 1033 cali_norm_en_alg_id = 0x9f210; 1034 cali_norm_en_mem = WMFW_ADSP2_XM; 1035 } 1036 break; 1037 default: 1038 cali_norm_en_alg_id = 0xbf210; 1039 cali_norm_en_mem = WMFW_ADSP2_XM; 1040 break; 1041 } 1042 1043 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1044 if (ret) 1045 return ret; 1046 1047 ret = cs35l56_wait_for_ps3(cs35l56_base); 1048 if (ret) { 1049 ret = -EBUSY; 1050 goto err_pm_put; 1051 } 1052 1053 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1054 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1055 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1056 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1057 1058 scoped_guard(mutex, &dsp->pwr_lock) { 1059 ctl = cs_dsp_get_ctl(dsp, 1060 calibration_controls->status, 1061 calibration_controls->mem_region, 1062 calibration_controls->alg_id); 1063 if (!ctl) { 1064 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1065 calibration_controls->status); 1066 ret = -EIO; 1067 goto err; 1068 } 1069 1070 val = cpu_to_be32(0); 1071 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1072 "CALI_NORM_EN", 1073 cali_norm_en_mem, 1074 cali_norm_en_alg_id), 1075 0, &val, sizeof(val)); 1076 if (ret < 0) { 1077 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1078 ret = -EIO; 1079 goto err; 1080 } 1081 1082 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1083 if (ret) { 1084 ret = -EIO; 1085 goto err; 1086 } 1087 1088 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1089 (val == cpu_to_be32(1)), 1090 CS35L56_CALIBRATION_POLL_US, 1091 CS35L56_CALIBRATION_TIMEOUT_US, 1092 true, 1093 ctl, 0, &val, sizeof(val))) { 1094 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1095 be32_to_cpu(val)); 1096 switch (be32_to_cpu(val)) { 1097 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1098 ret = -ERANGE; 1099 goto err; 1100 default: 1101 ret = -ETIMEDOUT; 1102 goto err; 1103 } 1104 } 1105 } 1106 1107 cs35l56_base->cal_data_valid = false; 1108 memset(&cal_data, 0, sizeof(cal_data)); 1109 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1110 if (ret) { 1111 ret = -EIO; 1112 goto err; 1113 } 1114 1115 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1116 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1117 1118 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1119 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1120 cs35l56_base->cal_data = cal_data; 1121 cs35l56_base->cal_data_valid = true; 1122 1123 ret = 0; 1124 1125 err: 1126 if (ngate_ch1_was_enabled) { 1127 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1128 CS35L56_AUX_NGATE_CHn_EN); 1129 } 1130 if (ngate_ch2_was_enabled) { 1131 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1132 CS35L56_AUX_NGATE_CHn_EN); 1133 } 1134 err_pm_put: 1135 pm_runtime_put(cs35l56_base->dev); 1136 1137 return ret; 1138 } 1139 1140 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1141 const char __user *from, size_t count, 1142 loff_t *ppos) 1143 { 1144 static const char * const options[] = { "factory", "store_uefi" }; 1145 char buf[11] = { 0 }; 1146 int num_amps, ret; 1147 1148 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1149 return -ENXIO; 1150 1151 if (*ppos) 1152 return -EINVAL; 1153 1154 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1155 if (ret < 0) 1156 return ret; 1157 1158 switch (sysfs_match_string(options, buf)) { 1159 case 0: 1160 ret = cs35l56_perform_calibration(cs35l56_base); 1161 if (ret < 0) 1162 return ret; 1163 break; 1164 case 1: 1165 if (!cs35l56_base->cal_data_valid) 1166 return -ENODATA; 1167 1168 num_amps = cs35l56_base->num_amps; 1169 if (num_amps == 0) 1170 num_amps = -1; 1171 1172 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1173 cs35l56_base->cal_index, 1174 num_amps, 1175 &cs35l56_base->cal_data); 1176 if (ret < 0) 1177 return ret; 1178 break; 1179 default: 1180 return -EOPNOTSUPP; 1181 } 1182 1183 return count; 1184 } 1185 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1186 1187 int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base) 1188 { 1189 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL)) 1190 return -ENXIO; 1191 1192 return cs35l56_perform_calibration(cs35l56_base); 1193 } 1194 EXPORT_SYMBOL_NS_GPL(cs35l56_factory_calibrate, "SND_SOC_CS35L56_SHARED"); 1195 1196 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1197 const char __user *from, size_t count, 1198 loff_t *ppos) 1199 { 1200 unsigned long val; 1201 int ret; 1202 1203 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1204 return -ENXIO; 1205 1206 if (*ppos) 1207 return -EINVAL; 1208 1209 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1210 if (ret) 1211 return ret; 1212 1213 ret = kstrtoul_from_user(from, count, 10, &val); 1214 if (ret < 0) 1215 goto out; 1216 1217 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1218 if (ret) 1219 ret = -EIO; 1220 out: 1221 pm_runtime_put(cs35l56_base->dev); 1222 1223 if (ret < 0) 1224 return ret; 1225 1226 return count; 1227 } 1228 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1229 1230 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1231 char __user *to, size_t count, 1232 loff_t *ppos) 1233 { 1234 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1235 return -ENXIO; 1236 1237 if (!cs35l56_base->cal_data_valid) 1238 return 0; 1239 1240 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1241 sizeof(cs35l56_base->cal_data)); 1242 } 1243 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1244 1245 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1246 const char __user *from, size_t count, 1247 loff_t *ppos) 1248 { 1249 struct cirrus_amp_cal_data cal_data; 1250 int ret; 1251 1252 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1253 return -ENXIO; 1254 1255 /* Only allow a full blob to be written */ 1256 if (*ppos || (count != sizeof(cal_data))) 1257 return -EMSGSIZE; 1258 1259 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1260 if (ret) 1261 return ret; 1262 1263 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1264 if (ret) 1265 return ret; 1266 1267 return count; 1268 } 1269 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1270 1271 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1272 const struct cs35l56_cal_debugfs_fops *fops) 1273 { 1274 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1275 return; 1276 1277 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1278 1279 debugfs_create_file("calibrate", 1280 0200, cs35l56_base->debugfs, cs35l56_base, 1281 &fops->calibrate); 1282 debugfs_create_file("cal_temperature", 1283 0200, cs35l56_base->debugfs, cs35l56_base, 1284 &fops->cal_temperature); 1285 debugfs_create_file("cal_data", 1286 0644, cs35l56_base->debugfs, cs35l56_base, 1287 &fops->cal_data); 1288 } 1289 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1290 1291 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1292 { 1293 debugfs_remove_recursive(cs35l56_base->debugfs); 1294 } 1295 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1296 1297 const char * const cs35l56_cal_set_status_text[] = { 1298 "Unknown", "Default", "Set", 1299 }; 1300 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1301 1302 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1303 struct snd_ctl_elem_value *uvalue) 1304 { 1305 struct cs_dsp *dsp = cs35l56_base->dsp; 1306 __be32 cal_set_status_be; 1307 int alg_id; 1308 int ret; 1309 1310 switch (cs35l56_base->type) { 1311 case 0x54: 1312 case 0x56: 1313 case 0x57: 1314 alg_id = 0x9f210; 1315 break; 1316 default: 1317 alg_id = 0xbf210; 1318 break; 1319 } 1320 1321 scoped_guard(mutex, &dsp->pwr_lock) { 1322 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1323 "CAL_SET_STATUS", 1324 WMFW_ADSP2_YM, alg_id), 1325 0, &cal_set_status_be, 1326 sizeof(cal_set_status_be)); 1327 } 1328 if (ret) { 1329 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1330 return 0; 1331 } 1332 1333 switch (be32_to_cpu(cal_set_status_be)) { 1334 case CS35L56_CAL_SET_STATUS_DEFAULT: 1335 case CS35L56_CAL_SET_STATUS_SET: 1336 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1337 return 0; 1338 default: 1339 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1340 return 0; 1341 } 1342 } 1343 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1344 1345 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1346 bool *fw_missing, unsigned int *fw_version) 1347 { 1348 unsigned int prot_status; 1349 int ret; 1350 1351 ret = regmap_read(cs35l56_base->regmap, 1352 cs35l56_base->fw_reg->prot_sts, &prot_status); 1353 if (ret) { 1354 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1355 return ret; 1356 } 1357 1358 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1359 1360 ret = regmap_read(cs35l56_base->regmap, 1361 cs35l56_base->fw_reg->fw_ver, fw_version); 1362 if (ret) { 1363 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1364 return ret; 1365 } 1366 1367 return 0; 1368 } 1369 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1370 1371 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1372 { 1373 unsigned int firmware_version; 1374 bool firmware_missing; 1375 int ret; 1376 1377 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1378 if (ret) 1379 return; 1380 1381 if (!firmware_missing) 1382 return; 1383 1384 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1385 } 1386 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1387 1388 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1389 { 1390 __be32 pid, sid, tid; 1391 unsigned int alg_id; 1392 int ret; 1393 1394 switch (cs35l56_base->type) { 1395 case 0x54: 1396 case 0x56: 1397 case 0x57: 1398 alg_id = 0x9f212; 1399 break; 1400 default: 1401 alg_id = 0xbf212; 1402 break; 1403 } 1404 1405 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1406 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1407 WMFW_ADSP2_XM, alg_id), 1408 0, &pid, sizeof(pid)); 1409 if (!ret) 1410 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1411 WMFW_ADSP2_XM, alg_id), 1412 0, &sid, sizeof(sid)); 1413 if (!ret) 1414 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1415 WMFW_ADSP2_XM, alg_id), 1416 0, &tid, sizeof(tid)); 1417 } 1418 1419 if (ret) 1420 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1421 else 1422 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1423 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1424 } 1425 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1426 1427 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1428 { 1429 int ret; 1430 unsigned int devid, revid, otpid, secured, fw_ver; 1431 bool fw_missing; 1432 1433 /* 1434 * When the system is not using a reset_gpio ensure the device is 1435 * awake, otherwise the device has just been released from reset and 1436 * the driver must wait for the control port to become usable. 1437 */ 1438 if (!cs35l56_base->reset_gpio) 1439 cs35l56_issue_wake_event(cs35l56_base); 1440 else 1441 cs35l56_wait_control_port_ready(); 1442 1443 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1444 if (ret < 0) { 1445 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1446 return ret; 1447 } 1448 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1449 cs35l56_set_fw_reg_table(cs35l56_base); 1450 1451 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1452 if (ret) 1453 return ret; 1454 1455 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1456 if (ret < 0) { 1457 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1458 return ret; 1459 } 1460 devid &= CS35L56_DEVID_MASK; 1461 1462 switch (devid) { 1463 case 0x35A54: 1464 case 0x35A56: 1465 case 0x35A57: 1466 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1467 break; 1468 case 0x35A630: 1469 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1470 devid = devid >> 4; 1471 break; 1472 default: 1473 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1474 return -ENODEV; 1475 } 1476 1477 cs35l56_base->type = devid & 0xFF; 1478 1479 /* Silicon is now identified and booted so exit cache-only */ 1480 regcache_cache_only(cs35l56_base->regmap, false); 1481 1482 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1483 if (ret) { 1484 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1485 return ret; 1486 } 1487 1488 /* When any bus is restricted treat the device as secured */ 1489 if (secured & CS35L56_RESTRICTED_MASK) 1490 cs35l56_base->secured = true; 1491 1492 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1493 if (ret < 0) { 1494 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1495 return ret; 1496 } 1497 1498 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1499 if (ret) 1500 return ret; 1501 1502 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1503 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1504 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1505 1506 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1507 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1508 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1509 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1510 0); 1511 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1512 CS35L56_TEMP_ERR_EINT1_MASK, 1513 0); 1514 1515 switch (cs35l56_base->type) { 1516 case 0x54: 1517 case 0x56: 1518 case 0x57: 1519 ret = cs35l56_read_silicon_uid(cs35l56_base); 1520 break; 1521 default: 1522 ret = cs35l63_read_silicon_uid(cs35l56_base); 1523 break; 1524 } 1525 if (ret) 1526 return ret; 1527 1528 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1529 1530 return 0; 1531 } 1532 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1533 1534 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1535 { 1536 struct gpio_descs *descs; 1537 u32 speaker_id; 1538 int i, ret; 1539 1540 /* Check for vendor-specific speaker ID method */ 1541 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1542 if (ret >= 0) { 1543 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1544 return ret; 1545 } else if (ret != -ENOENT) { 1546 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1547 return ret; 1548 } 1549 1550 /* Attempt to read the speaker type from a device property */ 1551 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1552 if (!ret) { 1553 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1554 return speaker_id; 1555 } 1556 1557 /* Read the speaker type qualifier from the motherboard GPIOs */ 1558 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1559 if (!descs) { 1560 return -ENOENT; 1561 } else if (IS_ERR(descs)) { 1562 ret = PTR_ERR(descs); 1563 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1564 } 1565 1566 speaker_id = 0; 1567 for (i = 0; i < descs->ndescs; i++) { 1568 ret = gpiod_get_value_cansleep(descs->desc[i]); 1569 if (ret < 0) { 1570 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1571 goto err; 1572 } 1573 1574 speaker_id |= (ret << i); 1575 } 1576 1577 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1578 ret = speaker_id; 1579 err: 1580 gpiod_put_array(descs); 1581 1582 return ret; 1583 } 1584 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1585 1586 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1587 const u32 *gpios, int num_gpios, 1588 const u32 *pulls, int num_pulls) 1589 { 1590 int max_gpio; 1591 int ret = 0; 1592 int i; 1593 1594 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1595 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1596 return -EOVERFLOW; 1597 1598 switch (cs35l56_base->type) { 1599 case 0x54: 1600 case 0x56: 1601 case 0x57: 1602 max_gpio = CS35L56_MAX_GPIO; 1603 break; 1604 default: 1605 max_gpio = CS35L63_MAX_GPIO; 1606 break; 1607 } 1608 1609 for (i = 0; i < num_gpios; i++) { 1610 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1611 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1612 /* Keep going so we log all bad values */ 1613 ret = -EINVAL; 1614 } 1615 1616 /* Change to zero-based */ 1617 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1618 } 1619 1620 for (i = 0; i < num_pulls; i++) { 1621 switch (pulls[i]) { 1622 case 0: 1623 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1624 break; 1625 case 1: 1626 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1627 break; 1628 case 2: 1629 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1630 break; 1631 default: 1632 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1633 /* Keep going so we log all bad values */ 1634 ret = -EINVAL; 1635 break; 1636 } 1637 } 1638 if (ret) 1639 return ret; 1640 1641 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1642 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1643 1644 return 0; 1645 } 1646 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1647 1648 /* Caller must pm_runtime resume before calling this function */ 1649 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1650 { 1651 struct regmap *regmap = cs35l56_base->regmap; 1652 unsigned int addr_offset, val; 1653 int num_gpios, num_pulls; 1654 int i, ret; 1655 1656 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1657 1658 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1659 return 0; 1660 1661 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1662 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1663 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1664 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1665 1666 for (i = 0; i < num_gpios; i++) { 1667 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1668 1669 /* Set unspecified pulls to NONE */ 1670 if (i < num_pulls) { 1671 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1672 cs35l56_base->onchip_spkid_pulls[i]); 1673 } else { 1674 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1675 } 1676 1677 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1678 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1679 val | CS35L56_PAD_GPIO_IE); 1680 if (ret) { 1681 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1682 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1683 return ret; 1684 } 1685 } 1686 1687 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1688 if (ret) { 1689 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1690 return ret; 1691 } 1692 1693 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1694 1695 return 0; 1696 } 1697 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1698 1699 /* Caller must pm_runtime resume before calling this function */ 1700 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1701 { 1702 struct regmap *regmap = cs35l56_base->regmap; 1703 unsigned int addr_offset, val; 1704 int num_gpios; 1705 int speaker_id = 0; 1706 int i, ret; 1707 1708 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1709 1710 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1711 return -ENOENT; 1712 1713 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1714 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1715 1716 for (i = 0; i < num_gpios; i++) { 1717 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1718 1719 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1720 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1721 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1722 if (ret) { 1723 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1724 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1725 return ret; 1726 } 1727 } 1728 1729 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1730 if (ret) { 1731 dev_err(cs35l56_base->dev, "GPIO%d status read failed: %d\n", 1732 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1733 return ret; 1734 } 1735 1736 for (i = 0; i < num_gpios; i++) { 1737 speaker_id <<= 1; 1738 1739 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1740 speaker_id |= 1; 1741 } 1742 1743 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1744 1745 return speaker_id; 1746 } 1747 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1748 1749 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1750 [0x0C] = 128000, 1751 [0x0F] = 256000, 1752 [0x11] = 384000, 1753 [0x12] = 512000, 1754 [0x15] = 768000, 1755 [0x17] = 1024000, 1756 [0x1A] = 1500000, 1757 [0x1B] = 1536000, 1758 [0x1C] = 2000000, 1759 [0x1D] = 2048000, 1760 [0x1E] = 2400000, 1761 [0x20] = 3000000, 1762 [0x21] = 3072000, 1763 [0x23] = 4000000, 1764 [0x24] = 4096000, 1765 [0x25] = 4800000, 1766 [0x27] = 6000000, 1767 [0x28] = 6144000, 1768 [0x29] = 6250000, 1769 [0x2A] = 6400000, 1770 [0x2E] = 8000000, 1771 [0x2F] = 8192000, 1772 [0x30] = 9600000, 1773 [0x32] = 12000000, 1774 [0x33] = 12288000, 1775 [0x37] = 13500000, 1776 [0x38] = 19200000, 1777 [0x39] = 22579200, 1778 [0x3B] = 24576000, 1779 }; 1780 1781 int cs35l56_get_bclk_freq_id(unsigned int freq) 1782 { 1783 int i; 1784 1785 if (freq == 0) 1786 return -EINVAL; 1787 1788 /* The BCLK frequency must be a valid PLL REFCLK */ 1789 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1790 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1791 return i; 1792 } 1793 1794 return -EINVAL; 1795 } 1796 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1797 1798 static const char * const cs35l56_supplies[/* auto-sized */] = { 1799 "VDD_P", 1800 "VDD_IO", 1801 "VDD_A", 1802 }; 1803 1804 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1805 { 1806 int i; 1807 1808 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1809 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1810 data[i].supply = cs35l56_supplies[i]; 1811 } 1812 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1813 1814 const char * const cs35l56_tx_input_texts[] = { 1815 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1816 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1817 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1818 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1819 }; 1820 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1821 1822 const unsigned int cs35l56_tx_input_values[] = { 1823 CS35L56_INPUT_SRC_NONE, 1824 CS35L56_INPUT_SRC_ASP1RX1, 1825 CS35L56_INPUT_SRC_ASP1RX2, 1826 CS35L56_INPUT_SRC_VMON, 1827 CS35L56_INPUT_SRC_IMON, 1828 CS35L56_INPUT_SRC_ERR_VOL, 1829 CS35L56_INPUT_SRC_CLASSH, 1830 CS35L56_INPUT_SRC_VDDBMON, 1831 CS35L56_INPUT_SRC_VBSTMON, 1832 CS35L56_INPUT_SRC_DSP1TX1, 1833 CS35L56_INPUT_SRC_DSP1TX2, 1834 CS35L56_INPUT_SRC_DSP1TX3, 1835 CS35L56_INPUT_SRC_DSP1TX4, 1836 CS35L56_INPUT_SRC_DSP1TX5, 1837 CS35L56_INPUT_SRC_DSP1TX6, 1838 CS35L56_INPUT_SRC_DSP1TX7, 1839 CS35L56_INPUT_SRC_DSP1TX8, 1840 CS35L56_INPUT_SRC_TEMPMON, 1841 CS35L56_INPUT_SRC_INTERPOLATOR, 1842 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1843 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1844 }; 1845 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1846 1847 const struct regmap_config cs35l56_regmap_i2c = { 1848 .reg_bits = 32, 1849 .val_bits = 32, 1850 .reg_stride = 4, 1851 .reg_format_endian = REGMAP_ENDIAN_BIG, 1852 .val_format_endian = REGMAP_ENDIAN_BIG, 1853 .max_register = CS35L56_DSP1_PMEM_5114, 1854 .reg_defaults = cs35l56_reg_defaults, 1855 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1856 .volatile_reg = cs35l56_volatile_reg, 1857 .readable_reg = cs35l56_readable_reg, 1858 .precious_reg = cs35l56_precious_reg, 1859 .cache_type = REGCACHE_MAPLE, 1860 }; 1861 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1862 1863 const struct regmap_config cs35l56_regmap_spi = { 1864 .reg_bits = 32, 1865 .val_bits = 32, 1866 .pad_bits = 16, 1867 .reg_stride = 4, 1868 .reg_format_endian = REGMAP_ENDIAN_BIG, 1869 .val_format_endian = REGMAP_ENDIAN_BIG, 1870 .max_register = CS35L56_DSP1_PMEM_5114, 1871 .reg_defaults = cs35l56_reg_defaults, 1872 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1873 .volatile_reg = cs35l56_volatile_reg, 1874 .readable_reg = cs35l56_readable_reg, 1875 .precious_reg = cs35l56_precious_reg, 1876 .cache_type = REGCACHE_MAPLE, 1877 }; 1878 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1879 1880 const struct regmap_config cs35l56_regmap_sdw = { 1881 .reg_bits = 32, 1882 .val_bits = 32, 1883 .reg_stride = 4, 1884 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1885 .val_format_endian = REGMAP_ENDIAN_BIG, 1886 .max_register = CS35L56_DSP1_PMEM_5114, 1887 .reg_defaults = cs35l56_reg_defaults, 1888 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1889 .volatile_reg = cs35l56_volatile_reg, 1890 .readable_reg = cs35l56_readable_reg, 1891 .precious_reg = cs35l56_precious_reg, 1892 .cache_type = REGCACHE_MAPLE, 1893 }; 1894 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1895 1896 const struct regmap_config cs35l63_regmap_i2c = { 1897 .reg_bits = 32, 1898 .val_bits = 32, 1899 .reg_stride = 4, 1900 .reg_base = 0x8000, 1901 .reg_format_endian = REGMAP_ENDIAN_BIG, 1902 .val_format_endian = REGMAP_ENDIAN_BIG, 1903 .max_register = CS35L56_DSP1_PMEM_5114, 1904 .reg_defaults = cs35l63_reg_defaults, 1905 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1906 .volatile_reg = cs35l63_volatile_reg, 1907 .readable_reg = cs35l56_readable_reg, 1908 .precious_reg = cs35l56_precious_reg, 1909 .cache_type = REGCACHE_MAPLE, 1910 }; 1911 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1912 1913 const struct regmap_config cs35l63_regmap_sdw = { 1914 .reg_bits = 32, 1915 .val_bits = 32, 1916 .reg_stride = 4, 1917 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1918 .val_format_endian = REGMAP_ENDIAN_BIG, 1919 .max_register = CS35L56_DSP1_PMEM_5114, 1920 .reg_defaults = cs35l63_reg_defaults, 1921 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1922 .volatile_reg = cs35l63_volatile_reg, 1923 .readable_reg = cs35l56_readable_reg, 1924 .precious_reg = cs35l56_precious_reg, 1925 .cache_type = REGCACHE_MAPLE, 1926 }; 1927 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1928 1929 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1930 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1931 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1932 MODULE_LICENSE("GPL"); 1933 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1934 MODULE_IMPORT_NS("FW_CS_DSP"); 1935