1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_asp_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 }; 47 48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base) 49 { 50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch, 51 ARRAY_SIZE(cs35l56_asp_patch)); 52 } 53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED"); 54 55 static const struct reg_sequence cs35l56_patch[] = { 56 /* 57 * Firmware can change these to non-defaults to satisfy SDCA. 58 * Ensure that they are at known defaults. 59 */ 60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 65 }; 66 67 static const struct reg_sequence cs35l56_patch_fw[] = { 68 /* These are not reset by a soft-reset, so patch to defaults. */ 69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 72 }; 73 74 static const struct reg_sequence cs35l63_patch_fw[] = { 75 /* These are not reset by a soft-reset, so patch to defaults. */ 76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 79 }; 80 81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 82 { 83 int ret; 84 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 86 ARRAY_SIZE(cs35l56_patch)); 87 if (ret) 88 return ret; 89 90 91 switch (cs35l56_base->type) { 92 case 0x54: 93 case 0x56: 94 case 0x57: 95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 96 ARRAY_SIZE(cs35l56_patch_fw)); 97 break; 98 case 0x63: 99 case 0x62: 100 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 101 ARRAY_SIZE(cs35l63_patch_fw)); 102 break; 103 default: 104 break; 105 } 106 107 return ret; 108 } 109 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 110 111 static const struct reg_default cs35l56_reg_defaults[] = { 112 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 113 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 114 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 115 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 116 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 117 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 118 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 119 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 120 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 121 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 122 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 123 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 124 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 125 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 126 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 127 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 128 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 129 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 130 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 131 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 132 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 133 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 134 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 135 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 136 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 137 }; 138 139 static const struct reg_default cs35l63_reg_defaults[] = { 140 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 141 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 142 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 143 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 144 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 145 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 146 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 147 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 148 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 149 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 150 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 151 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 152 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 153 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 154 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 155 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 156 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 157 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 158 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 159 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 160 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 161 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 162 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 163 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 164 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 165 }; 166 167 static bool cs35l56_is_dsp_memory(unsigned int reg) 168 { 169 switch (reg) { 170 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 171 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 172 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 173 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 174 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 175 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 176 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 184 { 185 switch (reg) { 186 case CS35L56_DEVID: 187 case CS35L56_REVID: 188 case CS35L56_RELID: 189 case CS35L56_OTPID: 190 case CS35L56_SFT_RESET: 191 case CS35L56_GLOBAL_ENABLES: 192 case CS35L56_BLOCK_ENABLES: 193 case CS35L56_BLOCK_ENABLES2: 194 case CS35L56_REFCLK_INPUT: 195 case CS35L56_GLOBAL_SAMPLE_RATE: 196 case CS35L56_OTP_MEM_53: 197 case CS35L56_OTP_MEM_54: 198 case CS35L56_OTP_MEM_55: 199 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 200 case CS35L56_UPDATE_REGS: 201 case CS35L56_ASP1_ENABLES1: 202 case CS35L56_ASP1_CONTROL1: 203 case CS35L56_ASP1_CONTROL2: 204 case CS35L56_ASP1_CONTROL3: 205 case CS35L56_ASP1_FRAME_CONTROL1: 206 case CS35L56_ASP1_FRAME_CONTROL5: 207 case CS35L56_ASP1_DATA_CONTROL1: 208 case CS35L56_ASP1_DATA_CONTROL5: 209 case CS35L56_DACPCM1_INPUT: 210 case CS35L56_DACPCM2_INPUT: 211 case CS35L56_ASP1TX1_INPUT: 212 case CS35L56_ASP1TX2_INPUT: 213 case CS35L56_ASP1TX3_INPUT: 214 case CS35L56_ASP1TX4_INPUT: 215 case CS35L56_DSP1RX1_INPUT: 216 case CS35L56_DSP1RX2_INPUT: 217 case CS35L56_SWIRE_DP3_CH1_INPUT: 218 case CS35L56_SWIRE_DP3_CH2_INPUT: 219 case CS35L56_SWIRE_DP3_CH3_INPUT: 220 case CS35L56_SWIRE_DP3_CH4_INPUT: 221 case CS35L56_IRQ1_CFG: 222 case CS35L56_IRQ1_STATUS: 223 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 224 case CS35L56_IRQ1_EINT_18: 225 case CS35L56_IRQ1_EINT_20: 226 case CS35L56_IRQ1_MASK_1: 227 case CS35L56_IRQ1_MASK_2: 228 case CS35L56_IRQ1_MASK_4: 229 case CS35L56_IRQ1_MASK_8: 230 case CS35L56_IRQ1_MASK_18: 231 case CS35L56_IRQ1_MASK_20: 232 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 233 case CS35L56_MIXER_NGATE_CH1_CFG: 234 case CS35L56_MIXER_NGATE_CH2_CFG: 235 case CS35L56_DSP_VIRTUAL1_MBOX_1: 236 case CS35L56_DSP_VIRTUAL1_MBOX_2: 237 case CS35L56_DSP_VIRTUAL1_MBOX_3: 238 case CS35L56_DSP_VIRTUAL1_MBOX_4: 239 case CS35L56_DSP_VIRTUAL1_MBOX_5: 240 case CS35L56_DSP_VIRTUAL1_MBOX_6: 241 case CS35L56_DSP_VIRTUAL1_MBOX_7: 242 case CS35L56_DSP_VIRTUAL1_MBOX_8: 243 case CS35L56_DIE_STS1: 244 case CS35L56_DIE_STS2: 245 case CS35L56_DSP_RESTRICT_STS1: 246 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 247 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 248 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 249 case CS35L56_DSP1_SCRATCH1: 250 case CS35L56_DSP1_SCRATCH2: 251 case CS35L56_DSP1_SCRATCH3: 252 case CS35L56_DSP1_SCRATCH4: 253 return true; 254 default: 255 return cs35l56_is_dsp_memory(reg); 256 } 257 } 258 259 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 260 { 261 switch (reg) { 262 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 263 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 264 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 265 return true; 266 default: 267 return false; 268 } 269 } 270 271 static bool cs35l56_common_volatile_reg(unsigned int reg) 272 { 273 switch (reg) { 274 case CS35L56_DEVID: 275 case CS35L56_REVID: 276 case CS35L56_RELID: 277 case CS35L56_OTPID: 278 case CS35L56_SFT_RESET: 279 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 280 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 281 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 282 case CS35L56_OTP_MEM_53: 283 case CS35L56_OTP_MEM_54: 284 case CS35L56_OTP_MEM_55: 285 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 286 case CS35L56_UPDATE_REGS: 287 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 288 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 289 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 290 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 291 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 292 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 293 case CS35L56_IRQ1_STATUS: 294 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 295 case CS35L56_IRQ1_EINT_18: 296 case CS35L56_IRQ1_EINT_20: 297 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 298 case CS35L56_MIXER_NGATE_CH1_CFG: 299 case CS35L56_MIXER_NGATE_CH2_CFG: 300 case CS35L56_DSP_VIRTUAL1_MBOX_1: 301 case CS35L56_DSP_VIRTUAL1_MBOX_2: 302 case CS35L56_DSP_VIRTUAL1_MBOX_3: 303 case CS35L56_DSP_VIRTUAL1_MBOX_4: 304 case CS35L56_DSP_VIRTUAL1_MBOX_5: 305 case CS35L56_DSP_VIRTUAL1_MBOX_6: 306 case CS35L56_DSP_VIRTUAL1_MBOX_7: 307 case CS35L56_DSP_VIRTUAL1_MBOX_8: 308 case CS35L56_DSP_RESTRICT_STS1: 309 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 311 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 312 case CS35L56_DSP1_SCRATCH1: 313 case CS35L56_DSP1_SCRATCH2: 314 case CS35L56_DSP1_SCRATCH3: 315 case CS35L56_DSP1_SCRATCH4: 316 return true; 317 default: 318 return cs35l56_is_dsp_memory(reg); 319 } 320 } 321 322 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 323 { 324 switch (reg) { 325 case CS35L56_MAIN_RENDER_USER_MUTE: 326 case CS35L56_MAIN_RENDER_USER_VOLUME: 327 case CS35L56_MAIN_POSTURE_NUMBER: 328 return false; 329 default: 330 return cs35l56_common_volatile_reg(reg); 331 } 332 } 333 334 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 335 { 336 switch (reg) { 337 case CS35L63_MAIN_RENDER_USER_MUTE: 338 case CS35L63_MAIN_RENDER_USER_VOLUME: 339 case CS35L63_MAIN_POSTURE_NUMBER: 340 return false; 341 default: 342 return cs35l56_common_volatile_reg(reg); 343 } 344 } 345 346 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 347 .fw_ver = CS35L56_DSP1_FW_VER, 348 .halo_state = CS35L56_DSP1_HALO_STATE, 349 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 350 .prot_sts = CS35L56_PROTECTION_STATUS, 351 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 352 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 353 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 354 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 355 }; 356 357 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 358 .fw_ver = CS35L56_DSP1_FW_VER, 359 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 360 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 361 .prot_sts = CS35L56_PROTECTION_STATUS, 362 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 363 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 364 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 365 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 366 }; 367 368 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 369 .fw_ver = CS35L63_DSP1_FW_VER, 370 .halo_state = CS35L63_DSP1_HALO_STATE, 371 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 372 .prot_sts = CS35L63_PROTECTION_STATUS, 373 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 374 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 375 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 376 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 377 }; 378 379 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 380 { 381 switch (cs35l56_base->type) { 382 default: 383 switch (cs35l56_base->rev) { 384 case 0xb0: 385 cs35l56_base->fw_reg = &cs35l56_fw_reg; 386 break; 387 default: 388 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 389 break; 390 } 391 break; 392 case 0x63: 393 case 0x62: 394 cs35l56_base->fw_reg = &cs35l63_fw_reg; 395 break; 396 } 397 } 398 399 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 400 { 401 unsigned int val; 402 int ret; 403 404 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 405 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 406 val, (val == 0), 407 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 408 if (ret) { 409 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 410 return ret; 411 } 412 413 return 0; 414 } 415 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 416 417 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 418 { 419 int ret; 420 unsigned int val; 421 422 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 423 if (ret) 424 return ret; 425 426 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 427 cs35l56_base->fw_reg->pm_cur_stat, 428 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 429 CS35L56_HALO_STATE_POLL_US, 430 CS35L56_HALO_STATE_TIMEOUT_US); 431 if (ret < 0) 432 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 433 val, ret); 434 return ret; 435 } 436 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 437 438 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 439 { 440 unsigned int val = 0; 441 int read_ret, poll_ret; 442 443 /* 444 * The regmap must remain in cache-only until the chip has 445 * booted, so use a bypassed read of the status register. 446 */ 447 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 448 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 449 CS35L56_HALO_STATE_POLL_US, 450 CS35L56_HALO_STATE_TIMEOUT_US, 451 false, 452 cs35l56_base->regmap, 453 cs35l56_base->fw_reg->halo_state, 454 &val); 455 456 if (poll_ret) { 457 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 458 read_ret, val); 459 return -EIO; 460 } 461 462 return 0; 463 } 464 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 465 466 void cs35l56_wait_control_port_ready(void) 467 { 468 /* Wait for control port to be ready (datasheet tIRS). */ 469 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 470 } 471 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 472 473 void cs35l56_wait_min_reset_pulse(void) 474 { 475 /* Satisfy minimum reset pulse width spec */ 476 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 477 } 478 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 479 480 static const struct { 481 u32 addr; 482 u32 value; 483 } cs35l56_spi_system_reset_stages[] = { 484 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 485 /* The next write is necessary to delimit the soft reset */ 486 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 487 }; 488 489 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 490 struct spi_device *spi) 491 { 492 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 493 struct spi_transfer t = { 494 .tx_buf = buf, 495 .len = sizeof(*buf), 496 }; 497 struct spi_message m; 498 int i, ret; 499 500 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 501 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 502 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 503 spi_message_init_with_transfers(&m, &t, 1); 504 ret = spi_sync_locked(spi, &m); 505 if (ret) 506 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 507 508 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 509 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 510 } 511 } 512 513 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 514 { 515 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 516 unsigned int val; 517 int read_ret, ret; 518 519 /* 520 * There must not be any other SPI bus activity while the amp is 521 * soft-resetting. 522 */ 523 ret = spi_bus_lock(spi->controller); 524 if (ret) { 525 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 526 return; 527 } 528 529 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 530 spi_bus_unlock(spi->controller); 531 532 /* 533 * Check firmware boot by testing for a response in MBOX_2. 534 * HALO_STATE cannot be trusted yet because the reset sequence 535 * can leave it with stale state. But MBOX is reset. 536 * The regmap must remain in cache-only until the chip has 537 * booted, so use a bypassed read. 538 */ 539 val = 0; 540 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 541 (val > 0) && (val < 0xffffffff), 542 CS35L56_HALO_STATE_POLL_US, 543 CS35L56_HALO_STATE_TIMEOUT_US, 544 false, 545 cs35l56_base->regmap, 546 CS35L56_DSP_VIRTUAL1_MBOX_2, 547 &val); 548 if (ret) { 549 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 550 read_ret, val); 551 } 552 } 553 554 static const struct reg_sequence cs35l56_system_reset_seq[] = { 555 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 556 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 557 }; 558 559 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 560 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 561 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 562 }; 563 564 static const struct reg_sequence cs35l63_system_reset_seq[] = { 565 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 566 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 567 }; 568 569 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 570 { 571 /* 572 * Must enter cache-only first so there can't be any more register 573 * accesses other than the controlled system reset sequence below. 574 */ 575 regcache_cache_only(cs35l56_base->regmap, true); 576 577 if (cs35l56_is_spi(cs35l56_base)) { 578 cs35l56_spi_system_reset(cs35l56_base); 579 return; 580 } 581 582 switch (cs35l56_base->type) { 583 case 0x54: 584 case 0x56: 585 case 0x57: 586 switch (cs35l56_base->rev) { 587 case 0xb0: 588 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 589 cs35l56_system_reset_seq, 590 ARRAY_SIZE(cs35l56_system_reset_seq)); 591 break; 592 default: 593 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 594 cs35l56_b2_system_reset_seq, 595 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 596 break; 597 } 598 break; 599 case 0x63: 600 case 0x62: 601 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 602 cs35l63_system_reset_seq, 603 ARRAY_SIZE(cs35l63_system_reset_seq)); 604 break; 605 default: 606 break; 607 } 608 609 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 610 if (is_soundwire) 611 return; 612 613 cs35l56_wait_control_port_ready(); 614 615 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 616 } 617 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 618 619 static irqreturn_t cs35l56_irq(int irq, void *data) 620 { 621 struct cs35l56_base *cs35l56_base = data; 622 unsigned int status1 = 0, status8 = 0, status20 = 0; 623 unsigned int mask1, mask8, mask20; 624 unsigned int val; 625 int rv; 626 627 if (!cs35l56_base->init_done) 628 return IRQ_NONE; 629 630 guard(mutex)(&cs35l56_base->irq_lock); 631 632 PM_RUNTIME_ACQUIRE_IF_ENABLED(cs35l56_base->dev, pm); 633 rv = PM_RUNTIME_ACQUIRE_ERR(&pm); 634 if (rv < 0) { 635 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 636 return IRQ_NONE; 637 } 638 639 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 640 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 641 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 642 return IRQ_NONE; 643 } 644 645 /* Ack interrupts */ 646 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 647 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 648 status1 &= ~mask1; 649 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 650 651 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 652 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 653 status8 &= ~mask8; 654 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 655 656 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 657 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 658 status20 &= ~mask20; 659 /* We don't want EINT20 but they default to unmasked: force mask */ 660 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 661 662 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 663 664 /* Check to see if unmasked bits are active */ 665 if (!status1 && !status8 && !status20) 666 return IRQ_NONE; 667 668 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 669 dev_crit(cs35l56_base->dev, "Amp short error\n"); 670 671 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 672 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 673 674 return IRQ_HANDLED; 675 } 676 677 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 678 { 679 int ret; 680 681 if (irq < 1) 682 return 0; 683 684 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 685 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 686 "cs35l56", cs35l56_base); 687 if (!ret) 688 cs35l56_base->irq = irq; 689 else 690 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 691 692 return ret; 693 } 694 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 695 696 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 697 { 698 unsigned int val; 699 int ret; 700 701 /* 702 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 703 * can't be used here to test for memory retention. 704 * Assume that tuning must be re-loaded. 705 */ 706 if (cs35l56_base->secured) 707 return true; 708 709 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 710 if (ret) { 711 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 712 return ret; 713 } 714 715 ret = regmap_read(cs35l56_base->regmap, 716 cs35l56_base->fw_reg->prot_sts, 717 &val); 718 if (ret) 719 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 720 else 721 ret = !!(val & CS35L56_FIRMWARE_MISSING); 722 723 pm_runtime_put_autosuspend(cs35l56_base->dev); 724 725 return ret; 726 } 727 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 728 729 static const struct reg_sequence cs35l56_hibernate_seq[] = { 730 /* This must be the last register access */ 731 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 732 }; 733 734 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 735 { 736 unsigned int val; 737 738 /* 739 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 740 * transactions to meet the minimum required time from the rising edge 741 * to the last falling edge of wake. 742 * 743 * It uses bypassed read because we must wake the chip before 744 * disabling regmap cache-only. 745 */ 746 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 747 748 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 749 750 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 751 752 cs35l56_wait_control_port_ready(); 753 } 754 755 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 756 { 757 unsigned int val; 758 int ret; 759 760 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 761 cs35l56_base->fw_reg->transducer_actual_ps, 762 val, (val >= CS35L56_PS3), 763 CS35L56_PS3_POLL_US, 764 CS35L56_PS3_TIMEOUT_US); 765 if (ret) 766 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 767 768 return ret; 769 } 770 771 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 772 { 773 if (!cs35l56_base->init_done) 774 return 0; 775 776 /* Firmware must have entered a power-save state */ 777 cs35l56_wait_for_ps3(cs35l56_base); 778 779 /* Clear BOOT_DONE so it can be used to detect a reboot */ 780 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 781 782 if (!cs35l56_base->can_hibernate) { 783 regcache_cache_only(cs35l56_base->regmap, true); 784 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 785 786 return 0; 787 } 788 789 /* 790 * Must enter cache-only first so there can't be any more register 791 * accesses other than the controlled hibernate sequence below. 792 */ 793 regcache_cache_only(cs35l56_base->regmap, true); 794 795 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 796 cs35l56_hibernate_seq, 797 ARRAY_SIZE(cs35l56_hibernate_seq)); 798 799 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 800 801 return 0; 802 } 803 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 804 805 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 806 { 807 unsigned int val; 808 int ret; 809 810 if (!cs35l56_base->init_done) 811 return 0; 812 813 /* Hibernate wake must be done before releasing cache-only */ 814 if (cs35l56_base->can_hibernate && !is_soundwire) 815 cs35l56_issue_wake_event(cs35l56_base); 816 817 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 818 if (ret) { 819 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 820 goto err; 821 } 822 823 regcache_cache_only(cs35l56_base->regmap, false); 824 825 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 826 if (ret) 827 goto err; 828 829 /* BOOT_DONE will be 1 if the amp reset */ 830 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 831 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 832 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 833 regcache_mark_dirty(cs35l56_base->regmap); 834 } 835 836 regcache_sync(cs35l56_base->regmap); 837 838 dev_dbg(cs35l56_base->dev, "Resumed"); 839 840 return 0; 841 842 err: 843 regcache_cache_only(cs35l56_base->regmap, true); 844 845 if (cs35l56_base->can_hibernate) { 846 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 847 cs35l56_hibernate_seq, 848 ARRAY_SIZE(cs35l56_hibernate_seq)); 849 } 850 851 return ret; 852 } 853 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 854 855 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 856 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 857 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 858 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 859 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 860 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 861 }; 862 863 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 864 { 865 cs_dsp->num = 1; 866 cs_dsp->type = WMFW_HALO; 867 cs_dsp->rev = 0; 868 cs_dsp->dev = cs35l56_base->dev; 869 cs_dsp->regmap = cs35l56_base->regmap; 870 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 871 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 872 cs_dsp->mem = cs35l56_dsp1_regions; 873 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 874 cs_dsp->no_core_startstop = true; 875 876 cs35l56_base->dsp = cs_dsp; 877 } 878 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 879 880 struct cs35l56_pte { 881 u8 x; 882 u8 wafer_id; 883 u8 pte[2]; 884 u8 lot[3]; 885 u8 y; 886 u8 unused[3]; 887 u8 dvs; 888 } __packed; 889 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 890 891 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 892 { 893 struct cs35l56_pte pte; 894 u64 unique_id; 895 int ret; 896 897 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 898 if (ret) { 899 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 900 return ret; 901 } 902 903 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 904 unique_id <<= 32; 905 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 906 ((u32)pte.dvs << 24); 907 908 cs35l56_base->silicon_uid = unique_id; 909 910 return 0; 911 } 912 913 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 914 { 915 u32 tmp[2]; 916 u64 unique_id; 917 int ret; 918 919 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 920 if (ret) { 921 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 922 return ret; 923 } 924 925 unique_id = tmp[1]; 926 unique_id <<= 32; 927 unique_id |= tmp[0]; 928 929 cs35l56_base->silicon_uid = unique_id; 930 931 return 0; 932 } 933 934 /* Firmware calibration controls */ 935 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 936 .alg_id = 0x9f210, 937 .mem_region = WMFW_ADSP2_YM, 938 .ambient = "CAL_AMBIENT", 939 .calr = "CAL_R", 940 .status = "CAL_STATUS", 941 .checksum = "CAL_CHECKSUM", 942 }; 943 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 944 945 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 946 .alg_id = 0xbf210, 947 .mem_region = WMFW_ADSP2_YM, 948 .ambient = "CAL_AMBIENT", 949 .calr = "CAL_R", 950 .status = "CAL_STATUS", 951 .checksum = "CAL_CHECKSUM", 952 }; 953 954 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 955 { 956 int ret; 957 958 /* Driver can't apply calibration to a secured part, so skip */ 959 if (cs35l56_base->secured) 960 return 0; 961 962 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 963 cs35l56_base->silicon_uid, 964 cs35l56_base->cal_index, 965 &cs35l56_base->cal_data); 966 967 /* Only return an error status if probe should be aborted */ 968 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 969 return 0; 970 971 if (ret < 0) 972 return ret; 973 974 cs35l56_base->cal_data_valid = true; 975 976 return 0; 977 } 978 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 979 980 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 981 const struct cirrus_amp_cal_data *data) 982 { 983 984 /* Ignore if it is empty */ 985 if (!data->calTime[0] && !data->calTime[1]) 986 return -ENODATA; 987 988 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 989 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 990 return -EINVAL; 991 } 992 993 cs35l56_base->cal_data = *data; 994 cs35l56_base->cal_data_valid = true; 995 996 return 0; 997 } 998 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 999 1000 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 1001 { 1002 const struct cirrus_amp_cal_controls *calibration_controls = 1003 cs35l56_base->calibration_controls; 1004 struct cs_dsp *dsp = cs35l56_base->dsp; 1005 struct cirrus_amp_cal_data cal_data; 1006 struct cs_dsp_coeff_ctl *ctl; 1007 bool ngate_ch1_was_enabled = false; 1008 bool ngate_ch2_was_enabled = false; 1009 int cali_norm_en_alg_id, cali_norm_en_mem; 1010 int ret; 1011 __be32 val; 1012 1013 if (cs35l56_base->silicon_uid == 0) { 1014 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1015 return -ENXIO; 1016 } 1017 1018 switch (cs35l56_base->type) { 1019 case 0x54: 1020 case 0x56: 1021 case 0x57: 1022 if (cs35l56_base->rev < 0xb2) { 1023 cali_norm_en_alg_id = 0x9f22f; 1024 cali_norm_en_mem = WMFW_ADSP2_YM; 1025 } else { 1026 cali_norm_en_alg_id = 0x9f210; 1027 cali_norm_en_mem = WMFW_ADSP2_XM; 1028 } 1029 break; 1030 default: 1031 cali_norm_en_alg_id = 0xbf210; 1032 cali_norm_en_mem = WMFW_ADSP2_XM; 1033 break; 1034 } 1035 1036 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1037 if (ret) 1038 return ret; 1039 1040 ret = cs35l56_wait_for_ps3(cs35l56_base); 1041 if (ret) { 1042 ret = -EBUSY; 1043 goto err_pm_put; 1044 } 1045 1046 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1047 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1048 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1049 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1050 1051 scoped_guard(mutex, &dsp->pwr_lock) { 1052 ctl = cs_dsp_get_ctl(dsp, 1053 calibration_controls->status, 1054 calibration_controls->mem_region, 1055 calibration_controls->alg_id); 1056 if (!ctl) { 1057 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1058 calibration_controls->status); 1059 ret = -EIO; 1060 goto err; 1061 } 1062 1063 val = cpu_to_be32(0); 1064 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1065 "CALI_NORM_EN", 1066 cali_norm_en_mem, 1067 cali_norm_en_alg_id), 1068 0, &val, sizeof(val)); 1069 if (ret < 0) { 1070 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1071 ret = -EIO; 1072 goto err; 1073 } 1074 1075 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1076 if (ret) { 1077 ret = -EIO; 1078 goto err; 1079 } 1080 1081 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1082 (val == cpu_to_be32(1)), 1083 CS35L56_CALIBRATION_POLL_US, 1084 CS35L56_CALIBRATION_TIMEOUT_US, 1085 true, 1086 ctl, 0, &val, sizeof(val))) { 1087 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1088 be32_to_cpu(val)); 1089 switch (be32_to_cpu(val)) { 1090 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1091 ret = -ERANGE; 1092 goto err; 1093 default: 1094 ret = -ETIMEDOUT; 1095 goto err; 1096 } 1097 } 1098 } 1099 1100 cs35l56_base->cal_data_valid = false; 1101 memset(&cal_data, 0, sizeof(cal_data)); 1102 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1103 if (ret) { 1104 ret = -EIO; 1105 goto err; 1106 } 1107 1108 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1109 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1110 1111 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1112 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1113 cs35l56_base->cal_data = cal_data; 1114 cs35l56_base->cal_data_valid = true; 1115 1116 ret = 0; 1117 1118 err: 1119 if (ngate_ch1_was_enabled) { 1120 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1121 CS35L56_AUX_NGATE_CHn_EN); 1122 } 1123 if (ngate_ch2_was_enabled) { 1124 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1125 CS35L56_AUX_NGATE_CHn_EN); 1126 } 1127 err_pm_put: 1128 pm_runtime_put(cs35l56_base->dev); 1129 1130 return ret; 1131 } 1132 1133 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1134 const char __user *from, size_t count, 1135 loff_t *ppos) 1136 { 1137 static const char * const options[] = { "factory", "store_uefi" }; 1138 char buf[11] = { 0 }; 1139 int num_amps, ret; 1140 1141 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1142 return -ENXIO; 1143 1144 if (*ppos) 1145 return -EINVAL; 1146 1147 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1148 if (ret < 0) 1149 return ret; 1150 1151 switch (sysfs_match_string(options, buf)) { 1152 case 0: 1153 ret = cs35l56_perform_calibration(cs35l56_base); 1154 if (ret < 0) 1155 return ret; 1156 break; 1157 case 1: 1158 if (!cs35l56_base->cal_data_valid) 1159 return -ENODATA; 1160 1161 num_amps = cs35l56_base->num_amps; 1162 if (num_amps == 0) 1163 num_amps = -1; 1164 1165 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1166 cs35l56_base->cal_index, 1167 num_amps, 1168 &cs35l56_base->cal_data); 1169 if (ret < 0) 1170 return ret; 1171 break; 1172 default: 1173 return -EOPNOTSUPP; 1174 } 1175 1176 return count; 1177 } 1178 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1179 1180 int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base) 1181 { 1182 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL)) 1183 return -ENXIO; 1184 1185 return cs35l56_perform_calibration(cs35l56_base); 1186 } 1187 EXPORT_SYMBOL_NS_GPL(cs35l56_factory_calibrate, "SND_SOC_CS35L56_SHARED"); 1188 1189 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1190 const char __user *from, size_t count, 1191 loff_t *ppos) 1192 { 1193 unsigned long val; 1194 int ret; 1195 1196 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1197 return -ENXIO; 1198 1199 if (*ppos) 1200 return -EINVAL; 1201 1202 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1203 if (ret) 1204 return ret; 1205 1206 ret = kstrtoul_from_user(from, count, 10, &val); 1207 if (ret < 0) 1208 goto out; 1209 1210 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1211 if (ret) 1212 ret = -EIO; 1213 out: 1214 pm_runtime_put(cs35l56_base->dev); 1215 1216 if (ret < 0) 1217 return ret; 1218 1219 return count; 1220 } 1221 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1222 1223 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1224 char __user *to, size_t count, 1225 loff_t *ppos) 1226 { 1227 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1228 return -ENXIO; 1229 1230 if (!cs35l56_base->cal_data_valid) 1231 return 0; 1232 1233 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1234 sizeof(cs35l56_base->cal_data)); 1235 } 1236 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1237 1238 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1239 const char __user *from, size_t count, 1240 loff_t *ppos) 1241 { 1242 struct cirrus_amp_cal_data cal_data; 1243 int ret; 1244 1245 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1246 return -ENXIO; 1247 1248 /* Only allow a full blob to be written */ 1249 if (*ppos || (count != sizeof(cal_data))) 1250 return -EMSGSIZE; 1251 1252 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1253 if (ret < 0) 1254 return ret; 1255 1256 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1257 if (ret) 1258 return ret; 1259 1260 return count; 1261 } 1262 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1263 1264 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1265 const struct cs35l56_cal_debugfs_fops *fops) 1266 { 1267 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1268 return; 1269 1270 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1271 1272 debugfs_create_file("calibrate", 1273 0200, cs35l56_base->debugfs, cs35l56_base, 1274 &fops->calibrate); 1275 debugfs_create_file("cal_temperature", 1276 0200, cs35l56_base->debugfs, cs35l56_base, 1277 &fops->cal_temperature); 1278 debugfs_create_file("cal_data", 1279 0644, cs35l56_base->debugfs, cs35l56_base, 1280 &fops->cal_data); 1281 } 1282 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1283 1284 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1285 { 1286 debugfs_remove_recursive(cs35l56_base->debugfs); 1287 cs35l56_base->debugfs = ERR_PTR(-ENOENT); 1288 } 1289 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1290 1291 const char * const cs35l56_cal_set_status_text[] = { 1292 "Unknown", "Default", "Set", 1293 }; 1294 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1295 1296 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1297 struct snd_ctl_elem_value *uvalue) 1298 { 1299 struct cs_dsp *dsp = cs35l56_base->dsp; 1300 __be32 cal_set_status_be; 1301 int alg_id; 1302 int ret; 1303 1304 switch (cs35l56_base->type) { 1305 case 0x54: 1306 case 0x56: 1307 case 0x57: 1308 alg_id = 0x9f210; 1309 break; 1310 default: 1311 alg_id = 0xbf210; 1312 break; 1313 } 1314 1315 scoped_guard(mutex, &dsp->pwr_lock) { 1316 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1317 "CAL_SET_STATUS", 1318 WMFW_ADSP2_YM, alg_id), 1319 0, &cal_set_status_be, 1320 sizeof(cal_set_status_be)); 1321 } 1322 if (ret) { 1323 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1324 return 0; 1325 } 1326 1327 switch (be32_to_cpu(cal_set_status_be)) { 1328 case CS35L56_CAL_SET_STATUS_DEFAULT: 1329 case CS35L56_CAL_SET_STATUS_SET: 1330 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1331 return 0; 1332 default: 1333 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1334 return 0; 1335 } 1336 } 1337 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1338 1339 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1340 bool *fw_missing, unsigned int *fw_version) 1341 { 1342 unsigned int prot_status; 1343 int ret; 1344 1345 ret = regmap_read(cs35l56_base->regmap, 1346 cs35l56_base->fw_reg->prot_sts, &prot_status); 1347 if (ret) { 1348 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1349 return ret; 1350 } 1351 1352 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1353 1354 ret = regmap_read(cs35l56_base->regmap, 1355 cs35l56_base->fw_reg->fw_ver, fw_version); 1356 if (ret) { 1357 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1358 return ret; 1359 } 1360 1361 return 0; 1362 } 1363 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1364 1365 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1366 { 1367 unsigned int firmware_version; 1368 bool firmware_missing; 1369 int ret; 1370 1371 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1372 if (ret) 1373 return; 1374 1375 if (!firmware_missing) 1376 return; 1377 1378 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1379 } 1380 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1381 1382 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1383 { 1384 __be32 pid, sid, tid; 1385 unsigned int alg_id; 1386 int ret; 1387 1388 switch (cs35l56_base->type) { 1389 case 0x54: 1390 case 0x56: 1391 case 0x57: 1392 alg_id = 0x9f212; 1393 break; 1394 default: 1395 alg_id = 0xbf212; 1396 break; 1397 } 1398 1399 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1400 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1401 WMFW_ADSP2_XM, alg_id), 1402 0, &pid, sizeof(pid)); 1403 if (!ret) 1404 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1405 WMFW_ADSP2_XM, alg_id), 1406 0, &sid, sizeof(sid)); 1407 if (!ret) 1408 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1409 WMFW_ADSP2_XM, alg_id), 1410 0, &tid, sizeof(tid)); 1411 } 1412 1413 if (ret) 1414 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1415 else 1416 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1417 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1418 } 1419 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1420 1421 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1422 { 1423 int ret; 1424 unsigned int devid, revid, otpid, secured, fw_ver; 1425 bool fw_missing; 1426 1427 /* 1428 * When the system is not using a reset_gpio ensure the device is 1429 * awake, otherwise the device has just been released from reset and 1430 * the driver must wait for the control port to become usable. 1431 */ 1432 if (!cs35l56_base->reset_gpio) 1433 cs35l56_issue_wake_event(cs35l56_base); 1434 else 1435 cs35l56_wait_control_port_ready(); 1436 1437 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1438 if (ret < 0) { 1439 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1440 return ret; 1441 } 1442 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1443 cs35l56_set_fw_reg_table(cs35l56_base); 1444 1445 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1446 if (ret) 1447 return ret; 1448 1449 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1450 if (ret < 0) { 1451 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1452 return ret; 1453 } 1454 devid &= CS35L56_DEVID_MASK; 1455 1456 switch (devid) { 1457 case 0x35A54: 1458 case 0x35A56: 1459 case 0x35A57: 1460 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1461 break; 1462 case 0x35A630: 1463 case 0x35A620: 1464 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1465 devid = devid >> 4; 1466 break; 1467 default: 1468 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1469 return -ENODEV; 1470 } 1471 1472 cs35l56_base->type = devid & 0xFF; 1473 1474 /* Silicon is now identified and booted so exit cache-only */ 1475 regcache_cache_only(cs35l56_base->regmap, false); 1476 1477 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1478 if (ret) { 1479 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1480 return ret; 1481 } 1482 1483 /* When any bus is restricted treat the device as secured */ 1484 if (secured & CS35L56_RESTRICTED_MASK) 1485 cs35l56_base->secured = true; 1486 1487 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1488 if (ret < 0) { 1489 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1490 return ret; 1491 } 1492 1493 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1494 if (ret) 1495 return ret; 1496 1497 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1498 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1499 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1500 1501 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1502 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1503 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1504 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1505 0); 1506 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1507 CS35L56_TEMP_ERR_EINT1_MASK, 1508 0); 1509 1510 switch (cs35l56_base->type) { 1511 case 0x54: 1512 case 0x56: 1513 case 0x57: 1514 ret = cs35l56_read_silicon_uid(cs35l56_base); 1515 break; 1516 default: 1517 ret = cs35l63_read_silicon_uid(cs35l56_base); 1518 break; 1519 } 1520 if (ret) 1521 return ret; 1522 1523 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1524 1525 return 0; 1526 } 1527 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1528 1529 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1530 { 1531 struct gpio_descs *descs; 1532 u32 speaker_id; 1533 int i, ret; 1534 1535 /* Check for vendor-specific speaker ID method */ 1536 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1537 if (ret >= 0) { 1538 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1539 return ret; 1540 } else if (ret != -ENOENT) { 1541 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1542 return ret; 1543 } 1544 1545 /* Attempt to read the speaker type from a device property */ 1546 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1547 if (!ret) { 1548 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1549 return speaker_id; 1550 } 1551 1552 /* Read the speaker type qualifier from the motherboard GPIOs */ 1553 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1554 if (!descs) { 1555 return -ENOENT; 1556 } else if (IS_ERR(descs)) { 1557 ret = PTR_ERR(descs); 1558 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1559 } 1560 1561 speaker_id = 0; 1562 for (i = 0; i < descs->ndescs; i++) { 1563 ret = gpiod_get_value_cansleep(descs->desc[i]); 1564 if (ret < 0) { 1565 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1566 goto err; 1567 } 1568 1569 speaker_id |= (ret << i); 1570 } 1571 1572 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1573 ret = speaker_id; 1574 err: 1575 gpiod_put_array(descs); 1576 1577 return ret; 1578 } 1579 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1580 1581 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1582 const u32 *gpios, int num_gpios, 1583 const u32 *pulls, int num_pulls) 1584 { 1585 int max_gpio; 1586 int ret = 0; 1587 int i; 1588 1589 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1590 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1591 return -EOVERFLOW; 1592 1593 switch (cs35l56_base->type) { 1594 case 0x54: 1595 case 0x56: 1596 case 0x57: 1597 max_gpio = CS35L56_MAX_GPIO; 1598 break; 1599 default: 1600 max_gpio = CS35L63_MAX_GPIO; 1601 break; 1602 } 1603 1604 for (i = 0; i < num_gpios; i++) { 1605 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1606 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1607 /* Keep going so we log all bad values */ 1608 ret = -EINVAL; 1609 } 1610 1611 /* Change to zero-based */ 1612 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1613 } 1614 1615 for (i = 0; i < num_pulls; i++) { 1616 switch (pulls[i]) { 1617 case 0: 1618 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1619 break; 1620 case 1: 1621 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1622 break; 1623 case 2: 1624 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1625 break; 1626 default: 1627 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1628 /* Keep going so we log all bad values */ 1629 ret = -EINVAL; 1630 break; 1631 } 1632 } 1633 if (ret) 1634 return ret; 1635 1636 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1637 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1638 1639 return 0; 1640 } 1641 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1642 1643 /* Caller must pm_runtime resume before calling this function */ 1644 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1645 { 1646 struct regmap *regmap = cs35l56_base->regmap; 1647 unsigned int addr_offset, val; 1648 int num_gpios, num_pulls; 1649 int i, ret; 1650 1651 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1652 1653 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1654 return 0; 1655 1656 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1657 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1658 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1659 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1660 1661 for (i = 0; i < num_gpios; i++) { 1662 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1663 1664 /* Set unspecified pulls to NONE */ 1665 if (i < num_pulls) { 1666 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1667 cs35l56_base->onchip_spkid_pulls[i]); 1668 } else { 1669 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1670 } 1671 1672 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1673 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1674 val | CS35L56_PAD_GPIO_IE); 1675 if (ret) { 1676 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1677 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1678 return ret; 1679 } 1680 } 1681 1682 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1683 if (ret) { 1684 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1685 return ret; 1686 } 1687 1688 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1689 1690 return 0; 1691 } 1692 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1693 1694 /* Caller must pm_runtime resume before calling this function */ 1695 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1696 { 1697 struct regmap *regmap = cs35l56_base->regmap; 1698 unsigned int addr_offset, val; 1699 int num_gpios; 1700 int speaker_id = 0; 1701 int i, ret; 1702 1703 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1704 1705 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1706 return -ENOENT; 1707 1708 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1709 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1710 1711 for (i = 0; i < num_gpios; i++) { 1712 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1713 1714 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1715 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1716 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1717 if (ret) { 1718 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1719 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1720 return ret; 1721 } 1722 } 1723 1724 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1725 if (ret) { 1726 dev_err(cs35l56_base->dev, "GPIO status read failed: %d\n", ret); 1727 return ret; 1728 } 1729 1730 for (i = 0; i < num_gpios; i++) { 1731 speaker_id <<= 1; 1732 1733 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1734 speaker_id |= 1; 1735 } 1736 1737 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1738 1739 return speaker_id; 1740 } 1741 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1742 1743 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1744 [0x0C] = 128000, 1745 [0x0F] = 256000, 1746 [0x11] = 384000, 1747 [0x12] = 512000, 1748 [0x15] = 768000, 1749 [0x17] = 1024000, 1750 [0x1A] = 1500000, 1751 [0x1B] = 1536000, 1752 [0x1C] = 2000000, 1753 [0x1D] = 2048000, 1754 [0x1E] = 2400000, 1755 [0x20] = 3000000, 1756 [0x21] = 3072000, 1757 [0x23] = 4000000, 1758 [0x24] = 4096000, 1759 [0x25] = 4800000, 1760 [0x27] = 6000000, 1761 [0x28] = 6144000, 1762 [0x29] = 6250000, 1763 [0x2A] = 6400000, 1764 [0x2E] = 8000000, 1765 [0x2F] = 8192000, 1766 [0x30] = 9600000, 1767 [0x32] = 12000000, 1768 [0x33] = 12288000, 1769 [0x37] = 13500000, 1770 [0x38] = 19200000, 1771 [0x39] = 22579200, 1772 [0x3B] = 24576000, 1773 }; 1774 1775 int cs35l56_get_bclk_freq_id(unsigned int freq) 1776 { 1777 int i; 1778 1779 if (freq == 0) 1780 return -EINVAL; 1781 1782 /* The BCLK frequency must be a valid PLL REFCLK */ 1783 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1784 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1785 return i; 1786 } 1787 1788 return -EINVAL; 1789 } 1790 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1791 1792 static const char * const cs35l56_supplies[/* auto-sized */] = { 1793 "VDD_P", 1794 "VDD_IO", 1795 "VDD_A", 1796 }; 1797 1798 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1799 { 1800 int i; 1801 1802 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1803 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1804 data[i].supply = cs35l56_supplies[i]; 1805 } 1806 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1807 1808 const char * const cs35l56_tx_input_texts[] = { 1809 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1810 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1811 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1812 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1813 }; 1814 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1815 1816 const unsigned int cs35l56_tx_input_values[] = { 1817 CS35L56_INPUT_SRC_NONE, 1818 CS35L56_INPUT_SRC_ASP1RX1, 1819 CS35L56_INPUT_SRC_ASP1RX2, 1820 CS35L56_INPUT_SRC_VMON, 1821 CS35L56_INPUT_SRC_IMON, 1822 CS35L56_INPUT_SRC_ERR_VOL, 1823 CS35L56_INPUT_SRC_CLASSH, 1824 CS35L56_INPUT_SRC_VDDBMON, 1825 CS35L56_INPUT_SRC_VBSTMON, 1826 CS35L56_INPUT_SRC_DSP1TX1, 1827 CS35L56_INPUT_SRC_DSP1TX2, 1828 CS35L56_INPUT_SRC_DSP1TX3, 1829 CS35L56_INPUT_SRC_DSP1TX4, 1830 CS35L56_INPUT_SRC_DSP1TX5, 1831 CS35L56_INPUT_SRC_DSP1TX6, 1832 CS35L56_INPUT_SRC_DSP1TX7, 1833 CS35L56_INPUT_SRC_DSP1TX8, 1834 CS35L56_INPUT_SRC_TEMPMON, 1835 CS35L56_INPUT_SRC_INTERPOLATOR, 1836 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1837 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1838 }; 1839 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1840 1841 const struct regmap_config cs35l56_regmap_i2c = { 1842 .reg_bits = 32, 1843 .val_bits = 32, 1844 .reg_stride = 4, 1845 .reg_format_endian = REGMAP_ENDIAN_BIG, 1846 .val_format_endian = REGMAP_ENDIAN_BIG, 1847 .max_register = CS35L56_DSP1_PMEM_5114, 1848 .reg_defaults = cs35l56_reg_defaults, 1849 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1850 .volatile_reg = cs35l56_volatile_reg, 1851 .readable_reg = cs35l56_readable_reg, 1852 .precious_reg = cs35l56_precious_reg, 1853 .cache_type = REGCACHE_MAPLE, 1854 }; 1855 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1856 1857 const struct regmap_config cs35l56_regmap_spi = { 1858 .reg_bits = 32, 1859 .val_bits = 32, 1860 .pad_bits = 16, 1861 .reg_stride = 4, 1862 .reg_format_endian = REGMAP_ENDIAN_BIG, 1863 .val_format_endian = REGMAP_ENDIAN_BIG, 1864 .max_register = CS35L56_DSP1_PMEM_5114, 1865 .reg_defaults = cs35l56_reg_defaults, 1866 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1867 .volatile_reg = cs35l56_volatile_reg, 1868 .readable_reg = cs35l56_readable_reg, 1869 .precious_reg = cs35l56_precious_reg, 1870 .cache_type = REGCACHE_MAPLE, 1871 }; 1872 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1873 1874 const struct regmap_config cs35l56_regmap_sdw = { 1875 .reg_bits = 32, 1876 .reg_base = 0x8000, 1877 .val_bits = 32, 1878 .reg_stride = 4, 1879 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1880 .val_format_endian = REGMAP_ENDIAN_BIG, 1881 .max_register = CS35L56_DSP1_PMEM_5114, 1882 .reg_defaults = cs35l56_reg_defaults, 1883 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1884 .volatile_reg = cs35l56_volatile_reg, 1885 .readable_reg = cs35l56_readable_reg, 1886 .precious_reg = cs35l56_precious_reg, 1887 .cache_type = REGCACHE_MAPLE, 1888 }; 1889 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1890 1891 const struct regmap_config cs35l63_regmap_i2c = { 1892 .reg_bits = 32, 1893 .val_bits = 32, 1894 .reg_stride = 4, 1895 .reg_base = 0x8000, 1896 .reg_format_endian = REGMAP_ENDIAN_BIG, 1897 .val_format_endian = REGMAP_ENDIAN_BIG, 1898 .max_register = CS35L56_DSP1_PMEM_5114, 1899 .reg_defaults = cs35l63_reg_defaults, 1900 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1901 .volatile_reg = cs35l63_volatile_reg, 1902 .readable_reg = cs35l56_readable_reg, 1903 .precious_reg = cs35l56_precious_reg, 1904 .cache_type = REGCACHE_MAPLE, 1905 }; 1906 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1907 1908 const struct regmap_config cs35l63_regmap_sdw = { 1909 .reg_bits = 32, 1910 .val_bits = 32, 1911 .reg_stride = 4, 1912 .reg_base = 0x8000, 1913 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1914 .val_format_endian = REGMAP_ENDIAN_BIG, 1915 .max_register = CS35L56_DSP1_PMEM_5114, 1916 .reg_defaults = cs35l63_reg_defaults, 1917 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1918 .volatile_reg = cs35l63_volatile_reg, 1919 .readable_reg = cs35l56_readable_reg, 1920 .precious_reg = cs35l56_precious_reg, 1921 .cache_type = REGCACHE_MAPLE, 1922 }; 1923 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1924 1925 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1926 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1927 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1928 MODULE_LICENSE("GPL"); 1929 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1930 MODULE_IMPORT_NS("FW_CS_DSP"); 1931