1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/firmware/cirrus/wmfw.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/spi/spi.h> 14 #include <linux/types.h> 15 #include <sound/cs-amp-lib.h> 16 17 #include "cs35l56.h" 18 19 static const struct reg_sequence cs35l56_patch[] = { 20 /* 21 * Firmware can change these to non-defaults to satisfy SDCA. 22 * Ensure that they are at known defaults. 23 */ 24 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 25 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 26 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 27 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 28 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 29 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 30 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 31 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 32 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 33 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 34 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 35 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 36 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 37 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 38 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 39 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 40 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 41 }; 42 43 static const struct reg_sequence cs35l56_patch_fw[] = { 44 /* These are not reset by a soft-reset, so patch to defaults. */ 45 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 46 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 47 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 48 }; 49 50 static const struct reg_sequence cs35l63_patch_fw[] = { 51 /* These are not reset by a soft-reset, so patch to defaults. */ 52 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 53 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 54 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 55 }; 56 57 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 58 { 59 int ret; 60 61 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 62 ARRAY_SIZE(cs35l56_patch)); 63 if (ret) 64 return ret; 65 66 67 switch (cs35l56_base->type) { 68 case 0x54: 69 case 0x56: 70 case 0x57: 71 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 72 ARRAY_SIZE(cs35l56_patch_fw)); 73 break; 74 case 0x63: 75 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 76 ARRAY_SIZE(cs35l63_patch_fw)); 77 break; 78 default: 79 break; 80 } 81 82 return ret; 83 } 84 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 85 86 static const struct reg_default cs35l56_reg_defaults[] = { 87 /* no defaults for OTP_MEM - first read populates cache */ 88 89 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 90 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 91 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 92 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 93 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 94 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 95 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 96 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 97 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 98 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 99 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 100 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 101 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 102 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 103 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 104 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 105 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 106 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 107 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 108 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 109 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 110 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 111 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 112 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 113 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 114 }; 115 116 static const struct reg_default cs35l63_reg_defaults[] = { 117 /* no defaults for OTP_MEM - first read populates cache */ 118 119 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 120 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 121 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 122 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 123 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 124 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 125 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 126 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 127 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 128 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 129 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 130 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 131 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 132 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 133 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 134 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 135 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 136 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 137 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 138 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 139 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 140 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 141 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 142 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 143 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 144 }; 145 146 static bool cs35l56_is_dsp_memory(unsigned int reg) 147 { 148 switch (reg) { 149 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 150 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 151 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 152 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 153 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 154 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 155 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case CS35L56_DEVID: 166 case CS35L56_REVID: 167 case CS35L56_RELID: 168 case CS35L56_OTPID: 169 case CS35L56_SFT_RESET: 170 case CS35L56_GLOBAL_ENABLES: 171 case CS35L56_BLOCK_ENABLES: 172 case CS35L56_BLOCK_ENABLES2: 173 case CS35L56_REFCLK_INPUT: 174 case CS35L56_GLOBAL_SAMPLE_RATE: 175 case CS35L56_OTP_MEM_53: 176 case CS35L56_OTP_MEM_54: 177 case CS35L56_OTP_MEM_55: 178 case CS35L56_ASP1_ENABLES1: 179 case CS35L56_ASP1_CONTROL1: 180 case CS35L56_ASP1_CONTROL2: 181 case CS35L56_ASP1_CONTROL3: 182 case CS35L56_ASP1_FRAME_CONTROL1: 183 case CS35L56_ASP1_FRAME_CONTROL5: 184 case CS35L56_ASP1_DATA_CONTROL1: 185 case CS35L56_ASP1_DATA_CONTROL5: 186 case CS35L56_DACPCM1_INPUT: 187 case CS35L56_DACPCM2_INPUT: 188 case CS35L56_ASP1TX1_INPUT: 189 case CS35L56_ASP1TX2_INPUT: 190 case CS35L56_ASP1TX3_INPUT: 191 case CS35L56_ASP1TX4_INPUT: 192 case CS35L56_DSP1RX1_INPUT: 193 case CS35L56_DSP1RX2_INPUT: 194 case CS35L56_SWIRE_DP3_CH1_INPUT: 195 case CS35L56_SWIRE_DP3_CH2_INPUT: 196 case CS35L56_SWIRE_DP3_CH3_INPUT: 197 case CS35L56_SWIRE_DP3_CH4_INPUT: 198 case CS35L56_IRQ1_CFG: 199 case CS35L56_IRQ1_STATUS: 200 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 201 case CS35L56_IRQ1_EINT_18: 202 case CS35L56_IRQ1_EINT_20: 203 case CS35L56_IRQ1_MASK_1: 204 case CS35L56_IRQ1_MASK_2: 205 case CS35L56_IRQ1_MASK_4: 206 case CS35L56_IRQ1_MASK_8: 207 case CS35L56_IRQ1_MASK_18: 208 case CS35L56_IRQ1_MASK_20: 209 case CS35L56_DSP_VIRTUAL1_MBOX_1: 210 case CS35L56_DSP_VIRTUAL1_MBOX_2: 211 case CS35L56_DSP_VIRTUAL1_MBOX_3: 212 case CS35L56_DSP_VIRTUAL1_MBOX_4: 213 case CS35L56_DSP_VIRTUAL1_MBOX_5: 214 case CS35L56_DSP_VIRTUAL1_MBOX_6: 215 case CS35L56_DSP_VIRTUAL1_MBOX_7: 216 case CS35L56_DSP_VIRTUAL1_MBOX_8: 217 case CS35L56_DIE_STS1: 218 case CS35L56_DIE_STS2: 219 case CS35L56_DSP_RESTRICT_STS1: 220 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 221 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 222 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 223 case CS35L56_DSP1_SCRATCH1: 224 case CS35L56_DSP1_SCRATCH2: 225 case CS35L56_DSP1_SCRATCH3: 226 case CS35L56_DSP1_SCRATCH4: 227 return true; 228 default: 229 return cs35l56_is_dsp_memory(reg); 230 } 231 } 232 233 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 234 { 235 switch (reg) { 236 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 237 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 238 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 239 return true; 240 default: 241 return false; 242 } 243 } 244 245 static bool cs35l56_common_volatile_reg(unsigned int reg) 246 { 247 switch (reg) { 248 case CS35L56_DEVID: 249 case CS35L56_REVID: 250 case CS35L56_RELID: 251 case CS35L56_OTPID: 252 case CS35L56_SFT_RESET: 253 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 254 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 255 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 256 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 257 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 258 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 259 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 260 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 261 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 262 case CS35L56_IRQ1_STATUS: 263 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 264 case CS35L56_IRQ1_EINT_18: 265 case CS35L56_IRQ1_EINT_20: 266 case CS35L56_DSP_VIRTUAL1_MBOX_1: 267 case CS35L56_DSP_VIRTUAL1_MBOX_2: 268 case CS35L56_DSP_VIRTUAL1_MBOX_3: 269 case CS35L56_DSP_VIRTUAL1_MBOX_4: 270 case CS35L56_DSP_VIRTUAL1_MBOX_5: 271 case CS35L56_DSP_VIRTUAL1_MBOX_6: 272 case CS35L56_DSP_VIRTUAL1_MBOX_7: 273 case CS35L56_DSP_VIRTUAL1_MBOX_8: 274 case CS35L56_DSP_RESTRICT_STS1: 275 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 276 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 277 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 278 case CS35L56_DSP1_SCRATCH1: 279 case CS35L56_DSP1_SCRATCH2: 280 case CS35L56_DSP1_SCRATCH3: 281 case CS35L56_DSP1_SCRATCH4: 282 return true; 283 default: 284 return cs35l56_is_dsp_memory(reg); 285 } 286 } 287 288 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 289 { 290 switch (reg) { 291 case CS35L56_MAIN_RENDER_USER_MUTE: 292 case CS35L56_MAIN_RENDER_USER_VOLUME: 293 case CS35L56_MAIN_POSTURE_NUMBER: 294 return false; 295 default: 296 return cs35l56_common_volatile_reg(reg); 297 } 298 } 299 300 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 301 { 302 switch (reg) { 303 case CS35L63_MAIN_RENDER_USER_MUTE: 304 case CS35L63_MAIN_RENDER_USER_VOLUME: 305 case CS35L63_MAIN_POSTURE_NUMBER: 306 return false; 307 default: 308 return cs35l56_common_volatile_reg(reg); 309 } 310 } 311 312 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 313 .fw_ver = CS35L56_DSP1_FW_VER, 314 .halo_state = CS35L56_DSP1_HALO_STATE, 315 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 316 .prot_sts = CS35L56_PROTECTION_STATUS, 317 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 318 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 319 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 320 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 321 }; 322 323 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 324 .fw_ver = CS35L56_DSP1_FW_VER, 325 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 326 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 327 .prot_sts = CS35L56_PROTECTION_STATUS, 328 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 329 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 330 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 331 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 332 }; 333 334 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 335 .fw_ver = CS35L63_DSP1_FW_VER, 336 .halo_state = CS35L63_DSP1_HALO_STATE, 337 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 338 .prot_sts = CS35L63_PROTECTION_STATUS, 339 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 340 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 341 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 342 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 343 }; 344 345 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 346 { 347 switch (cs35l56_base->type) { 348 default: 349 switch (cs35l56_base->rev) { 350 case 0xb0: 351 cs35l56_base->fw_reg = &cs35l56_fw_reg; 352 break; 353 default: 354 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 355 break; 356 } 357 break; 358 case 0x63: 359 cs35l56_base->fw_reg = &cs35l63_fw_reg; 360 break; 361 } 362 } 363 364 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 365 { 366 unsigned int val; 367 int ret; 368 369 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 370 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 371 val, (val == 0), 372 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 373 if (ret) { 374 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 375 return ret; 376 } 377 378 return 0; 379 } 380 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 381 382 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 383 { 384 int ret; 385 unsigned int val; 386 387 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 388 if (ret) 389 return ret; 390 391 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 392 cs35l56_base->fw_reg->pm_cur_stat, 393 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 394 CS35L56_HALO_STATE_POLL_US, 395 CS35L56_HALO_STATE_TIMEOUT_US); 396 if (ret < 0) 397 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 398 val, ret); 399 return ret; 400 } 401 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 402 403 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 404 { 405 unsigned int val = 0; 406 int read_ret, poll_ret; 407 408 /* 409 * The regmap must remain in cache-only until the chip has 410 * booted, so use a bypassed read of the status register. 411 */ 412 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 413 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 414 CS35L56_HALO_STATE_POLL_US, 415 CS35L56_HALO_STATE_TIMEOUT_US, 416 false, 417 cs35l56_base->regmap, 418 cs35l56_base->fw_reg->halo_state, 419 &val); 420 421 if (poll_ret) { 422 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 423 read_ret, val); 424 return -EIO; 425 } 426 427 return 0; 428 } 429 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 430 431 void cs35l56_wait_control_port_ready(void) 432 { 433 /* Wait for control port to be ready (datasheet tIRS). */ 434 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 435 } 436 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 437 438 void cs35l56_wait_min_reset_pulse(void) 439 { 440 /* Satisfy minimum reset pulse width spec */ 441 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 442 } 443 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 444 445 static const struct { 446 u32 addr; 447 u32 value; 448 } cs35l56_spi_system_reset_stages[] = { 449 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 450 /* The next write is necessary to delimit the soft reset */ 451 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 452 }; 453 454 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 455 struct spi_device *spi) 456 { 457 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 458 struct spi_transfer t = { 459 .tx_buf = buf, 460 .len = sizeof(*buf), 461 }; 462 struct spi_message m; 463 int i, ret; 464 465 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 466 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 467 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 468 spi_message_init_with_transfers(&m, &t, 1); 469 ret = spi_sync_locked(spi, &m); 470 if (ret) 471 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 472 473 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 474 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 475 } 476 } 477 478 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 479 { 480 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 481 unsigned int val; 482 int read_ret, ret; 483 484 /* 485 * There must not be any other SPI bus activity while the amp is 486 * soft-resetting. 487 */ 488 ret = spi_bus_lock(spi->controller); 489 if (ret) { 490 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 491 return; 492 } 493 494 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 495 spi_bus_unlock(spi->controller); 496 497 /* 498 * Check firmware boot by testing for a response in MBOX_2. 499 * HALO_STATE cannot be trusted yet because the reset sequence 500 * can leave it with stale state. But MBOX is reset. 501 * The regmap must remain in cache-only until the chip has 502 * booted, so use a bypassed read. 503 */ 504 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 505 (val > 0) && (val < 0xffffffff), 506 CS35L56_HALO_STATE_POLL_US, 507 CS35L56_HALO_STATE_TIMEOUT_US, 508 false, 509 cs35l56_base->regmap, 510 CS35L56_DSP_VIRTUAL1_MBOX_2, 511 &val); 512 if (ret) { 513 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 514 read_ret, val); 515 } 516 } 517 518 static const struct reg_sequence cs35l56_system_reset_seq[] = { 519 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 520 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 521 }; 522 523 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 524 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 525 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 526 }; 527 528 static const struct reg_sequence cs35l63_system_reset_seq[] = { 529 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 530 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 531 }; 532 533 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 534 { 535 /* 536 * Must enter cache-only first so there can't be any more register 537 * accesses other than the controlled system reset sequence below. 538 */ 539 regcache_cache_only(cs35l56_base->regmap, true); 540 541 if (cs35l56_is_spi(cs35l56_base)) { 542 cs35l56_spi_system_reset(cs35l56_base); 543 return; 544 } 545 546 switch (cs35l56_base->type) { 547 case 0x54: 548 case 0x56: 549 case 0x57: 550 switch (cs35l56_base->rev) { 551 case 0xb0: 552 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 553 cs35l56_system_reset_seq, 554 ARRAY_SIZE(cs35l56_system_reset_seq)); 555 break; 556 default: 557 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 558 cs35l56_b2_system_reset_seq, 559 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 560 break; 561 } 562 break; 563 case 0x63: 564 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 565 cs35l63_system_reset_seq, 566 ARRAY_SIZE(cs35l63_system_reset_seq)); 567 break; 568 default: 569 break; 570 } 571 572 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 573 if (is_soundwire) 574 return; 575 576 cs35l56_wait_control_port_ready(); 577 578 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 579 } 580 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 581 582 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 583 { 584 int ret; 585 586 if (irq < 1) 587 return 0; 588 589 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 590 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 591 "cs35l56", cs35l56_base); 592 if (!ret) 593 cs35l56_base->irq = irq; 594 else 595 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 596 597 return ret; 598 } 599 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 600 601 irqreturn_t cs35l56_irq(int irq, void *data) 602 { 603 struct cs35l56_base *cs35l56_base = data; 604 unsigned int status1 = 0, status8 = 0, status20 = 0; 605 unsigned int mask1, mask8, mask20; 606 unsigned int val; 607 int rv; 608 609 irqreturn_t ret = IRQ_NONE; 610 611 if (!cs35l56_base->init_done) 612 return IRQ_NONE; 613 614 mutex_lock(&cs35l56_base->irq_lock); 615 616 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 617 if (rv < 0) { 618 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 619 goto err_unlock; 620 } 621 622 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 623 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 624 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 625 goto err; 626 } 627 628 /* Ack interrupts */ 629 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 630 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 631 status1 &= ~mask1; 632 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 633 634 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 635 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 636 status8 &= ~mask8; 637 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 638 639 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 640 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 641 status20 &= ~mask20; 642 /* We don't want EINT20 but they default to unmasked: force mask */ 643 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 644 645 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 646 647 /* Check to see if unmasked bits are active */ 648 if (!status1 && !status8 && !status20) 649 goto err; 650 651 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 652 dev_crit(cs35l56_base->dev, "Amp short error\n"); 653 654 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 655 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 656 657 ret = IRQ_HANDLED; 658 659 err: 660 pm_runtime_put(cs35l56_base->dev); 661 err_unlock: 662 mutex_unlock(&cs35l56_base->irq_lock); 663 664 return ret; 665 } 666 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 667 668 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 669 { 670 unsigned int val; 671 int ret; 672 673 /* 674 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 675 * can't be used here to test for memory retention. 676 * Assume that tuning must be re-loaded. 677 */ 678 if (cs35l56_base->secured) 679 return true; 680 681 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 682 if (ret) { 683 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 684 return ret; 685 } 686 687 ret = regmap_read(cs35l56_base->regmap, 688 cs35l56_base->fw_reg->prot_sts, 689 &val); 690 if (ret) 691 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 692 else 693 ret = !!(val & CS35L56_FIRMWARE_MISSING); 694 695 pm_runtime_put_autosuspend(cs35l56_base->dev); 696 697 return ret; 698 } 699 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 700 701 static const struct reg_sequence cs35l56_hibernate_seq[] = { 702 /* This must be the last register access */ 703 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 704 }; 705 706 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 707 { 708 unsigned int val; 709 710 /* 711 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 712 * transactions to meet the minimum required time from the rising edge 713 * to the last falling edge of wake. 714 * 715 * It uses bypassed read because we must wake the chip before 716 * disabling regmap cache-only. 717 */ 718 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 719 720 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 721 722 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 723 724 cs35l56_wait_control_port_ready(); 725 } 726 727 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 728 { 729 unsigned int val; 730 int ret; 731 732 if (!cs35l56_base->init_done) 733 return 0; 734 735 /* Firmware must have entered a power-save state */ 736 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 737 cs35l56_base->fw_reg->transducer_actual_ps, 738 val, (val >= CS35L56_PS3), 739 CS35L56_PS3_POLL_US, 740 CS35L56_PS3_TIMEOUT_US); 741 if (ret) 742 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 743 744 /* Clear BOOT_DONE so it can be used to detect a reboot */ 745 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 746 747 if (!cs35l56_base->can_hibernate) { 748 regcache_cache_only(cs35l56_base->regmap, true); 749 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 750 751 return 0; 752 } 753 754 /* 755 * Must enter cache-only first so there can't be any more register 756 * accesses other than the controlled hibernate sequence below. 757 */ 758 regcache_cache_only(cs35l56_base->regmap, true); 759 760 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 761 cs35l56_hibernate_seq, 762 ARRAY_SIZE(cs35l56_hibernate_seq)); 763 764 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 765 766 return 0; 767 } 768 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 769 770 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 771 { 772 unsigned int val; 773 int ret; 774 775 if (!cs35l56_base->init_done) 776 return 0; 777 778 if (!cs35l56_base->can_hibernate) 779 goto out_sync; 780 781 /* Must be done before releasing cache-only */ 782 if (!is_soundwire) 783 cs35l56_issue_wake_event(cs35l56_base); 784 785 out_sync: 786 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 787 if (ret) { 788 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 789 goto err; 790 } 791 792 regcache_cache_only(cs35l56_base->regmap, false); 793 794 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 795 if (ret) 796 goto err; 797 798 /* BOOT_DONE will be 1 if the amp reset */ 799 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 800 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 801 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 802 regcache_mark_dirty(cs35l56_base->regmap); 803 } 804 805 regcache_sync(cs35l56_base->regmap); 806 807 dev_dbg(cs35l56_base->dev, "Resumed"); 808 809 return 0; 810 811 err: 812 regcache_cache_only(cs35l56_base->regmap, true); 813 814 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 815 cs35l56_hibernate_seq, 816 ARRAY_SIZE(cs35l56_hibernate_seq)); 817 818 return ret; 819 } 820 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 821 822 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 823 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 824 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 825 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 826 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 827 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 828 }; 829 830 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 831 { 832 cs_dsp->num = 1; 833 cs_dsp->type = WMFW_HALO; 834 cs_dsp->rev = 0; 835 cs_dsp->dev = cs35l56_base->dev; 836 cs_dsp->regmap = cs35l56_base->regmap; 837 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 838 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 839 cs_dsp->mem = cs35l56_dsp1_regions; 840 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 841 cs_dsp->no_core_startstop = true; 842 } 843 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 844 845 struct cs35l56_pte { 846 u8 x; 847 u8 wafer_id; 848 u8 pte[2]; 849 u8 lot[3]; 850 u8 y; 851 u8 unused[3]; 852 u8 dvs; 853 } __packed; 854 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 855 856 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 857 { 858 struct cs35l56_pte pte; 859 u64 unique_id; 860 int ret; 861 862 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 863 if (ret) { 864 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 865 return ret; 866 } 867 868 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 869 unique_id <<= 32; 870 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 871 ((u32)pte.dvs << 24); 872 873 *uid = unique_id; 874 875 return 0; 876 } 877 878 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 879 { 880 u32 tmp[2]; 881 int ret; 882 883 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 884 if (ret) { 885 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 886 return ret; 887 } 888 889 *uid = tmp[1]; 890 *uid <<= 32; 891 *uid |= tmp[0]; 892 893 return 0; 894 } 895 896 /* Firmware calibration controls */ 897 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 898 .alg_id = 0x9f210, 899 .mem_region = WMFW_ADSP2_YM, 900 .ambient = "CAL_AMBIENT", 901 .calr = "CAL_R", 902 .status = "CAL_STATUS", 903 .checksum = "CAL_CHECKSUM", 904 }; 905 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 906 907 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 908 .alg_id = 0xbf210, 909 .mem_region = WMFW_ADSP2_YM, 910 .ambient = "CAL_AMBIENT", 911 .calr = "CAL_R", 912 .status = "CAL_STATUS", 913 .checksum = "CAL_CHECKSUM", 914 }; 915 916 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 917 { 918 u64 silicon_uid = 0; 919 int ret; 920 921 /* Driver can't apply calibration to a secured part, so skip */ 922 if (cs35l56_base->secured) 923 return 0; 924 925 switch (cs35l56_base->type) { 926 case 0x54: 927 case 0x56: 928 case 0x57: 929 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 930 break; 931 case 0x63: 932 ret = cs35l63_read_silicon_uid(cs35l56_base, &silicon_uid); 933 break; 934 default: 935 ret = -ENODEV; 936 break; 937 } 938 939 if (ret < 0) 940 return ret; 941 942 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", silicon_uid); 943 944 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 945 cs35l56_base->cal_index, 946 &cs35l56_base->cal_data); 947 948 /* Only return an error status if probe should be aborted */ 949 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 950 return 0; 951 952 if (ret < 0) 953 return ret; 954 955 cs35l56_base->cal_data_valid = true; 956 957 return 0; 958 } 959 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 960 961 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 962 bool *fw_missing, unsigned int *fw_version) 963 { 964 unsigned int prot_status; 965 int ret; 966 967 ret = regmap_read(cs35l56_base->regmap, 968 cs35l56_base->fw_reg->prot_sts, &prot_status); 969 if (ret) { 970 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 971 return ret; 972 } 973 974 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 975 976 ret = regmap_read(cs35l56_base->regmap, 977 cs35l56_base->fw_reg->fw_ver, fw_version); 978 if (ret) { 979 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 980 return ret; 981 } 982 983 return 0; 984 } 985 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 986 987 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 988 { 989 __be32 pid, sid, tid; 990 unsigned int alg_id; 991 int ret; 992 993 switch (cs35l56_base->type) { 994 case 0x54: 995 case 0x56: 996 case 0x57: 997 alg_id = 0x9f212; 998 break; 999 default: 1000 alg_id = 0xbf212; 1001 break; 1002 } 1003 1004 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1005 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1006 WMFW_ADSP2_XM, alg_id), 1007 0, &pid, sizeof(pid)); 1008 if (!ret) 1009 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1010 WMFW_ADSP2_XM, alg_id), 1011 0, &sid, sizeof(sid)); 1012 if (!ret) 1013 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1014 WMFW_ADSP2_XM, alg_id), 1015 0, &tid, sizeof(tid)); 1016 } 1017 1018 if (ret) 1019 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1020 else 1021 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1022 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1023 } 1024 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1025 1026 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1027 { 1028 int ret; 1029 unsigned int devid, revid, otpid, secured, fw_ver; 1030 bool fw_missing; 1031 1032 /* 1033 * When the system is not using a reset_gpio ensure the device is 1034 * awake, otherwise the device has just been released from reset and 1035 * the driver must wait for the control port to become usable. 1036 */ 1037 if (!cs35l56_base->reset_gpio) 1038 cs35l56_issue_wake_event(cs35l56_base); 1039 else 1040 cs35l56_wait_control_port_ready(); 1041 1042 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1043 if (ret < 0) { 1044 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1045 return ret; 1046 } 1047 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1048 cs35l56_set_fw_reg_table(cs35l56_base); 1049 1050 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1051 if (ret) 1052 return ret; 1053 1054 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1055 if (ret < 0) { 1056 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1057 return ret; 1058 } 1059 devid &= CS35L56_DEVID_MASK; 1060 1061 switch (devid) { 1062 case 0x35A54: 1063 case 0x35A56: 1064 case 0x35A57: 1065 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1066 break; 1067 case 0x35A630: 1068 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1069 devid = devid >> 4; 1070 break; 1071 default: 1072 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1073 return -ENODEV; 1074 } 1075 1076 cs35l56_base->type = devid & 0xFF; 1077 1078 /* Silicon is now identified and booted so exit cache-only */ 1079 regcache_cache_only(cs35l56_base->regmap, false); 1080 1081 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1082 if (ret) { 1083 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1084 return ret; 1085 } 1086 1087 /* When any bus is restricted treat the device as secured */ 1088 if (secured & CS35L56_RESTRICTED_MASK) 1089 cs35l56_base->secured = true; 1090 1091 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1092 if (ret < 0) { 1093 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1094 return ret; 1095 } 1096 1097 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1098 if (ret) 1099 return ret; 1100 1101 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1102 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1103 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1104 1105 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1106 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1107 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1108 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1109 0); 1110 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1111 CS35L56_TEMP_ERR_EINT1_MASK, 1112 0); 1113 1114 return 0; 1115 } 1116 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1117 1118 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1119 { 1120 struct gpio_descs *descs; 1121 u32 speaker_id; 1122 int i, ret; 1123 1124 /* Check for vendor-specific speaker ID method */ 1125 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1126 if (ret >= 0) { 1127 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1128 return ret; 1129 } else if (ret != -ENOENT) { 1130 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1131 return ret; 1132 } 1133 1134 /* Attempt to read the speaker type from a device property */ 1135 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1136 if (!ret) { 1137 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1138 return speaker_id; 1139 } 1140 1141 /* Read the speaker type qualifier from the motherboard GPIOs */ 1142 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1143 if (!descs) { 1144 return -ENOENT; 1145 } else if (IS_ERR(descs)) { 1146 ret = PTR_ERR(descs); 1147 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1148 } 1149 1150 speaker_id = 0; 1151 for (i = 0; i < descs->ndescs; i++) { 1152 ret = gpiod_get_value_cansleep(descs->desc[i]); 1153 if (ret < 0) { 1154 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1155 goto err; 1156 } 1157 1158 speaker_id |= (ret << i); 1159 } 1160 1161 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1162 ret = speaker_id; 1163 err: 1164 gpiod_put_array(descs); 1165 1166 return ret; 1167 } 1168 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1169 1170 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1171 [0x0C] = 128000, 1172 [0x0F] = 256000, 1173 [0x11] = 384000, 1174 [0x12] = 512000, 1175 [0x15] = 768000, 1176 [0x17] = 1024000, 1177 [0x1A] = 1500000, 1178 [0x1B] = 1536000, 1179 [0x1C] = 2000000, 1180 [0x1D] = 2048000, 1181 [0x1E] = 2400000, 1182 [0x20] = 3000000, 1183 [0x21] = 3072000, 1184 [0x23] = 4000000, 1185 [0x24] = 4096000, 1186 [0x25] = 4800000, 1187 [0x27] = 6000000, 1188 [0x28] = 6144000, 1189 [0x29] = 6250000, 1190 [0x2A] = 6400000, 1191 [0x2E] = 8000000, 1192 [0x2F] = 8192000, 1193 [0x30] = 9600000, 1194 [0x32] = 12000000, 1195 [0x33] = 12288000, 1196 [0x37] = 13500000, 1197 [0x38] = 19200000, 1198 [0x39] = 22579200, 1199 [0x3B] = 24576000, 1200 }; 1201 1202 int cs35l56_get_bclk_freq_id(unsigned int freq) 1203 { 1204 int i; 1205 1206 if (freq == 0) 1207 return -EINVAL; 1208 1209 /* The BCLK frequency must be a valid PLL REFCLK */ 1210 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1211 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1212 return i; 1213 } 1214 1215 return -EINVAL; 1216 } 1217 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1218 1219 static const char * const cs35l56_supplies[/* auto-sized */] = { 1220 "VDD_P", 1221 "VDD_IO", 1222 "VDD_A", 1223 }; 1224 1225 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1226 { 1227 int i; 1228 1229 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1230 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1231 data[i].supply = cs35l56_supplies[i]; 1232 } 1233 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1234 1235 const char * const cs35l56_tx_input_texts[] = { 1236 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1237 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1238 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1239 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1240 }; 1241 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1242 1243 const unsigned int cs35l56_tx_input_values[] = { 1244 CS35L56_INPUT_SRC_NONE, 1245 CS35L56_INPUT_SRC_ASP1RX1, 1246 CS35L56_INPUT_SRC_ASP1RX2, 1247 CS35L56_INPUT_SRC_VMON, 1248 CS35L56_INPUT_SRC_IMON, 1249 CS35L56_INPUT_SRC_ERR_VOL, 1250 CS35L56_INPUT_SRC_CLASSH, 1251 CS35L56_INPUT_SRC_VDDBMON, 1252 CS35L56_INPUT_SRC_VBSTMON, 1253 CS35L56_INPUT_SRC_DSP1TX1, 1254 CS35L56_INPUT_SRC_DSP1TX2, 1255 CS35L56_INPUT_SRC_DSP1TX3, 1256 CS35L56_INPUT_SRC_DSP1TX4, 1257 CS35L56_INPUT_SRC_DSP1TX5, 1258 CS35L56_INPUT_SRC_DSP1TX6, 1259 CS35L56_INPUT_SRC_DSP1TX7, 1260 CS35L56_INPUT_SRC_DSP1TX8, 1261 CS35L56_INPUT_SRC_TEMPMON, 1262 CS35L56_INPUT_SRC_INTERPOLATOR, 1263 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1264 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1265 }; 1266 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1267 1268 const struct regmap_config cs35l56_regmap_i2c = { 1269 .reg_bits = 32, 1270 .val_bits = 32, 1271 .reg_stride = 4, 1272 .reg_format_endian = REGMAP_ENDIAN_BIG, 1273 .val_format_endian = REGMAP_ENDIAN_BIG, 1274 .max_register = CS35L56_DSP1_PMEM_5114, 1275 .reg_defaults = cs35l56_reg_defaults, 1276 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1277 .volatile_reg = cs35l56_volatile_reg, 1278 .readable_reg = cs35l56_readable_reg, 1279 .precious_reg = cs35l56_precious_reg, 1280 .cache_type = REGCACHE_MAPLE, 1281 }; 1282 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1283 1284 const struct regmap_config cs35l56_regmap_spi = { 1285 .reg_bits = 32, 1286 .val_bits = 32, 1287 .pad_bits = 16, 1288 .reg_stride = 4, 1289 .reg_format_endian = REGMAP_ENDIAN_BIG, 1290 .val_format_endian = REGMAP_ENDIAN_BIG, 1291 .max_register = CS35L56_DSP1_PMEM_5114, 1292 .reg_defaults = cs35l56_reg_defaults, 1293 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1294 .volatile_reg = cs35l56_volatile_reg, 1295 .readable_reg = cs35l56_readable_reg, 1296 .precious_reg = cs35l56_precious_reg, 1297 .cache_type = REGCACHE_MAPLE, 1298 }; 1299 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1300 1301 const struct regmap_config cs35l56_regmap_sdw = { 1302 .reg_bits = 32, 1303 .val_bits = 32, 1304 .reg_stride = 4, 1305 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1306 .val_format_endian = REGMAP_ENDIAN_BIG, 1307 .max_register = CS35L56_DSP1_PMEM_5114, 1308 .reg_defaults = cs35l56_reg_defaults, 1309 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1310 .volatile_reg = cs35l56_volatile_reg, 1311 .readable_reg = cs35l56_readable_reg, 1312 .precious_reg = cs35l56_precious_reg, 1313 .cache_type = REGCACHE_MAPLE, 1314 }; 1315 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1316 1317 const struct regmap_config cs35l63_regmap_i2c = { 1318 .reg_bits = 32, 1319 .val_bits = 32, 1320 .reg_stride = 4, 1321 .reg_base = 0x8000, 1322 .reg_format_endian = REGMAP_ENDIAN_BIG, 1323 .val_format_endian = REGMAP_ENDIAN_BIG, 1324 .max_register = CS35L56_DSP1_PMEM_5114, 1325 .reg_defaults = cs35l63_reg_defaults, 1326 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1327 .volatile_reg = cs35l63_volatile_reg, 1328 .readable_reg = cs35l56_readable_reg, 1329 .precious_reg = cs35l56_precious_reg, 1330 .cache_type = REGCACHE_MAPLE, 1331 }; 1332 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1333 1334 const struct regmap_config cs35l63_regmap_sdw = { 1335 .reg_bits = 32, 1336 .val_bits = 32, 1337 .reg_stride = 4, 1338 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1339 .val_format_endian = REGMAP_ENDIAN_BIG, 1340 .max_register = CS35L56_DSP1_PMEM_5114, 1341 .reg_defaults = cs35l63_reg_defaults, 1342 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1343 .volatile_reg = cs35l63_volatile_reg, 1344 .readable_reg = cs35l56_readable_reg, 1345 .precious_reg = cs35l56_precious_reg, 1346 .cache_type = REGCACHE_MAPLE, 1347 }; 1348 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1349 1350 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1351 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1352 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1353 MODULE_LICENSE("GPL"); 1354 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1355 MODULE_IMPORT_NS("FW_CS_DSP"); 1356