1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/sched.h> 29 #include <linux/spi/spi.h> 30 #include <linux/spi/spi-mem.h> 31 #include <linux/timer.h> 32 33 #define CQSPI_NAME "cadence-qspi" 34 #define CQSPI_MAX_CHIPSELECT 4 35 36 static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX); 37 38 /* Quirks */ 39 #define CQSPI_NEEDS_WR_DELAY BIT(0) 40 #define CQSPI_DISABLE_DAC_MODE BIT(1) 41 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 42 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 43 #define CQSPI_SLOW_SRAM BIT(4) 44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) 45 #define CQSPI_RD_NO_IRQ BIT(6) 46 #define CQSPI_DMA_SET_MASK BIT(7) 47 #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) 48 #define CQSPI_DISABLE_STIG_MODE BIT(9) 49 #define CQSPI_DISABLE_RUNTIME_PM BIT(10) 50 #define CQSPI_NO_INDIRECT_MODE BIT(11) 51 #define CQSPI_HAS_WR_PROTECT BIT(12) 52 53 /* Capabilities */ 54 #define CQSPI_SUPPORTS_OCTAL BIT(0) 55 #define CQSPI_SUPPORTS_QUAD BIT(1) 56 57 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 58 59 enum { 60 CLK_QSPI_REF = 0, 61 CLK_QSPI_APB, 62 CLK_QSPI_AHB, 63 CLK_QSPI_NUM, 64 }; 65 66 struct cqspi_st; 67 68 struct cqspi_flash_pdata { 69 struct cqspi_st *cqspi; 70 u32 clk_rate; 71 u32 read_delay; 72 u32 tshsl_ns; 73 u32 tsd2d_ns; 74 u32 tchsh_ns; 75 u32 tslch_ns; 76 u8 cs; 77 }; 78 79 static const struct clk_bulk_data cqspi_clks[CLK_QSPI_NUM] = { 80 [CLK_QSPI_APB] = { .id = "apb" }, 81 [CLK_QSPI_AHB] = { .id = "ahb" }, 82 }; 83 84 struct cqspi_st { 85 struct platform_device *pdev; 86 struct spi_controller *host; 87 struct clk_bulk_data clks[CLK_QSPI_NUM]; 88 unsigned int sclk; 89 90 void __iomem *iobase; 91 void __iomem *ahb_base; 92 resource_size_t ahb_size; 93 struct completion transfer_complete; 94 95 struct dma_chan *rx_chan; 96 struct completion rx_dma_complete; 97 dma_addr_t mmap_phys_base; 98 99 int current_cs; 100 unsigned long master_ref_clk_hz; 101 bool is_decoded_cs; 102 u32 fifo_depth; 103 u32 fifo_width; 104 u32 num_chipselect; 105 bool rclk_en; 106 u32 trigger_address; 107 u32 wr_delay; 108 bool use_direct_mode; 109 bool use_direct_mode_wr; 110 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 111 bool use_dma_read; 112 u32 pd_dev_id; 113 bool wr_completion; 114 bool slow_sram; 115 bool apb_ahb_hazard; 116 117 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 118 bool is_rzn1; /* Flag for Renesas RZ/N1 SoC */ 119 bool disable_stig_mode; 120 refcount_t refcount; 121 refcount_t inflight_ops; 122 123 const struct cqspi_driver_platdata *ddata; 124 }; 125 126 struct cqspi_driver_platdata { 127 u32 hwcaps_mask; 128 u16 quirks; 129 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 130 u_char *rxbuf, loff_t from_addr, size_t n_rx); 131 u32 (*get_dma_status)(struct cqspi_st *cqspi); 132 }; 133 134 /* Operation timeout value */ 135 #define CQSPI_TIMEOUT_MS 500 136 #define CQSPI_READ_TIMEOUT_MS 10 137 #define CQSPI_BUSYWAIT_TIMEOUT_US 500 138 139 /* Runtime_pm autosuspend delay */ 140 #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 141 142 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 143 #define CQSPI_DUMMY_BYTES_MAX 4 144 #define CQSPI_DUMMY_CLKS_MAX 31 145 146 #define CQSPI_STIG_DATA_LEN_MAX 8 147 148 /* Register map */ 149 #define CQSPI_REG_CONFIG 0x00 150 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 151 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 152 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 153 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 154 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 155 #define CQSPI_REG_CONFIG_BAUD_LSB 19 156 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 157 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 158 #define CQSPI_REG_CONFIG_IDLE_LSB 31 159 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 160 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 161 #define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) 162 #define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) 163 164 #define CQSPI_REG_RD_INSTR 0x04 165 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 166 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 167 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 168 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 169 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 170 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 171 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 172 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 173 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 174 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 175 176 #define CQSPI_REG_WR_INSTR 0x08 177 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 178 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 179 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 180 181 #define CQSPI_REG_DELAY 0x0C 182 #define CQSPI_REG_DELAY_TSLCH_LSB 0 183 #define CQSPI_REG_DELAY_TCHSH_LSB 8 184 #define CQSPI_REG_DELAY_TSD2D_LSB 16 185 #define CQSPI_REG_DELAY_TSHSL_LSB 24 186 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 187 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 188 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 189 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 190 191 #define CQSPI_REG_READCAPTURE 0x10 192 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 193 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 194 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 195 196 #define CQSPI_REG_SIZE 0x14 197 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 198 #define CQSPI_REG_SIZE_PAGE_LSB 4 199 #define CQSPI_REG_SIZE_BLOCK_LSB 16 200 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 201 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 202 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 203 204 #define CQSPI_REG_SRAMPARTITION 0x18 205 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 206 207 #define CQSPI_REG_DMA 0x20 208 #define CQSPI_REG_DMA_SINGLE_LSB 0 209 #define CQSPI_REG_DMA_BURST_LSB 8 210 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 211 #define CQSPI_REG_DMA_BURST_MASK 0xFF 212 213 #define CQSPI_REG_REMAP 0x24 214 #define CQSPI_REG_MODE_BIT 0x28 215 216 #define CQSPI_REG_SDRAMLEVEL 0x2C 217 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 218 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 219 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 220 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 221 222 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 223 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 224 225 #define CQSPI_REG_IRQSTATUS 0x40 226 #define CQSPI_REG_IRQMASK 0x44 227 228 #define CQSPI_REG_WR_PROT_CTRL 0x58 229 230 #define CQSPI_REG_INDIRECTRD 0x60 231 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 232 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 233 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 234 235 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 236 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 237 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 238 239 #define CQSPI_REG_CMDCTRL 0x90 240 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 241 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 242 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 243 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 244 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 245 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 246 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 247 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 248 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 249 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 250 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 251 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 252 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 253 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 254 255 #define CQSPI_REG_INDIRECTWR 0x70 256 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 257 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 258 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 259 260 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 261 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 262 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 263 264 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 265 266 #define CQSPI_REG_CMDADDRESS 0x94 267 #define CQSPI_REG_CMDREADDATALOWER 0xA0 268 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 269 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 270 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 271 272 #define CQSPI_REG_POLLING_STATUS 0xB0 273 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 274 275 #define CQSPI_REG_OP_EXT_LOWER 0xE0 276 #define CQSPI_REG_OP_EXT_READ_LSB 24 277 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 278 #define CQSPI_REG_OP_EXT_STIG_LSB 0 279 280 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 281 282 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 283 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 284 285 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 286 287 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 288 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 289 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 290 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 291 292 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 293 294 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 295 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 296 297 /* Interrupt status bits */ 298 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 299 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 300 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 301 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 302 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 303 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 304 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 305 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 306 307 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 308 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 309 CQSPI_REG_IRQ_IND_COMP) 310 311 #define CQSPI_IRQ_MASK_RD_SLOW_SRAM (CQSPI_REG_IRQ_WATERMARK | \ 312 CQSPI_REG_IRQ_IND_COMP) 313 314 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 315 CQSPI_REG_IRQ_WATERMARK | \ 316 CQSPI_REG_IRQ_UNDERFLOW) 317 318 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 319 #define CQSPI_DMA_UNALIGN 0x3 320 321 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 322 323 static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, 324 void __iomem *reg, const u32 mask, bool clr, 325 bool busywait) 326 { 327 u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC; 328 u32 val; 329 330 if (busywait) { 331 int ret = readl_relaxed_poll_timeout(reg, val, 332 (((clr ? ~val : val) & mask) == mask), 333 0, CQSPI_BUSYWAIT_TIMEOUT_US); 334 335 if (ret != -ETIMEDOUT) 336 return ret; 337 338 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; 339 } 340 341 return readl_relaxed_poll_timeout(reg, val, 342 (((clr ? ~val : val) & mask) == mask), 343 10, timeout_us); 344 } 345 346 static bool cqspi_is_idle(struct cqspi_st *cqspi) 347 { 348 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 349 350 return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB); 351 } 352 353 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 354 { 355 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 356 357 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 358 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 359 } 360 361 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 362 { 363 u32 dma_status; 364 365 dma_status = readl(cqspi->iobase + 366 CQSPI_REG_VERSAL_DMA_DST_I_STS); 367 writel(dma_status, cqspi->iobase + 368 CQSPI_REG_VERSAL_DMA_DST_I_STS); 369 370 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 371 } 372 373 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 374 { 375 struct cqspi_st *cqspi = dev; 376 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 377 unsigned int irq_status; 378 379 /* Read interrupt status */ 380 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 381 382 /* Clear interrupt */ 383 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 384 385 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 386 if (ddata->get_dma_status(cqspi)) { 387 complete(&cqspi->transfer_complete); 388 return IRQ_HANDLED; 389 } 390 } else if (cqspi->slow_sram) { 391 irq_status &= CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR; 392 } else { 393 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 394 } 395 396 if (irq_status) 397 complete(&cqspi->transfer_complete); 398 399 return IRQ_HANDLED; 400 } 401 402 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 403 { 404 u32 rdreg = 0; 405 406 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 407 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 408 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 409 410 return rdreg; 411 } 412 413 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 414 { 415 unsigned int dummy_clk; 416 417 if (!op->dummy.nbytes) 418 return 0; 419 420 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 421 if (op->cmd.dtr) 422 dummy_clk /= 2; 423 424 return dummy_clk; 425 } 426 427 static int cqspi_wait_idle(struct cqspi_st *cqspi) 428 { 429 const unsigned int poll_idle_retry = 3; 430 unsigned int count = 0; 431 unsigned long timeout; 432 433 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 434 while (1) { 435 /* 436 * Read few times in succession to ensure the controller 437 * is indeed idle, that is, the bit does not transition 438 * low again. 439 */ 440 if (cqspi_is_idle(cqspi)) 441 count++; 442 else 443 count = 0; 444 445 if (count >= poll_idle_retry) 446 return 0; 447 448 if (time_after(jiffies, timeout)) { 449 /* Timeout, in busy mode. */ 450 dev_err(&cqspi->pdev->dev, 451 "QSPI is still busy after %dms timeout.\n", 452 CQSPI_TIMEOUT_MS); 453 return -ETIMEDOUT; 454 } 455 456 cpu_relax(); 457 } 458 } 459 460 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 461 { 462 void __iomem *reg_base = cqspi->iobase; 463 int ret; 464 465 /* Write the CMDCTRL without start execution. */ 466 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 467 /* Start execute */ 468 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 469 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 470 471 /* Polling for completion. */ 472 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, 473 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true); 474 if (ret) { 475 dev_err(&cqspi->pdev->dev, 476 "Flash command execution timed out.\n"); 477 return ret; 478 } 479 480 /* Polling QSPI idle status. */ 481 return cqspi_wait_idle(cqspi); 482 } 483 484 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 485 const struct spi_mem_op *op, 486 unsigned int shift) 487 { 488 struct cqspi_st *cqspi = f_pdata->cqspi; 489 void __iomem *reg_base = cqspi->iobase; 490 unsigned int reg; 491 u8 ext; 492 493 if (op->cmd.nbytes != 2) 494 return -EINVAL; 495 496 /* Opcode extension is the LSB. */ 497 ext = op->cmd.opcode & 0xff; 498 499 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 500 reg &= ~(0xff << shift); 501 reg |= ext << shift; 502 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 503 504 return 0; 505 } 506 507 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 508 const struct spi_mem_op *op, unsigned int shift) 509 { 510 struct cqspi_st *cqspi = f_pdata->cqspi; 511 void __iomem *reg_base = cqspi->iobase; 512 unsigned int reg; 513 int ret; 514 515 reg = readl(reg_base + CQSPI_REG_CONFIG); 516 517 /* 518 * We enable dual byte opcode here. The callers have to set up the 519 * extension opcode based on which type of operation it is. 520 */ 521 if (op->cmd.dtr) { 522 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 523 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 524 525 /* Set up command opcode extension. */ 526 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 527 if (ret) 528 return ret; 529 } else { 530 unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE; 531 /* Shortcut if DTR is already disabled. */ 532 if ((reg & mask) == 0) 533 return 0; 534 reg &= ~mask; 535 } 536 537 writel(reg, reg_base + CQSPI_REG_CONFIG); 538 539 return cqspi_wait_idle(cqspi); 540 } 541 542 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 543 const struct spi_mem_op *op) 544 { 545 struct cqspi_st *cqspi = f_pdata->cqspi; 546 void __iomem *reg_base = cqspi->iobase; 547 u8 *rxbuf = op->data.buf.in; 548 u8 opcode; 549 size_t n_rx = op->data.nbytes; 550 unsigned int rdreg; 551 unsigned int reg; 552 unsigned int dummy_clk; 553 size_t read_len; 554 int status; 555 556 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 557 if (status) 558 return status; 559 560 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 561 dev_err(&cqspi->pdev->dev, 562 "Invalid input argument, len %zu rxbuf 0x%p\n", 563 n_rx, rxbuf); 564 return -EINVAL; 565 } 566 567 if (op->cmd.dtr) 568 opcode = op->cmd.opcode >> 8; 569 else 570 opcode = op->cmd.opcode; 571 572 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 573 574 rdreg = cqspi_calc_rdreg(op); 575 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 576 577 dummy_clk = cqspi_calc_dummy(op); 578 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 579 return -EOPNOTSUPP; 580 581 if (dummy_clk) 582 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 583 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 584 585 reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB); 586 587 /* 0 means 1 byte. */ 588 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 589 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 590 591 /* setup ADDR BIT field */ 592 if (op->addr.nbytes) { 593 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 594 reg |= ((op->addr.nbytes - 1) & 595 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 596 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 597 598 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 599 } 600 601 status = cqspi_exec_flash_cmd(cqspi, reg); 602 if (status) 603 return status; 604 605 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 606 607 /* Put the read value into rx_buf */ 608 read_len = (n_rx > 4) ? 4 : n_rx; 609 memcpy(rxbuf, ®, read_len); 610 rxbuf += read_len; 611 612 if (n_rx > 4) { 613 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 614 615 read_len = n_rx - read_len; 616 memcpy(rxbuf, ®, read_len); 617 } 618 619 /* Reset CMD_CTRL Reg once command read completes */ 620 writel(0, reg_base + CQSPI_REG_CMDCTRL); 621 622 return 0; 623 } 624 625 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 626 const struct spi_mem_op *op) 627 { 628 struct cqspi_st *cqspi = f_pdata->cqspi; 629 void __iomem *reg_base = cqspi->iobase; 630 u8 opcode; 631 const u8 *txbuf = op->data.buf.out; 632 size_t n_tx = op->data.nbytes; 633 unsigned int reg; 634 unsigned int data; 635 size_t write_len; 636 int ret; 637 638 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 639 if (ret) 640 return ret; 641 642 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 643 dev_err(&cqspi->pdev->dev, 644 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 645 n_tx, txbuf); 646 return -EINVAL; 647 } 648 649 reg = cqspi_calc_rdreg(op); 650 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 651 652 if (op->cmd.dtr) 653 opcode = op->cmd.opcode >> 8; 654 else 655 opcode = op->cmd.opcode; 656 657 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 658 659 if (op->addr.nbytes) { 660 reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 661 reg |= ((op->addr.nbytes - 1) & 662 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 663 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 664 665 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 666 } 667 668 if (n_tx) { 669 reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB); 670 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 671 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 672 data = 0; 673 write_len = (n_tx > 4) ? 4 : n_tx; 674 memcpy(&data, txbuf, write_len); 675 txbuf += write_len; 676 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 677 678 if (n_tx > 4) { 679 data = 0; 680 write_len = n_tx - 4; 681 memcpy(&data, txbuf, write_len); 682 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 683 } 684 } 685 686 ret = cqspi_exec_flash_cmd(cqspi, reg); 687 688 /* Reset CMD_CTRL Reg once command write completes */ 689 writel(0, reg_base + CQSPI_REG_CMDCTRL); 690 691 return ret; 692 } 693 694 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 695 const struct spi_mem_op *op) 696 { 697 struct cqspi_st *cqspi = f_pdata->cqspi; 698 void __iomem *reg_base = cqspi->iobase; 699 unsigned int dummy_clk = 0; 700 unsigned int reg; 701 int ret; 702 u8 opcode; 703 704 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 705 if (ret) 706 return ret; 707 708 if (op->cmd.dtr) 709 opcode = op->cmd.opcode >> 8; 710 else 711 opcode = op->cmd.opcode; 712 713 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 714 reg |= cqspi_calc_rdreg(op); 715 716 /* Setup dummy clock cycles */ 717 dummy_clk = cqspi_calc_dummy(op); 718 719 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 720 return -EOPNOTSUPP; 721 722 if (dummy_clk) 723 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 724 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 725 726 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 727 728 /* Set address width */ 729 reg = readl(reg_base + CQSPI_REG_SIZE); 730 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 731 reg |= (op->addr.nbytes - 1); 732 writel(reg, reg_base + CQSPI_REG_SIZE); 733 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 734 return 0; 735 } 736 737 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 738 u8 *rxbuf, loff_t from_addr, 739 const size_t n_rx) 740 { 741 struct cqspi_st *cqspi = f_pdata->cqspi; 742 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); 743 struct device *dev = &cqspi->pdev->dev; 744 void __iomem *reg_base = cqspi->iobase; 745 void __iomem *ahb_base = cqspi->ahb_base; 746 unsigned int remaining = n_rx; 747 unsigned int mod_bytes = n_rx % 4; 748 unsigned int bytes_to_read = 0; 749 u8 *rxbuf_end = rxbuf + n_rx; 750 int ret = 0; 751 752 if (!refcount_read(&cqspi->refcount)) 753 return -ENODEV; 754 755 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 756 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 757 758 /* Clear all interrupts. */ 759 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 760 761 /* 762 * On SoCFPGA platform reading the SRAM is slow due to 763 * hardware limitation and causing read interrupt storm to CPU, 764 * so enabling only watermark interrupt to disable all read 765 * interrupts later as we want to run "bytes to read" loop with 766 * all the read interrupts disabled for max performance. 767 */ 768 769 if (use_irq && cqspi->slow_sram) 770 writel(CQSPI_IRQ_MASK_RD_SLOW_SRAM, reg_base + CQSPI_REG_IRQMASK); 771 else if (use_irq) 772 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 773 else 774 writel(0, reg_base + CQSPI_REG_IRQMASK); 775 776 reinit_completion(&cqspi->transfer_complete); 777 writel(CQSPI_REG_INDIRECTRD_START_MASK, 778 reg_base + CQSPI_REG_INDIRECTRD); 779 readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ 780 781 while (remaining > 0) { 782 ret = 0; 783 if (use_irq && 784 !wait_for_completion_timeout(&cqspi->transfer_complete, 785 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 786 ret = -ETIMEDOUT; 787 788 /* 789 * Prevent lost interrupt and race condition by reinitializing early. 790 * A spurious wakeup and another wait cycle can occur here, 791 * which is preferable to waiting until timeout if interrupt is lost. 792 */ 793 if (use_irq) 794 reinit_completion(&cqspi->transfer_complete); 795 796 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 797 798 if (ret && bytes_to_read == 0) { 799 dev_err(dev, "Indirect read timeout, no bytes\n"); 800 goto failrd; 801 } 802 803 while (bytes_to_read != 0) { 804 unsigned int word_remain = round_down(remaining, 4); 805 806 bytes_to_read *= cqspi->fifo_width; 807 bytes_to_read = bytes_to_read > remaining ? 808 remaining : bytes_to_read; 809 bytes_to_read = round_down(bytes_to_read, 4); 810 /* Read 4 byte word chunks then single bytes */ 811 if (bytes_to_read) { 812 ioread32_rep(ahb_base, rxbuf, 813 (bytes_to_read / 4)); 814 } else if (!word_remain && mod_bytes) { 815 unsigned int temp = ioread32(ahb_base); 816 817 bytes_to_read = mod_bytes; 818 memcpy(rxbuf, &temp, min((unsigned int) 819 (rxbuf_end - rxbuf), 820 bytes_to_read)); 821 } 822 rxbuf += bytes_to_read; 823 remaining -= bytes_to_read; 824 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 825 } 826 } 827 828 /* Check indirect done status */ 829 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, 830 CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true); 831 if (ret) { 832 dev_err(dev, "Indirect read completion error (%i)\n", ret); 833 goto failrd; 834 } 835 836 /* Disable interrupt */ 837 writel(0, reg_base + CQSPI_REG_IRQMASK); 838 839 /* Clear indirect completion status */ 840 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 841 842 return 0; 843 844 failrd: 845 /* Disable interrupt */ 846 writel(0, reg_base + CQSPI_REG_IRQMASK); 847 848 /* Cancel the indirect read */ 849 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 850 reg_base + CQSPI_REG_INDIRECTRD); 851 return ret; 852 } 853 854 static void cqspi_device_reset(struct cqspi_st *cqspi) 855 { 856 u32 reg; 857 858 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 859 reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; 860 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 861 /* 862 * NOTE: Delay timing implementation is derived from 863 * spi_nor_hw_reset() 864 */ 865 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 866 usleep_range(1, 5); 867 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 868 usleep_range(100, 150); 869 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 870 usleep_range(1000, 1200); 871 } 872 873 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 874 { 875 void __iomem *reg_base = cqspi->iobase; 876 unsigned int reg; 877 878 reg = readl(reg_base + CQSPI_REG_CONFIG); 879 880 if (enable) 881 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 882 else 883 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 884 885 writel(reg, reg_base + CQSPI_REG_CONFIG); 886 } 887 888 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 889 u_char *rxbuf, loff_t from_addr, 890 size_t n_rx) 891 { 892 struct cqspi_st *cqspi = f_pdata->cqspi; 893 struct device *dev = &cqspi->pdev->dev; 894 void __iomem *reg_base = cqspi->iobase; 895 u32 reg, bytes_to_dma; 896 loff_t addr = from_addr; 897 void *buf = rxbuf; 898 dma_addr_t dma_addr; 899 u8 bytes_rem; 900 int ret = 0; 901 902 bytes_rem = n_rx % 4; 903 bytes_to_dma = (n_rx - bytes_rem); 904 905 if (!bytes_to_dma) 906 goto nondmard; 907 908 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 909 if (ret) 910 return ret; 911 912 cqspi_controller_enable(cqspi, 0); 913 914 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 915 reg |= CQSPI_REG_CONFIG_DMA_MASK; 916 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 917 918 cqspi_controller_enable(cqspi, 1); 919 920 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 921 if (dma_mapping_error(dev, dma_addr)) { 922 dev_err(dev, "dma mapping failed\n"); 923 return -ENOMEM; 924 } 925 926 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 927 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 928 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 929 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 930 931 /* Clear all interrupts. */ 932 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 933 934 /* Enable DMA done interrupt */ 935 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 936 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 937 938 /* Default DMA periph configuration */ 939 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 940 941 /* Configure DMA Dst address */ 942 writel(lower_32_bits(dma_addr), 943 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 944 writel(upper_32_bits(dma_addr), 945 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 946 947 /* Configure DMA Src address */ 948 writel(cqspi->trigger_address, reg_base + 949 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 950 951 /* Set DMA destination size */ 952 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 953 954 /* Set DMA destination control */ 955 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 956 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 957 958 writel(CQSPI_REG_INDIRECTRD_START_MASK, 959 reg_base + CQSPI_REG_INDIRECTRD); 960 961 reinit_completion(&cqspi->transfer_complete); 962 963 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 964 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 965 ret = -ETIMEDOUT; 966 goto failrd; 967 } 968 969 /* Disable DMA interrupt */ 970 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 971 972 /* Clear indirect completion status */ 973 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 974 cqspi->iobase + CQSPI_REG_INDIRECTRD); 975 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 976 977 cqspi_controller_enable(cqspi, 0); 978 979 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 980 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 981 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 982 983 cqspi_controller_enable(cqspi, 1); 984 985 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 986 PM_OSPI_MUX_SEL_LINEAR); 987 if (ret) 988 return ret; 989 990 nondmard: 991 if (bytes_rem) { 992 addr += bytes_to_dma; 993 buf += bytes_to_dma; 994 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 995 bytes_rem); 996 if (ret) 997 return ret; 998 } 999 1000 return 0; 1001 1002 failrd: 1003 /* Disable DMA interrupt */ 1004 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 1005 1006 /* Cancel the indirect read */ 1007 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1008 reg_base + CQSPI_REG_INDIRECTRD); 1009 1010 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 1011 1012 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1013 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 1014 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1015 1016 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 1017 1018 return ret; 1019 } 1020 1021 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 1022 const struct spi_mem_op *op) 1023 { 1024 unsigned int reg; 1025 int ret; 1026 struct cqspi_st *cqspi = f_pdata->cqspi; 1027 void __iomem *reg_base = cqspi->iobase; 1028 u8 opcode; 1029 1030 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 1031 if (ret) 1032 return ret; 1033 1034 if (op->cmd.dtr) 1035 opcode = op->cmd.opcode >> 8; 1036 else 1037 opcode = op->cmd.opcode; 1038 1039 /* Set opcode. */ 1040 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 1041 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 1042 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 1043 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 1044 reg = cqspi_calc_rdreg(op); 1045 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 1046 1047 /* 1048 * SPI NAND flashes require the address of the status register to be 1049 * passed in the Read SR command. Also, some SPI NOR flashes like the 1050 * cypress Semper flash expect a 4-byte dummy address in the Read SR 1051 * command in DTR mode. 1052 * 1053 * But this controller does not support address phase in the Read SR 1054 * command when doing auto-HW polling. So, disable write completion 1055 * polling on the controller's side. spinand and spi-nor will take 1056 * care of polling the status register. 1057 */ 1058 if (cqspi->wr_completion) { 1059 reg = CQSPI_REG_WR_DISABLE_AUTO_POLL; 1060 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1061 /* 1062 * DAC mode require auto polling as flash needs to be polled 1063 * for write completion in case of bubble in SPI transaction 1064 * due to slow CPU/DMA master. 1065 */ 1066 cqspi->use_direct_mode_wr = false; 1067 } 1068 1069 reg = readl(reg_base + CQSPI_REG_SIZE); 1070 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1071 reg |= (op->addr.nbytes - 1); 1072 writel(reg, reg_base + CQSPI_REG_SIZE); 1073 readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ 1074 return 0; 1075 } 1076 1077 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 1078 loff_t to_addr, const u8 *txbuf, 1079 const size_t n_tx) 1080 { 1081 struct cqspi_st *cqspi = f_pdata->cqspi; 1082 struct device *dev = &cqspi->pdev->dev; 1083 void __iomem *reg_base = cqspi->iobase; 1084 unsigned int remaining = n_tx; 1085 unsigned int write_bytes; 1086 int ret; 1087 1088 if (!refcount_read(&cqspi->refcount)) 1089 return -ENODEV; 1090 1091 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 1092 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 1093 1094 /* Clear all interrupts. */ 1095 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 1096 1097 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 1098 1099 reinit_completion(&cqspi->transfer_complete); 1100 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1101 reg_base + CQSPI_REG_INDIRECTWR); 1102 readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ 1103 1104 /* 1105 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1106 * Controller programming sequence, couple of cycles of 1107 * QSPI_REF_CLK delay is required for the above bit to 1108 * be internally synchronized by the QSPI module. Provide 5 1109 * cycles of delay. 1110 */ 1111 if (cqspi->wr_delay) 1112 ndelay(cqspi->wr_delay); 1113 1114 /* 1115 * If a hazard exists between the APB and AHB interfaces, perform a 1116 * dummy readback from the controller to ensure synchronization. 1117 */ 1118 if (cqspi->apb_ahb_hazard) 1119 readl(reg_base + CQSPI_REG_INDIRECTWR); 1120 1121 while (remaining > 0) { 1122 size_t write_words, mod_bytes; 1123 1124 write_bytes = remaining; 1125 write_words = write_bytes / 4; 1126 mod_bytes = write_bytes % 4; 1127 /* Write 4 bytes at a time then single bytes. */ 1128 if (write_words) { 1129 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1130 txbuf += (write_words * 4); 1131 } 1132 if (mod_bytes) { 1133 unsigned int temp = 0xFFFFFFFF; 1134 1135 memcpy(&temp, txbuf, mod_bytes); 1136 iowrite32(temp, cqspi->ahb_base); 1137 txbuf += mod_bytes; 1138 } 1139 1140 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1141 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1142 dev_err(dev, "Indirect write timeout\n"); 1143 ret = -ETIMEDOUT; 1144 goto failwr; 1145 } 1146 1147 remaining -= write_bytes; 1148 1149 if (remaining > 0) 1150 reinit_completion(&cqspi->transfer_complete); 1151 } 1152 1153 /* Check indirect done status */ 1154 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, 1155 CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false); 1156 if (ret) { 1157 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1158 goto failwr; 1159 } 1160 1161 /* Disable interrupt. */ 1162 writel(0, reg_base + CQSPI_REG_IRQMASK); 1163 1164 /* Clear indirect completion status */ 1165 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1166 1167 cqspi_wait_idle(cqspi); 1168 1169 return 0; 1170 1171 failwr: 1172 /* Disable interrupt. */ 1173 writel(0, reg_base + CQSPI_REG_IRQMASK); 1174 1175 /* Cancel the indirect write */ 1176 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1177 reg_base + CQSPI_REG_INDIRECTWR); 1178 return ret; 1179 } 1180 1181 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1182 { 1183 struct cqspi_st *cqspi = f_pdata->cqspi; 1184 void __iomem *reg_base = cqspi->iobase; 1185 unsigned int chip_select = f_pdata->cs; 1186 unsigned int reg; 1187 1188 reg = readl(reg_base + CQSPI_REG_CONFIG); 1189 if (cqspi->is_decoded_cs) { 1190 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1191 } else { 1192 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1193 1194 /* Convert CS if without decoder. 1195 * CS0 to 4b'1110 1196 * CS1 to 4b'1101 1197 * CS2 to 4b'1011 1198 * CS3 to 4b'0111 1199 */ 1200 chip_select = 0xF & ~BIT(chip_select); 1201 } 1202 1203 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1204 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1205 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1206 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1207 writel(reg, reg_base + CQSPI_REG_CONFIG); 1208 } 1209 1210 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1211 const unsigned int ns_val) 1212 { 1213 unsigned int ticks; 1214 1215 ticks = ref_clk_hz / 1000; /* kHz */ 1216 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1217 1218 return ticks; 1219 } 1220 1221 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1222 { 1223 struct cqspi_st *cqspi = f_pdata->cqspi; 1224 void __iomem *iobase = cqspi->iobase; 1225 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1226 unsigned int tshsl, tchsh, tslch, tsd2d; 1227 unsigned int reg; 1228 unsigned int tsclk; 1229 1230 /* calculate the number of ref ticks for one sclk tick */ 1231 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1232 1233 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1234 /* this particular value must be at least one sclk */ 1235 if (tshsl < tsclk) 1236 tshsl = tsclk; 1237 1238 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1239 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1240 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1241 1242 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1243 << CQSPI_REG_DELAY_TSHSL_LSB; 1244 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1245 << CQSPI_REG_DELAY_TCHSH_LSB; 1246 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1247 << CQSPI_REG_DELAY_TSLCH_LSB; 1248 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1249 << CQSPI_REG_DELAY_TSD2D_LSB; 1250 writel(reg, iobase + CQSPI_REG_DELAY); 1251 } 1252 1253 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1254 { 1255 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1256 void __iomem *reg_base = cqspi->iobase; 1257 u32 reg, div; 1258 1259 /* Recalculate the baudrate divisor based on QSPI specification. */ 1260 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1261 1262 /* Maximum baud divisor */ 1263 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1264 div = CQSPI_REG_CONFIG_BAUD_MASK; 1265 dev_warn(&cqspi->pdev->dev, 1266 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1267 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1268 } 1269 1270 reg = readl(reg_base + CQSPI_REG_CONFIG); 1271 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1272 reg |= div << CQSPI_REG_CONFIG_BAUD_LSB; 1273 writel(reg, reg_base + CQSPI_REG_CONFIG); 1274 } 1275 1276 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1277 const bool bypass, 1278 const unsigned int delay) 1279 { 1280 void __iomem *reg_base = cqspi->iobase; 1281 unsigned int reg; 1282 1283 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1284 1285 if (bypass) 1286 reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1287 else 1288 reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); 1289 1290 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1291 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1292 1293 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1294 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1295 1296 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1297 } 1298 1299 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1300 unsigned long sclk) 1301 { 1302 struct cqspi_st *cqspi = f_pdata->cqspi; 1303 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1304 int switch_ck = (cqspi->sclk != sclk); 1305 1306 if (switch_cs || switch_ck) 1307 cqspi_controller_enable(cqspi, 0); 1308 1309 /* Switch chip select. */ 1310 if (switch_cs) { 1311 cqspi->current_cs = f_pdata->cs; 1312 cqspi_chipselect(f_pdata); 1313 } 1314 1315 /* Setup baudrate divisor and delays */ 1316 if (switch_ck) { 1317 cqspi->sclk = sclk; 1318 cqspi_config_baudrate_div(cqspi); 1319 cqspi_delay(f_pdata); 1320 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1321 f_pdata->read_delay); 1322 } 1323 1324 if (switch_cs || switch_ck) 1325 cqspi_controller_enable(cqspi, 1); 1326 } 1327 1328 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1329 const struct spi_mem_op *op) 1330 { 1331 struct cqspi_st *cqspi = f_pdata->cqspi; 1332 loff_t to = op->addr.val; 1333 size_t len = op->data.nbytes; 1334 const u_char *buf = op->data.buf.out; 1335 int ret; 1336 1337 ret = cqspi_write_setup(f_pdata, op); 1338 if (ret) 1339 return ret; 1340 1341 /* 1342 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1343 * address (all 0s) with the read status register command in DTR mode. 1344 * But this controller does not support sending dummy address bytes to 1345 * the flash when it is polling the write completion register in DTR 1346 * mode. So, we can not use direct mode when in DTR mode for writing 1347 * data. 1348 */ 1349 if ((!op->cmd.dtr && cqspi->use_direct_mode && 1350 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) || 1351 (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1352 memcpy_toio(cqspi->ahb_base + to, buf, len); 1353 return cqspi_wait_idle(cqspi); 1354 } 1355 1356 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1357 } 1358 1359 static void cqspi_rx_dma_callback(void *param) 1360 { 1361 struct cqspi_st *cqspi = param; 1362 1363 complete(&cqspi->rx_dma_complete); 1364 } 1365 1366 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1367 u_char *buf, loff_t from, size_t len) 1368 { 1369 struct cqspi_st *cqspi = f_pdata->cqspi; 1370 struct device *dev = &cqspi->pdev->dev; 1371 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1372 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1373 int ret = 0; 1374 struct dma_async_tx_descriptor *tx; 1375 dma_cookie_t cookie; 1376 dma_addr_t dma_dst; 1377 struct device *ddev; 1378 1379 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1380 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1381 return 0; 1382 } 1383 1384 ddev = cqspi->rx_chan->device->dev; 1385 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1386 if (dma_mapping_error(ddev, dma_dst)) { 1387 dev_err(dev, "dma mapping failed\n"); 1388 return -ENOMEM; 1389 } 1390 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1391 len, flags); 1392 if (!tx) { 1393 dev_err(dev, "device_prep_dma_memcpy error\n"); 1394 ret = -EIO; 1395 goto err_unmap; 1396 } 1397 1398 tx->callback = cqspi_rx_dma_callback; 1399 tx->callback_param = cqspi; 1400 cookie = tx->tx_submit(tx); 1401 reinit_completion(&cqspi->rx_dma_complete); 1402 1403 ret = dma_submit_error(cookie); 1404 if (ret) { 1405 dev_err(dev, "dma_submit_error %d\n", cookie); 1406 ret = -EIO; 1407 goto err_unmap; 1408 } 1409 1410 dma_async_issue_pending(cqspi->rx_chan); 1411 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1412 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1413 dmaengine_terminate_sync(cqspi->rx_chan); 1414 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1415 ret = -ETIMEDOUT; 1416 goto err_unmap; 1417 } 1418 1419 err_unmap: 1420 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1421 1422 return ret; 1423 } 1424 1425 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1426 const struct spi_mem_op *op) 1427 { 1428 struct cqspi_st *cqspi = f_pdata->cqspi; 1429 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 1430 loff_t from = op->addr.val; 1431 size_t len = op->data.nbytes; 1432 u_char *buf = op->data.buf.in; 1433 u64 dma_align = (u64)(uintptr_t)buf; 1434 int ret; 1435 1436 ret = cqspi_read_setup(f_pdata, op); 1437 if (ret) 1438 return ret; 1439 1440 if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) || 1441 (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) 1442 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1443 1444 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1445 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1446 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1447 1448 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1449 } 1450 1451 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1452 { 1453 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1454 struct cqspi_flash_pdata *f_pdata; 1455 1456 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 1457 cqspi_configure(f_pdata, op->max_freq); 1458 1459 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1460 /* 1461 * Performing reads in DAC mode forces to read minimum 4 bytes 1462 * which is unsupported on some flash devices during register 1463 * reads, prefer STIG mode for such small reads. 1464 */ 1465 if (!op->addr.nbytes || 1466 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && 1467 !cqspi->disable_stig_mode)) 1468 return cqspi_command_read(f_pdata, op); 1469 1470 return cqspi_read(f_pdata, op); 1471 } 1472 1473 if (!op->addr.nbytes || !op->data.buf.out) 1474 return cqspi_command_write(f_pdata, op); 1475 1476 return cqspi_write(f_pdata, op); 1477 } 1478 1479 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1480 { 1481 int ret; 1482 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1483 struct device *dev = &cqspi->pdev->dev; 1484 1485 if (refcount_read(&cqspi->inflight_ops) == 0) 1486 return -ENODEV; 1487 1488 if (!refcount_read(&cqspi->refcount)) 1489 return -EBUSY; 1490 1491 refcount_inc(&cqspi->inflight_ops); 1492 1493 if (!refcount_read(&cqspi->refcount)) { 1494 if (refcount_read(&cqspi->inflight_ops)) 1495 refcount_dec(&cqspi->inflight_ops); 1496 return -EBUSY; 1497 } 1498 1499 ret = pm_runtime_resume_and_get(dev); 1500 if (ret) { 1501 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); 1502 goto dec_inflight_refcount; 1503 } 1504 1505 ret = cqspi_mem_process(mem, op); 1506 1507 pm_runtime_put_autosuspend(dev); 1508 1509 if (ret) 1510 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1511 1512 dec_inflight_refcount: 1513 if (refcount_read(&cqspi->inflight_ops) > 1) 1514 refcount_dec(&cqspi->inflight_ops); 1515 1516 return ret; 1517 } 1518 1519 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1520 const struct spi_mem_op *op) 1521 { 1522 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1523 bool all_true, all_false; 1524 1525 /* 1526 * op->dummy.dtr is required for converting nbytes into ncycles. 1527 * Also, don't check the dtr field of the op phase having zero nbytes. 1528 */ 1529 all_true = op->cmd.dtr && 1530 (!op->addr.nbytes || op->addr.dtr) && 1531 (!op->dummy.nbytes || op->dummy.dtr) && 1532 (!op->data.nbytes || op->data.dtr); 1533 1534 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1535 !op->data.dtr; 1536 1537 if (all_true) { 1538 /* Right now we only support 8-8-8 DTR mode. */ 1539 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1540 return false; 1541 if (op->addr.nbytes && op->addr.buswidth != 8) 1542 return false; 1543 if (op->data.nbytes && op->data.buswidth != 8) 1544 return false; 1545 1546 if (cqspi->is_rzn1) 1547 return false; 1548 } else if (!all_false) { 1549 /* Mixed DTR modes are not supported. */ 1550 return false; 1551 } 1552 1553 return spi_mem_default_supports_op(mem, op); 1554 } 1555 1556 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1557 struct cqspi_flash_pdata *f_pdata, 1558 struct device_node *np) 1559 { 1560 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1561 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1562 return -ENXIO; 1563 } 1564 1565 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1566 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1567 return -ENXIO; 1568 } 1569 1570 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1571 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1572 return -ENXIO; 1573 } 1574 1575 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1576 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1577 return -ENXIO; 1578 } 1579 1580 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1581 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1582 return -ENXIO; 1583 } 1584 1585 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1586 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1587 return -ENXIO; 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1594 { 1595 struct device *dev = &cqspi->pdev->dev; 1596 struct device_node *np = dev->of_node; 1597 u32 id[2]; 1598 1599 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1600 1601 if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1602 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1603 /* Zero signals FIFO depth should be runtime detected. */ 1604 cqspi->fifo_depth = 0; 1605 } 1606 1607 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) 1608 cqspi->fifo_width = 4; 1609 1610 if (of_property_read_u32(np, "cdns,trigger-address", 1611 &cqspi->trigger_address)) { 1612 dev_err(dev, "couldn't determine trigger-address\n"); 1613 return -ENXIO; 1614 } 1615 } 1616 1617 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1618 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1619 1620 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1621 1622 if (!of_property_read_u32_array(np, "power-domains", id, 1623 ARRAY_SIZE(id))) 1624 cqspi->pd_dev_id = id[1]; 1625 1626 return 0; 1627 } 1628 1629 static void cqspi_controller_init(struct cqspi_st *cqspi) 1630 { 1631 u32 reg; 1632 1633 /* Configure the remap address register, no remap */ 1634 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1635 1636 /* Disable all interrupts. */ 1637 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1638 1639 if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1640 /* Configure the SRAM split to 1:1 . */ 1641 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1642 /* Load indirect trigger address. */ 1643 writel(cqspi->trigger_address, 1644 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1645 1646 /* Program read watermark -- 1/2 of the FIFO. */ 1647 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1648 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1649 /* Program write watermark -- 1/8 of the FIFO. */ 1650 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1651 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1652 } 1653 1654 /* Disable write protection at controller level */ 1655 if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) 1656 writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); 1657 1658 /* Disable direct access controller */ 1659 if (!cqspi->use_direct_mode) { 1660 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1661 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1662 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1663 } 1664 1665 /* Enable DMA interface */ 1666 if (cqspi->use_dma_read) { 1667 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1668 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1669 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1670 } 1671 } 1672 1673 static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi) 1674 { 1675 struct device *dev = &cqspi->pdev->dev; 1676 u32 reg, fifo_depth; 1677 1678 if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE) 1679 return; 1680 1681 /* 1682 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N 1683 * the FIFO depth. 1684 */ 1685 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1686 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1687 fifo_depth = reg + 1; 1688 1689 /* FIFO depth of zero means no value from devicetree was provided. */ 1690 if (cqspi->fifo_depth == 0) { 1691 cqspi->fifo_depth = fifo_depth; 1692 dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth); 1693 } else if (fifo_depth != cqspi->fifo_depth) { 1694 dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n", 1695 fifo_depth, cqspi->fifo_depth); 1696 } 1697 } 1698 1699 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1700 { 1701 dma_cap_mask_t mask; 1702 1703 dma_cap_zero(mask); 1704 dma_cap_set(DMA_MEMCPY, mask); 1705 1706 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1707 if (IS_ERR(cqspi->rx_chan)) { 1708 int ret = PTR_ERR(cqspi->rx_chan); 1709 1710 cqspi->rx_chan = NULL; 1711 if (ret == -ENODEV) { 1712 /* DMA support is not mandatory */ 1713 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n"); 1714 return 0; 1715 } 1716 1717 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1718 } 1719 init_completion(&cqspi->rx_dma_complete); 1720 1721 return 0; 1722 } 1723 1724 static const char *cqspi_get_name(struct spi_mem *mem) 1725 { 1726 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1727 struct device *dev = &cqspi->pdev->dev; 1728 1729 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 1730 spi_get_chipselect(mem->spi, 0)); 1731 } 1732 1733 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1734 .exec_op = cqspi_exec_mem_op, 1735 .get_name = cqspi_get_name, 1736 .supports_op = cqspi_supports_mem_op, 1737 }; 1738 1739 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1740 .dtr = true, 1741 .per_op_freq = true, 1742 }; 1743 1744 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1745 { 1746 struct platform_device *pdev = cqspi->pdev; 1747 struct device *dev = &pdev->dev; 1748 struct cqspi_flash_pdata *f_pdata; 1749 int ret, cs, max_cs = -1; 1750 1751 /* Get flash device data */ 1752 for_each_available_child_of_node_scoped(dev->of_node, np) { 1753 ret = of_property_read_u32(np, "reg", &cs); 1754 if (ret) { 1755 dev_err(dev, "Couldn't determine chip select.\n"); 1756 return ret; 1757 } 1758 1759 if (cs >= cqspi->num_chipselect) { 1760 dev_err(dev, "Chip select %d out of range.\n", cs); 1761 return -EINVAL; 1762 } 1763 1764 max_cs = max_t(int, cs, max_cs); 1765 1766 f_pdata = &cqspi->f_pdata[cs]; 1767 f_pdata->cqspi = cqspi; 1768 f_pdata->cs = cs; 1769 1770 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1771 if (ret) 1772 return ret; 1773 } 1774 1775 if (max_cs < 0) { 1776 dev_err(dev, "No flash device declared\n"); 1777 return -ENODEV; 1778 } 1779 1780 cqspi->num_chipselect = max_cs + 1; 1781 return 0; 1782 } 1783 1784 static int cqspi_probe(struct platform_device *pdev) 1785 { 1786 const struct cqspi_driver_platdata *ddata; 1787 struct reset_control *rstc, *rstc_ocp, *rstc_ref; 1788 struct device *dev = &pdev->dev; 1789 struct spi_controller *host; 1790 struct resource *res_ahb; 1791 struct cqspi_st *cqspi; 1792 int ret, irq; 1793 1794 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); 1795 if (!host) 1796 return -ENOMEM; 1797 1798 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1799 host->mem_ops = &cqspi_mem_ops; 1800 host->mem_caps = &cqspi_mem_caps; 1801 1802 cqspi = spi_controller_get_devdata(host); 1803 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) 1804 cqspi->is_jh7110 = true; 1805 if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) 1806 cqspi->is_rzn1 = true; 1807 1808 cqspi->pdev = pdev; 1809 cqspi->host = host; 1810 cqspi->ddata = ddata = of_device_get_match_data(dev); 1811 platform_set_drvdata(pdev, cqspi); 1812 1813 /* Obtain configuration from OF. */ 1814 ret = cqspi_of_get_pdata(cqspi); 1815 if (ret) { 1816 dev_err(dev, "Cannot get mandatory OF data.\n"); 1817 return -ENODEV; 1818 } 1819 1820 ret = cqspi_setup_flash(cqspi); 1821 if (ret) { 1822 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1823 return ret; 1824 } 1825 1826 /* Obtain QSPI clocks. */ 1827 memcpy(&cqspi->clks, &cqspi_clks, sizeof(cqspi->clks)); 1828 ret = devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); 1829 if (ret) 1830 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1831 1832 if (!cqspi->clks[CLK_QSPI_REF].clk) { 1833 dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); 1834 return -ENODEV; 1835 } 1836 1837 /* Obtain and remap controller address. */ 1838 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1839 if (IS_ERR(cqspi->iobase)) { 1840 dev_err(dev, "Cannot remap controller address.\n"); 1841 ret = PTR_ERR(cqspi->iobase); 1842 return ret; 1843 } 1844 1845 /* Obtain and remap AHB address. */ 1846 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1847 if (IS_ERR(cqspi->ahb_base)) { 1848 dev_err(dev, "Cannot remap AHB address.\n"); 1849 ret = PTR_ERR(cqspi->ahb_base); 1850 return ret; 1851 } 1852 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1853 cqspi->ahb_size = resource_size(res_ahb); 1854 1855 init_completion(&cqspi->transfer_complete); 1856 1857 /* Obtain IRQ line. */ 1858 irq = platform_get_irq(pdev, 0); 1859 if (irq < 0) 1860 return -ENXIO; 1861 1862 ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 1863 if (ret) { 1864 dev_err(dev, "Cannot enable QSPI clocks.\n"); 1865 return ret; 1866 } 1867 1868 /* Obtain QSPI reset control */ 1869 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1870 if (IS_ERR(rstc)) { 1871 ret = PTR_ERR(rstc); 1872 dev_err(dev, "Cannot get QSPI reset.\n"); 1873 goto disable_clks; 1874 } 1875 1876 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1877 if (IS_ERR(rstc_ocp)) { 1878 ret = PTR_ERR(rstc_ocp); 1879 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1880 goto disable_clks; 1881 } 1882 1883 if (cqspi->is_jh7110) { 1884 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1885 if (IS_ERR(rstc_ref)) { 1886 ret = PTR_ERR(rstc_ref); 1887 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1888 goto disable_clks; 1889 } 1890 reset_control_assert(rstc_ref); 1891 reset_control_deassert(rstc_ref); 1892 } 1893 1894 reset_control_assert(rstc); 1895 reset_control_deassert(rstc); 1896 1897 reset_control_assert(rstc_ocp); 1898 reset_control_deassert(rstc_ocp); 1899 1900 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); 1901 if (!cqspi->is_rzn1) { 1902 host->max_speed_hz = cqspi->master_ref_clk_hz; 1903 } else { 1904 host->max_speed_hz = cqspi->master_ref_clk_hz / 2; 1905 host->min_speed_hz = cqspi->master_ref_clk_hz / 32; 1906 } 1907 1908 /* write completion is supported by default */ 1909 cqspi->wr_completion = true; 1910 1911 if (ddata) { 1912 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1913 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1914 cqspi->master_ref_clk_hz); 1915 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1916 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1917 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD) 1918 host->mode_bits |= SPI_TX_QUAD; 1919 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1920 cqspi->use_direct_mode = true; 1921 cqspi->use_direct_mode_wr = true; 1922 } 1923 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1924 cqspi->use_dma_read = true; 1925 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1926 cqspi->wr_completion = false; 1927 if (ddata->quirks & CQSPI_SLOW_SRAM) 1928 cqspi->slow_sram = true; 1929 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1930 cqspi->apb_ahb_hazard = true; 1931 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1932 cqspi->disable_stig_mode = true; 1933 1934 if (ddata->quirks & CQSPI_DMA_SET_MASK) { 1935 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1936 if (ret) 1937 goto disable_clks; 1938 } 1939 } 1940 1941 refcount_set(&cqspi->refcount, 1); 1942 refcount_set(&cqspi->inflight_ops, 1); 1943 1944 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1945 pdev->name, cqspi); 1946 if (ret) { 1947 dev_err(dev, "Cannot request IRQ.\n"); 1948 goto disable_clks; 1949 } 1950 1951 cqspi_wait_idle(cqspi); 1952 cqspi_controller_enable(cqspi, 0); 1953 cqspi_controller_detect_fifo_depth(cqspi); 1954 cqspi_controller_init(cqspi); 1955 cqspi_controller_enable(cqspi, 1); 1956 cqspi->current_cs = -1; 1957 cqspi->sclk = 0; 1958 1959 pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT); 1960 pm_runtime_use_autosuspend(dev); 1961 pm_runtime_get_noresume(dev); 1962 pm_runtime_set_active(dev); 1963 pm_runtime_enable(dev); 1964 1965 host->num_chipselect = cqspi->num_chipselect; 1966 1967 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) 1968 cqspi_device_reset(cqspi); 1969 1970 if (cqspi->use_direct_mode && !cqspi->is_rzn1) { 1971 ret = cqspi_request_mmap_dma(cqspi); 1972 if (ret == -EPROBE_DEFER) { 1973 dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); 1974 goto disable_rpm; 1975 } 1976 } 1977 1978 ret = spi_register_controller(host); 1979 if (ret) { 1980 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1981 goto release_dma_chan; 1982 } 1983 1984 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 1985 pm_runtime_put_autosuspend(dev); 1986 1987 return 0; 1988 1989 release_dma_chan: 1990 if (cqspi->rx_chan) 1991 dma_release_channel(cqspi->rx_chan); 1992 disable_rpm: 1993 pm_runtime_disable(dev); 1994 pm_runtime_set_suspended(dev); 1995 pm_runtime_put_noidle(dev); 1996 pm_runtime_dont_use_autosuspend(dev); 1997 1998 cqspi_controller_enable(cqspi, 0); 1999 disable_clks: 2000 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2001 2002 return ret; 2003 } 2004 2005 static void cqspi_remove(struct platform_device *pdev) 2006 { 2007 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 2008 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 2009 int ret = 0; 2010 2011 spi_unregister_controller(cqspi->host); 2012 2013 refcount_set(&cqspi->refcount, 0); 2014 2015 if (!refcount_dec_and_test(&cqspi->inflight_ops)) 2016 cqspi_wait_idle(cqspi); 2017 2018 if (cqspi->rx_chan) 2019 dma_release_channel(cqspi->rx_chan); 2020 2021 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2022 ret = pm_runtime_get_sync(&pdev->dev); 2023 2024 if (ret >= 0) { 2025 cqspi_controller_enable(cqspi, 0); 2026 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2027 } 2028 2029 pm_runtime_disable(&pdev->dev); 2030 pm_runtime_set_suspended(&pdev->dev); 2031 pm_runtime_put_noidle(&pdev->dev); 2032 pm_runtime_dont_use_autosuspend(&pdev->dev); 2033 } 2034 2035 static int cqspi_runtime_suspend(struct device *dev) 2036 { 2037 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2038 2039 cqspi_controller_enable(cqspi, 0); 2040 clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2041 return 0; 2042 } 2043 2044 static int cqspi_runtime_resume(struct device *dev) 2045 { 2046 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2047 int ret; 2048 2049 ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 2050 if (ret) 2051 return ret; 2052 2053 cqspi_wait_idle(cqspi); 2054 cqspi_controller_enable(cqspi, 0); 2055 cqspi_controller_init(cqspi); 2056 cqspi_controller_enable(cqspi, 1); 2057 2058 cqspi->current_cs = -1; 2059 cqspi->sclk = 0; 2060 return 0; 2061 } 2062 2063 static int cqspi_suspend(struct device *dev) 2064 { 2065 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2066 int ret; 2067 2068 ret = spi_controller_suspend(cqspi->host); 2069 if (ret) 2070 return ret; 2071 2072 return pm_runtime_force_suspend(dev); 2073 } 2074 2075 static int cqspi_resume(struct device *dev) 2076 { 2077 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2078 int ret; 2079 2080 ret = pm_runtime_force_resume(dev); 2081 if (ret) { 2082 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 2083 return ret; 2084 } 2085 2086 return spi_controller_resume(cqspi->host); 2087 } 2088 2089 static const struct dev_pm_ops cqspi_dev_pm_ops = { 2090 RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL) 2091 SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume) 2092 }; 2093 2094 static const struct cqspi_driver_platdata cdns_qspi = { 2095 .quirks = CQSPI_DISABLE_DAC_MODE, 2096 }; 2097 2098 static const struct cqspi_driver_platdata k2g_qspi = { 2099 .quirks = CQSPI_NEEDS_WR_DELAY, 2100 }; 2101 2102 static const struct cqspi_driver_platdata am654_ospi = { 2103 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, 2104 .quirks = CQSPI_NEEDS_WR_DELAY, 2105 }; 2106 2107 static const struct cqspi_driver_platdata intel_lgm_qspi = { 2108 .quirks = CQSPI_DISABLE_DAC_MODE, 2109 }; 2110 2111 static const struct cqspi_driver_platdata socfpga_qspi = { 2112 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2113 CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE | 2114 CQSPI_DISABLE_RUNTIME_PM, 2115 }; 2116 2117 static const struct cqspi_driver_platdata versal_ospi = { 2118 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2119 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | 2120 CQSPI_DMA_SET_MASK, 2121 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2122 .get_dma_status = cqspi_get_versal_dma_status, 2123 }; 2124 2125 static const struct cqspi_driver_platdata versal2_ospi = { 2126 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2127 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | 2128 CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET, 2129 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2130 .get_dma_status = cqspi_get_versal_dma_status, 2131 }; 2132 2133 static const struct cqspi_driver_platdata jh7110_qspi = { 2134 .quirks = CQSPI_DISABLE_DAC_MODE, 2135 }; 2136 2137 static const struct cqspi_driver_platdata pensando_cdns_qspi = { 2138 .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, 2139 }; 2140 2141 static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = { 2142 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2143 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2144 CQSPI_RD_NO_IRQ, 2145 }; 2146 2147 static const struct cqspi_driver_platdata renesas_rzn1_qspi = { 2148 .hwcaps_mask = CQSPI_SUPPORTS_QUAD, 2149 .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | 2150 CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, 2151 }; 2152 2153 static const struct of_device_id cqspi_dt_ids[] = { 2154 { 2155 .compatible = "cdns,qspi-nor", 2156 .data = &cdns_qspi, 2157 }, 2158 { 2159 .compatible = "ti,k2g-qspi", 2160 .data = &k2g_qspi, 2161 }, 2162 { 2163 .compatible = "ti,am654-ospi", 2164 .data = &am654_ospi, 2165 }, 2166 { 2167 .compatible = "intel,lgm-qspi", 2168 .data = &intel_lgm_qspi, 2169 }, 2170 { 2171 .compatible = "xlnx,versal-ospi-1.0", 2172 .data = &versal_ospi, 2173 }, 2174 { 2175 .compatible = "intel,socfpga-qspi", 2176 .data = &socfpga_qspi, 2177 }, 2178 { 2179 .compatible = "starfive,jh7110-qspi", 2180 .data = &jh7110_qspi, 2181 }, 2182 { 2183 .compatible = "amd,pensando-elba-qspi", 2184 .data = &pensando_cdns_qspi, 2185 }, 2186 { 2187 .compatible = "mobileye,eyeq5-ospi", 2188 .data = &mobileye_eyeq5_ospi, 2189 }, 2190 { 2191 .compatible = "amd,versal2-ospi", 2192 .data = &versal2_ospi, 2193 }, 2194 { 2195 .compatible = "renesas,rzn1-qspi", 2196 .data = &renesas_rzn1_qspi, 2197 }, 2198 { /* end of table */ } 2199 }; 2200 2201 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 2202 2203 static struct platform_driver cqspi_platform_driver = { 2204 .probe = cqspi_probe, 2205 .remove = cqspi_remove, 2206 .driver = { 2207 .name = CQSPI_NAME, 2208 .pm = pm_ptr(&cqspi_dev_pm_ops), 2209 .of_match_table = cqspi_dt_ids, 2210 }, 2211 }; 2212 2213 module_platform_driver(cqspi_platform_driver); 2214 2215 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 2216 MODULE_LICENSE("GPL v2"); 2217 MODULE_ALIAS("platform:" CQSPI_NAME); 2218 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 2219 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 2220 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 2221 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 2222 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 2223