1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Perf PMU sysfs events attributes for available CPU-measurement counters
4 *
5 */
6
7 #include <linux/slab.h>
8 #include <linux/perf_event.h>
9 #include <asm/cpu_mf.h>
10
11
12 /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
13
14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
24 CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
25 CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
26 CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
27 CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
28 CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
29 CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
30 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
31 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
32 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
33 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
34 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46 CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47 CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50 CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51 CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
54 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
55 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
56 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
57 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
58 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
59 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
60 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
61 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
62 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
63 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
64 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
65 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
66 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
67 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
68 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
69 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
70 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
71 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
72 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
73 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
74 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
75 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
76 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
77 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
78 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
79 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
80 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
81 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
82 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
83 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
84 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
85 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
86 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
87 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
88 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
89 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
90 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
91 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
92 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
93 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
94 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
95 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
96 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
97 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
98 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
99 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
100 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
101 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
102 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
103 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
104 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
105 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
106 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
107 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
108 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
109 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
110 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
111 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
112 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
113 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
114 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
115 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
116 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
117 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
118 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
119 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
120 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
121 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
122 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
123 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
124 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
125 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
126 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
127 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
128 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
129 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
130 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
131 CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
132 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
133 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
134 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
135 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
136 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
137 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
138 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
139 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
140 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
141 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
142 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
143 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
144 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
145 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
150 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
151 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
152 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
153 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
154 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
155 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
156 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
157 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
158 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
159 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
160 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
161 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
162 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
163 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
168 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
169 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
170 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
171 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
172 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
173 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
174 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
175 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
176 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
177 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
178 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
179 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
180 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
181 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
182 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
183 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
184 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
185 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
186 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
187 CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
188 CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
189 CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
190 CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
191 CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
192 CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
193 CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
194 CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
195 CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
196 CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
197 CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
198 CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
199 CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
200 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
201 CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
202 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
203 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
204 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
205 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
206 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
207 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
208 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
209 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
210 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
211 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
212 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
213 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
214 CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
215 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
216 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
217 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
218 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
219 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
220 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
221 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
222 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
223 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
224 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
225 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
226 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
227 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
228 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
229 CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
230 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
231 CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
232 CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
233 CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
234 CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
235 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
236 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240 CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
241 CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
242 CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
243 CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083);
244 CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084);
245 CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085);
246 CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086);
247 CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087);
248 CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088);
249 CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089);
250 CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a);
251 CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b);
252 CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c);
253 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d);
254 CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f);
255 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
256 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
257 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
258 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
259 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
260 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
261 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
262 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
263 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
264 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
265 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
266 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
267 CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
268 CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
269 CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
270 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
271 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
272 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
273 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
274 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
275 CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
276 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
277 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
278 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
279 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
280 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
281 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
282 CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
283 CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
284 CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
285 CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1);
286 CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2);
287 CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8);
288 CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3);
289 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4);
290 CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5);
291 CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7);
292 CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc);
293 CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x0108);
294 CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x0109);
295 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
296 CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
297 CPUMF_EVENT_ATTR(cf_z16, L1D_RO_EXCL_WRITES, 0x0080);
298 CPUMF_EVENT_ATTR(cf_z16, DTLB2_WRITES, 0x0081);
299 CPUMF_EVENT_ATTR(cf_z16, DTLB2_MISSES, 0x0082);
300 CPUMF_EVENT_ATTR(cf_z16, CRSTE_1MB_WRITES, 0x0083);
301 CPUMF_EVENT_ATTR(cf_z16, DTLB2_GPAGE_WRITES, 0x0084);
302 CPUMF_EVENT_ATTR(cf_z16, ITLB2_WRITES, 0x0086);
303 CPUMF_EVENT_ATTR(cf_z16, ITLB2_MISSES, 0x0087);
304 CPUMF_EVENT_ATTR(cf_z16, TLB2_PTE_WRITES, 0x0089);
305 CPUMF_EVENT_ATTR(cf_z16, TLB2_CRSTE_WRITES, 0x008a);
306 CPUMF_EVENT_ATTR(cf_z16, TLB2_ENGINES_BUSY, 0x008b);
307 CPUMF_EVENT_ATTR(cf_z16, TX_C_TEND, 0x008c);
308 CPUMF_EVENT_ATTR(cf_z16, TX_NC_TEND, 0x008d);
309 CPUMF_EVENT_ATTR(cf_z16, L1C_TLB2_MISSES, 0x008f);
310 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ, 0x0091);
311 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_IV, 0x0092);
312 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_CHIP_HIT, 0x0093);
313 CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_DRAWER_HIT, 0x0094);
314 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP, 0x0095);
315 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_IV, 0x0096);
316 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_CHIP_HIT, 0x0097);
317 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
318 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE, 0x0099);
319 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER, 0x009a);
320 CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER, 0x009b);
321 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_MEMORY, 0x009c);
322 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE_MEMORY, 0x009d);
323 CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER_MEMORY, 0x009e);
324 CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER_MEMORY, 0x009f);
325 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_IV, 0x00a0);
326 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
327 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
328 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_IV, 0x00a3);
329 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
330 CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
331 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_IV, 0x00a6);
332 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
333 CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
334 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ, 0x00a9);
335 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_IV, 0x00aa);
336 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_CHIP_HIT, 0x00ab);
337 CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_DRAWER_HIT, 0x00ac);
338 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP, 0x00ad);
339 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_IV, 0x00ae);
340 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_CHIP_HIT, 0x00af);
341 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
342 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE, 0x00b1);
343 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER, 0x00b2);
344 CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER, 0x00b3);
345 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_MEMORY, 0x00b4);
346 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE_MEMORY, 0x00b5);
347 CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER_MEMORY, 0x00b6);
348 CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER_MEMORY, 0x00b7);
349 CPUMF_EVENT_ATTR(cf_z16, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
350 CPUMF_EVENT_ATTR(cf_z16, VX_BCD_EXECUTION_SLOTS, 0x00e1);
351 CPUMF_EVENT_ATTR(cf_z16, DECIMAL_INSTRUCTIONS, 0x00e2);
352 CPUMF_EVENT_ATTR(cf_z16, LAST_HOST_TRANSLATIONS, 0x00e8);
353 CPUMF_EVENT_ATTR(cf_z16, TX_NC_TABORT, 0x00f4);
354 CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_NO_SPECIAL, 0x00f5);
355 CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_SPECIAL, 0x00f6);
356 CPUMF_EVENT_ATTR(cf_z16, DFLT_ACCESS, 0x00f8);
357 CPUMF_EVENT_ATTR(cf_z16, DFLT_CYCLES, 0x00fd);
358 CPUMF_EVENT_ATTR(cf_z16, SORTL, 0x0100);
359 CPUMF_EVENT_ATTR(cf_z16, DFLT_CC, 0x0109);
360 CPUMF_EVENT_ATTR(cf_z16, DFLT_CCFINISH, 0x010a);
361 CPUMF_EVENT_ATTR(cf_z16, NNPA_INVOCATIONS, 0x010b);
362 CPUMF_EVENT_ATTR(cf_z16, NNPA_COMPLETIONS, 0x010c);
363 CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
364 CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
365 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
366 CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
367 CPUMF_EVENT_ATTR(cf_z17, L1D_RO_EXCL_WRITES, 0x0080);
368 CPUMF_EVENT_ATTR(cf_z17, DTLB2_WRITES, 0x0081);
369 CPUMF_EVENT_ATTR(cf_z17, DTLB2_MISSES, 0x0082);
370 CPUMF_EVENT_ATTR(cf_z17, CRSTE_1MB_WRITES, 0x0083);
371 CPUMF_EVENT_ATTR(cf_z17, DTLB2_GPAGE_WRITES, 0x0084);
372 CPUMF_EVENT_ATTR(cf_z17, ITLB2_WRITES, 0x0086);
373 CPUMF_EVENT_ATTR(cf_z17, ITLB2_MISSES, 0x0087);
374 CPUMF_EVENT_ATTR(cf_z17, TLB2_PTE_WRITES, 0x0089);
375 CPUMF_EVENT_ATTR(cf_z17, TLB2_CRSTE_WRITES, 0x008a);
376 CPUMF_EVENT_ATTR(cf_z17, TLB2_ENGINES_BUSY, 0x008b);
377 CPUMF_EVENT_ATTR(cf_z17, TX_C_TEND, 0x008c);
378 CPUMF_EVENT_ATTR(cf_z17, TX_NC_TEND, 0x008d);
379 CPUMF_EVENT_ATTR(cf_z17, L1C_TLB2_MISSES, 0x008f);
380 CPUMF_EVENT_ATTR(cf_z17, DCW_REQ, 0x0091);
381 CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_IV, 0x0092);
382 CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_CHIP_HIT, 0x0093);
383 CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_DRAWER_HIT, 0x0094);
384 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP, 0x0095);
385 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_IV, 0x0096);
386 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_CHIP_HIT, 0x0097);
387 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
388 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE, 0x0099);
389 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER, 0x009a);
390 CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER, 0x009b);
391 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_MEMORY, 0x009c);
392 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE_MEMORY, 0x009d);
393 CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER_MEMORY, 0x009e);
394 CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER_MEMORY, 0x009f);
395 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_IV, 0x00a0);
396 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
397 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
398 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_IV, 0x00a3);
399 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
400 CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
401 CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_IV, 0x00a6);
402 CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
403 CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
404 CPUMF_EVENT_ATTR(cf_z17, ICW_REQ, 0x00a9);
405 CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_IV, 0x00aa);
406 CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_CHIP_HIT, 0x00ab);
407 CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_DRAWER_HIT, 0x00ac);
408 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP, 0x00ad);
409 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_IV, 0x00ae);
410 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_CHIP_HIT, 0x00af);
411 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
412 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_MODULE, 0x00b1);
413 CPUMF_EVENT_ATTR(cf_z17, ICW_ON_DRAWER, 0x00b2);
414 CPUMF_EVENT_ATTR(cf_z17, ICW_OFF_DRAWER, 0x00b3);
415 CPUMF_EVENT_ATTR(cf_z17, CYCLES_SAMETHRD, 0x00ca);
416 CPUMF_EVENT_ATTR(cf_z17, CYCLES_DIFFTHRD, 0x00cb);
417 CPUMF_EVENT_ATTR(cf_z17, INST_SAMETHRD, 0x00cc);
418 CPUMF_EVENT_ATTR(cf_z17, INST_DIFFTHRD, 0x00cd);
419 CPUMF_EVENT_ATTR(cf_z17, WRONG_BRANCH_PREDICTION, 0x00ce);
420 CPUMF_EVENT_ATTR(cf_z17, VX_BCD_EXECUTION_SLOTS, 0x00e1);
421 CPUMF_EVENT_ATTR(cf_z17, DECIMAL_INSTRUCTIONS, 0x00e2);
422 CPUMF_EVENT_ATTR(cf_z17, LAST_HOST_TRANSLATIONS, 0x00e8);
423 CPUMF_EVENT_ATTR(cf_z17, TX_NC_TABORT, 0x00f4);
424 CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_NO_SPECIAL, 0x00f5);
425 CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_SPECIAL, 0x00f6);
426 CPUMF_EVENT_ATTR(cf_z17, DFLT_ACCESS, 0x00f8);
427 CPUMF_EVENT_ATTR(cf_z17, DFLT_CYCLES, 0x00fd);
428 CPUMF_EVENT_ATTR(cf_z17, SORTL, 0x0100);
429 CPUMF_EVENT_ATTR(cf_z17, DFLT_CC, 0x0109);
430 CPUMF_EVENT_ATTR(cf_z17, DFLT_CCFINISH, 0x010a);
431 CPUMF_EVENT_ATTR(cf_z17, NNPA_INVOCATIONS, 0x010b);
432 CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPLETIONS, 0x010c);
433 CPUMF_EVENT_ATTR(cf_z17, NNPA_WAIT_LOCK, 0x010d);
434 CPUMF_EVENT_ATTR(cf_z17, NNPA_HOLD_LOCK, 0x010e);
435 CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_ONCHIP, 0x0110);
436 CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_OFFCHIP, 0x0111);
437 CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_DIFF, 0x0112);
438 CPUMF_EVENT_ATTR(cf_z17, NNPA_4K_PREFETCH, 0x0114);
439 CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPL_LOCK, 0x0115);
440 CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK, 0x0116);
441 CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO, 0x0117);
442 CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
443 CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
444
445 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
446 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
447 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
448 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
449 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
450 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
451 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
452 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
453 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
454 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
455 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
456 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
457 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
458 NULL,
459 };
460
461 static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
462 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
463 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
464 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
465 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
466 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
467 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
468 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
469 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
470 NULL,
471 };
472
473 static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
474 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
475 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
476 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
477 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
478 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
479 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
480 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
481 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
482 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
483 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
484 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
485 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
486 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
487 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
488 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
489 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
490 NULL,
491 };
492
493 static struct attribute *cpumcf_svn_678_pmu_event_attr[] __initdata = {
494 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
495 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
496 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
497 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
498 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
499 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
500 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
501 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
502 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
503 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
504 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
505 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
506 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
507 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
508 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
509 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
510 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
511 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
512 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
513 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
514 NULL,
515 };
516
517 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
518 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
519 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
520 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
521 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
522 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
523 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
524 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
525 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
526 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
527 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
528 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
529 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
530 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
531 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
532 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
533 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
534 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
535 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
536 NULL,
537 };
538
539 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
540 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
541 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
542 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
543 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
544 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
545 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
546 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
547 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
548 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
549 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
550 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
551 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
552 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
553 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
554 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
555 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
556 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
557 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
558 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
559 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
560 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
561 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
562 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
563 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
564 NULL,
565 };
566
567 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
568 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
569 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
570 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
571 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
572 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
573 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
574 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
575 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
576 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
577 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
578 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
579 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
580 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
581 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
582 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
583 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
584 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
585 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
586 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
587 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
588 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
589 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
590 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
591 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
592 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
593 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
594 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
595 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
596 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
597 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
598 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
599 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
600 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
601 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
602 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
603 NULL,
604 };
605
606 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
607 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
608 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
609 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
610 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
611 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
612 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
613 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
614 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
615 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
616 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
617 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
618 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
619 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
620 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
621 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
622 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
623 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
624 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
625 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
626 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
627 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
628 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
629 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
630 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
631 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
632 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
633 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
634 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
635 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
636 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
637 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
638 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
639 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
640 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
641 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
642 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
643 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
644 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
645 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
646 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
647 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
648 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
649 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
650 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
651 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
652 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
653 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
654 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
655 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
656 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
657 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
658 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
659 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
660 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
661 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
662 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
663 NULL,
664 };
665
666 static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
667 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
668 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
669 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
670 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
671 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
672 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
673 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
674 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
675 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
676 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
677 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
678 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
679 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
680 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
681 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
682 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
683 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
684 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
685 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
686 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
687 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
688 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
689 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
690 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
691 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
692 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
693 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
694 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
695 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
696 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
697 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
698 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
699 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
700 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
701 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
702 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
703 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
704 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
705 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
706 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
707 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
708 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
709 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
710 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
711 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
712 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
713 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
714 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
715 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
716 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
717 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
718 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
719 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
720 NULL,
721 };
722
723 static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = {
724 CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES),
725 CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES),
726 CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES),
727 CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES),
728 CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES),
729 CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES),
730 CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES),
731 CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES),
732 CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES),
733 CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES),
734 CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES),
735 CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY),
736 CPUMF_EVENT_PTR(cf_z15, TX_C_TEND),
737 CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND),
738 CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES),
739 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES),
740 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
741 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
742 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES),
743 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
744 CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
745 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
746 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
747 CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
748 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES),
749 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
750 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
751 CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES),
752 CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES),
753 CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
754 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES),
755 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
756 CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
757 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES),
758 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
759 CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
760 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
761 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
762 CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
763 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES),
764 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
765 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
766 CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES),
767 CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES),
768 CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS),
769 CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS),
770 CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS),
771 CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS),
772 CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT),
773 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL),
774 CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL),
775 CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS),
776 CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES),
777 CPUMF_EVENT_PTR(cf_z15, DFLT_CC),
778 CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH),
779 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
780 CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
781 NULL,
782 };
783
784 static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
785 CPUMF_EVENT_PTR(cf_z16, L1D_RO_EXCL_WRITES),
786 CPUMF_EVENT_PTR(cf_z16, DTLB2_WRITES),
787 CPUMF_EVENT_PTR(cf_z16, DTLB2_MISSES),
788 CPUMF_EVENT_PTR(cf_z16, CRSTE_1MB_WRITES),
789 CPUMF_EVENT_PTR(cf_z16, DTLB2_GPAGE_WRITES),
790 CPUMF_EVENT_PTR(cf_z16, ITLB2_WRITES),
791 CPUMF_EVENT_PTR(cf_z16, ITLB2_MISSES),
792 CPUMF_EVENT_PTR(cf_z16, TLB2_PTE_WRITES),
793 CPUMF_EVENT_PTR(cf_z16, TLB2_CRSTE_WRITES),
794 CPUMF_EVENT_PTR(cf_z16, TLB2_ENGINES_BUSY),
795 CPUMF_EVENT_PTR(cf_z16, TX_C_TEND),
796 CPUMF_EVENT_PTR(cf_z16, TX_NC_TEND),
797 CPUMF_EVENT_PTR(cf_z16, L1C_TLB2_MISSES),
798 CPUMF_EVENT_PTR(cf_z16, DCW_REQ),
799 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_IV),
800 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_CHIP_HIT),
801 CPUMF_EVENT_PTR(cf_z16, DCW_REQ_DRAWER_HIT),
802 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP),
803 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_IV),
804 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_CHIP_HIT),
805 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT),
806 CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE),
807 CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER),
808 CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER),
809 CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_MEMORY),
810 CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE_MEMORY),
811 CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER_MEMORY),
812 CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER_MEMORY),
813 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_IV),
814 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT),
815 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT),
816 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_IV),
817 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT),
818 CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT),
819 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_IV),
820 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT),
821 CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT),
822 CPUMF_EVENT_PTR(cf_z16, ICW_REQ),
823 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_IV),
824 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_CHIP_HIT),
825 CPUMF_EVENT_PTR(cf_z16, ICW_REQ_DRAWER_HIT),
826 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP),
827 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_IV),
828 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_CHIP_HIT),
829 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT),
830 CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE),
831 CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER),
832 CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER),
833 CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_MEMORY),
834 CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE_MEMORY),
835 CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER_MEMORY),
836 CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER_MEMORY),
837 CPUMF_EVENT_PTR(cf_z16, BCD_DFP_EXECUTION_SLOTS),
838 CPUMF_EVENT_PTR(cf_z16, VX_BCD_EXECUTION_SLOTS),
839 CPUMF_EVENT_PTR(cf_z16, DECIMAL_INSTRUCTIONS),
840 CPUMF_EVENT_PTR(cf_z16, LAST_HOST_TRANSLATIONS),
841 CPUMF_EVENT_PTR(cf_z16, TX_NC_TABORT),
842 CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_NO_SPECIAL),
843 CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_SPECIAL),
844 CPUMF_EVENT_PTR(cf_z16, DFLT_ACCESS),
845 CPUMF_EVENT_PTR(cf_z16, DFLT_CYCLES),
846 CPUMF_EVENT_PTR(cf_z16, SORTL),
847 CPUMF_EVENT_PTR(cf_z16, DFLT_CC),
848 CPUMF_EVENT_PTR(cf_z16, DFLT_CCFINISH),
849 CPUMF_EVENT_PTR(cf_z16, NNPA_INVOCATIONS),
850 CPUMF_EVENT_PTR(cf_z16, NNPA_COMPLETIONS),
851 CPUMF_EVENT_PTR(cf_z16, NNPA_WAIT_LOCK),
852 CPUMF_EVENT_PTR(cf_z16, NNPA_HOLD_LOCK),
853 CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
854 CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
855 NULL,
856 };
857
858 static struct attribute *cpumcf_z17_pmu_event_attr[] __initdata = {
859 CPUMF_EVENT_PTR(cf_z17, L1D_RO_EXCL_WRITES),
860 CPUMF_EVENT_PTR(cf_z17, DTLB2_WRITES),
861 CPUMF_EVENT_PTR(cf_z17, DTLB2_MISSES),
862 CPUMF_EVENT_PTR(cf_z17, CRSTE_1MB_WRITES),
863 CPUMF_EVENT_PTR(cf_z17, DTLB2_GPAGE_WRITES),
864 CPUMF_EVENT_PTR(cf_z17, ITLB2_WRITES),
865 CPUMF_EVENT_PTR(cf_z17, ITLB2_MISSES),
866 CPUMF_EVENT_PTR(cf_z17, TLB2_PTE_WRITES),
867 CPUMF_EVENT_PTR(cf_z17, TLB2_CRSTE_WRITES),
868 CPUMF_EVENT_PTR(cf_z17, TLB2_ENGINES_BUSY),
869 CPUMF_EVENT_PTR(cf_z17, TX_C_TEND),
870 CPUMF_EVENT_PTR(cf_z17, TX_NC_TEND),
871 CPUMF_EVENT_PTR(cf_z17, L1C_TLB2_MISSES),
872 CPUMF_EVENT_PTR(cf_z17, DCW_REQ),
873 CPUMF_EVENT_PTR(cf_z17, DCW_REQ_IV),
874 CPUMF_EVENT_PTR(cf_z17, DCW_REQ_CHIP_HIT),
875 CPUMF_EVENT_PTR(cf_z17, DCW_REQ_DRAWER_HIT),
876 CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP),
877 CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_IV),
878 CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_CHIP_HIT),
879 CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT),
880 CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE),
881 CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER),
882 CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER),
883 CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_MEMORY),
884 CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE_MEMORY),
885 CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER_MEMORY),
886 CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER_MEMORY),
887 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_IV),
888 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT),
889 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT),
890 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_IV),
891 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT),
892 CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT),
893 CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_IV),
894 CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT),
895 CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT),
896 CPUMF_EVENT_PTR(cf_z17, ICW_REQ),
897 CPUMF_EVENT_PTR(cf_z17, ICW_REQ_IV),
898 CPUMF_EVENT_PTR(cf_z17, ICW_REQ_CHIP_HIT),
899 CPUMF_EVENT_PTR(cf_z17, ICW_REQ_DRAWER_HIT),
900 CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP),
901 CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_IV),
902 CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_CHIP_HIT),
903 CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT),
904 CPUMF_EVENT_PTR(cf_z17, ICW_ON_MODULE),
905 CPUMF_EVENT_PTR(cf_z17, ICW_ON_DRAWER),
906 CPUMF_EVENT_PTR(cf_z17, ICW_OFF_DRAWER),
907 CPUMF_EVENT_PTR(cf_z17, CYCLES_SAMETHRD),
908 CPUMF_EVENT_PTR(cf_z17, CYCLES_DIFFTHRD),
909 CPUMF_EVENT_PTR(cf_z17, INST_SAMETHRD),
910 CPUMF_EVENT_PTR(cf_z17, INST_DIFFTHRD),
911 CPUMF_EVENT_PTR(cf_z17, WRONG_BRANCH_PREDICTION),
912 CPUMF_EVENT_PTR(cf_z17, VX_BCD_EXECUTION_SLOTS),
913 CPUMF_EVENT_PTR(cf_z17, DECIMAL_INSTRUCTIONS),
914 CPUMF_EVENT_PTR(cf_z17, LAST_HOST_TRANSLATIONS),
915 CPUMF_EVENT_PTR(cf_z17, TX_NC_TABORT),
916 CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_NO_SPECIAL),
917 CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_SPECIAL),
918 CPUMF_EVENT_PTR(cf_z17, DFLT_ACCESS),
919 CPUMF_EVENT_PTR(cf_z17, DFLT_CYCLES),
920 CPUMF_EVENT_PTR(cf_z17, SORTL),
921 CPUMF_EVENT_PTR(cf_z17, DFLT_CC),
922 CPUMF_EVENT_PTR(cf_z17, DFLT_CCFINISH),
923 CPUMF_EVENT_PTR(cf_z17, NNPA_INVOCATIONS),
924 CPUMF_EVENT_PTR(cf_z17, NNPA_COMPLETIONS),
925 CPUMF_EVENT_PTR(cf_z17, NNPA_WAIT_LOCK),
926 CPUMF_EVENT_PTR(cf_z17, NNPA_HOLD_LOCK),
927 CPUMF_EVENT_PTR(cf_z17, NNPA_INST_ONCHIP),
928 CPUMF_EVENT_PTR(cf_z17, NNPA_INST_OFFCHIP),
929 CPUMF_EVENT_PTR(cf_z17, NNPA_INST_DIFF),
930 CPUMF_EVENT_PTR(cf_z17, NNPA_4K_PREFETCH),
931 CPUMF_EVENT_PTR(cf_z17, NNPA_COMPL_LOCK),
932 CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK),
933 CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO),
934 CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
935 CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
936 NULL,
937 };
938
939 /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
940
941 static struct attribute_group cpumcf_pmu_events_group = {
942 .name = "events",
943 };
944
945 PMU_FORMAT_ATTR(event, "config:0-63");
946
947 static struct attribute *cpumcf_pmu_format_attr[] = {
948 &format_attr_event.attr,
949 NULL,
950 };
951
952 static struct attribute_group cpumcf_pmu_format_group = {
953 .name = "format",
954 .attrs = cpumcf_pmu_format_attr,
955 };
956
957 static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
958 &cpumcf_pmu_events_group,
959 &cpumcf_pmu_format_group,
960 NULL,
961 };
962
963
merge_attr(struct attribute ** a,struct attribute ** b,struct attribute ** c)964 static __init struct attribute **merge_attr(struct attribute **a,
965 struct attribute **b,
966 struct attribute **c)
967 {
968 struct attribute **new;
969 int j, i;
970
971 for (j = 0; a[j]; j++)
972 ;
973 for (i = 0; b[i]; i++)
974 j++;
975 for (i = 0; c[i]; i++)
976 j++;
977 j++;
978
979 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
980 if (!new)
981 return NULL;
982 j = 0;
983 for (i = 0; a[i]; i++)
984 new[j++] = a[i];
985 for (i = 0; b[i]; i++)
986 new[j++] = b[i];
987 for (i = 0; c[i]; i++)
988 new[j++] = c[i];
989 new[j] = NULL;
990
991 return new;
992 }
993
cpumf_cf_event_group(void)994 __init const struct attribute_group **cpumf_cf_event_group(void)
995 {
996 struct attribute **combined, **model, **cfvn, **csvn;
997 struct attribute *none[] = { NULL };
998 struct cpumf_ctr_info ci;
999 struct cpuid cpu_id;
1000
1001 /* Determine generic counters set(s) */
1002 qctri(&ci);
1003 switch (ci.cfvn) {
1004 case 1:
1005 cfvn = cpumcf_fvn1_pmu_event_attr;
1006 break;
1007 case 3:
1008 cfvn = cpumcf_fvn3_pmu_event_attr;
1009 break;
1010 default:
1011 cfvn = none;
1012 }
1013
1014 /* Determine version specific crypto set */
1015 csvn = none;
1016 if (ci.csvn >= 1 && ci.csvn <= 5)
1017 csvn = cpumcf_svn_12345_pmu_event_attr;
1018 else if (ci.csvn >= 6)
1019 csvn = cpumcf_svn_678_pmu_event_attr;
1020
1021 /* Determine model-specific counter set(s) */
1022 get_cpu_id(&cpu_id);
1023 switch (cpu_id.machine) {
1024 case 0x2097:
1025 case 0x2098:
1026 model = cpumcf_z10_pmu_event_attr;
1027 break;
1028 case 0x2817:
1029 case 0x2818:
1030 model = cpumcf_z196_pmu_event_attr;
1031 break;
1032 case 0x2827:
1033 case 0x2828:
1034 model = cpumcf_zec12_pmu_event_attr;
1035 break;
1036 case 0x2964:
1037 case 0x2965:
1038 model = cpumcf_z13_pmu_event_attr;
1039 break;
1040 case 0x3906:
1041 case 0x3907:
1042 model = cpumcf_z14_pmu_event_attr;
1043 break;
1044 case 0x8561:
1045 case 0x8562:
1046 model = cpumcf_z15_pmu_event_attr;
1047 break;
1048 case 0x3931:
1049 case 0x3932:
1050 model = cpumcf_z16_pmu_event_attr;
1051 break;
1052 case 0x9175:
1053 case 0x9176:
1054 model = cpumcf_z17_pmu_event_attr;
1055 break;
1056 default:
1057 model = none;
1058 break;
1059 }
1060
1061 combined = merge_attr(cfvn, csvn, model);
1062 if (combined)
1063 cpumcf_pmu_events_group.attrs = combined;
1064 return cpumcf_pmu_attr_groups;
1065 }
1066